A communication system of a plurality of ring communication paths

Abstract

The present application relates to chip design technical field, especially to a plurality of ring communication path communication system, its system includes: F group accelerator G and F ring communication path Ring;Wherein, when the xth accelerator P f x As a source accelerator and the yth accelerator P f y As a destination accelerator, P f x Through a private set of network topology path GR f x Communicate;Wherein, GR f x Including a direct path and E cross-group transit path, the transit accelerator of each cross-group transit path is an accelerator in the f+1 group, and the GR f x All cross-group transit paths in the GR are different. An accelerator in each ring communication path transmits data to the next accelerator through an accelerator in another group as a transit, which improves the bandwidth and increases the throughput of the system.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a communication system with multiple ring communication paths. Background Technology

[0002] In multi-GPU deep learning training, data often needs to be transferred and copied between different GPUs. For example, in parallel model training, different GPUs are responsible for processing different parts of the model, requiring intermediate results to be copied from one GPU to another for subsequent computation. Similarly, in high-performance computing fields such as scientific computing and graphics rendering, D2D cross-GPU memory copying is also necessary when multiple GPUs work together. For instance, in large-scale fluid simulations and ray tracing, different GPUs may be responsible for computations in different regions or stages, requiring data transfer and sharing between the cards. GPUs can directly transfer data when dealing with memory copying without intermediaries in host memory. For example, in a multi-GPU system, memory data on one GPU can be directly copied to the memory of another GPU using RDMA, significantly improving data transfer efficiency and reducing CPU involvement and latency.

[0003] For an interconnected topology with N accelerators, when the N accelerators are directly interconnected point-to-point, each accelerator has one direct path and at most N-1 relay paths via a single relay accelerator. This relay path scheme is particularly complex in communication systems with multiple ring communication paths. If each accelerator uses N-1 relay paths, resource contention will inevitably occur, with multiple paths sharing the same high-speed interconnect link. This not only reduces the bandwidth of each relay path but also leads to decreased throughput and increased latency. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a communication system with multiple ring communication paths, the system comprising: F groups of accelerators G and F ring communication paths (Rings). The f-th ring communication path includes all accelerators in the f-th group, 1 ≤ f ≤ F, and F ≥ 2; wherein the x-th accelerator P in the f-th group... f x With the y-th accelerator P f y Connect, where y = x + 1 when 0 ≤ x < N - 1; y = 0 when x = N - 1, and N is the number of accelerators in each group. Where P f x As a source accelerator and P f y When communicating as a target accelerator, Pf x Through a private set of network topology paths GR f x To communicate; where GR f x This includes one direct route and E cross-group transit routes, with each cross-group transit route using a transit accelerator in the (f+1)th group. The GR... f x The transfer accelerators for all cross-group transfer routes are different.

[0005] The present invention has at least the following beneficial effects:

[0006] Embodiment 3 of the present invention provides a communication system with multiple ring communication paths. The communication system includes multiple ring communication paths. When an accelerator in each ring communication path transmits data to the next accelerator, it uses an accelerator from another group as a relay, thereby improving bandwidth and increasing the system throughput. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a flowchart of a video memory copying method based on a multi-accelerator interconnect topology provided in Embodiment 1 of the present invention;

[0009] Figure 2 This is a flowchart of the video memory copying steps provided in Embodiment 1 of the present invention;

[0010] Figure 3 This is a schematic diagram of a communication system with a single ring communication path provided in Embodiment 2 of the present invention;

[0011] Figure 4 This is a schematic diagram of the cross-group transfer path of an accelerator in the first group provided in Embodiment 3 of the present invention;

[0012] Figure 5 This is a schematic diagram of the cross-group transfer path of an accelerator in the second group provided in Embodiment 3 of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0015] Example 1

[0016] Please see Figure 1 It illustrates a memory copying method based on a multi-accelerator interconnect topology, the method comprising the following steps:

[0017] S100, obtain the maximum number of parallel transmission paths M for each accelerator in the multi-accelerator interconnect topology.

[0018] In one implementation, the multi-accelerator interconnect topology comprises N accelerators directly interconnected point-to-point. That is, any two accelerators are directly connected via a high-speed interconnect interface.

[0019] In one implementation, the high-speed interconnect interfaces are interconnected using a bus conforming to the MetaX Link, NVLink, Infinity Fabric, or UCIe standards.

[0020] In one embodiment, the accelerator is a graphics processing unit (GPU), a vector processor, or an AI processor. Other types of accelerators also fall within the scope of this invention.

[0021] Each accelerator's transmission path includes a direct path and a relay path. The current accelerator is the source accelerator, and another designated accelerator in the multi-accelerator interconnection topology is the destination accelerator. A direct path is the direct route from the source accelerator to the destination accelerator without any intermediate accelerators. A relay path is the path that involves transmission between the source and destination accelerators via an intermediate accelerator. In other words, there are direct paths and M-1 relay paths between the same source and destination accelerators that can transmit in parallel simultaneously to improve transmission efficiency.

[0022] S300: Obtain the video memory in the source accelerator that stores the video memory copy operation request, and divide the video memory of the source accelerator into M buffers according to the bandwidth ratio of the M transmission paths. Each buffer is bound to a corresponding transmission path, and the M transmission paths are transmitted in parallel.

[0023] Among them, video memory is the dedicated memory in the accelerator used to store image data, textures, frame buffers and other information.

[0024] The video memory copy operation request is the process of directly copying data between the video memory of the source accelerator and the destination accelerator. This operation transfers data directly between accelerators through high-speed interconnect technologies (such as NVLink or PCIe bus) without going through host memory (CPU's memory), which is a D2D (Device-to-Device) mode.

[0025] Among them, the video memory copy operation data is the specific data content that is transferred during the video memory copy process.

[0026] Each transmission path has its own bandwidth. The bandwidth of the transmission paths can be the same or different.

[0027] In one implementation, S300, the M transmission paths include a direct path connecting the source accelerator to the destination accelerator and M-1 relay paths.

[0028] In one implementation, the buffer is split by programming the video memory into multiple logical regions, each buffer used to store different data or allocate different tasks. This split is virtual; the video memory itself remains contiguous. As an example, when M=3 and the bandwidth ratio of the three transmission paths is 2:2:1, the buffer is split according to a 2:2:1 storage capacity ratio.

[0029] In one embodiment, the method further includes: S400, when the e-th buffer of the source accelerator is configured with a transmission path R e When the direct path is defined, the e-th buffer of the source accelerator is not split; where the value of e ranges from 1 to M, and e ≠ i.

[0030] S500, the source accelerator completes the video memory copying through the M transmission paths.

[0031] For further information, please refer to [link / reference]. Figure 2 The process of copying video memory also includes:

[0032] S510, when the i-th buffer of the source accelerator is bound to the transmission path R iWhen serving as a relay path, the i-th buffer of the source accelerator is split into K buffer blocks; where i ranges from 1 to M-1; the R i This includes a first path from the source accelerator to the intermediate accelerator, and a second path from the intermediate accelerator to the destination accelerator.

[0033] The buffer block is the basic unit of the buffer. By dividing the buffer of the transit path into K buffer blocks, each buffer can be independently processed during data transit. This allows the K buffer blocks to form a pipeline pattern in the transit path, reducing waiting time and improving transmission efficiency and throughput.

[0034] In one implementation, S500 further includes: S520, where the relay accelerator allocates a relay cache block for temporary storage of relay data, and the relay cache block is allocated in a pre-allocation mode or a dynamic allocation mode.

[0035] In one implementation, the pre-allocation mode is as follows: the relay accelerator pre-allocates a memory pool, which includes K relay cache blocks of the same size; wherein, the k-th relay cache block of the memory pool is used to temporarily store the data of the video memory copy operation request of the k-th cache block of the i-th buffer of the source accelerator, where i ranges from 1 to K. Since the relay cache blocks are pre-allocated, they can be used directly after receiving a video memory copy operation request, reducing allocation time. Furthermore, the pre-allocation mode ensures that the system still has enough relay cache blocks available under high load, avoiding task blocking caused by dynamic allocation failure. The management of the relay cache blocks is simpler, eliminating the need for frequent allocation and release.

[0036] In another implementation, a dynamic allocation mode is used: the relay accelerator pre-allocates a memory pool, which includes K relay cache blocks of the same size; when the relay accelerator receives a video memory copy operation request for the k-th cache block of the i-th buffer of the source accelerator, the relay accelerator dynamically allocates a relay cache block for temporary data storage. After the video memory copy operation request task is completed, the cache block is released back to the memory pool. The dynamic allocation mode can allocate cache blocks on demand, avoiding memory waste.

[0037] S520, within the same clock cycle, when the data corresponding to the k-th cache block of the i-th buffer is in R i During the first path transmission, the data corresponding to the (k-1)th buffer block of the i-th buffer is in R. i The second path is transmitted in parallel; where k ranges from 1 to K.

[0038] Among them, R i The purpose of splitting the corresponding buffer into K buffer blocks is to make R iData transmitted on the first and second paths can be transmitted in parallel, improving transmission efficiency. That is, for data in the k-th buffer block of the i-th buffer, this data in R... i The data is transmitted serially in the first and second paths. However, for different buffer blocks in the i-th buffer, the data is transmitted serially in R. i Data is transmitted in parallel through the first and second paths. For different buffer blocks of the i-th buffer, once the first path has completed transmitting a portion of data and handed it over to the relay accelerator for processing, the first path can immediately begin transmitting the next portion of data without waiting for the second path to complete. In other words, the transmissions of the first and second paths can overlap, reducing waiting time. The relay path is always busy, improving transmission efficiency and throughput.

[0039] In one implementation, when relaying via a relay path, the source accelerator initiates a first memory copy operation request, requesting the data of the k-th cache block of the i-th buffer to the relay cache block of the relay node; the relay accelerator initiates a second memory copy operation request, requesting the data to be transferred from the relay cache block of the relay node to the destination accelerator.

[0040] In one implementation, after the second memory copy operation request for the (k-2)th cache block of the i-th buffer of the source accelerator is completed, the first memory copy operation request for the k-th cache block of the i-th buffer begins, and the intermediate cache block released by the (k-2)th cache block of the i-th buffer is reused. That is, for the i-th buffer, the first memory copy operation request for the k-th cache block depends on the second memory copy operation request for the (k-2)th cache block, thus ensuring sufficient parallelism. The reuse of the intermediate cache block reused by the (k-2)th cache block of the i-th buffer by the k-th cache block improves resource utilization.

[0041] In one embodiment, the switch is interconnected with each accelerator in the communication system. Each accelerator's relay path also includes a relay path with the switch as the relay node, and the relay paths provided by the switch can further increase the throughput and transmission bandwidth of a single accelerator. Other interconnection topologies between the switch and accelerators in the communication system, and their relay paths, also fall within the scope of this invention.

[0042] In one embodiment, the communication system further includes a switch, which acts as a relay node to relay data via a relay path provided by the switch. The relay path provided by the switch, together with other relay paths, splits video memory according to bandwidth ratio. The relay path of the switch is bound to a buffer, and the bound buffer is split into K cache blocks.

[0043] In summary, the video memory copying method provided in Embodiment 1 of this invention improves transmission efficiency by dividing the video memory of the source accelerator into multiple buffers, binding each buffer to a transmission path, and allowing all transmission paths to transmit in parallel. Furthermore, the buffer of the relay path is further divided into multiple cache blocks, allowing multiple cache blocks within the same buffer to be transmitted independently in the relay path. The first and second paths of the relay accelerator transmit in parallel, reducing waiting time and further improving transmission efficiency.

[0044] Embodiment 1 of the present invention also provides a non-transitory computer-readable storage medium, which can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0045] Embodiment 1 of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0046] For an interconnected topology with N accelerators, when the N accelerators are directly interconnected point-to-point, each accelerator has one direct path and at most N-1 relay paths via a single relay accelerator. However, if each accelerator uses N-1 relay paths, resource contention will occur. For example, consider two relay paths: the first relay path connects the first, second, and third accelerators, where the first accelerator is the source accelerator, the second is the relay accelerator, and the third is the destination accelerator; the second relay path connects the fourth, second, and third accelerators, where the fourth is the source accelerator, the second is the relay accelerator, and the third is the destination accelerator. In other words, the first and second relay paths share the same high-speed interconnect link from the second accelerator to the third accelerator. The total bandwidth of this high-speed interconnect link needs to be shared by these two paths, leading not only to a reduction in the bandwidth of each relay path but also to decreased throughput and increased latency. To address the aforementioned problems caused by the sharing of high-speed interconnect links, the present invention also provides Embodiments Two and Three.

[0047] Example 2

[0048] Embodiment 2 of the present invention also provides a communication system with a single ring communication path, the system comprising: N accelerators and a ring communication path.

[0049] Furthermore, each of the accelerators is directly connected to the other N-1 accelerators via a high-speed interconnect link, forming a point-to-point interconnect topology.

[0050] The high-speed interconnect link uses a bus that conforms to the MetaX Link, NVLink, Infinity Fabric, or UCIe standards.

[0051] Furthermore, the ring communication path includes N sets of network topology paths GR connected end-to-end, where GR = {GR0, GR1, ..., GR...} j ,…,GR N-1}, GR j For the j-th network topology path, j ranges from 0 to N-1; GR j Including the j-th accelerator P from the ring communication path j To the q-th accelerator P of the ring communication path q A direct route DR j There are M-1 transit paths TR; where q = j+1 when 0 ≤ j < N-1; q = 0 when j = N-1; and M < N.

[0052] In this ring communication path, communication occurs sequentially from beginning to end, forming a loop. Each accelerator in the loop can communicate directly with the next accelerator via a direct path or via a relay path. These direct and relay paths form a set of network topology paths. The direct paths and all relay paths in each set of network topology paths can transmit in parallel.

[0053] It should be noted that each transit route passes through a transit accelerator.

[0054] Among them, GR j The source accelerators for all M paths are P. j And the target accelerators are all P q That is, GR j The source accelerator for each transit path is P. j The destination accelerator for each transit path is P. q Since each accelerator has a high-speed interconnection link directly connecting it to other accelerators, all accelerators except the source accelerator and the destination accelerator can act as relay accelerators, resulting in a relay path formed by the source accelerator, relay accelerator and destination accelerator.

[0055] Furthermore, the DR j To directly connect P via a high-speed interconnect link j and P q The path that forms.

[0056] It should be noted that for each accelerator, if N-2 accelerators (excluding the source and destination accelerators) are directly used as relay accelerators to obtain N-2 relay paths for data transmission, the same high-speed interconnect link will be shared by multiple relay paths, leading to reduced bandwidth and throughput, and increased latency. To solve this problem, the embodiments of the present invention achieve the goal of each relay path using an independent high-speed interconnect link through the following topology.

[0057] Furthermore, the TR = {TR} j,1 TR j,2 ,…,TR j,t ,…,TR j,M-1}, TR j,t P connected sequentially via high-speed interconnect links j The t-th transfer accelerator and P q The formed GR j The t-th relay path, where t ranges from 1 to M-1; the t-th relay accelerator is the r-th accelerator P of the ring communication path. r When j+t+1<N, r=j+t+1; otherwise, r=(j+t+1)mod N; where M-1 satisfies: M-1=(N-2) / 2.

[0058] Here, mod is the modulo operation. (j+t+1)mod N is (j+t+1) modulo N. As an example, when N=4, j=3, t=2, j+t+1=6, 6mod 4 equals 2, that is, r=2.

[0059] In one implementation, N is equal to 4, 6, 8, 10, 12, 14, or 16. Alternatively, N = 24 or 32. Other values ​​of N also fall within the scope of protection of this invention.

[0060] In one implementation, when N=4, the point-to-point interconnection topology includes four accelerators: P0, P1, P2, and P3. For each accelerator, the number of transit paths is M-1 = (N-2) / 2, which is one path. For the network topology path GR0 in group 0, its direct path is the path composed of accelerators {P0, P1}; j=0, t=1, resulting in r=2, and the transit path is the path composed of accelerators {P0, P2, P1}. For GR1, its direct path is the path composed of accelerators {P1, P2}; j=0, t=2, resulting in r=3, and the transit path is the path composed of accelerators {P1, P3, P2}. For GR2, its direct path is the path composed of accelerators {P2, P3}; j=0, t=3, resulting in r=0, and the transit path is the path composed of accelerators {P2, P0, P3}. For GR3, its direct path is the path composed of accelerators {P3, P0}; j = 0, t = 4, resulting in r = 1, and the relay path is the path composed of accelerators {P3, P1, P0}. In the prior art, relaying occurs through each accelerator other than the source and destination accelerators. Each relay path may compete with another path for a high-speed interconnect link, and the bandwidth of each path competing for the same high-speed interconnect link is half the bandwidth of the high-speed interconnect link. However, in the embodiment of this invention, the bandwidth of each path is equal to the bandwidth of the high-speed interconnect link. Therefore, for a ring communication system with four accelerators, the bandwidth of the ring communication system provided by the embodiment of this invention is twice that of the prior art.

[0061] In another implementation, please refer to Figure 2 When N=8, the point-to-point interconnection topology includes 8 accelerators: P0, P1, P2, P3, P4, P5, P6, and P7. For each accelerator, the number of transit paths is M-1 = (N-2) / 2, which is 3 paths. For GR0, please refer to [link / reference]. Figure 2 ,exist Figure 2The direct path and three transit paths in GR0 are highlighted with bold black lines. The direct path in GR0 is the path composed of accelerators {P0, P1}; j = 0, t = 1, resulting in r = 2. The first transit path is the path composed of accelerators {P0, P2, P1}; j = 0, t = 2, resulting in r = 3. The second transit path is the path composed of accelerators {P0, P3, P1}; j = 0, t = 3, resulting in r = 4. The third transit path is the path composed of accelerators {P0, P4, P1}. Similarly, for GR1, its direct path is the path composed of accelerators {P1, P2}; j = 1, t = 1, resulting in r = 3. The first transit path is the path composed of accelerators {P1, P3, P2}; j = 1, t = 2, resulting in r = 4. The second transit path is the path composed of accelerators {P1, P4, P2}; j = 1, t = 3, resulting in r = 5. The third transit path is the path composed of accelerators {P1, P5, P2}. For GR2, its direct path is the path composed of accelerators {P2, P3}; the first transit path is the path composed of accelerators {P2, P4, P3}; the second transit path is the path composed of accelerators {P2, P5, P3}; and the third transit path is the path composed of accelerators {P2, P6, P3}. For GR3, the direct path is the path composed of accelerators {P3, P4}; the first transit path is the path composed of accelerators {P3, P5, P4}; the second transit path is the path composed of accelerators {P3, P6, P4}; and the third transit path is the path composed of accelerators {P3, P7, P4}. For GR4, the direct path is the path composed of accelerators {P4, P5}; the first transit path is the path composed of accelerators {P4, P6, P5}; the second transit path is the path composed of accelerators {P4, P7, P5}; and the third transit path is the path composed of accelerators {P4, P0, P5}. For GR5, the direct path is the path composed of accelerators {P5, P6}; the first transit path is the path composed of accelerators {P5, P7, P6}; the second transit path is the path composed of accelerators {P5, P0, P6}; and the third transit path is the path composed of accelerators {P5, P1, P6}. For GR6, the direct path is the path composed of accelerators {P6, P7}; the first transit path is the path composed of accelerators {P6, P0, P7}; the second transit path is the path composed of accelerators {P6, P1, P7}; and the third transit path is the path composed of accelerators {P6, P2, P7}. For GR7, the direct path is the path composed of accelerators {P7,P0}; the first transit path is the path composed of accelerators {P7,P1,P0}; the second transit path is the path composed of accelerators {P7,P2,P0}; and the third transit path is the path composed of accelerators {P7,P3,P0}.Similarly, in a ring communication system with four accelerators, in existing technologies, each relay path competes with the other three paths for a single high-speed interconnect link, and the bandwidth of each path competing for the same high-speed interconnect link is one-quarter of the high-speed interconnect link's bandwidth. However, in this embodiment of the invention, the bandwidth of each path is equal to the bandwidth of the high-speed interconnect link. Therefore, for a ring communication system with eight accelerators, the bandwidth of the ring communication system provided by this embodiment is four times higher than that of existing technologies.

[0062] By controlling the number of transit paths and configuring a reasonable topology, the bandwidth of this ring system can be increased by M times.

[0063] In one implementation, the accelerator's video memory includes M buffers, each buffer being bound to either a direct path or a relay path. It should be noted that a path is bound to only one buffer, and a buffer is bound to only one path; the two have a one-to-one mapping relationship. The definitions and splitting methods of video memory and buffers in Embodiment 1 are applicable to Embodiment 2 and will not be repeated here.

[0064] In one implementation, when the buffer is bound to a relay path, the buffer is split into multiple cache blocks. It should be noted that the video memory copying method provided in Embodiment 1 of this invention is applicable to Embodiment 2 of this invention, and will not be described again.

[0065] In one embodiment, the communication system further includes a switch interconnected with each accelerator in the communication system, and each accelerator's relay path also includes a relay path with the switch as the relay node. The relay paths provided by the switch can further increase the throughput and transmission bandwidth of a single accelerator. Other interconnection topologies between the switch and the accelerators in the communication system, and their relay paths, also fall within the scope of protection of this invention.

[0066] This invention provides a communication system with a single ring communication path. The system includes N accelerators and a ring communication path. Each accelerator in the ring communication path has M-1 = (N-2) / 2 relay paths, and each relay path has a relay accelerator P. r The following conditions must be met: when j+t+1 < N, r = j+t+1; otherwise, r = (j+t+1) mod N. In this communication system, each path independently occupies a high-speed interconnect link. Compared to existing technologies, the bandwidth of the communication system provided by this invention is increased by M times.

[0067] The ring communication system provided in Embodiment 2 of the present invention is for the case where there is only one ring topology. When there are multiple ring topologies in the system, the relay path is no longer limited to the accelerator in the current ring communication path, and the relay path is more complex. At this time, Embodiment 2 is no longer the optimal solution. Therefore, the present invention provides Embodiment 3.

[0068] Example 3

[0069] This invention provides a communication system with multiple ring communication paths, comprising: F groups of accelerators and F ring communication paths. The f-th ring communication path includes all accelerators in the f-th group, 1 ≤ f ≤ F, and F ≥ 2; wherein the x-th accelerator P in the f-th group... f x With the y-th accelerator P f y Connect, where y = x + 1 when 0 ≤ x < N - 1; y = 0 when x = N - 1, and N is the number of accelerators in each group. Where P f x As a source accelerator and P f y When communicating as a target accelerator, P f x Through a private set of network topology paths GR f x To communicate; where GR f x This includes one direct route and E cross-group transit routes, with each cross-group transit route using a transit accelerator in the (f+1)th group. The GR... f x The transfer accelerators for all cross-group transfer routes are different.

[0070] In one implementation, P f x Each accelerator in group f+1 is directly interconnected with each accelerator in group f+1 via a high-speed interconnect link. In other words, each accelerator in group f is directly interconnected with all accelerators in group f+1 via high-speed interconnect links. Each accelerator in group f can also be relayed through two accelerators in group f+1.

[0071] In one implementation, P f x It is directly interconnected with the other N-2 accelerators in group f via high-speed interconnect links.

[0072] In one implementation, F = 2, which constitutes a dual-loop communication path. In another implementation, F equals 3, 4, 5, or 6; other values ​​of F also fall within the scope of protection of this invention.

[0073] In one implementation, N is equal to 4, 6, or 8. Other values ​​of N also fall within the scope of protection of this invention.

[0074] In one implementation, N=4 and F=2. The communication system comprises two groups of four accelerators each, for a total of eight accelerators; and each group forms a ring communication path. The relay accelerator in the relay path corresponding to one accelerator in the current group is one accelerator in the other group.

[0075] In one implementation, all accelerators in the communication system are mounted on an OAM (OCP Accelerator Module) board and use the OAM standard.

[0076] In one implementation, please refer to Figure 4 and Figure 5 When N=4 and F=2, all accelerators in each of the two groups of accelerators in the communication system are directly interconnected via high-speed interconnect links, and each accelerator in each group is directly interconnected with all accelerators in the other group via high-speed interconnect links; the ring communication path of the first group is accelerator {P} 1 0, P 1 1, P 1 2, P 1 3) The first and last connected circular paths form a ring path; the second group of circular communication paths is the accelerator {P} 2 4, P 2 5, P 2 6, P 2 7} A circular path formed by connecting the beginning and end; for the first group of circular communication paths, P 1 0 to P 1 The two cross-group transfer paths of 1 are via P 2 6. The transit route and via P 2 7. The transit route. Similarly, P 1 1 to P 1 The two cross-group transfer paths for 2 are via P 2 7. The transit route and via P 2 4. The transit route. P 1 2 to P 1 The two cross-group transfer paths for 3 are via P 2 4. The transit route and via P 2 5. The transit route. P 1 3 to P 1The two cross-group transfer paths for 0 are via P 2 5. The transit route and via P 2 6. The transit path. To facilitate understanding of cross-group transit paths, in Figure 4 The diagram shows the ring communication path of the first group, P 1 0 to P 1 Group 1 has one direct path and two cross-group relay paths. For the ring communication path of Group 2, P 2 4 to P 2 The two cross-group transfer paths for 5 are via P 1 0 is the transit path and via P 1 1. The transit route. P 2 5 to P 2 The two cross-group transfer paths for 6 are via P 1 1. The transit route and via P 1 2. The transit route. P 2 6 to P 2 The two cross-group transfer paths for 7 are via P 1 2. The transit route and via P 1 3. The transit route. P 2 7 to P 2 The two cross-group transfer paths for 4 are via P 1 3. The transit route and via P 1 0 is the transit path. To facilitate understanding of cross-group transit paths, in Figure 5 The diagram shows the ring communication path in the second group, P 2 4 to P 2 The system features one direct path and two cross-group relay paths. It utilizes accelerators from other groups as relays, ensuring high-speed interconnect links do not conflict; and compared to the traditional 8-card fully interconnected solution, bandwidth is increased by 3 times.

[0077] In one embodiment, the communication system further includes a switch interconnected with each accelerator in the system, and the communication system also includes a relay path for each accelerator with the switch as the relay node. The relay path provided by the switch can further increase the throughput and transmission bandwidth of a single accelerator. Other interconnection topologies between the switch and the accelerators in the communication system, and their relay paths, also fall within the scope of this invention.

[0078] In one implementation, P f xEach cross-group relay path is allocated an independent buffer, which is divided into multiple cache blocks, and the cache block is the basic unit of transmission for each cross-group relay path. The video memory copying method provided in Embodiment 1 of this invention is applicable to Embodiment 3 of this invention, and will not be described again.

[0079] Embodiment 3 of the present invention provides a communication system with multiple ring communication paths. The communication system includes multiple ring communication paths. When an accelerator in each ring communication path transmits data to the next accelerator, it uses an accelerator from another group as a relay, thereby improving bandwidth and increasing the system throughput.

[0080] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0081] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A communication system with multiple ring communication paths, characterized in that, The system includes: F groups of accelerators G and F ring communication paths (Ring); The f-th ring communication path includes all accelerators in the f-th group, 1 ≤ f ≤ F, and F ≥ 2; where the x-th accelerator P in the f-th group... f x With the y-th accelerator P f y Connect the accelerators, where y = x + 1 when 0 ≤ x < N - 1, and y = 0 when x = N - 1, where N is the number of accelerators in each group. Where, when P f x As a source accelerator and P f y When communicating as a target accelerator, P f x Through a private set of network topology paths GR f x To communicate; where GR f x This includes one direct route and E cross-group transit routes, with each cross-group transit route using a transit accelerator in the (f+1)th group. The GR... f x The transfer accelerators for all cross-group transfer paths are different.

2. The system according to claim 1, characterized in that, P f x It is directly interconnected with each accelerator in group f+1 via a high-speed interconnect link.

3. The system according to claim 1, characterized in that, P f x It is directly interconnected with the other N-2 accelerators in group f via high-speed interconnect links.

4. The system according to claim 1, characterized in that, All accelerators in the communication system are mounted on OAM boards and use the OAM standard.

5. The system according to claim 1, characterized in that, The N=4 and F=2.

6. The system according to claim 5, characterized in that, The first group of ring communication paths in the communication system is the accelerator {P} 1 0, P 1 1, P 1 2, P 1 3) The first and last connected circular paths form a ring path; the second group of circular communication paths is the accelerator {P} 2 4, P 2 5, P 2 6, P 2 7) A circular path formed by connecting the beginning and end; For the first group of ring communication paths, P 1 0 to P 1 The two cross-group transfer paths of 1 are via P 2 6. The transit route and via P 2 7. The transit route; P 1 1 to P 1 The two cross-group transfer paths for 2 are via P 2 7. The transit route and via P 2 4. Transit route; P 1 2 to P 1 The two cross-group transfer paths for 3 are via P 2 4. The transit route and via P 2 5. Transit route; P 1 3 to P 1 The two cross-group transfer paths for 0 are via P 2 5. The transit route and via P 2 6. The transit route; For the second group of ring communication paths, P 2 4 to P 2 The two cross-group transfer paths for 5 are via P 1 0 is the transit path and via P 1 1. The transit route; P 2 5 to P 2 The two cross-group transfer paths for 6 are via P 1 1. The transit route and via P 1 2. The transit route; P 2 6 to P 2 The two cross-group transfer paths for 7 are via P 1 2. The transit route and via P 1 3. The transit route; P 2 7 to P 2 The two cross-group transfer paths for 4 are via P 1 3. The transit route and via P 1 0 is the transit path.

7. The system according to claim 5, characterized in that, The communication system also includes a switch interconnected with each accelerator in the communication system, and the communication system also includes a relay path for each accelerator with the switch as the relay node.

8. The system according to claim 1, characterized in that, For P f x Each cross-group transit path is allocated an independent buffer, which is divided into multiple cache blocks, which are the basic units of transmission for each cross-group transit path.

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