Dies, methods, and devices for die-to-die communication

Abstract

A die, method, and device for die-to-die communication are provided. A die includes a bus including a plurality of bus lanes, at least one functional block connected to the bus, an interface circuit configured to provide communication with another die through a plurality of die-to-die (D2D) lanes, and a routing circuit configured to perform lane mapping between the bus and the interface circuit based on a signal received through the bus.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2025-0057040, filed on April 30, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to die-to-die (D2D) communication, and more specifically, to dies, methods, and devices for D2D communication. Background Technology

[0004] Wafers manufactured using semiconductor processes can be diced into multiple dies, and these dies can be designed to have unique functions. Heterogeneous dies can be included in a single package to provide various functions, or homogeneous dies can be included in a single package for high-speed parallel processing. Furthermore, multiple dies can be included in a single package to prevent process yield degradation and improve cost efficiency. Dies included in a package can communicate with each other, and this communication between dies is routed through interconnects exposed on the outside of the die, thus potentially involving different requirements compared to intra-die communication between internal blocks. Summary of the Invention

[0005] Some aspects of this disclosure provide die-to-die (D2D) communication, as well as low-power D2D devices and methods of operation thereof, for example, providing dynamic channel distribution.

[0006] For example, some aspects of this disclosure provide dies, devices, and methods for providing D2D communication with high efficiency.

[0007] According to some implementations of this disclosure, a die is provided, comprising: a bus including a plurality of bus channels; at least one functional block connected to the bus; interface circuitry configured to provide communication with another die via a plurality of die-to-die (D2D) channels; and routing circuitry configured to perform channel mapping between the bus and the interface circuitry based on signals received from the bus.

[0008] According to some implementations of this disclosure, a method for die-to-die (D2D) communication is provided, the method comprising: mapping each of a plurality of bus channels included in a bus to at least one D2D channel of a plurality of D2D channels. The bus is connected to at least one functional block of a die. The mapping may include mapping a first bus channel of the plurality of bus channels to two or more D2D channels of the plurality of D2D channels.

[0009] According to some implementations of this disclosure, a device for die-to-die (D2D) communication is provided, comprising a first die and a second die communicating with each other via a plurality of D2D channels. The first die may include a first bus and a first routing circuit, the first bus including a plurality of first bus channels, the first routing circuit being configured to perform a first channel mapping between the plurality of first bus channels and the plurality of D2D channels. The second die may include a second bus and a second routing circuit, the second bus including a plurality of second bus channels, the second routing circuit being configured to perform a second channel mapping between the plurality of second bus channels and the plurality of D2D channels. The mapping between each of the plurality of first bus channels and one or more of the plurality of D2D channels is the same as the mapping between a corresponding second bus channel and one or more of the plurality of D2D channels. Attached Figure Description

[0010] The foregoing and other aspects, features and advantages provided in this disclosure will become apparent and more readily understood from the following description taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a block diagram illustrating an example of the device;

[0012] Figure 2 This is a block diagram showing an example of a die;

[0013] Figure 3 This is a block diagram illustrating an example of the device;

[0014] Figure 4 This is a block diagram illustrating an example of an interface circuit;

[0015] Figure 5A and Figure 5B This is a block diagram illustrating an example of a routing circuit;

[0016] Figure 6 This is a diagram illustrating an example of D2D communication;

[0017] Figure 7A and Figure 7B This is a block diagram illustrating an example of the device;

[0018] Figure 8 This is a block diagram illustrating an example of the device;

[0019] Figure 9 This is a flowchart illustrating an example of a method for D2D communication;

[0020] Figure 10 This is a flowchart illustrating an example of a method for D2D communication;

[0021] Figure 11A and Figure 11BThis is a flowchart illustrating an example of a method for D2D communication; and

[0022] Figure 12 This is a block diagram illustrating an example of a System-on-Chip (SoC). Detailed Implementation

[0023] Figure 1 This is a block diagram illustrating an example of device 10. (As shown...) Figure 1 As shown, device 10 may include a first die 11, a second die 12, a third die 13, a fourth die 14, a fifth die 15, and a sixth die 16. It should be noted that the number of dies included in device 10 is not limited to... Figure 1 The quantities shown are as indicated. In some implementations, device 10 may be a semiconductor package including a first die 11, a second die 12, a third die 13, a fourth die 14, a fifth die 15, and a sixth die 16.

[0024] A wafer manufactured using semiconductor manufacturing processes can be diced into multiple dies. Dies can be designed to have unique functions, and in some implementations, dies diced from a single wafer can provide the same function. Device 10 may include homogeneous or heterogeneous dies. In some implementations, the first die 11, the second die 12, the third die 13, the fourth die 14, the fifth die 15, and the sixth die 16 may be homogeneous and each provide the same function. In some implementations, two or more of the first die 11, the second die 12, the third die 13, the fourth die 14, the fifth die 15, and the sixth die 16 may be heterogeneous and each provide different functions. For example, the first die 11, the second die 12, the third die 13, the fourth die 14, the fifth die 15, and the sixth die 16 may include memory dies, input / output (I / O) dies, core dies, and / or sensor dies.

[0025] In device 10, each of the first die 11, the second die 12, the third die 13, the fourth die 14, the fifth die 15, and the sixth die 16 can communicate with another die. In some implementations, each of the first die 11, the second die 12, the third die 13, the fourth die 14, the fifth die 15, and the sixth die 16 can communicate directly with another die, and this communication method can be referred to as die-to-die (D2D) communication. For example, as... Figure 1 As shown, the first die 11 can communicate directly with the second die 12 and the fourth die 14, and the second die 12 can communicate directly with the first die 11, the third die 13 and the fifth die 15, and the third die 13 can communicate directly with the second die 12 and the sixth die 16. D2D communication can be based on any protocol, and in some implementations, two or more different protocols can be used for D2D communication in device 10.

[0026] Applications such as high-performance computing (HPC) and artificial intelligence (AI) that rely on parallel processing of complex computational tasks can leverage high D2D communication bandwidth, and therefore, multi-channel D2D communication can be employed. Multi-channel D2D communication can include multiple channels, and high bandwidth can be achieved through multiple channels. In this document, unless otherwise described, D2D communication can be assumed to be multi-channel D2D communication, and the channels included in D2D communication can be referred to as D2D channels.

[0027] D2D channels may include interconnects exposed on the outside of the die. In some implementations, first die 11, second die 12, third die 13, fourth die 14, fifth die 15, and sixth die 16 may be mounted on an interposer, and the D2D channel may include a pattern of the interposer. In some implementations, at least two of the first die 11, second die 12, third die 13, fourth die 14, fifth die 15, and sixth die 16 may be stacked, and the D2D channel may include leads for wire bonding, bumps for chip-to-chip bonding, or through-silicon vias (TSVs). Therefore, D2D channels may exhibit high resistance and / or capacitance compared to communication between blocks within the die (such as bus communication), which may result in relatively high power consumption.

[0028] As described below with reference to the accompanying drawings, the number of D2D channels can be dynamically adjusted. Therefore, the power consumption of D2D communication can be reduced, and the power consumption of device 10 can also be reduced. Furthermore, interleaved transactions can be sent and received via the D2D channels, which improves the efficiency of D2D communication. As the efficiency of D2D communication increases, idle periods can occur or be extended during D2D communication, which can therefore reduce power consumption.

[0029] Figure 2 This is a block diagram illustrating an example of die 20. (See above reference.) Figure 1 As described, die 20 can be included in a device along with another die and can communicate with the other die via a D2D channel. Figure 2 As shown, die 20 may include at least one functional block 21, bus 22, routing circuit 23, interface circuit 24 and power management circuit 25.

[0030] At least one functional block 21 may be connected to bus 22 and may provide the functionality of the design. For example, at least one functional block 21 may include at least one of a programmable functional block such as a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU), a reconfigurable functional block such as a field-programmable gate array (FPGA), and an intellectual property (IP) functional block such as a hardware accelerator that provides fixed functionality. The routing circuitry 23, described later, may also provide D2D communication with another die as a functional block connected to bus 22.

[0031] Bus 22 provides communication between functional blocks included in die 20 (e.g., between at least one functional block 21 and routing circuitry 23). Bus 22 may be based on an on-chip communication bus protocol, and at least one functional block 21 and routing circuitry 23 may communicate with each other via bus 22 based on the on-chip communication bus protocol. On-chip communication bus protocols may include, but are not limited to, Advanced Microcontroller Bus Architecture (AMBA), Wishbone, CoreConnect, IPBus, Avalon, HyperTransport (HT), Quick Path Interconnect (QPI), and TileLink.

[0032] Bus 22 may include multiple channels and may be referred to as a multi-channel bus. For example, bus 22 may be an Advanced Extensible Interface (AXI) bus, which is part of the AMBA specification, and an AXI bus may include read address channels, write address channels, read data channels, write data channels, and write response channels. In some implementations, the channels included in bus 22 may operate independently of each other. In this document, the channels included in bus 22 may be referred to as bus channels, and bus 22 may be referred to as the system bus.

[0033] Interface circuit 24 provides D2D communication between die 20 and another die. (See above reference.) Figure 1 As described, D2D communication may include multiple D2D channels, and interface circuitry 24 can provide D2D communication through these multiple D2D channels. To this end, interface circuitry 24 may include multiple components, each of which corresponds to a multiple D2D channel. See below for further details. Figure 4 An example describing interface circuit 24.

[0034] Routing circuit 23 can perform channel mapping between bus 22 and interface circuit 24. As described above, bus 22 can include multiple bus channels as a multi-channel bus, and D2D communication can also include multiple D2D channels. Routing circuit 23 can perform channel mapping between multiple bus channels and multiple D2D channels based on signals received from bus 22. For example, when at least one functional block 21 sends data to another die, routing circuit 23 can generate a transaction (hereinafter referred to as a D2D transaction) from the transaction received from bus 22 (hereinafter referred to as a bus transaction) and provide the D2D transaction to interface circuit 24 for interleaving. In addition, when at least one functional block 21 receives data from another die, routing circuit 23 can receive D2D transactions from interface circuit 24, assemble D2D transactions, and provide the assembled transactions (in other words, bus transactions) to at least one functional block 21 through bus 22. Therefore, the number of D2D channels can be dynamically adjusted, and the power consumption of D2D communication can be reduced. Furthermore, interleaved transactions can be sent and received through scheduled D2D channels, which can improve transmission speed and efficiency.

[0035] Power management circuit 25 can control the power supplied to the components of die 20. For example, power management circuit 25 can generate one or more internal supply voltages from the external supply voltage received from die 20 and supply these one or more internal supply voltages to the components of die 20, such as at least one functional block 21, routing circuit 23, and interface circuit 24. In some implementations, based on the channel mapping of routing circuit 23, at least one of the bus channel and / or D2D channel may be unused, and the sub-circuit corresponding to the unused channel may be powered down by power management circuit 25. For example, power management circuit 25 can block the supply voltage to power down the sub-circuit. To identify the powered-down sub-circuit, power management circuit 25 can communicate with routing circuit 23, as referred to later. Figure 5A and Figure 5B As stated above.

[0036] Figure 3 This is a block diagram illustrating an example of device 30. For example, Figure 3 The block diagram illustrates a device 30 comprising a first die 31 and a second die 32 communicating with each other via four D2D channels. In the following description, D2D communication comprising four D2D channels will be given primarily reference to the accompanying drawings; however, it should be noted that the number of D2D channels included in D2D communication is not limited thereto. Figure 3 In the description, it is assumed that the first die 31 sends data to the second die 32, and redundant details already provided in the foregoing description of the reference figure will be omitted.

[0037] refer to Figure 3The first die 31 and the second die 32 can communicate with each other through the first D2D channel D1 to the fourth D2D channel D4. For example, Figure 3 The diagram shows that all of the first D2D channels D1 through the fourth D2D channel D4 are used for communication between the first die 31 and the second die 32. The first die 31 may include a first bus BUS1, a first routing circuit RT1, and a first interface circuit IF1, and the second die 32 may include a second bus BUS2, a second routing circuit RT2, and a second interface circuit IF2. The first die 31 may also include at least one functional block connected to the first bus BUS1, and the second die 32 may also include at least one functional block connected to the second bus BUS2.

[0038] Each of the first bus BUS1 and the second bus BUS2 can be a multi-channel bus. For example, such as Figure 3 As illustrated, the first bus BUS1 may include first bus channels B11 to fourth bus channels B14, and the second bus BUS2 may also include first bus channels B21 to fourth bus channels B24. In some implementations, the number of bus channels included in the first bus BUS1 may be the same as the number of bus channels included in the second bus BUS2. In some implementations, the number of bus channels included in the first bus BUS1 may be equal to or less than the number of D2D channels.

[0039] The first interface circuit IF1 and the second interface circuit IF2 can send and receive D2D transactions through the first D2D channel D1 to the fourth D2D channel D4. (See later for reference.) Figure 4 Each of the first interface circuit IF1 and the second interface circuit IF2 may include four components corresponding to the first D2D channel D1 to the fourth D2D channel D4. For example... Figure 3 As shown, when signals are transmitted through the first D2D channel D1 to the fourth D2D channel D4, all four components in each of the first interface circuit IF1 and the second interface circuit IF2 are operational. (See later for reference.) Figure 8 When a signal is transmitted through some of the first D2D channels D1 to the fourth D2D channels D4, some of the four components included in each of the first interface circuit IF1 and the second interface circuit IF2 can be de-energized.

[0040] The first routing circuit RT1 can perform channel mapping between the first bus channels B11 to the fourth bus channel B14 and the first D2D channels D1 to the fourth D2D channels D4. For example, the first routing circuit RT1 can identify the channel mapping based on signals received through the first bus BUS1. The first routing circuit RT1 can map each of the first bus channels B11 to the fourth bus channel B14 to one of the first D2D channels D1 to the fourth D2D channels D4 based on the identified channel mapping. Therefore, transactions received through each of the first bus channels B11 to the fourth bus channel B14 can be sent to the second die 32 through at least one of the mapped first D2D channels D1 to the fourth D2D channels D4. Similarly, the second routing circuit RT2 can also perform channel mapping between the first bus channels B21 to the fourth bus channel B24 and the first D2D channels D1 to the fourth D2D channels D4. The channel mapping of the first routing circuit RT1 and the channel mapping of the second routing circuit RT2 can be the same. For example, the D2D channel of the first bus channel B11 mapped to the first bus channel B21 in the second die 32 can be mapped to the first bus channel B21 in the second die 32. Therefore, the function block of the first die 31 can detect that the function block of the second die 32 is connected to the first bus BUS1, and the function block of the second die 32 can detect that the function block of the first die 31 is connected to the second bus BUS2.

[0041] In some implementations, the first routing circuit RT1 can map one of the bus channels from the first bus channel B11 to the fourth bus channel B14 to two or more D2D channels from the first D2D channel D1 to the fourth D2D channel D4. For example, as Figure 3 As shown, the first routing circuit RT1 can map the first bus channel B11 to the first D2D channels D1 through D4. To this end, the first routing circuit RT1 can generate multiple D2D transactions from bus transactions received through the first bus channel B11 and provide these multiple D2D transactions to the first interface circuit IF1 for interleaved transmission through the first D2D channels D1 through D4 to the second die 32. Additionally, the second routing circuit RT2 can receive multiple D2D transactions from the second interface circuit IF2 through the first D2D channels D1 through D4 and generate bus transactions from these multiple D2D transactions to send the bus transactions through the first bus channel B21. Therefore, bus transactions received from the first bus channel B11 can be sent through the first D2D channels D1 through D4, and the transmission time can be shortened.

[0042] Figure 4 This is a block diagram illustrating an example of interface circuitry 40. For example, Figure 4An interface circuit 40 is shown that provides D2D communication including a first D2D channel D1 to a fourth D2D channel D4. (Refer to the above...) Figure 3 As described, the interface circuit 40 can be positioned between the D2D channel and the routing circuit. For example... Figure 4 As shown, the interface circuit 40 may include a first channel controller 41 to a fourth channel controller 44 and a first physical layer (PHY) circuit 45 to a fourth physical layer (PHY) circuit 48. In this document, each of the first channel controller 41 to the fourth channel controller 44 and each of the first PHY circuit 45 to the fourth PHY circuit 48 may be referred to as a sub-circuit of the interface circuit 40.

[0043] The first PHY circuit 45 through the fourth PHY circuit 48 can implement the PHY for D2D communication. For example, the PHY can correspond to the lowest layer in the Open Systems Interconnection (OSI) reference model and provide the physical means for transmitting and receiving signals. In some implementations, each of the first PHY circuit 45 through the fourth PHY circuit 48 can perform signal encoding, signal decoding, and channel equalization, and handle preambles for synchronization. Figure 4 As shown, the first PHY circuit 45 to the fourth PHY circuit 48 can correspond to the first D2D channel D1 to the fourth D2D channel D4.

[0044] The first channel controllers 41 to 44 can implement the upper layer of D2D communication. For example, the first channel controllers 41 to 44 can implement the upper layer of the PHY, such as the data link layer. The first channel controllers 41 to 44 can detect and correct errors that may occur in the PHY and implement protocols defined for establishing and terminating access. The first channel controllers 41 to 44 can process transactions provided from the routing circuit and provide the processed transactions to each of the first PHY circuits 45 to 48. Furthermore, the first channel controllers 41 to 44 can process transactions provided from the first PHY circuits 45 to 48 and provide the processed transactions to the routing circuit. Figure 4 As shown, the first channel controller 41 to the fourth channel controller 44 can correspond to the first D2D channel D1 to the fourth D2D channel D4.

[0045] In some implementations, the first D2D channels D1 to the fourth D2D channels D4 can be independent of each other. For example, the first channel controller 41 to the fourth channel controller 44 can implement the upper layer independently, and the first PHY circuit 45 to the fourth PHY circuit 48 can also implement the PHY independently. Therefore, the channel controllers and PHY circuits corresponding to unused D2D channels among the first D2D channels D1 to the fourth D2D channels D4 can be powered down, and the power consumption of the interface circuit 40 can be reduced. As described below with reference to the accompanying drawings, the D2D channels can be scheduled by the routing circuit, and when the channel controllers and PHY circuits corresponding to unused D2D channels are powered down, the power consumption of the interface circuit 40, the die including the interface circuit 40, and the devices including the die can be reduced.

[0046] Figure 5A and Figure 5B This is a block diagram illustrating an example of a routing circuit. For example, Figure 5A The block diagram shows a routing circuit 50a including elements for sending transactions, and Figure 5B The block diagram shows a routing circuit 50b including elements for receiving transactions. In some implementations, Figure 5A and Figure 5B The components shown may be included in a routing circuit. As described above with reference to the accompanying drawings, routing circuits 50a and 50b may be positioned between the system bus and the interface circuitry, and may perform channel mapping between the bus channel and the D2D channel. (The following will omit...) Figure 5A and Figure 5B Redundant details in the description.

[0047] refer to Figure 5A The routing circuit 50a may include a first tagger TG1, a second tagger TG2, a third tagger TG3, and a fourth tagger TG4, a distributor 51, and at least one register 53. The at least one register 53 may store channel mapping information. For example, a function block included in the die along with the routing circuit 50a may provide channel mapping information to the routing circuit 50a via a bus. The routing circuit 50a may store the channel mapping information in the at least one register 53 based on signals received via the bus. In some implementations, the at least one register 53 may be configured during device boot of the device including the routing circuit 50a. In some implementations, the at least one register 53 may be configured by a function block during device operation. Therefore, the channel mapping can be dynamically and optimally configured depending on the die's communication state. In some implementations, reconfiguration of the channel mapping by configuring the at least one register 53 may be performed during idle periods of the channel.

[0048] Each of the first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can receive bus transactions from the first bus channel, the second bus channel, the third bus channel, and the fourth bus channel. The first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can mark bus transactions using identification information of the bus channels. For example, the first marker TG1 can mark the first identification information of the first bus channel, the second marker TG2 can mark the second identification information of the second bus channel, the third marker TG3 can mark the third identification information of the third bus channel, and the fourth marker TG4 can mark the fourth identification information of the fourth bus channel. As described later, the marked identification information of the bus channels can be used to identify the bus channels on the receiving side. Each of the first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can provide marked bus transactions to the distributor 51. In some implementations, each of the first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can obtain channel identification information based on the value of at least one register 53; therefore, the channel identification information can be changed through the configuration of at least one register 53. In some implementations, the first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can track transactions. For example, the first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can send transactions and receive responses received through the D2D channel from the allocator 51. The first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4 can identify whether the transmission of a transaction has ended based on the response.

[0049] Distributor 51 can receive bus transactions from the first marker TG1, the second marker TG2, the third marker TG3, and the fourth marker TG4, and generate D2D transactions by interleaving the bus transactions based on channel mapping information. For example, distributor 51 can access at least one register 53 and identify the channel mapping information stored in at least one register 53. Distributor 51 can identify at least one D2D channel corresponding to a bus channel based on the channel mapping information, and provide transactions interleaved from bus transactions received through the bus channel to the interface circuitry for transmission through at least one identified D2D channel. In some implementations, distributor 51 can mark the interleaved transactions with identification information of the bus channel.

[0050] In some implementations, allocator 51 may interleave bus transactions based on size. For example, allocator 51 may generate transactions of a predetermined size from bus transactions and perform interleaving to send transactions alternately through identified D2D channels. In some implementations, allocator 51 may identify the size of a transaction based on a value stored in at least one register 53, and therefore, the unit of interleaving (in other words, the transaction size) may be adjusted by configuring at least one register 53. In some implementations, allocator 51 may generate transactions of a predetermined size based on the address used for the bus transaction. For example, when performing interleaving in 1KB units, allocator 51 may generate transactions in address intervals of 0x400. For example, allocator 51 may generate transactions to be interleaved based on the eleventh bit from the least significant bit (LSB) of the address and at least one or more additional higher-order bits. For example, when transactions are interleaved across four channels in 1KB units, the transaction may be assigned to one of the four channels based on a 2-bit value from the address (in other words, the values ​​of the twelfth and eleventh bits).

[0051] In some implementations, routing circuit 50a can be used with power management circuitry (e.g., Figure 2 The power management circuit 25) communicates. See later for reference. Figure 8 As described, depending on the channel mapping, at least one of the D2D channels may be unused. A sub-circuit corresponding to at least one unused D2D channel in the routing circuit 50a and / or interface circuit can be de-energized. To this end, the routing circuit 50a may provide information about the de-energized sub-circuit to the power management circuit, and the power management circuit may de-energize the sub-circuit by blocking the supply voltage to the sub-circuit.

[0052] refer to Figure 5B The routing circuit 50b may include an assembler 52, at least one register 53, and first remappers DTG1 to fourth remappers DTG4. First remappers DTG1 to fourth remappers DTG4 can receive D2D transactions from the interface circuit from the first D2D channel to the fourth D2D channel. As described above, a D2D transaction may include identification information of the bus channel marked in the die on the transmitting side. First remappers DTG1 to fourth remappers DTG4 can extract the identification information of the bus channel included in the D2D transaction and provide the extracted identification information to the assembler 52. A D2D transaction may be a transaction interleaved with bus transactions from the die on the transmitting side.

[0053] Assembler 52 can receive D2D transactions and bus channel identification information from the first mapper DTG1 to the fourth mapper DTG4. Assembler 52 can assemble D2D transactions corresponding to the identification information of the same bus channel and generate assembled transactions, in other words, bus transactions. Assembler 52 can send bus transactions through the bus channels corresponding to the identification information.

[0054] In some implementations, at least one register 53 may store bus channel mapping information. For example, the first-level mapper DTG1 to the fourth-level mapper DTG4 may identify the bus channel mapping information by accessing at least one register 53, and identify the receiving-side bus channel corresponding to the identification information of the transmitting-side bus channel based on the bus channel mapping information, the identification information of the transmitting-side bus channel being obtained from D2D transactions received through the first to fourth D2D channels. The first-level mapper DTG1 to the fourth-level mapper DTG4 may provide the identified receiving-side bus channel information along with the transaction to the assembler 52. As another example, the assembler 52 may identify the bus channel mapping information by accessing at least one register 53. For example, at least one register 53 may store mapping information between the transmitting-side bus channel and the receiving-side bus channel. Assembler 52 can identify the bus channel corresponding to the identification information of the bus channel on the transmitting side provided by the first mapper DTG1 to the fourth mapper DTG4 based on the bus channel mapping information stored in at least one register 53, assemble D2D transactions corresponding to the identified bus channel on the receiving side, and send the assembled transactions (in other words, bus transactions) through the bus channel on the receiving side.

[0055] Figure 6 This is a diagram illustrating an example of D2D communication. For example, Figure 6 Examples of bus transactions and D2D transactions in D2D communication are shown. In some implementations, Figure 6 D2D communication can be Figure 3 The following is executed in device 30. Figure 3 right Figure 6 Please provide an explanation.

[0056] refer to Figure 6Bus transactions BT can occur. For example, bus transactions BT can be generated by a function block connected to the first bus BUS1, and the first routing circuit RT1 of the first die 31 can receive bus transactions BT through the first bus channel B11. The first routing circuit RT1 can identify that the first bus channel B11 is mapped to the first D2D channels D1 to the fourth D2D channels D4 based on channel mapping information. Therefore, the first routing circuit RT1 can generate first D2D transactions DT1 to the fourth D2D transactions DT4 from the bus transactions BT. In some implementations, the first D2D transactions DT1 to the fourth D2D transactions DT4 can have the same size, and the first routing circuit RT1 can additionally generate D2D transactions according to the size of the bus transactions BT. Figure 6 As shown, each of the first D2D transactions DT1 to the fourth D2D transactions DT4 may include identification information ID representing the first bus channel B11. The first routing circuit RT1 may provide the first D2D transactions DT1 to the fourth D2D transactions DT4 to the first interface circuit IF1 for independent transmission via the first D2D channels D1 to the fourth D2D channels D4.

[0057] The second routing circuit RT2 of the second die 32 can receive first D2D transactions DT1 to fourth D2D transactions DT4 received through the second interface circuit IF2 via the first D2D channel D1 to the fourth D2D channel D4. The second routing circuit RT2 can extract identification information ID from the first D2D transactions DT1 to the fourth D2D transactions DT4 and identify the first bus channel B21 based on this identification information ID. The second routing circuit RT2 can assemble the first D2D transactions DT1 to the fourth D2D transactions DT4 corresponding to the first bus channel B21 and generate a bus transaction BT'. The second routing circuit RT2 can send the bus transaction BT' through the first bus channel B21 based on the identification information ID.

[0058] Figure 7A and Figure 7B This is a block diagram illustrating an example of a device. For example, Figure 7A The block diagram shows device 70a, where the system bus includes a bus channel, and Figure 7B The block diagram shows device 70b, where the system bus includes two bus channels. In some implementations, such as... Figure 7A and Figure 7B As shown, the number of bus channels can be less than the number of D2D channels. As described later, bus transactions sent and received via a small number of bus channels can be sent and received via a larger number of D2D channels, which can therefore increase bandwidth. Figure 7A and Figure 7BIn the description, it is assumed that the first die 71 sends data to the second die 72 based on D2D communication, and redundant details already provided in the preceding description will be omitted.

[0059] refer to Figure 7A Device 70a may include a first die 71 and a second die 72 that communicate with each other via a first D2D channel D1 to a fourth D2D channel D4. The first die 71 may include a first bus BUS1, a first routing circuit RT1, and a first interface circuit IF1, and the second die 72 may include a second bus BUS2, a second routing circuit RT2, and a second interface circuit IF2. The first bus BUS1 may include a first bus channel B11, and the second bus BUS2 may also include a first bus channel B21.

[0060] The first routing circuit RT1 can receive bus transactions through the first bus channel B11. The first routing circuit RT1 can generate D2D transactions from the bus transactions and identify the first D2D channels D1 to the fourth D2D channels D4 based on channel mapping information. The first routing circuit RT1 can provide the D2D transactions to the first interface circuit IF1 for interleaving and transmission through the first D2D channels D1 to the fourth D2D channels D4. In some implementations, such as... Figure 7A As shown, when the number of bus channels included in the first bus BUS1 is one, the first routing circuit RT1 may omit the identification information marking the first bus channel B11. The first interface circuit IF1 can send interleaved D2D transactions to the second die 72 through the first D2D channel D1 to the fourth D2D channel D4.

[0061] The second interface circuit IF2 of the second die 72 can receive D2D transactions through the first D2D channel D1 to the fourth D2D channel D4. The second routing circuit RT2 can receive D2D transactions from the second interface circuit IF2 and identify the first bus channel B21 based on the identification information included in the D2D transactions. In some implementations, such as Figure 7A As shown, when the number of bus channels included in the second bus BUS2 is one, the second routing circuit RT2 can omit the extraction and identification of identification information.

[0062] refer to Figure 7BDevice 70b may include a first die 71 and a second die 72 that communicate with each other via a first D2D channel D1 to a fourth D2D channel D4. The first die 71 may include a first bus BUS1, a first routing circuit RT1, and a first interface circuit IF1, and the second die 72 may include a second bus BUS2, a second routing circuit RT2, and a second interface circuit IF2. The first bus BUS1 may include a first bus channel B11 and a second bus channel B12, and the second bus BUS2 may also include a first bus channel B21 and a second bus channel B22.

[0063] The first routing circuit RT1 can receive bus transactions through the first bus channel B11 and the second bus channel B12. The first routing circuit RT1 can generate D2D transactions from the bus transactions received through the first bus channel B11 and the second bus channel B12. The first routing circuit RT1 can use the first identification information of the first bus channel B11 to mark the D2D transactions generated from the bus transactions received through the first bus channel B11, and simultaneously use the second identification information of the second bus channel B12 to mark the D2D transactions generated from the bus transactions received through the second bus channel B12. The first routing circuit RT1 can identify the first D2D channel D1 to the fourth D2D channel D4 based on channel mapping information, and the first routing circuit RT1 can provide D2D transactions to the first interface circuit IF1 for interleaving and transmission through the first D2D channel D1 to the fourth D2D channel D4. The first interface circuit IF1 can send the interleaved D2D transactions to the second die 72 through the first D2D channel D1 to the fourth D2D channel D4.

[0064] The second interface circuit IF2 of the second die 72 can receive interleaved D2D transactions through the first D2D channel D1 to the fourth D2D channel D4. The second routing circuit RT2 can receive D2D transactions from the second interface circuit IF2 and identify the first bus channel B21 or the second bus channel B22 based on the identification information included in the D2D transactions. The second routing circuit RT2 can generate a first bus transaction by assembling D2D transactions corresponding to the first bus channel B21 and send the first bus transaction through the first bus channel B21, and simultaneously generate a second bus transaction by assembling D2D transactions corresponding to the second bus channel B22 and send the second bus transaction through the second bus channel B22.

[0065] Figure 8 This is a block diagram illustrating an example of device 80. For example, Figure 8 This illustrates an example where only some of the multiple D2D channels are used for D2D communication. Figure 8In the description, it is assumed that the first die 81 sends data to the second die 82 based on D2D communication, and redundant details already provided in the foregoing description of the reference figure will be omitted.

[0066] refer to Figure 8 Device 80 may include a first die 81 and a second die 82 that communicate with each other via a first D2D channel D1 to a fourth D2D channel D4. The first die 81 may include a first bus BUS1, a first routing circuit RT1, and a first interface circuit IF1, and the second die 82 may include a second bus BUS2, a second routing circuit RT2, and a second interface circuit IF2. The first bus BUS1 may include a first bus channel B11 and a second bus channel B12, and the second bus BUS2 may also include a first bus channel B21 and a second bus channel B22.

[0067] like Figure 8 As shown, each of the first bus channel B11 and the second bus channel B12 of the first bus BUS1 can be mapped to the third D2D channel D3 and the fourth D2D channel D4, and each of the first bus channel B21 and the second bus channel B22 of the second bus BUS2 can also be mapped to the third D2D channel D3 and the fourth D2D channel D4. Therefore, as Figure 8 As shown, the first D2D channel D1 and the second D2D channel D2 may not be used in D2D communication.

[0068] The first routing circuit RT1 can provide control signals to the first interface circuit IF1 to power off the sub-circuits of the first interface circuit IF1 based on channel mapping information. For example, as Figure 8 As shown, when the first D2D channel D1 and the second D2D channel D2 are identified as unused based on the channel mapping information, the first routing circuit RT1 can provide a control signal to the first interface circuit IF1 to allow the sub-circuits corresponding to the first D2D channel D1 and the second D2D channel D2 (e.g., Figure 4 The first channel controller 41, the second channel controller 42, the first PHY circuit 45, and the second PHY circuit 46 are de-energized. The first interface circuit IF1 can de-energize the sub-circuits corresponding to the first D2D channel D1 and the second D2D channel D2 based on control signals received from the first routing circuit RT1. The second routing circuit RT2 can also provide control signals to the second interface circuit IF2, and the second interface circuit IF2 can de-energize the sub-circuits corresponding to the first D2D channel D1 and the second D2D channel D2. Therefore, the power consumption of device 80 can be reduced.

[0069] Figure 9 This is a flowchart illustrating an example of a method for D2D communication. (Example) Figure 9 As shown, the method for D2D communication may include multiple operations S100 to S300. In some implementations, Figure 9 The method can be derived from Figure 2 The die 20 or any die described herein shall be used for execution. See below for reference. Figure 2 right Figure 9 Please provide an explanation.

[0070] refer to Figure 9 Registers can be configured in operation S100. For example, routing circuit 23 may include one or more registers. At least one functional block 21 can send signals to routing circuit 23 via bus 22, and routing circuit 23 can set one or more registers based on the signals received via bus 22. At least one configured register can store channel mapping information. In some implementations, one or more registers can store information about the interleaving unit, in other words, information about the size of the transaction. In some implementations, routing circuit 23 can receive signals from functional blocks that control channel mapping via a dedicated channel, without via bus 22, and can set one or more registers based on the received signals.

[0071] In operation S200, each of the multiple bus channels can be mapped to at least one D2D channel. For example, routing circuit 23 can map a bus channel to at least one D2D channel based on channel mapping information stored in registers configured in operation S100. (See later...) Figure 10 Describe an example of operation S200.

[0072] In operation S300, D2D communication can be performed. For example, die 20 can perform D2D communication with another die via a D2D channel. D2D transactions sent via the D2D channel can originate from bus transactions sent via a bus channel, which is mapped to the D2D channel in operation S200. Therefore, channels can be dynamically mapped, thereby improving the performance and efficiency of D2D communication.

[0073] Figure 10 This is a flowchart illustrating an example of a method for D2D communication. For example, Figure 10 The flowchart shows Figure 9 Operation S200. As mentioned above. Figure 9 As described in Figure 10 In operation S200', each of the multiple bus channels can be mapped to at least one D2D channel. For example... Figure 10 As shown, operation S200' may include multiple operations S210 to S230. In some implementations, operation S200' can be... Figure 8 It may be executed in device 80, or in another of the aforementioned devices. See below for reference. Figure 8 right Figure 10 Please provide an explanation.

[0074] refer to Figure 10 Channel mapping information can be identified during operation S210. For example, the first routing circuit RT1 may include one or more registers, and channel mapping information is identified based on the values ​​stored in the one or more registers. (See above reference...) Figure 9 As described, one or more registers can be configured by a function block outside the first routing circuit RT1.

[0075] In operation S220, one bus channel can be mapped to two or more D2D channels. For example, the first routing circuit RT1 can identify, based on the channel mapping information identified in operation S210, that a bus channel included in the first bus BUS1 (e.g., first bus channel B11) is mapped to the third D2D channel D3 and the fourth D2D channel D4. Additionally, the first routing circuit RT1 can identify, based on the channel mapping information, that a second bus channel B12 is mapped to the third D2D channel D3 and the fourth D2D channel D4. (See later...) Figure 11A and Figure 11B Describe an example of operation S220.

[0076] In operation S230, at least one sub-circuit can be de-energized. For example, unused D2D channels can be identified based on channel mapping information identified in operation S210. The first interface circuit IF1 can de-energize the sub-circuit corresponding to the first D2D channel D1 and the second D2D channel D2 based on the control signal of the first routing circuit RT1. Furthermore, the second interface circuit IF2 can de-energize the sub-circuit corresponding to the first D2D channel D1 and the second D2D channel D2 based on the control of the second routing circuit RT2.

[0077] Figure 11A and Figure 11B This is a flowchart illustrating an example of a method for D2D communication. For example, Figure 11A and Figure 11B The flowchart can be shown Figure 10 Operation S220. See above for reference. Figure 10 As mentioned above, in Figure 11A Operation of S220a and Figure 11B In operation S220b, one bus channel can be mapped to two or more D2D channels. In some implementations, Figure 11A Operation 220a can be performed by Figure 3 The first routing circuit RT1 is executed, and Figure 11B The operation of S220b can be performed by Figure 3 The second routing circuit RT2 is executed. See below for reference. Figure 3 right Figure 11A and Figure 11B Describe it.

[0078] refer to Figure 11A Operation S220a may include multiple operations S221 to S223. In operation S221, multiple D2D transactions can be generated from bus transactions. For example, the first routing circuit RT1 can generate multiple D2D transactions to send bus transactions received through each of the first bus channels B11 to the fourth bus channel B14 via the first D2D channel D1 to the fourth D2D channel D4. In some implementations, the multiple D2D transactions may have the same size.

[0079] In operation S222, multiple D2D transactions can be marked using identification information of the bus channel. For example, the first routing circuit RT1 can mark multiple D2D transactions using identification information corresponding to the bus channel receiving the bus transaction, which is generated from the bus transaction in operation S221. Therefore, a D2D transaction can include information about the bus channel corresponding to itself among the first bus channel B11 to the fourth bus channel B14.

[0080] In operation S223, multiple D2D transactions can be provided to two or more D2D channels. For example, the first routing circuit RT1 can provide multiple D2D transactions to the first interface circuit IF1 to allow multiple D2D transactions marked with identification information in operation S222 to be interleaved and sent through the first D2D channel D1 to the fourth D2D channel D4.

[0081] refer to Figure 11B Identification information can be extracted from multiple D2D transactions in operation S224. For example, the second routing circuit RT2 can receive multiple D2D transactions from the second interface circuit IF2 and extract the identification information included in the multiple D2D transactions. As described above, the identification information can be marked by the first routing circuit RT1 and can represent the bus channel corresponding to the D2D transaction.

[0082] In operation S225, a bus transaction can be generated from multiple D2D transactions. For example, the second routing circuit RT2 can generate a bus transaction from multiple D2D transactions corresponding to the same bus channel based on the identification information extracted in operation S224.

[0083] In operation S226, the bus channel can be identified based on the identification information, and in operation S227, the bus transaction can be provided to the bus channel. For example, the second routing circuit RT2 can identify one of the first bus channel B21 to the fourth bus channel B24 based on the identification information extracted in operation S224. The second routing circuit RT2 can provide the bus transaction generated in operation S225 to the bus channel identified in operation S226.

[0084] Figure 12 This is a block diagram illustrating an example of a System-on-a-Chip (SoC). SoC 120 can be a semiconductor device that implements complex blocks, such as intellectual property (IP) cores that perform various functions on a single chip. SoC 120 may include two or more dies performing the D2D communication described in the above reference diagram. Reference Figure 12 The SoC 120 may be a functional block and may include a modem 122, a display controller 123, a memory 124, an external memory controller 125, a central processing unit (CPU) 126, a transaction unit 127, a power management integrated circuit (PMIC) 128, and a graphics processing unit (GPU) 129.

[0085] Functional blocks of the SoC 120 can be included in a single die along with another functional block, or implemented independently in a single die. When functional blocks are distributed across two or more dies, the functional blocks can have an optimal structure and can improve the yield of the SoC 120. Functional blocks included in a single die can communicate via the system bus, and simultaneously, functional blocks included in different dies can perform D2D communication as described above.

[0086] The CPU 126, which controls the operation of SoC 120 at the top level, can also control the operation of other functional blocks 122 to 129. The modem 122 can demodulate signals received from outside SoC 120 or modulate signals generated internally by SoC 120 for transmission to the outside. The external memory controller 125 can control the sending and receiving of data from external memory devices connected to SoC 120. For example, under the control of the external memory controller 125, programs and / or data stored in external memory devices can be provided to the CPU 126 or GPU 129. The GPU 129 can execute program instructions related to graphics processing. The GPU 129 can receive graphics data through the external memory controller 125 and send the graphics data processed by the GPU 129 to the outside of SoC 120 through the external memory controller 125. The transaction unit 127 can monitor data transactions for each functional block, and the PMIC 128 can control the power supplied to each functional block based on the control of the transaction unit 127. Display controller 123 can send data generated within SoC 120 to a display (or display device) external to SoC 120. Memory 124 may include non-volatile memory such as electrically erasable programmable read-only memory (EEPROM) or flash memory, or volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0087] While this disclosure includes numerous specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in this disclosure in the context of a single implementation may also be implemented in combination within that single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0088] While various examples have been described in detail above, the scope of this disclosure is not limited thereto, and it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure. Furthermore, the foregoing implementations can be implemented with the removal of some components, and each example can be implemented in combination with one another.

Claims

1. A die, the die comprising: A bus, which includes multiple bus channels; At least one functional block is connected to the bus; An interface circuit is configured to provide communication with another die via multiple die-to-die D2D channels; and A routing circuit is configured to perform channel mapping between the plurality of bus channels and the plurality of D2D channels based on signals received from the bus.

2. The die according to claim 1, wherein, The routing circuit is configured to map a first bus channel among the plurality of bus channels to two or more D2D channels among the plurality of D2D channels.

3. The die according to claim 2, wherein, The routing circuit is configured as follows: Generate multiple first D2D transactions from bus transactions received from the first bus channel; and The plurality of first D2D transactions are provided to the two or more D2D channels.

4. The die according to claim 3, wherein, The routing circuit is configured to generate the plurality of first D2D transactions based on the address used for the bus transaction.

5. The die according to claim 3, wherein, The routing circuit is configured to mark the plurality of first D2D transactions using first identification information that identifies the first bus channel.

6. The die according to claim 3, wherein, The routing circuit includes registers configured based on the signal, and The routing circuit is configured to determine the size of each of the plurality of first D2D transactions based on the value stored in the register.

7. The die according to claim 3, wherein, The routing circuit is configured as follows: Map the second bus channel among the plurality of bus channels to the two or more D2D channels; Multiple second D2D transactions are generated from the second bus transactions received through the second bus channel; and Provide the plurality of second D2D transactions to the two or more D2D channels.

8. The die according to claim 2, wherein, The routing circuit is configured as follows: A first bus transaction is generated from a plurality of first D2D transactions received from the two or more D2D channels; and Provide the first bus transaction to the first bus channel.

9. The die according to claim 8, wherein, The routing circuit is configured as follows: Extract first identification information from the plurality of first D2D transactions; and The first bus channel is identified based on the first identification information.

10. The die according to claim 2, wherein, The interface circuit is configured to de-energize at least one sub-circuit of the interface circuit based on the mapping from the first bus channel to the two or more D2D channels. The at least one sub-circuit corresponds to at least one D2D channel that is excluded from the two or more D2D channels and included in the plurality of D2D channels.

11. The die according to claim 1, wherein, The routing circuit includes a register configured based on the signal and is configured to perform the channel mapping based on the value stored in the register.

12. A method for die-to-die D2D communication, the method comprising: Each of the multiple bus channels included in the bus is mapped to at least one of the multiple D2D channels, wherein the bus is connected to at least one functional block of the die. The mapping includes mapping a first bus channel among the plurality of bus channels to two or more D2D channels among the plurality of D2D channels.

13. The method according to claim 12, wherein, Mapping the first bus channel to the two or more D2D channels includes: Generate multiple first D2D transactions from bus transactions sent via the first bus channel; and The plurality of first D2D transactions are provided to the two or more D2D channels.

14. The method according to claim 13, wherein, Mapping the first bus channel to the two or more D2D channels includes marking the plurality of first D2D transactions using first identification information that identifies the first bus channel.

15. The method according to claim 13, wherein, Mapping each bus channel to at least one of the plurality of D2D channels includes mapping a second bus channel of the plurality of bus channels to the two or more D2D channels, and Mapping the second bus channel to the two or more D2D channels includes: Multiple second D2D transactions are generated from bus transactions sent via the second bus channel; and Provide the plurality of second D2D transactions to the two or more D2D channels.

16. The method according to claim 12, wherein, Mapping the first bus channel to the two or more D2D channels includes: A first bus transaction is generated from a plurality of first D2D transactions received from the two or more D2D channels; and Provide the first bus transaction to the first bus channel.

17. The method according to claim 16, wherein, Mapping the first bus channel to the two or more D2D channels includes: Extract first identification information from the plurality of first D2D transactions; and The first bus channel is identified based on the first identification information.

18. The method of claim 12, further comprising, based on the mapping from the first bus channel to the two or more D2D channels, de-energizing at least one sub-circuit of the interface circuit, wherein, The at least one sub-circuit corresponds to at least one D2D channel that is excluded from the two or more D2D channels and included in the plurality of D2D channels.

19. The method of claim 12, further comprising configuring a register based on signals transmitted via the bus, and in, Mapping each bus channel to at least one of the plurality of D2D channels includes identifying the mapping information based on values ​​stored in the register.

20. A device for die-to-die D2D communication, comprising a first die and a second die communicatively connected via a plurality of D2D channels. in, The first die includes: The first bus, which includes multiple first bus channels, and A first routing circuit is configured to perform a first channel mapping between the plurality of first bus channels and the plurality of D2D channels. The second die includes: The second bus includes multiple second bus channels; and A second routing circuit is configured to perform second channel mapping between the plurality of second bus channels and the plurality of D2D channels, and The mapping between each of the plurality of first bus channels and one or more of the plurality of D2D channels is the same as the mapping between the corresponding second bus channel of the plurality of second bus channels and one or more of the plurality of D2D channels.

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