An interconnect network, method and integrated circuit chip for an integrated circuit chip

Abstract

The embodiment of the application discloses an interconnection network, a method and an integrated circuit chip for the integrated circuit chip, relates to the technical field of integrated circuits, and is invented to improve arbitration balance of a selector. The interconnection network comprises: a plurality of ports of a first logical operation module are used for one-to-one corresponding reception of requests sent by a plurality of request senders; the first logical operation module is used for logical operation of a corresponding authorization code sequence of a previous period and the requests sent by the plurality of request senders, to obtain an authorized request sequence; a first arbitrator, an input end of the first arbitrator is connected with an output end of the first logical operation module, and the first arbitrator is used for, in an enabled state of the first arbitrator, determination of a first target authorized request from the authorized request sequence according to a first preset selection strategy, and obtaining an output of the first arbitrator based on the first target authorized request. The application is suitable for selection of a plurality of requests.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to an interconnection network, method, and integrated circuit chip for use in integrated circuit chips. Background Technology

[0002] Interconnect networks in integrated circuit chips enable parallel communication and efficient data transmission between multiple nodes. Based on this multi-node parallel communication and efficient data transmission, the interconnect network arbitrates requests from different directions at each node to ensure that each request is processed evenly and quickly as it passes through the nodes. The balance of the arbitration directly affects the bandwidth of each request initiator (Master) on the interconnect network.

[0003] In existing technologies, arbitration scheduling often employs a time-slice-based round-robin method. This method uses a fixed-priority scheduling strategy: once the arbitrator selects and schedules a request from multiple requests, it lowers the priority of the port corresponding to that request to the lowest level; during the scheduling process of the next time slice, the arbitrator prioritizes serving other ports, also selecting them according to priority. However, the balance of this method depends on the order in which requests are input to the arbitrator. When requests are unevenly distributed, it can easily lead to significant differences in the scheduling opportunities obtained by each port, resulting in poor balance. Summary of the Invention

[0004] In view of this, embodiments of this application provide an interconnection network, method, and integrated circuit chip for integrated circuit chips, which can improve the arbitration balance of selectors.

[0005] In a first aspect, embodiments of this application provide an interconnection network for integrated circuit chips, comprising: a first selector; the first selector comprising: a first logic operation module, wherein multiple ports of the first logic operation module are respectively used to receive requests sent by multiple request senders in a one-to-one correspondence; the first logic operation module is used to perform logical operations on the authorization code sequence corresponding to the previous period and the requests sent by the multiple request senders to obtain an authorization request sequence; wherein, each position of the authorization code sequence corresponds one-to-one with each port of the first logic operation module, and when the authorization code in the authorization code sequence is a first value, it indicates that the request received by the port of the first logic operation module corresponding to that position has been selected as output by the first selector before the current period; when the authorization code in the authorization code sequence is a second value, it indicates that the request received by the port of the first logic operation module corresponding to that position has not been selected by the first selector before the current period; and a first arbitrator, wherein the input terminal of the first arbitrator is connected to the output terminal of the first logic operation module, and is used to determine a first target authorization request from the authorization request sequence according to a first preset selection strategy when the first arbitrator is in an enabled state, and obtain the output of the first arbitrator based on the first target authorization request.

[0006] According to a specific implementation of an embodiment of this application, the interconnection network further includes: a trigger, the trigger being used to store the authorization code sequence corresponding to the previous period; the trigger being connected to the first logic operation module; the first logic operation module being used to obtain the authorization code sequence corresponding to the previous period from the trigger.

[0007] According to a specific implementation of an embodiment of this application, the Internet further includes: a modification module, configured to, when the target authorization request is issued from the node where the first selector is located, modify the value at the position corresponding to the target authorization request in the authorization code sequence from a second value to a first value to obtain a new authorization code sequence; and store the new authorization code sequence in the trigger.

[0008] According to a specific implementation of an embodiment of this application, the interconnection network further includes a second selector and a weight compensation structure; wherein the second selector is connected to the first selector and is located at the stage preceding the first selector; the weight compensation structure is connected to the second selector and is used to obtain n requests based on the output of the second selector, and input the n requests one-to-one into the n ports of the first logic operation module; wherein n is the number of requests received by the second selector.

[0009] According to a specific implementation of this application, the second selector is connected to the weight compensation structure via a physical line; the weight compensation structure includes a data distributor, which is connected to each of the n ports of the first logic operation module via n connection lines; the data distributor is used to determine the requests to be input to the n ports of the first logic operation module based on the received single-bit valid request, the port identifier selected by the second selector, and the number n requests received by the second selector, and to input the n requests to the n ports of the first logic operation module one by one according to a preset correspondence between requests and port identifiers.

[0010] According to a specific implementation of an embodiment of this application, the weight compensation structure includes: n connecting lines, each of which is connected to one of the n ports of the first logic operation module, for inputting the output of the second selector to the n ports of the first logic operation module in a one-to-one correspondence.

[0011] According to a specific implementation of an embodiment of this application, the first selector further includes: a second first logic operation module, the second first logic operation module being connected to the first logic operation module, used to perform bitwise logic operations on the authorization request sequence output by the first logic operation module to obtain an enable signal; and a second arbitrator, the second arbitrator being connected to the output terminals of the second first logic operation module and the second selector respectively, used to determine the second target authorization request from the requests input to the input terminal of the second arbitrator according to a second preset selection strategy when the enable signal is a third value, and obtain the output of the second arbitrator based on the second target authorization request; wherein, the first arbitrator is connected to the second first logic operation module, specifically used to determine the first target authorization request from the authorization request sequence according to a first preset selection strategy when the enable signal is a fourth value, and obtain the output of the first arbitrator based on the first target authorization request.

[0012] Secondly, embodiments of this application provide an arbitration method for integrated circuit chips, comprising: a first logic operation module receiving requests sent by multiple request senders; the first logic operation module performing logical operations on an authorization code sequence corresponding to the previous cycle and the requests sent by the multiple request senders to obtain an authorization request sequence; and a first arbitrator determining a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtaining the output of the first arbitrator based on the first target authorization request.

[0013] According to a specific implementation of an embodiment of this application, before obtaining the authorization request sequence, the method further includes: a first logic operation module obtaining the authorization code sequence corresponding to the previous cycle from the trigger.

[0014] According to a specific implementation of an embodiment of this application, when the target authorization request is issued from the node where the first selector is located, the method further includes: modifying the value at the position corresponding to the target authorization request in the authorization code sequence from a second value to a first value to obtain a new authorization code sequence; and storing the new authorization code sequence in the trigger.

[0015] According to a specific implementation of an embodiment of this application, the first logic operation module receives requests sent by multiple request senders, including: obtaining n requests based on the output of the second selector, and inputting the n requests one-to-one into the n ports of the first logic operation module; wherein n is the number of requests received by the second selector.

[0016] According to a specific implementation of an embodiment of this application, the step of obtaining n requests based on the output of the second selector and inputting the n requests one-to-one into the n ports of the first logic operation module includes: determining the requests to be input into the n ports of the first logic operation module based on the single-bit valid request output of the second selector, the port identifier selected by the second selector, and the number of requests n received by the second selector; and inputting the n requests one-to-one into the n ports of the first logic operation module according to a preset correspondence between requests and port identifiers.

[0017] According to a specific implementation of an embodiment of this application, the step of obtaining n requests based on the output of the second selector and inputting the n requests one-to-one into the n ports of the first logic operation module includes: inputting the output of the second selector one-to-one into the n ports of the first logic operation module.

[0018] According to a specific implementation of an embodiment of this application, the method further includes: a second logic operation module performing bitwise logic operations on the authorization request sequence output by the first logic operation module to obtain an enable signal; when the enable signal is a third value, a second arbitrator determining a second target authorization request from the requests input to the input terminal of the second arbitrator according to a second preset selection strategy, and obtaining the output of the second arbitrator based on the second target authorization request; the first arbitrator determining a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtaining the output of the first arbitrator based on the first target authorization request, including: when the enable signal is a fourth value, the first arbitrator determining a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtaining the output of the first arbitrator based on the first target authorization request.

[0019] Thirdly, embodiments of this application provide an integrated circuit chip, including: an interconnection network, wherein the interconnection network is the interconnection network described in any of the foregoing embodiments.

[0020] In this embodiment, the interconnection network, method, and integrated circuit chip for integrated circuit chips are described. Each position in the authorization code sequence corresponds one-to-one with each port of the first logic operation module. When the authorization code in the authorization code sequence has different values, it indicates that the request received by the port of the first logic operation module corresponding to that position was either selected as output by the first selector or not selected in the previous cycle. Logical operations are performed on the authorization code sequence corresponding to the previous cycle and the requests sent by multiple request senders to obtain an authorization request sequence. With the first arbitrator enabled, a first target authorization request is determined from the authorization request sequence according to a preset selection strategy, and based on the first target authorization request... The first arbitrator outputs the following: Since the authorization code sequence used in the current period masks one port that was selected (scheduled) in a previous period, the first arbitrator will not select a previously selected port when selecting the output of the current period. Furthermore, the authorization code sequence corresponding to the previous period is logically operated on with the requests sent by multiple request senders. Thus, ports without valid requests in the current period and ports that were selected (scheduled) in a previous period are masked. In this way, the first arbitrator can select ports with valid requests in the current period from the authorization request sequence for scheduling, thereby improving the arbitration balance of the selector. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the interconnection network for an integrated circuit chip provided in an embodiment of this application; Figure 2 A schematic diagram of the interconnection network for an integrated circuit chip provided in yet another embodiment of this application; Figure 3 A schematic diagram of the interconnection network for an integrated circuit chip provided in another embodiment of this application; Figure 4 An arbitration method for integrated circuit chips is provided as an embodiment of this application.

[0023] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0025] Figure 1 This is a schematic diagram of the structure of an interconnection network for an integrated circuit chip provided in an embodiment of this application. The interconnection network in this embodiment can be a network on chip or a digital circuit with arbitration logic.

[0026] like Figure 1 In the illustrated embodiment, the interconnection network for the integrated circuit chip may include: a first selector 1; the first selector 1 includes: a first logic operation module and a first arbitrator 12.

[0027] The first logic operation module has multiple ports, each used to receive requests from multiple request senders in a one-to-one correspondence; the first logic operation module is used to perform logical operations on the authorization code sequence corresponding to the previous cycle and the requests sent by multiple request senders to obtain an authorization request sequence.

[0028] In this sequence, each position of the authorization code corresponds one-to-one with each port of the first logic operation module. When the authorization code in the authorization code sequence is the first value, it means that the request received by the port of the first logic operation module corresponding to that position has been selected as the output by the first selector 1 before the current period. When the authorization code in the authorization code sequence is the second value, it means that the request received by the port of the first logic operation module corresponding to that position has not been selected by the first selector 1 before the current period.

[0029] Each port of the first logic operation module receives a request from one requester, and multiple ports correspond one-to-one to receive requests from multiple requesters. For example, request A from requester A is sent to port A of the first logic operation module, and request B from requester B is sent to port B of the first logic operation module.

[0030] The number of authorization codes in the authorization code sequence is equal to the number of ports of the first logic operation module, and the authorization codes can be represented by binary numbers.

[0031] In this embodiment, the authorization code indicates whether the request received by the port was selected by the first selector 1 before the current period, and the value of the authorization code can be a first value or a second value.

[0032] In some cases, the first value can be 0 and the second value can be 1; in other cases, the first value can be 1 and the second value can be 0.

[0033] In some examples, the first value is 0, the second value is 1, the authorization code sequence GrantMask corresponding to the previous period is 1110, the request sequence ReqVldIn formed by multiple request senders in the current period is 1011 (0 indicates an invalid request, 1 indicates a valid request), and the authorization request sequence ReqGnted obtained by performing a bitwise AND operation on the two is 1010.

[0034] The authorization code sequence used in the current cycle masks a port that has been selected (scheduled) in a previous cycle, so the port that has been scheduled in the previous cycle will not be scheduled in the current cycle.

[0035] The input terminal of the first arbitrator 12 is connected to the output terminal of the first logic operation module. When the first arbitrator 12 is enabled, it determines the first target authorization request from the authorization request sequence according to a preset selection strategy, and obtains the output of the first arbitrator 12 based on the first target authorization request.

[0036] The first arbitrator 12 determines an authorization request from the authorization request sequence according to a selection strategy. For example, if the authorization request sequence is 1010, the second and fourth requests from the right are valid requests. One of these two requests can be selected. It can follow the principle of low-order priority, selecting the request corresponding to the second request as the first target authorization request, resulting in an output of 0010 for the first arbitrator 12. Alternatively, it can follow the principle of high-order priority, selecting the request corresponding to the fourth request as the first target authorization request, resulting in an output of 1000 for the first arbitrator 12. It is understood that the selection strategy can also be other than the two mentioned above.

[0037] In some cases, the selection strategy can be configured, which allows for flexible setting and modification of the selection strategy.

[0038] In this embodiment, each position of the authorization code sequence corresponds one-to-one with each port of the first logic operation module. When the authorization code in the authorization code sequence has different values, it indicates that the request received by the port of the first logic operation module corresponding to that position has been selected as output by the first selector 1 or has not been selected in the previous period. The authorization code sequence corresponding to the previous period is logically operated with the requests sent by multiple request senders to obtain the authorization request sequence. When the first arbitrator 12 is enabled, the first target authorization request is determined from the authorization request sequence according to the preset selection strategy, and the output of the first arbitrator 12 is obtained based on the first target authorization request. Since the authorization code sequence used in the current period is the one that has been selected (scheduled) in the previous period, the authorization code sequence used in the current period is the one that has been selected in the previous period. One port is masked, and the authorization code sequence corresponding to the previous period is logically operated on with the requests sent by multiple request senders. In this way, the port without a valid request in the current period and the port that has been selected (scheduled) in the previous period are masked. Thus, the first arbitrator can select the port with a valid request in the current period from the authorization request sequence for scheduling, which improves the arbitration balance of the selector and avoids the problem of poor balance caused by the balance depending on the order of the request input to the arbitrator in the prior art. In addition, it avoids the situation where the same request corresponding to the same port is selected multiple times in a short period of time, resulting in one request sender occupying the Internet for a long time and causing other ports to not get a scheduling opportunity, resulting in a "starvation" phenomenon.

[0039] The authorization code sequence corresponding to the previous cycle can be stored in the first logic operation module, but this requires the storage resources of the first logic operation module. To reduce the storage resource usage of the first logic operation module, in some embodiments, such as... Figure 1 As shown, the interconnection network may further include: a trigger 2, which is used to store the authorization code sequence corresponding to the previous cycle; the trigger 2 is connected to the first logic operation module; the first logic operation module is used to obtain the authorization code sequence corresponding to the previous cycle from the trigger 2.

[0040] Flip-flop 2, specifically a D flip-flop 2 (DFF). In this embodiment, flip-flop 2 samples the value at the input on the rising (or falling) edge of the clock and stores that value at the output until the next trigger. This allows the license code sequence from the previous cycle to be stored in flip-flop 2 for use in the current cycle.

[0041] If the target authorization request for the current period is issued from the node where the first selector 1 is located, it indicates that the selection is valid. In order to facilitate the continued normal operation of the first selector 1 in the next period, in some examples, the Internet may also include: a modification module, which is used to modify the value at the position corresponding to the target authorization request in the authorization code sequence from the second value to the first value when the target authorization request is issued from the node where the first selector 1 is located, to obtain a new authorization code sequence; and store the new authorization code sequence in trigger 2.

[0042] If the current period authorization code sequence is 1110, and the current period multiple request senders send requests of 1011 (0 indicates an invalid request, 1 indicates a valid request), the authorization request sequence obtained by performing a bitwise AND operation on the two is 1010. After the first logic operation module, the port request corresponding to the second bit on the right is selected as the first target authorization request, and then 1010 is modified to 1000.

[0043] In the prior art, in the Internet, there is an arbitration imbalance problem caused by physical location or multiple request initiators (Masters) sharing a path. To solve this problem, in some examples, the Internet may also include a second selector 3 and a weight compensation structure 4; wherein, the second selector 3 is connected to the first selector 1 and is at the level preceding the first selector 1.

[0044] The weight compensation structure 4 is connected to the second selector 3 and is used to obtain n requests based on the output of the second selector 3, and input the n requests one-to-one into the n ports of the first logic operation module; where n is the number of requests received by the second selector 3.

[0045] The supplementary structure in this embodiment can, based on the number of requests n received by the second selector 3, use the weight compensation structure 4 to ensure that the n ports of the first logic operation module can receive the desired requests, thereby avoiding the problem of poor arbitration balance caused by the first selector 1 ignoring the number of requests n received by the second selector 3 when making selections.

[0046] To address the arbitration imbalance caused by multiple request initiators (Masters) sharing a single path, in some examples, the second selector 3 is connected to the weight compensation structure via a physical line. The weight compensation structure 4 includes a data distributor 40, which is connected to each of the n ports of the first logic operation module via n connection lines. The data distributor 40 is used to determine the requests to be input to the n ports of the second selector 3 based on the received single-bit valid request, the port identifier selected by the second selector 3, and the number of requests n received by the second selector 3. Based on a preset correspondence between requests and port identifiers, the data distributor 40 inputs the n requests to the n ports of the first logic operation module one by one.

[0047] If the input of the second selector 3 includes four ports A, B, C, and D, and port A corresponds to request 0 from request initiator A, port B corresponds to request 1 from request initiator B, port C corresponds to request 1 from request initiator C, and port D corresponds to request 1 from request initiator D (i.e., request 0111), and if the second selector 3 selects request 1 from request initiator B corresponding to port B as the output, then vld=1 transmitted on the shared path, along with the identifier of port B, and combined with the number of requests n received by the second selector 3, determines the n ports to be input to the first logic operation module. For a request to a port, if 1 represents a valid request, then the request input to the n ports of the first logic operation module is 0100. According to a preset correspondence between requests and port identifiers, the n requests are input one-to-one to the n ports of the first logic operation module. For example, the preset correspondence between requests and port identifiers is as follows: the first bit of the request corresponds to port A1 of the first logic operation module, the second bit corresponds to port B1, the third bit corresponds to port C1, and the fourth bit corresponds to port D1. If the request is 0100, then the first bit is input to port A1, the second bit to port B1, the third bit to port C1, and the fourth bit to port D1.

[0048] like Figure 2 In one specific embodiment shown, the request signal vld transmitted on the shared path is a single bit. Therefore, the second selector 3 (Mux2) will select one Master from multiple request initiators. If there is no weight compensation structure 4, the request selected by the second selector 3 will be compared with other requests input to the first selector 1 (Mux1). The arbitration at the first selector 1 arbitrates the multiple input requests, which will ignore the multiple requests corresponding to the output of the second selector 3, resulting in an unbalanced arbitration. In this embodiment, the data distributor 40 first restores the number of Masters corresponding to a single bit on the shared path (multiple requests input to the second selector 3Mux1) before arbitration.

[0049] The compensation mechanism of data allocator 40 is to instantiate the number of Masters represented by the current vld, and to instantiate one vld into n Master-level vlds. After passing through the shared path, the vlds are restored by data allocator 40 to the Master vlds initiated by multiple request initiators at Mux1.

[0050] In the interconnected structure of multi-level selectors, the arbitration becomes unbalanced as intermediate selectors introduce requests from other request initiators (Masters). To address this issue, in some cases, the weight compensation structure 4 includes n connection lines 42, each connected to one of the n ports of the first logic operation module, to input the output of the second selector 3 to the n ports of the first logic operation module.

[0051] This embodiment is equivalent to copying the output of the second selector 3 and inputting it into n ports respectively, thereby equalizing the port arbitration opportunities on the first selector 1.

[0052] like Figure 3 In the specific embodiment shown, the second selector 3 (Mux2) receives two input requests, mux0_port0 and mux0_port1. Without compensation, the two requests pass through the second selector 3 and output a mux0_port to a port of the first selector 1 (Mux1). mux1_port0 and mux1_port1 are directly input to the first selector 1. Thus, the weights of the three requests—mux0_port, mux1_port0, and mux1_port1—are 1 / 3 in the first selector 1, and 1 / 6 in mux0_port0 and mux0_port1, respectively, resulting in an unbalanced weight distribution. This embodiment inputs mux0_port to the two ports of the first logic operation module in a one-to-one correspondence, thereby compensating the weight of mux0_port to 1 / 2 and resolving the weight imbalance problem caused by requests from different sources passing through different numbers of selectors.

[0053] The interconnection network in this embodiment can handle requests regardless of whether the requests sent by the request initiator Master are balanced or not, and can be implemented regardless of whether the positions of the request initiators are symmetrical.

[0054] If there is no valid request in the authorization request sequence, the first arbitrator 12 cannot select the first target authorization request, that is, the first arbitrator 12 has no output in the current cycle, which means that the current cycle introduces a bubble and causes a decrease in bandwidth. In order to solve this problem, in some embodiments, the first selector 1 may further include: a second logic operation module and a second arbitrator 14; wherein, the second logic operation module is connected to the first logic operation module 10 and is used to perform bitwise logic operations on the authorization request sequence output by the first logic operation module 10 to obtain an enable signal; the second arbitrator 14 is connected to the output terminals of the second logic operation module and the second selector 3 respectively, and is used to determine the second target authorization request from the requests input to the input terminal of the second arbitrator 14 according to the second preset selection strategy when the enable signal is a third value, and obtain the output of the second arbitrator 14 based on the second target authorization request.

[0055] The third value is the value that enables the second arbitrator 14 to be in the enabled state, that is, the state in which the second arbitrator 14 can work. The third value can be 0.

[0056] The authorization request sequence is performed bitwise logically, which means performing logical operations on the values ​​of each bit in the authorization request sequence. In some cases, the authorization request sequence can be bitwise ORed. For example, when the value of each bit is 0, the enable signal is 0; if the value of each bit is 1, the enable signal is 1.

[0057] The first arbitrator 12 is connected to the output of the second logic operation module. Specifically, when the enable signal is the fourth value, it determines the first target authorization request from the authorization request sequence according to the first preset selection strategy, and obtains the output of the first arbitrator 12 based on the first target authorization request.

[0058] The fourth value is the state that enables the first arbitrator 12 to be in the enabled state, i.e., to work. The fourth value is different from the third value. The fourth value can be 1.

[0059] like Figure 1 In the specific embodiment shown, when the authorization request sequence ReqGnted is all 0, it may be due to the authorization code sequence GrantMask being all 0. In this case, the requests input to the first logic operation module 10 include valid requests, but when the authorization request sequence ReqGnted is all 0, the first arbitrator 12 cannot arbitrate a valid request. If there is no second arbitrator 14, the first selector 1 in the current cycle will not output, and the network bandwidth will decrease. To solve this problem, such as Figure 1In the illustrated embodiment, the authorization request sequence ReqGnted output by the first logic operation module 10 is input to the first arbiter 12. When the enable signal |ReqGnted obtained by performing a logical operation such as bitwise OR operation on the authorization request sequence ReqGnted is 1, the first arbiter 12 is enabled and can arbitrate the authorization request sequence to obtain a first target authorization request. Based on the first target authorization request, the output of the first arbiter 12 is obtained. The output result of the second selector 3 is input to the second arbiter 14. When the enable signal is 0, the second arbiter 14 is enabled and can arbitrate the input request input to the second selector 3 to obtain a second target authorization request. Based on the second target authorization request, the output of the second arbiter 14 is obtained.

[0060] In this embodiment, when the enable signal is 1, the first arbitrator 12 is enabled and arbitrates the authorization request sequence to obtain an output result, which can be used as the output result of the first selector 1. When the enable signal is 0, the first arbitrator 12 does not work, and the second arbitrator 14 arbitrates the requests input to the second arbitrator 14 to obtain an output result, which can be used as the output result of the first selector 1. In this way, even when the authorization code sequence is all 0, the first selector 1 also has an output, thereby improving network bandwidth.

[0061] The first selector 1 in this embodiment has a simple structure and small area. In some embodiments, only AND gates and OR gates are needed to realize the function of the first selector 1.

[0062] In this embodiment, the structure formed by the first selector 1, the second selector 3, the weight supplement structure, and the connection relationship is applicable to any scenario with a selection structure, so as to improve the balance and guarantee bandwidth.

[0063] Figure 4 An arbitration method for integrated circuit chips provided in one embodiment of this application, such as Figure 4 As shown, the method in this embodiment may include: S101, The first logic operation module receives requests sent by multiple request senders.

[0064] S102. The first logic operation module performs logical operations on the authorization code sequence corresponding to the previous cycle and the requests sent by multiple request senders to obtain the authorization request sequence.

[0065] In this sequence, each position of the authorization code corresponds one-to-one with each port of the first logic operation module. When the authorization code in the authorization code sequence is a first value, it indicates that the request received by the port of the first logic operation module corresponding to that position has been selected as output by the first selector before the current period. When the authorization code in the authorization code sequence is a second value, it indicates that the request received by the port of the first logic operation module corresponding to that position has not been selected by the first selector before the current period.

[0066] S103. The first arbitrator determines a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtains the output of the first arbitrator based on the first target authorization request.

[0067] The method in this embodiment is similar in principle and technical effect to the interconnection network for integrated circuit chips in the foregoing embodiments. The specific implementation means can be referred to the corresponding parts of the foregoing embodiments.

[0068] In this embodiment, each position in the authorization code sequence corresponds one-to-one with each port of the first logic operation module. When the authorization code in the authorization code sequence has different values, it indicates that the request received by the port of the first logic operation module corresponding to that position has been selected as output by the first selector 1 or has not been selected in the previous period. The authorization code sequence corresponding to the previous period is logically operated with the requests sent by multiple request senders to obtain the authorization request sequence. When the first arbitrator is in the enabled state, the first target authorization request is determined from the authorization request sequence according to the preset selection strategy, and the output of the first arbitrator is obtained based on the first target authorization request. Since the authorization code sequence used in the current period is the one that has been selected (scheduled) in the previous period, the authorization code sequence used in the current period is the one that has been selected (scheduled) in the previous period. One port is masked, and the authorization code sequence corresponding to the previous period is logically processed with the requests sent by multiple request senders. In this way, the port without a valid request in the current period and the port that has been selected (scheduled) in the previous period are masked. Thus, the first arbitrator can select the port with a valid request in the current period from the authorization request sequence for scheduling, which improves the arbitration balance of the selector and avoids the problem of poor balance caused by the balance depending on the order of the request input to the arbitrator in the prior art. In addition, it avoids the situation where the same request sender selects the same port multiple times in a short period of time, resulting in one request sender occupying the Internet for a long time and causing other ports to not get a scheduling opportunity, resulting in a "starvation" phenomenon.

[0069] As an optional implementation, before obtaining the authorization request sequence, the method further includes: a first logic operation module obtaining the authorization code sequence corresponding to the previous cycle from the trigger.

[0070] As an optional implementation, when the target authorization request is issued from the node where the first selector is located, the method further includes: modifying the value at the position corresponding to the target authorization request in the authorization code sequence from a second value to a first value to obtain a new authorization code sequence; and storing the new authorization code sequence in the trigger.

[0071] As an optional implementation, the first logic operation module receives requests from multiple request senders, including: obtaining n requests based on the output of the second selector, and inputting the n requests one-to-one into the n ports of the first logic operation module; wherein n is the number of requests received by the second selector.

[0072] As an optional implementation, the step of obtaining n requests based on the output of the second selector and inputting the n requests one-to-one into the n ports of the first logic operation module includes: determining the requests to be input into the n ports of the first logic operation module based on the single-bit valid request output of the second selector, the port identifier selected by the second selector, and the number of requests n received by the second selector; and inputting the n requests one-to-one into the n ports of the first logic operation module according to a preset correspondence between requests and port identifiers.

[0073] As an optional implementation, obtaining n requests based on the output of the second selector and inputting the n requests one-to-one into the n ports of the first logic operation module includes: inputting the output of the second selector one-to-one into the n ports of the first logic operation module.

[0074] As an optional implementation, the method further includes: a second logic operation module performing bitwise logic operations on the authorization request sequence output by the first logic operation module to obtain an enable signal; when the enable signal is a third value, a second arbitrator determining a second target authorization request from the requests input to the input terminal of the second arbitrator according to a second preset selection strategy, and obtaining the output of the second arbitrator based on the second target authorization request; the first arbitrator determining a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtaining the output of the first arbitrator based on the first target authorization request, including: when the enable signal is a fourth value, the first arbitrator determining a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtaining the output of the first arbitrator based on the first target authorization request.

[0075] The methods in the above embodiments are similar in principle and technical effect to the technical solutions in the foregoing embodiments, and will not be repeated here.

[0076] One embodiment of this application provides an integrated circuit chip, which includes an interconnection network, wherein the interconnection network is the interconnection network in any of the above embodiments.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0078] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An interconnect network for integrated circuit chips, characterized in that, include: First selector; The first selector includes: A first logic operation module has multiple ports that are respectively used to receive requests sent by multiple request senders in a one-to-one correspondence. The first logic operation module is used to perform logical operations on the authorization code sequence corresponding to the previous period and the requests sent by multiple request senders to obtain an authorization request sequence. Each position in the authorization code sequence corresponds one-to-one with each port of the first logic operation module. When the authorization code in the authorization code sequence is a first value, it indicates that the request received by the port of the first logic operation module corresponding to that position has been selected as output by the first selector before the current period. When the authorization code in the authorization code sequence is a second value, it indicates that the request received by the port of the first logic operation module corresponding to that position has not been selected by the first selector before the current period. A first arbitrator, the input of which is connected to the output of the first logic operation module, is used to determine a first target authorization request from the authorization request sequence according to a first preset selection strategy when the first arbitrator is enabled, and to obtain the output of the first arbitrator based on the first target authorization request.

2. The Internet according to claim 1, characterized in that, The interconnection network further includes: a trigger, the trigger being used to store the authorization code sequence corresponding to the previous period; The trigger is connected to the first logic operation module; The first logic operation module is used to obtain the authorization code sequence corresponding to the previous cycle from the trigger.

3. The Internet according to claim 2, characterized in that, The interconnection network also includes: The modification module is used to modify the value at the position corresponding to the target authorization request in the authorization code sequence from a second value to a first value when the target authorization request is issued from the node where the first selector is located, so as to obtain a new authorization code sequence; and to store the new authorization code sequence in the trigger.

4. The Internet according to claim 1, characterized in that, The interconnection network further includes a second selector and a weight compensation structure; wherein the second selector is connected to the first selector and is located at the stage preceding the first selector; The weight compensation structure is connected to the second selector and is used to obtain n requests based on the output of the second selector, and input the n requests one-to-one into the n ports of the first logic operation module; wherein n is the number of requests received by the second selector.

5. The Internet according to claim 4, characterized in that, The second selector is connected to the weight compensation structure via a physical line; The weight compensation structure includes: A data distributor is connected to each of the n ports of the first logic operation module via n connection lines. The data distributor is used to determine the requests to be input to the n ports of the first logic operation module based on the received single-bit valid request, the port identifier selected by the second selector, and the number n requests received by the second selector. According to a preset correspondence between requests and port identifiers, the data distributor inputs the n requests to the n ports of the first logic operation module one by one.

6. The Internet according to claim 4, characterized in that, The weight compensation structure includes: n connecting lines, The n connecting lines are respectively connected to the n ports of the first logic operation module, and are used to input the output of the second selector to the n ports of the first logic operation module.

7. The Internet according to claim 4, characterized in that, The first selector also includes: The second logic operation module, which is connected to the first logic operation module, is used to perform bitwise logic operations on the authorization request sequence output by the first logic operation module to obtain an enable signal. The second arbitrator is connected to the output terminals of the second logic operation module and the second selector, respectively. When the enable signal is a third value, it determines the second target authorization request from the requests input from the input terminal of the second arbitrator according to the second preset selection strategy, and obtains the output of the second arbitrator based on the second target authorization request. The first arbitrator is connected to the second logic operation module and is specifically used to determine a first target authorization request from the authorization request sequence according to a first preset selection strategy when the enable signal is the fourth value, and to obtain the output of the first arbitrator based on the first target authorization request.

8. An arbitration method for integrated circuit chips, characterized in that, include: The first logic operation module receives requests from multiple request senders; The first logic operation module performs logical operations on the authorization code sequence corresponding to the previous cycle and the requests sent by multiple request senders to obtain the authorization request sequence; The first arbitrator determines a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtains the output of the first arbitrator based on the first target authorization request.

9. The method according to claim 8, characterized in that, Before obtaining the authorization request sequence, the method further includes: The first logic operation module obtains the authorization code sequence corresponding to the previous cycle from the flip-flop.

10. The method according to claim 9, characterized in that, When the target authorization request originates from the node where the first selector resides, the method further includes: The value at the position corresponding to the target authorization request in the authorization code sequence is changed from the second value to the first value to obtain a new authorization code sequence; The new authorization code sequence is stored in the trigger.

11. The method according to claim 8, characterized in that, The first logic operation module receives requests from multiple request senders, including: Based on the output of the second selector, n requests are obtained, and the n requests are input one-to-one to the n ports of the first logic operation module; where n is the number of requests received by the second selector.

12. The method according to claim 11, characterized in that, Based on the output of the second selector, n requests are obtained, and these n requests are respectively input into the n ports of the first logic operation module in a one-to-one correspondence, including: Based on the single-bit valid request output by the second selector, the port identifier selected by the second selector, and the number n requests received by the second selector, the requests input to the n ports of the first logic operation module are determined, and according to the preset correspondence between requests and port identifiers, the n requests are input to the n ports of the first logic operation module one by one.

13. The method according to claim 11, characterized in that, Based on the output of the second selector, n requests are obtained, and these n requests are respectively input into the n ports of the first logic operation module in a one-to-one correspondence, including: The output of the second selector is input one-to-one to the n ports of the first logic operation module.

14. The method according to claim 11, characterized in that, The method further includes: The second logic operation module performs bitwise logic operations on the authorization request sequence output by the first logic operation module to obtain an enable signal; When the enable signal is a third value, the second arbitrator determines the second target authorization request from the requests input from the input terminal of the second arbitrator according to the second preset selection strategy, and obtains the output of the second arbitrator based on the second target authorization request; The first arbitrator determines a first target authorization request from the authorization request sequence according to a first preset selection strategy, and obtains the output of the first arbitrator based on the first target authorization request, including: When the enable signal is the fourth value, the first arbitrator determines the first target authorization request from the authorization request sequence according to the first preset selection strategy, and obtains the output of the first arbitrator based on the first target authorization request.

15. An integrated circuit chip, characterized in that, include: The Internet is the Internet as described in any one of claims 1-7.

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