Control method, control device, storage circuit, computing and storage system and electronic device

Abstract

The application provides a control method, a control device, a storage circuit, a storage-computing system and an electronic device, and relates to the technical field of semiconductors. The control method is used for controlling a storage circuit, the storage circuit comprises a storage-computing unit, the storage-computing unit comprises a plurality of storage unit blocks, the plurality of storage unit blocks comprise a first effective block and a backup block, and the control method comprises the following steps: reading first data stored in a first storage area of the first effective block; and in the case that the read first data has an error, backing up the data stored in the first storage area to a second storage area in the backup block. The scheme can improve the reliability of the storage-computing integrated architecture.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a control method, control device, storage circuit, memory computing system, and electronic device. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architecture physically merges storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architecture can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architecture still faces challenges; for example, its reliability still needs improvement. Summary of the Invention

[0004] This application provides a control method, control device, storage circuit, in-memory computing system, and electronic device that can improve the reliability of in-memory computing architecture.

[0005] In a first aspect, a control method is provided for controlling a storage circuit, the storage circuit including a storage and computing unit, the storage and computing unit including multiple storage cell blocks, the multiple storage cell blocks including a first valid block and a backup block, the control method including: reading first data stored in a first storage area of ​​the first valid block; and backing up the data stored in the first storage area to a second storage area in the backup block if an error occurs in the read first data.

[0006] The technical solution of this application embodiment sets up a backup block within the in-memory computing unit of the storage circuit. Using this backup block, erroneous data occurring within the in-memory computing unit can be backed up. This effectively reduces the recurrence of problems at the same location on the storage medium in subsequent operations, thereby improving the storage accuracy of the storage circuit. When the storage circuit is used in the in-memory computing system, the backup data remains within the in-memory computing unit, thus not affecting the corresponding calculations and improving the reliability of the in-memory computing system. Furthermore, this solution can back up data within the storage area of ​​the valid block. Compared to refreshing the entire valid block's data, the backup time is shorter, resulting in a higher backup speed. This reduces latency caused by data backup or refresh, allowing for faster initiation of the next calculation, further improving the computing performance of the in-memory computing system and increasing its response efficiency to computing tasks.

[0007] In some implementations of the first aspect, the second storage area and the first storage area belong to the same sub-in-memory unit, and the data stored in the same sub-in-memory unit is used for the same calculation.

[0008] Based on this implementation method, when a data read error occurs in the first storage area, the correct data in the first storage area can be backed up to the second storage area located in the same sub-in-memory unit as the first storage area. The correct data can still be used for the calculation of the sub-in-memory unit, which can reduce the impact on the calculation of the in-memory system, reduce the backup waiting latency, and help simplify the control logic of the control device, thereby improving the overall calculation efficiency or calculation speed of the in-memory system.

[0009] In some implementations of the first aspect, multiple storage cell blocks are arranged along a first direction, one of the multiple storage cell blocks includes a multi-layer storage cell array arranged along a third direction, multiple storage cell arrays located on the same layer in the third direction belong to the same sub-storage unit, and one storage cell array includes multiple storage cell sub-arrays arranged along the first direction, and one storage cell sub-array includes multiple storage cells arranged along a second direction; the first storage region includes a first storage cell sub-array of the first valid block, and the second storage region includes a second storage cell sub-array of the backup block.

[0010] The implementation method provided in this application is beneficial for the in-memory computing control of storage circuits with high storage density. For example, the storage circuit may include a three-dimensional storage array, which may have a larger storage density or storage capacity, so that the in-memory computing system can support larger model deployments.

[0011] In some implementations of the first aspect, the control method further includes: when a refresh condition is met, controlling the refresh of data stored in the target valid block in the storage unit to the backup block, wherein the refresh condition includes one or more of the following conditions: the refresh timing of the target valid block or the storage unit has arrived; the backup block stores backup data in the storage unit subarray of the first sub-storage unit of the storage unit; the backup block stores backup data in the storage unit subarray of the first sub-storage unit of the storage unit, and an error occurs in the second data read from the first sub-storage unit; the storage unit includes multiple backup blocks, and the multiple backup blocks store backup data in the storage unit subarray of the first sub-storage unit of the storage unit; the storage unit includes multiple backup blocks, and the multiple backup blocks store backup data in the storage unit subarray of the first sub-storage unit of the storage unit, and an error occurs in the second data read from the first sub-storage unit.

[0012] Among the above control methods, refresh conditions are used to trigger the refresh of the storage circuit, thereby improving the storage accuracy of the storage circuit during use and thus improving the reliability of the in-memory computing system. Furthermore, by setting backup blocks, while improving storage accuracy, the impact of storage circuit refresh on business can be reduced, thereby improving the overall responsiveness of the in-memory computing system to business.

[0013] In some implementations of the first aspect, the target valid block has the largest number of memory cell subarrays with read errors among multiple memory cell blocks, or the target valid block has the earliest read data error among multiple memory cell blocks. This allows for priority refresh of the valid block with the most or earliest errors, improving storage accuracy. Under the refresh condition, the data of the target valid block can be refreshed first, reducing the impact of erroneous data in the target valid block on the accuracy of the computation results of the in-memory computing unit, thus better improving the computation accuracy of the in-memory computing unit. In some alternative examples, the target valid block can also be other valid blocks in the in-memory computing unit, for example, it can be a valid block specified by preset rules; this application does not limit this.

[0014] In some implementations of the first aspect, the control method further includes: updating the first mapping relationship to a second mapping relationship based on backup, wherein the first mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the first storage area, and the second mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the second storage area.

[0015] The above technical solutions enable the recording and maintenance of logical and physical addresses related to valid data, improving the accuracy and reliability of data operations, thereby further enhancing the storage and computing performance of the storage circuit.

[0016] In some implementations of the first aspect, the number of valid blocks within the in-memory unit is greater than the number of backup blocks. This results in a smaller proportion of backup blocks within the in-memory unit, allowing more resources to be used for data storage or computation. This benefits data refresh or backup within the in-memory unit while reducing waste of storage or computing resources.

[0017] In some implementations of the first aspect, the storage unit includes 8 valid blocks and 1 backup block.

[0018] In some implementations of the first aspect, each of the multiple storage unit blocks includes the same number of storage areas. For example, the number of first storage areas in a valid block can be equal to the number of second storage areas in a backup block. This facilitates the backup of the corresponding areas in the backup block for the first storage areas in the valid block, avoiding situations where the second storage areas in the backup block are insufficient or redundant. This improves the data backup effect of the backup block, thereby enhancing the computing performance of the in-memory computing unit, and also facilitates the full utilization of storage space within the in-memory computing unit, while simplifying control logic. As another example, when the in-memory computing unit includes multiple valid blocks, the number of first storage areas in these multiple valid blocks can be the same. This facilitates data read / write control of multiple valid blocks, or computational control of the valid blocks, further improving the computing performance of the in-memory computing unit. In some embodiments, the storage area may include a read / write unit of a storage circuit.

[0019] In some implementations of the first aspect, the control method further includes: after backup, controlling the in-memory computing unit to perform calculations, with the second storage area replacing the first storage area in the calculations. This can effectively improve the response speed and efficiency of the calculations.

[0020] Secondly, a storage circuit is provided, including: a storage and computing unit, the storage and computing unit including multiple storage cell blocks, the multiple storage cell blocks including valid blocks and backup blocks, the backup blocks being used to back up data stored in a first storage area in the valid blocks, wherein the data in the first storage area contains errors during the reading process.

[0021] In some implementations of the second aspect, the second storage area in the backup block is used to back up the data stored in the first storage area. The second storage area and the first storage area belong to the same sub-memory unit, and the data stored in the same sub-memory unit is used for the same calculation.

[0022] In some implementations of the second aspect, a storage cell block of multiple storage cell blocks includes a multi-layer storage cell array arranged along a third direction, multiple storage cell arrays located on the same layer in the third direction belong to the same sub-storage unit, and a storage cell array includes multiple storage cell sub-arrays arranged along a first direction, and a storage cell sub-array includes multiple storage cells arranged along a second direction; a first storage region includes a first storage cell sub-array of valid blocks, and a second storage region includes a second storage cell sub-array of backup blocks.

[0023] In some implementations of the second aspect, the storage circuit is further configured to store a first mapping relationship before backup and a second mapping relationship after backup, wherein the first mapping relationship is used to indicate the correspondence between a first logical address and a physical address of a first storage region, and the second mapping relationship is used to indicate the correspondence between a first logical address and a physical address of a second storage region in the backup block.

[0024] In some implementations of the second aspect, the number of valid blocks within the storage unit is greater than the number of backup blocks.

[0025] In some implementations of the second aspect, the storage unit includes 8 valid blocks and 1 backup block.

[0026] In some implementations of the second aspect, each of the multiple storage cell blocks includes the same number of storage areas.

[0027] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0028] Thirdly, a control device is provided, comprising: an interface circuit for communicating with a storage circuit; and at least one processing circuit for executing any of the control methods of the first aspect.

[0029] Fourthly, a storage computing system is provided, comprising: a storage circuit according to any of the second aspects; and a control device for executing a control method according to any of the first aspects to control the storage circuit.

[0030] Fifthly, an electronic device is provided, including the storage and computing system of the fourth aspect. Attached Figure Description

[0031] Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0032] Figure 2 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0033] Figure 3A schematic diagram of a storage circuit according to an exemplary embodiment of this application is shown.

[0034] Figure 4 A schematic diagram of a control method according to an exemplary embodiment of this application is shown.

[0035] Figure 5 A schematic diagram of a three-dimensional memory array in a memory circuit according to an exemplary embodiment of this application is shown.

[0036] Figure 6 A schematic diagram of a memory computing unit according to an exemplary embodiment of this application is shown.

[0037] Figure 7 A schematic diagram of another control method according to an exemplary embodiment of this application is shown.

[0038] Figure 8 A schematic diagram of the storage state of a memory computing unit according to an exemplary embodiment of this application is shown.

[0039] Figure 9 A schematic diagram of the storage state of another memory computing unit according to an exemplary embodiment of this application is shown.

[0040] Figure 10 A schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application is shown.

[0041] Figure 11 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0042] Figure 12 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0044] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0045] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0046] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0047] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0048] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0049] For ease of understanding, Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. This in-memory computing system is described as an example of implementing in-memory computation using memory as a carrier.

[0050] like Figure 1As shown, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0051] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0052] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0053] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0054] As an example, Figure 2 A schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application is shown.

[0055] like Figure 2 As shown, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,r], j∈[1,t], r is the number of rows in the storage cell array, and t is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S rj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0056]

[0057] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0058] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense, amplify, or process the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in Figure 2 In the example, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0059] Figure 2 This is merely an example illustrating a connection method of storage cells in a storage cell array 210, except... Figure 2Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells are connected in columns with collinearity, and the output terminals of the memory cells are connected in rows with collinearity. Furthermore, the input terminals of the memory cells may include the gate of a transistor memory device, or the input terminals of the memory cells may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0060] Storage media inevitably have some physical limitations. For example, high-density storage media, such as NAND flash memory, may experience interference problems between storage cells, such as read disturb. Furthermore, storage media may face data retention issues during long-term storage. These problems can affect the storage performance of the media, especially when used in in-memory computing systems. These systems operate at high speeds and process large amounts of data. The weight data stored in the storage cells is frequently used in calculations, further amplifying these problems and affecting the accuracy of the weight data or calculation results, leading to a decrease in the reliability of the in-memory computing system.

[0061] In view of this, the present application provides a technical solution that can promptly store and back up the data when a data read error occurs in the storage circuit, without affecting the impact of the data on the calculation, thereby improving the storage performance of the storage circuit and reducing the impact of the physical limitations of the storage medium on the storage performance when it is applied to the computing system, improving the accuracy of the calculation results, and thus improving the reliability of the storage computing system.

[0062] As an example, Figure 3 A schematic diagram of a storage circuit according to an exemplary embodiment of this application is shown.

[0063] like Figure 3 As shown, the storage circuit 300 includes one or more storage units, which can be used as units for computation, i.e., storage space opened or introduced in a single computation; this storage unit can also be called a storage-computing unit 310. The storage-computing unit 310 includes multiple storage unit blocks, including valid blocks (e.g., storage unit blocks B1 and B2 shown in the figure) and backup blocks (e.g., storage unit block B' shown in the figure). The backup blocks are used to back up the data stored in the storage area of ​​the valid blocks, where errors may occur during the reading process. The storage-computing unit 310 may include multiple storage areas; for ease of description, the storage area where errors occur during the reading process can be referred to as the first storage area.

[0064] In the embodiments of this application, the computation may include in-memory computation and near-memory computation. For example, in in-memory computation, the in-memory computation unit may perform analog domain multiplication and accumulation computation based on the stored weight data and the input data received by the in-memory computation unit. As another example, in near-memory computation, the weight data stored in the in-memory computation unit may also be read out, and the processing circuit outside the storage circuit is used to perform digital domain multiplication and accumulation computation. The processing circuit may be packaged together with the storage circuit to realize near-memory computation. The processing circuit may include a control circuit, or may be integrated with the control circuit, for example, implemented in the form of a system on chip (SOC).

[0065] In this embodiment, the multiple storage unit blocks allow for flexible data transfer within the storage unit, such as data refresh or backup. When backing up erroneous data within the storage unit, the backed-up data can be the corrected data after verification, or it can be correct data obtained from other data sources outside the storage circuitry.

[0066] The technical solution of this application embodiment sets up a backup block within the in-memory computing unit of the storage circuit. Using this backup block, erroneous data occurring within the in-memory computing unit can be backed up. This effectively reduces the recurrence of problems at the same location on the storage medium in subsequent operations, thereby improving the storage accuracy of the storage circuit. When the storage circuit is used in the in-memory computing system, the backup data remains within the in-memory computing unit, thus not affecting the corresponding calculations and improving the reliability of the in-memory computing system. Furthermore, this solution can back up data within the storage area of ​​the valid block. Compared to refreshing the entire valid block's data, the backup time is shorter, resulting in a higher backup speed. This reduces latency caused by data backup or refresh, allowing for faster initiation of the next calculation, further improving the computing performance of the in-memory computing system and increasing its response efficiency to computing tasks.

[0067] In some embodiments of this application, the storage unit block of the in-memory computing unit can serve as an erase unit in the storage circuit. Thus, when a backup block is insufficient to continue data backup during use, it can be erased or refreshed promptly.

[0068] Optionally, in some embodiments, valid blocks in the in-memory computing unit can be used to store valid data of the in-memory computing unit, which can be used for reading or calculation, for example, including weight data for calculation. Backup blocks can be used to store empty or invalid data, which is not used for reading or calculation. For example, empty data can include data after the storage unit has been erased, and the empty data can include, but is not limited to, "1" or "0". When a backup block stores empty data, the backup block can be marked as "empty". When a backup block stores invalid data, the backup block can be marked as "invalid". During subsequent data writing, the invalid data in the backup block can be erased first, and then valid data can be written into it. As data is refreshed or backed up, backup blocks and valid blocks can change dynamically in the in-memory computing unit. For example, at a first time, one storage unit block in the in-memory computing unit is a valid block and another storage unit block is a backup block; at a second time, the one storage unit block becomes a backup block and the other storage unit block becomes a valid block.

[0069] In some embodiments of this application, the number of valid blocks within the in-memory computing unit is greater than the number of backup blocks. This results in a smaller proportion of backup blocks within the in-memory computing unit, allowing more resources to be used for data storage or computation. This benefits data refresh or backup within the in-memory computing unit while reducing waste of storage or computing resources. As an example and not a limitation, the number of valid blocks m1 within the in-memory computing unit can be any positive integer between 4 and 8, and the number of backup blocks m2 within the in-memory computing unit can be less than or equal to... The values ​​of m1 and m2 are any positive integers. For example, m1 = 8, m2 = 1; or m1 = 8, m2 = 2; or m1 = 6, m2 = 3; m1 = 7, m2 = 2, etc. This application does not limit the specific values ​​of m1 and m2 in its embodiments.

[0070] In some examples of this application, the first storage area in a valid block may include all or part of the storage areas in that valid block. The second storage area in a backup block used to back up data in the first storage area may also be all or part of the storage areas in the backup block. Optionally, the capacity of the second storage area may be greater than or equal to the capacity of the first storage area, providing sufficient storage space for the data to be backed up in the first valid block. In some examples, the capacity of the second storage area may be equal to the capacity of the first storage area, which facilitates full utilization of the internal storage space of the backup block and improves the data backup capability of the backup block. The capacity of this storage area characterizes the storage capacity of the storage area and can be replaced by parameters such as storage space, storage size, storage limit, storage scale, storage range, and storage quota.

[0071] Optionally, each of the multiple storage unit blocks within the in-memory computing unit includes the same number of storage areas. For example, the number of first storage areas in a valid block can be equal to the number of second storage areas in a backup block. This facilitates the backup of the corresponding areas in the backup block for the first storage area in the valid block, avoiding insufficient or redundant second storage areas in the backup block. This improves the data backup effect of the backup block, thereby enhancing the computing performance of the in-memory computing unit, and also promotes full utilization of storage space within the in-memory computing unit, while simplifying control logic. As another example, when the in-memory computing unit includes multiple valid blocks, the number of first storage areas in these multiple valid blocks can be the same. This facilitates data read / write control of multiple valid blocks, or computational control of the valid blocks, further improving the computing performance of the in-memory computing unit. In some embodiments, the storage area may include a read / write unit of a storage circuit.

[0072] This application also provides a control method. This control method can be executed by a control device (e.g., the control circuit in the above embodiments). As an example, Figure 4 A schematic diagram of a control method according to an exemplary embodiment of this application is shown.

[0073] like Figure 4 As shown, the control method 400 may include the following steps.

[0074] S410: Read the first data stored in the first storage area of ​​the first valid block in the storage unit.

[0075] S420: If an error occurs in the first data read, the data stored in the first storage area is backed up to the second storage area in the backup block.

[0076] In some embodiments of this application, the first valid block of the in-memory computing unit can be any valid block of the in-memory computing unit. After the control device executes S410 and reads the first data in the first storage area of ​​the first valid block, it can perform verification on the first data and determine whether the first data contains an error. For example, verification can be performed using an error correction code. This application does not limit the type of error correction code; for example, the error correction code can include, but is not limited to, error correction codes (ECC) or low-density parity-check codes (LDPC).

[0077] In step S420, if an error occurs in the first data being read, the control device writes the data stored in the first storage area to the second storage area of ​​the backup block. The data stored in the first storage area is the data that should be correctly stored or correctly read from the first storage area. The control device can correct the first data using error correction codes to obtain the correct data and then write this correct data to the second storage area of ​​the backup block. Alternatively, the control device can obtain the correct data that should be stored in the first storage area from an internal or external data source and then write this correct data to the second storage area of ​​the backup block.

[0078] In some embodiments of this application, after backing up the data stored in the first storage area to the second storage area in the backup block, the control device can control the computing unit to perform calculations, and the second storage area participates in the calculations in place of the first storage area. In this way, the response speed and efficiency of the calculations can be effectively improved.

[0079] In some embodiments of this application, the first storage area in the valid block and the second storage area in the backup block may belong to the same sub-store unit within the storage unit, and the data stored in the same sub-store unit is used for the same calculation. For example, the same sub-store unit includes one or more storage unit groups, and the output terminals of multiple storage units in a storage unit group can be connected collinearly. The multiplication and accumulation calculation of these multiple storage units can be performed as described above. Figure 2As described, the data stored in the same sub-in-memory unit can be used for the same multiply-accumulate calculation. Based on the technical solution of this embodiment, when a read error occurs in the data of the first storage area, the correct data of the first storage area can be backed up to a second storage area located in the same sub-in-memory unit as the first storage area. The correct data can still be used for the calculation of the sub-in-memory unit, which can reduce the impact on the calculation of the in-memory computing system, reduce the backup waiting latency, and help simplify the control logic of the control device, thereby improving the overall calculation efficiency or calculation speed of the in-memory computing system.

[0080] The above implementation method is beneficial for in-memory computing control of storage circuits with high storage density. For example, in some embodiments, the storage circuit may include a three-dimensional storage array, which can have a larger storage density or storage capacity, enabling the in-memory computing system to support larger model deployments. As an example, Figure 5 A schematic diagram of a three-dimensional memory array in a memory circuit according to an exemplary embodiment of this application is shown.

[0081] like Figure 5 As shown, the storage circuit 500 includes a plurality of storage units P1-P1 arranged along the X direction. x Where x is a positive integer greater than 1. A storage unit P u Includes multiple memory cell blocks B arranged along the Y direction u1 -B uy Where u∈[1,x], and y is a positive integer greater than 1. A storage unit block B uv Includes multiple memory cell arrays A arranged along the Z direction uv1 -A uvz Where v∈[1,y], and z is a positive integer greater than 1. Storage cell array A uvw The storage cell array A has a two-dimensional structure. uvw This includes storage cells arranged along the X and Y directions, where w ∈ [1, z]. A storage cell array may include multiple subarrays of storage cells arranged along the Y direction (illustrated as E in the figure), and a subarray of storage cells may include multiple storage cells arranged along the X direction. For example, as shown... Figure 2 The storage cell array 210 shown may include one or more storage cell arrays, and when it includes multiple storage cell arrays, the multiple storage cell arrays may be located in the same storage unit P. u The multiple storage cell arrays are located in different storage cell blocks. In some embodiments, the multiple storage cell arrays may be located in the same storage unit P. u In the same layer along the Z direction, multiple memory cell arrays in that same layer can be referred to as a sub-memory cell (e.g., A shown in the figure). xwA sub-in-memory unit can include multiple groups of memory cells. A group of memory cells can include memory cells from multiple memory cell blocks arranged along the Y direction with the same X-coordinate position. The outputs of these memory cells are collinearly connected and can be used to perform multiply-accumulate calculations. For example, memory cell block B... u1 -B uy The output terminals of storage cells with the same X coordinate located on the same layer in the Z direction can be connected collinearly.

[0082] For ease of distinction, in some embodiments of this application, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction. The X, Y, and Z directions can be any three distinct directions in three-dimensional space. In some examples, any two of the X, Y, and Z directions are perpendicular to each other.

[0083] In some examples, the storage circuitry includes, but is not limited to, NAND flash memory; the storage unit is called, for example, a plane or a bank; the storage unit block is called, for example, a block; and the storage unit subarray is called, for example, a page. This application is not limited thereto, and storage circuitry with different three-dimensional structures may have different names.

[0084] In some embodiments of this application, Figure 5 A storage unit P is shown. u Multiple memory cell arrays located on the same layer in the Z direction can belong to the same sub-memory cell, for example, Figure 5 In-memory computing unit P x Multiple memory cell arrays located in the w-th layer form array A. xw Array A xw They can belong to the same sub-memory unit. This array A xw The storage units in the memory can perform the same calculation, such as a multiply-accumulate calculation.

[0085] Optionally, based on Figure 5 The storage circuit shown can include a storage area within a storage cell block that may include a storage cell subarray. In a plurality of storage cell blocks, the first storage area of ​​a first valid block may include a first storage cell subarray, and the second storage area of ​​a backup block may include a second storage cell subarray. The first and second storage cell subarrays can be at the same layer in the storage circuit, i.e., belong to the same sub-memory unit.

[0086] As an example, Figure 6 A schematic diagram of a memory computing unit according to an exemplary embodiment of this application is shown. Figure 6The following description uses an in-memory computing unit comprising nine storage unit blocks (shown as storage unit blocks B1 to B9 in the figure), wherein the nine storage unit blocks include eight valid blocks (shown as storage unit blocks B1 to B8 in the figure) and one backup block (shown as storage unit blocks B9 / B' in the figure) as an example. The following description is for illustrative purposes only and is not a limitation. In other alternative examples, the number of valid blocks and backup blocks in the in-memory computing unit may be other values, and the position of the backup block in the in-memory computing unit is not limited in this application.

[0087] like Figure 6 As shown in part (a), nine memory cell blocks located in the same layer of memory cells along the Z direction can belong to the same sub-memory cell S. This memory cell can include multiple sub-memory cells arranged along the Z direction.

[0088] like Figure 6 As shown in section (b), in a sub-in-memory unit S, each valid block may include h storage cell subarrays E, which are used to store valid data, where h is a positive integer. Optionally, in a sub-in-memory unit S, the number of storage cell subarrays in a backup block may be the same as the number of storage cell subarrays in a valid block. For example, the backup block B' shown in the figure may also include h storage cell subarrays E, which are used to store empty or invalid data. Alternatively, as an alternative example, in a sub-in-memory unit S, the number of storage cell subarrays in a backup block may be different from the number of storage cell subarrays in a valid block. Optionally, in a sub-in-memory unit S, the number of storage cell subarrays in different valid blocks may also be different.

[0089] exist Figure 6 In the example shown, for a sub-memory unit S, the h storage cell subarrays in backup block B' can be used to provide backup space for the 8h storage cell subarrays in the 8 valid blocks. If the data of q storage cell subarrays in the 8h storage cell subarrays is corrupted, the correct data of the q storage cell subarrays can be backed up to the q storage cell subarrays in backup block B', where q is a positive integer less than or equal to h.

[0090] Through the technical solution of this application embodiment, the backup block can provide backup space for multiple valid blocks in the in-memory computing unit. In the event of an error in the data of any one or more valid blocks' storage cell subarrays, the backup block can be used to back up the correct data for one or more storage cell subarrays, thereby enabling subsequent data reading or computation. This improves the storage accuracy of the storage circuit, and when the storage circuit is used for computation, it can enhance the computational performance of the in-memory computing system. Furthermore, in this implementation, if one or more valid blocks in the in-memory computing unit malfunction, it is not necessary to back up or refresh all the data of those one or more valid blocks. This reduces the data backup or refresh time, facilitating rapid data backup and enabling the in-memory computing unit to respond to computational tasks quickly, thus significantly improving the computational efficiency of the storage circuit.

[0091] The above embodiments are described using a single backup block as an example. The storage unit may also include more backup blocks to provide more backup space for the valid blocks, which can cope with more data errors, postpone the need for overall refresh of the storage unit or storage block in the storage system, reduce the impact on the computing tasks of the storage system, and improve the response speed or efficiency of the storage system to computing tasks.

[0092] During use, storage circuits may experience precision loss, affecting the accuracy of the stored data. Therefore, the data stored in the storage circuit can be refreshed. When storage circuits are applied to in-memory computing systems, precision loss can lead to a decrease in the accuracy of weight data, which may result in a decrease in the accuracy of calculation results and affect the reliability of the in-memory computing system. Therefore, the need to refresh storage circuits in in-memory computing systems still exists to improve the reliability of the system. In some embodiments of this application, the valid data within the in-memory computing unit can be refreshed. The following description is in conjunction with the accompanying drawings.

[0093] Figure 7 A schematic diagram of another control method according to an exemplary embodiment of this application is shown.

[0094] like Figure 7 As shown, the control method 700 may include the following steps.

[0095] S710: Read the first data stored in the first storage area of ​​the first valid block in the storage unit.

[0096] S720, in the event of an error in the first data read, backs up the data stored in the first storage area to the second storage area in the backup block.

[0097] S730, when the refresh conditions are met, controls the refresh of the data stored in the target valid block to the backup block.

[0098] The target valid block is a valid block in the storage unit, which may include the first valid block or other valid blocks.

[0099] In the embodiments of this application, the relevant descriptions of S710 and S720 can be found in the embodiments above.

[0100] For S730, the control device can refresh the data stored in the target valid block to the backup block when the refresh conditions are met. This refresh can include refreshing all or part of the data stored in the target valid block.

[0101] The aforementioned refresh refers to the process of rewriting the data (e.g., weight data) stored in the valid blocks of the storage circuit. This rewriting can be done to a backup block. For example, the data originally stored in the target valid block may lose precision as usage time or frequency increases. Rewriting this data in-place or to other storage blocks restores its initial storage precision. This initial precision is higher than the precision after the target valid block has been used, effectively improving the reliability of the storage system. For instance, assuming the target weight data is 1, when initially written to the target valid block, it has the first precision of initial storage, for example, the equivalent stored weight data is 1.01. As usage time or frequency increases, the storage precision decreases, for example, the equivalent stored weight data changes to 0.6. Rewriting the target weight data to the backup block restores the target weight data to the second precision of initial storage, for example, the equivalent stored weight data is 0.98. This improves the storage precision of the storage circuit.

[0102] Among the above control methods, refresh conditions are used to trigger the refresh of the storage circuit, thereby improving the storage accuracy of the storage circuit during use and thus improving the reliability of the in-memory computing system. Furthermore, by setting backup blocks, while improving storage accuracy, the impact of storage circuit refresh on business can be reduced, thereby improving the overall responsiveness of the in-memory computing system to business.

[0103] In the S730, refresh conditions can include one or more of the following conditions:

[0104] (1) The refresh time for the target valid block or storage unit has arrived;

[0105] (2) The backup block stores backup data in the storage unit subarray of the first sub-storage unit of the storage unit;

[0106] (3) The storage unit includes multiple backup blocks, and the multiple backup blocks store backup data in the storage unit subarray of the first sub-storage unit of the storage unit.

[0107] (4) The backup block stores backup data in the storage cell subarray of the first sub-storage unit of the storage unit, and the second data read from the first sub-storage unit is incorrect;

[0108] (5) The storage unit includes multiple backup blocks. The multiple backup blocks store backup data in the storage unit subarray of the first sub-storage unit of the storage unit, and the second data read from the first sub-storage unit is incorrect.

[0109] Condition (1)

[0110] Refresh triggering methods can include periodic triggering or event triggering. For example, a refresh cycle can be set for the storage blocks within a memory unit. The refresh cycles of the storage blocks within the memory unit are the same, but the refresh start times are different, thus forming a rotating periodic refresh. This simplifies the control logic and ensures a balanced wear level among the storage blocks. Alternatively, event triggering conditions can include the storage block's precision being less than or equal to a precision threshold, or the number of reads or calculations reaching a threshold. This allows for timely refresh of the storage block when its precision decreases to the point where it might affect the computation result. Furthermore, periodic triggering and event triggering can be combined to jointly control the refresh of the memory unit. This application does not restrict the refresh triggering method, as long as the refresh frequency among the storage blocks is as balanced as possible.

[0111] In some implementations, the refresh timing of the target valid block or memory unit can be related to the precision of the target valid block or memory unit. For example, the refresh timing may include: a first precision index exceeding a preset precision index range, wherein the first precision index includes the precision index of the memory unit or the precision index of the target valid block. When the first precision index includes the precision index of the memory unit, the refresh can be initiated based on the precision of the memory unit, and the refresh can be performed in rotation, eliminating the need to perform a refresh condition judgment for each memory unit block, thus simplifying implementation. When the first precision index includes the precision index of the target valid block, the refresh of the corresponding target valid block can be initiated based on the precision of the target valid block, resulting in finer refresh control granularity. This allows for timely refresh of a valid block when its precision decreases, reducing precision degradation caused by premature or late refreshes.

[0112] In some possible embodiments, the first precision index may be acquired periodically. For example, the first precision index is acquired periodically, and when the first precision index exceeds a preset precision index range, the refresh of the target valid block of the memory computing unit is initiated. The target valid block may include any valid block in the memory computing unit, or may include the valid block in the memory computing unit with the longest time since the last refresh, or may include the valid block with the lowest precision in the memory computing unit.

[0113] In some possible embodiments, the first precision indicator may be event-triggered, for example, triggered after the in-memory computing unit continuously executes computational services or after the target valid block continuously executes computational services. Alternatively, it may be triggered based on the runtime of the in-memory computing unit or the target valid block, for example, when the runtime of the in-memory computing unit or the target valid block reaches or exceeds a time threshold.

[0114] The aforementioned first precision index refers to an index that reflects the computational or storage precision of a computing unit or effective block. This application does not limit the type of this index. For example, it may include usage time, number of uses, sampled values ​​of computation results, or bit error rate. Depending on the type of index, exceeding the preset precision index range may include being greater than or equal to the preset precision index threshold, or it may include being less than or equal to the preset precision index threshold.

[0115] In this implementation, by setting a refresh cycle, setting event refresh conditions, or combining cycle refresh and event refresh, the refresh timing of the target valid block or memory unit is determined, thereby dynamically refreshing the memory circuit. This improves the flexibility and timeliness of memory circuit refresh, ensuring that the storage accuracy of the memory circuit remains at a high level, further enhancing the accuracy of calculations, and thus further improving the reliability of the in-memory computing architecture. Furthermore, this scheme can make the wear and tear among the memory unit blocks more even.

[0116] Condition (2)

[0117] See back Figure 6 As shown, in a sub-in-memory unit S (an example of the first sub-in-memory unit), if all h storage cell subarrays of backup block B' store backup data, the refresh condition is met. In this implementation, if all storage cell subarrays of the backup block within a sub-in-memory unit store backup data, then for that sub-in-memory unit, the backup space of the backup block is fully occupied, and subsequent data backup cannot continue. In this case, timely activation of the refresh process to refresh and back up the data stored in the target valid block can reduce errors in the stored data in the target valid block, improve the accuracy of the stored data, and thus further improve the accuracy of the calculation.

[0118] Condition (3)

[0119] Optionally, Figure 6 In the illustrated embodiment, there can be multiple backup blocks B'. Within a sub-memory unit S, the number of storage cell subarrays for different backup blocks B' can be the same or different. As a possible implementation, in a sub-memory unit S, if all storage cell subarrays of multiple backup blocks B' store backup data, then the refresh condition is met.

[0120] In this implementation, multiple backup blocks can provide larger backup storage space for the in-memory unit and its sub-in-memory units, accommodating more erroneous data and improving the computational response speed and efficiency of the in-memory unit. For the sub-in-memory unit, if multiple backup blocks all store backup data in their respective storage subarrays (i.e., the backup space of multiple backup blocks is fully occupied), timely activation of the refresh process to refresh and back up the data stored in the target valid block can reduce errors in the stored data, improve data accuracy, and further enhance computational accuracy.

[0121] Condition (4)

[0122] See Figure 6 As shown, in a sub-memory unit S, if all h storage cell subarrays of backup block B' store backup data, and the data read by the control device from any storage cell subarray or any storage cell block (including backup block and valid block) in the sub-memory unit S is incorrect, then the refresh condition is met.

[0123] In this implementation, the refresh conditions include not only the storage status judgment of the storage unit subarray within a sub-in-memory unit of the backup block, but also the correctness judgment of the read data. Combining the two judgments can make the refresh timing of the target valid block or in-memory unit more accurate, further delaying the need for overall refresh of the in-memory unit or storage unit block in the in-memory computing system, reducing the impact on the computing tasks of the in-memory computing system, and improving the response speed or efficiency of the in-memory computing system to computing tasks.

[0124] Condition (5)

[0125] Optionally, Figure 6 In the illustrated embodiment, the number of backup blocks B' can be multiple. As one possible implementation, in a sub-memory unit S, if all storage cell subarrays of multiple backup blocks B' store backup data, and the data read by the control device from any storage cell subarray or any storage cell block (including backup blocks and valid blocks) in the sub-memory unit S is erroneous, then the refresh condition is met.

[0126] In this implementation, multiple backup blocks can provide larger backup storage space for the in-memory computing unit and its sub-in-memory computing units, accommodating more erroneous data backups and improving the response speed and efficiency of the in-memory computing unit. Furthermore, this implementation allows for more precise timing of refreshes to target valid blocks or in-memory computing units, which helps to further postpone the need for overall refreshes of in-memory computing units or storage unit blocks in the in-memory computing system, reducing the impact on the computing tasks of the in-memory computing system and improving its response speed or efficiency.

[0127] For conditions (2) to (5) above, the storage unit may include multiple sub-storage units, and the sub-storage unit S can be any one of the multiple sub-storage units. When any one or more of the conditions (2) to (5) above are satisfied by any one of the sub-storage units of the storage unit, the control device can control the refresh of the target valid block storage data.

[0128] The target valid block may include any valid block in the in-memory computing unit. In some embodiments, the target valid block may be a subarray of storage cells with the most read errors among multiple storage cell blocks, where a read error refers to an error occurring during the reading of data stored in the storage cell subarray. In some examples, the target valid block may be the one with the earliest read data error among multiple storage cell blocks. In this way, the refresh of the valid block with the most or earliest errors can be prioritized, improving storage accuracy. Under the refresh condition, the data of the target valid block can be refreshed first, reducing the impact of erroneous data in the target valid block on the accuracy of the calculation results of the in-memory computing unit, and thus improving the calculation accuracy of the in-memory computing unit. In some alternative examples, the target valid block may also be other valid blocks in the in-memory computing unit, for example, it may be a valid block specified by a preset rule, which is not limited in this application.

[0129] In some embodiments of this application, the control device can control a single refresh of the in-memory computing unit (e.g., refreshing the storage data of the target valid block in the above embodiment) according to a set rule. For example, the set rule can indicate the order in which storage unit blocks in the in-memory computing unit are used as backup blocks; or, for example, the set rule can indicate the target storage unit block of the storage unit blocks in the in-memory computing unit, etc.; thereby, when the refresh is controlled according to the set rule, the wear degree among the storage unit blocks of the in-memory computing unit is balanced, which can reduce the difference in the lifespan between the storage unit blocks in the in-memory computing unit, reduce the probability of bad blocks, and extend the overall lifespan of the in-memory computing unit.

[0130] Optionally, a single refresh of a storage unit can refresh either a portion of the valid data in the storage unit or all the valid data in the storage unit.

[0131] Refreshing only a portion of valid data takes less time than refreshing all valid data in a single refresh, allowing for timely response to business data processing after a single refresh. For example, in some embodiments, a set rule can be used to instruct the order in which m storage unit blocks are used to store empty or invalid data; wherein the storage unit block currently storing empty or invalid data is called the first storage unit block, and the storage unit block to be stored with empty or invalid data is called the second storage unit block. In a single refresh (e.g., the first refresh), the control device can control the writing of data from the second storage unit block to the first storage unit block according to the set order. This set order can be used to characterize the refresh order of the storage unit blocks. This application does not restrict the refresh setting order, as long as the number of refreshes among the storage unit blocks is as balanced as possible.

[0132] As an example, Figure 8 and Figure 9 Schematic diagrams showing different storage states of a memory computing unit according to exemplary embodiments of this application are provided. Figure 8 and Figure 9 The following description is based on an in-memory computing unit comprising nine storage unit blocks (shown as storage unit blocks B1 to B9 in the figure), and the nine storage unit blocks including one or two backup blocks (shown as storage unit block B' in the figure). The following description is for illustrative purposes only and is not a limitation. In other alternative examples, the number of storage unit blocks and backup blocks in the in-memory computing unit may be other values, and the location of the backup blocks in the in-memory computing unit is not limited in this application.

[0133] like Figure 8 As shown in part (a), in the current state of the in-memory computing unit, storage blocks B1 to B8 store valid data D1 to D8, and storage block B9 stores invalid or empty data. Storage block B9 is the storage block currently storing empty or invalid data (which can be called the first storage block). According to the set rules or set order, storage block B1 is the storage block to be storing empty or invalid data (which can be called the second storage block). According to the set rules, controlling the in-memory computing unit refresh includes: controlling the writing of data from storage block B1 to storage block B9. After the refresh is completed, the storage state of the in-memory computing unit can be as follows: Figure 8 As shown in section (b).

[0134] Setting rules or setting order determines the refresh order between storage unit blocks within a storage unit; in other words, it sets the order in which storage unit blocks store empty or invalid data in turn. The setting order can, for example, include: B1 to B... m The storage cell block currently storing empty or invalid data (referred to as the first storage cell block) is storage cell block B. k At that time, storage unit block B k+1The storage unit block to be stored for empty or invalid data (referred to as the second storage unit block) is defined as follows: k ∈ [1, m], where m is the number of storage unit blocks within the storage unit. When k+1 is greater than the number of storage unit blocks m in the storage unit, for example, when k+1 is greater than 9, the starting storage unit block in this set order is used as the storage unit block to be stored for empty or invalid data, i.e., the second storage unit block. For example, when B9 is the first storage unit block, B1 is the second storage unit block.

[0135] like Figure 9 As shown in section (a), in the current state, storage unit blocks B1 to B7 store valid data D1 to D7, while storage unit blocks B8 and B9 store invalid or empty data. During the first refresh in the current state, storage unit block B8 becomes the first storage unit block, and storage unit block B1 becomes the second storage unit block. According to the set rules, the first refresh of the valid data in the storage unit is controlled, including controlling the writing of data from storage unit block B1 to storage unit block B8. After the first refresh is completed, the storage state of the storage unit can be as follows: Figure 9 As shown in section (b).

[0136] like Figure 9 As shown in section (b), in the current state, storage blocks B2 to B8 store valid data D2 to D7 and D1, while storage blocks B9 and B1 store invalid or empty data. During a refresh in the current state, storage block B9 becomes the first storage block, and storage block B2 becomes the second storage block. According to set rules, the refresh of valid data in the storage unit is controlled, including controlling the writing of data from storage block B2 to storage block B9. After the refresh is complete, the storage state of the storage unit can be as follows: Figure 9 As shown in section (c).

[0137] Optionally, it can be completed in a single refresh. Figure 9 Refreshing sections (b) and (c).

[0138] For example, setting rules or setting order may include: storage cell block group 1; storage cell block group 2; storage cell block group m0, where m0 can be half of m. A storage cell block group includes a number of redundant storage cell blocks. Taking two as an example, the storage cell block currently storing empty or invalid data is storage cell block B. k and B g At that time, storage unit block B k and storage unit block B g For the first storage unit block, storage unit block B k+1 and storage unit block B g+1Let B be the second storage unit block, where k∈[1,m0], g∈[1,m0], and k≠g. When k+1 or g+1 is greater than the number m of storage unit blocks in the storage unit, for example, when k+1 or g+1 is greater than 9, the initial storage unit block group in this set order is used as the storage unit block to store empty or invalid data, that is, the second storage unit block. For example, when storage unit block B8 is the first storage unit block, storage unit block B1 is the second storage unit block; when storage unit block B9 is the first storage unit block, B2 is the second storage unit block.

[0139] In the above embodiments, the first storage unit block can be the backup block in the above embodiments, and the second storage unit block can be the target valid block in the above embodiments.

[0140] Refreshing all valid data is more advantageous for refresh control logic than refreshing only some valid data, and the overall accuracy of the storage and computing units is more consistent. For example, in some embodiments, a set rule can be used to indicate the target storage block for each of m storage block blocks. In one refresh, based on the set rule, the data stored in the storage block currently storing some valid data is written to the target storage block indicated by the set rule, and the target storage block of the storage block currently storing empty or invalid data is controlled to be empty or invalid. In this way, according to the set rule, the valid data of the storage and computing unit can be refreshed in one refresh of the storage and computing unit, reducing the overall number of refreshes of the storage and computing unit and improving the accuracy consistency of the valid data of the entire storage and computing unit.

[0141] Figure 10 A schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application is shown. Figure 10 The following description uses an in-memory computing unit comprising nine storage unit blocks (shown as storage unit blocks B1 to B9 in the diagram), and these nine storage unit blocks including one backup block (shown as storage unit block B' in the diagram), as an example. This description is for illustrative purposes only and is not limiting. In other alternative examples, the number of storage unit blocks and backup blocks in the in-memory computing unit can be other values, and the location of the backup block in the in-memory computing unit is not limited in this application. In this example, the setting rules may include: storage unit block B... k The target storage unit block is storage unit block B. g k∈[1,m], g∈[1,m], and k≠g. For example, g=k+1, and k<m, when k=m, g=1. For example, the target storage unit block of storage unit block B9 is storage unit block B1.

[0142] like Figure 10As shown in part (a), in the current state of the in-memory computing unit, storage blocks B1 to B8 store partially valid data, while storage block B9 is currently storing empty or invalid data. During the first refresh, based on a set rule, the data D1 to D8 stored in storage blocks B1 to B8 are written to the target storage blocks B2 to B9 indicated by the set rule, and the state of target storage block B1 of storage block B9 is controlled to be empty or invalid. After the first refresh is completed, the storage state of the in-memory computing unit can be as follows: Figure 10 As shown in section (b).

[0143] According to some embodiments, the setting rules for the target storage unit block can correspond to the write order of the storage unit blocks. First, data whose target storage unit block is currently storing empty or invalid data is written to that storage unit block. Then, writes are sequentially executed to target storage unit blocks whose data source was from the last write. For example, according to the setting rules, the target storage unit block for storage unit block B8 is storage unit block B9, and storage unit block B8 is the target storage unit block for storage unit block B7. Thus, it is possible to control the writing of data stored in storage unit block B8 to target storage unit block B9 first, and then write the data stored in storage unit block B7 to target storage unit block B8. And so on, thus, a refresh can be completed using the storage unit blocks within the computing unit.

[0144] like Figure 10 As shown in section (b), in the current state, storage unit blocks B2 to B9 store partially valid data, while storage unit block B1 stores either empty or invalid data. During refresh in the current state, based on set rules, the data D1 to D8 stored in storage units B2 to B9 are written to target storage units B3 to B9 and B1 as indicated by the set rules. The state of target storage unit block B2 of storage unit block B1 is controlled to be empty or invalid. After refresh, the storage state of the storage unit can be as follows: Figure 10 As shown in section (c).

[0145] Through the technical solutions described in the above embodiments, during a single refresh of the in-memory computing unit, some or all of the valid data in the in-memory computing unit can be refreshed according to set rules. This not only facilitates wear leveling among multiple storage unit blocks within the in-memory computing unit, but also simplifies refresh control, improves refresh fairness, prevents some storage unit blocks from missing refresh resources, and provides predictability for the refreshed in-memory computing units, thus facilitating the control of computing operations.

[0146] According to some embodiments, a refresh can be performed using storage blocks other than the compute unit. For example, data stored in storage block B8 can be controlled to be written to storage blocks other than storage blocks B1 to B9 first. Then, data stored in storage block B7 can be controlled to be written to the target storage block B8. Subsequently, data stored in storage block B8 can be written to storage block B9 from storage blocks other than storage blocks B1 to B9 at any stage of the first refresh. This improves the flexibility of the refresh.

[0147] In some embodiments of this application, the control device may update the first mapping relationship to a second mapping relationship based on the backup of the data stored in the first storage area of ​​the first valid block. The first mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the first storage area in the first valid block, and the second mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the second storage area in the backup block.

[0148] In some embodiments of this application, the control device may update the third mapping relationship to a fourth mapping relationship based on the refresh of the target valid block storage data. The third mapping relationship is used to indicate the correspondence between the second logical address and the physical address of the target valid block, and the fourth mapping relationship is used to indicate the correspondence between the second logical address and the physical address of the backup block.

[0149] As one possible implementation, the storage circuit can store the first mapping relationship, the second mapping relationship, the third mapping relationship and the fourth mapping relationship described above.

[0150] As an example, the control device can obtain an initial mapping relationship between logical addresses and physical addresses. Based on this initial mapping relationship, the control device can control the writing of data to storage cell regions and storage cell blocks within the storage unit. After data in a storage cell region is backed up, the mapping relationship between the physical and logical addresses of the storage cell region storing the backed-up data can be updated. After data in a storage cell block is refreshed, the mapping relationship between the physical and logical addresses of the storage cell block storing the refreshed data can be updated.

[0151] The above technical solutions enable the recording and maintenance of logical and physical addresses related to valid data, improving the accuracy and reliability of data operations, thereby further enhancing the storage and computing performance of the storage circuit.

[0152] This application embodiment also provides a control device, which may be located in or include the above-mentioned control circuit, and the control device may be located in Figure 1 or Figure 2The control circuit 120 / 220 shown, or independent of the control circuit 120 / 220. This control device can be used to execute any of the above control methods.

[0153] This application also provides a control device, which can be found in the embodiments of this application. Figure 11 . Figure 11 A schematic diagram of a control device according to an exemplary embodiment of this application is shown. Figure 11 As shown, the control device 1100 includes at least one processing circuit 1110 and an interface circuit 1120. The interface circuit 1120 is used for signal connection with a storage circuit, and the at least one processing circuit 1110 is used to execute any of the control methods provided in the above embodiments. The control device 1100 may also include a storage device for storing setting rules. The storage device may include volatile memory or non-volatile memory.

[0154] For example, in some embodiments, the processing circuit may include an application-specific integrated circuit (ASIC), which implements some or all of the functions of the control device by designing the logical relationships between the devices within the circuit; as another example, in some embodiments, the processing circuit may be implemented by a programmable logic device (PLD) circuit, which may include a large number of logic devices, and the logical relationships between the logic devices are configured through a configuration file, thereby implementing some or all of the functions of the control device.

[0155] Optionally, the control device provided in the embodiments of this application can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0156] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, such as a central processing unit (CPU), microcontroller unit (MCU), graphics processing unit (GPU), or digital signal processor. Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), deep learning processing unit (DPU), etc.

[0157] This application also provides a memory computing system, which includes: a memory circuit as described in any of the above embodiments; and a control device for executing any of the control methods described in the embodiments of this application to control the memory circuit.

[0158] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0159] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0160] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0161] This application also provides an electronic device, which can be found in [reference 1]. Figure 12 . Figure 12 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 12 As shown, the electronic device 1200 may include any of the above-mentioned in-memory computing systems 1210 for processing data from the electronic device. The electronic device may also include an input / output device 1220 for receiving user input or outputting processing results. This application does not limit the input and output types; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 1230, which can process data provided to the in-memory computing system 1210 or process the output data of the in-memory computing system 1210. The output of the input / output device 1220 may be based on the output of the processor 1230 or the output of the in-memory computing system 1210.

[0162] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0163] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method, characterized in that, For controlling a storage circuit, the storage circuit includes a storage computing unit, the storage computing unit includes multiple storage unit blocks, the multiple storage unit blocks include a first valid block and a backup block, the control method includes: Read the first data stored in the first storage area of ​​the first valid block; If an error occurs in the first data being read, the data stored in the first storage area is backed up to the second storage area in the backup block.

2. The control method according to claim 1, characterized in that, The second storage area and the first storage area belong to the same sub-in-memory unit, and the data stored in the same sub-in-memory unit is used for the same calculation.

3. The control method according to claim 2, characterized in that, The plurality of storage cell blocks are arranged along a first direction. One of the storage cell blocks includes a multi-layer storage cell array arranged along a third direction. The plurality of storage cell arrays located on the same layer in the third direction belong to the same sub-storage unit. One storage cell array includes a plurality of storage cell sub-arrays arranged along the first direction. One storage cell sub-array includes a plurality of storage cells arranged along a second direction. The first storage area includes a first storage cell subarray of the first valid block, and the second storage area includes a second storage cell subarray of the backup block.

4. The control method according to claim 3, characterized in that, The control method further includes: When the refresh conditions are met, the control refreshes the data stored in the target valid block in the storage unit to the backup block. The refresh conditions include one or more of the following: The refresh timing for the target valid block or the storage unit has arrived; The backup block stores backup data in the storage unit subarray of the first sub-in-memory unit of the storage unit. The backup block stores backup data in the storage unit subarray of the first sub-storage unit of the storage unit, and the second data read from the first sub-storage unit is incorrect; The storage unit includes multiple backup blocks, and each of the multiple backup blocks stores backup data in the storage unit subarray of the first sub-storage unit of the storage unit. The storage and computing unit includes multiple backup blocks, each of which stores backup data in a storage unit subarray within the first sub-storage and computing unit of the storage and computing unit, and the second data read from the first sub-storage and computing unit is erroneous.

5. The control method according to claim 4, characterized in that, The target valid block has the largest number of read-error storage cell subarrays among the multiple storage cell blocks.

6. The control method according to claim 4, characterized in that, The target valid block is the first among the multiple storage unit blocks to experience a read data error.

7. The control method according to any one of claims 1 to 6, characterized in that, Also includes: Based on the backup, the first mapping relationship is updated to a second mapping relationship. The first mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the first storage area, and the second mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the second storage area.

8. The control method according to any one of claims 1 to 7, characterized in that, The number of valid blocks in the storage unit is greater than the number of backup blocks.

9. The control method according to claim 8, characterized in that, The storage unit includes 8 valid blocks and 1 backup block.

10. The control method according to any one of claims 1 to 9, characterized in that, Each of the plurality of storage cell blocks includes the same number of storage areas.

11. The control method according to any one of claims 1 to 9, characterized in that, Also includes: After the backup, the storage unit is controlled to perform calculations, with the second storage area replacing the first storage area in the calculations.

12. A storage circuit, characterized in that, include: The storage and computing unit includes multiple storage unit blocks, each including a valid block and a backup block. The backup block is used to back up the data stored in a first storage area of ​​the valid block, wherein the data in the first storage area contains errors during the reading process.

13. The storage circuit according to claim 12, characterized in that, The second storage area in the backup block is used to back up the data stored in the first storage area. The second storage area and the first storage area belong to the same sub-computing unit, and the data stored in the same sub-computing unit is used for the same calculation.

14. The storage circuit according to claim 13, characterized in that, One of the plurality of storage cell blocks includes a multi-layer storage cell array arranged along a third direction. The plurality of storage cell arrays located on the same layer in the third direction belong to the same sub-storage unit. Furthermore, one storage cell array includes a plurality of storage cell sub-arrays arranged along a first direction, and one storage cell sub-array includes a plurality of storage cells arranged along a second direction. The first storage area includes a first storage cell subarray of the valid blocks, and the second storage area includes a second storage cell subarray of the backup blocks.

15. The storage circuit according to any one of claims 12 to 14, characterized in that, The storage circuit is further configured to store a first mapping relationship before the backup and a second mapping relationship after the backup. The first mapping relationship is used to indicate the correspondence between a first logical address and the physical address of the first storage area, and the second mapping relationship is used to indicate the correspondence between the first logical address and the physical address of the second storage area in the backup block.

16. The storage circuit according to any one of claims 12 to 15, characterized in that, The number of valid blocks in the storage unit is greater than the number of backup blocks.

17. The storage circuit according to claim 16, characterized in that, The storage unit includes 8 valid blocks and 1 backup block.

18. The storage circuit according to any one of claims 12 to 17, characterized in that, Each of the plurality of storage cell blocks includes the same number of storage areas.

19. A control device, characterized in that, include: Interface circuitry used to communicate with storage circuitry; At least one processing circuit is used to perform the control method as described in any one of claims 1 to 11.

20. An in-memory computing system, characterized in that, include: The storage circuit as described in any one of claims 12 to 18; A control device for performing the control method as described in any one of claims 1 to 11 to control the storage circuit.

21. An electronic device, characterized in that, Including the in-memory computing system as described in claim 20.

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