Computing node, computing node cluster, supernode server, and power-on control method

Abstract

The application discloses a kind of computing node, computing node cluster, super node server and power-on control method, it is related to computer technical field, computing node includes adapter plate and multiple baseband board, the first end of adapter plate is connected with mainboard side, the second end of adapter plate is connected with multiple baseband board;Each baseband board includes an acceleration unit and a re-timer;The architecture reduces maintenance loss when single acceleration unit or single re-timer fails, and the architecture makes the connection between the acceleration unit and the re-timer in a single baseband board avoid the case of long-distance wiring;By distributing the management bus and the data bus to each baseband board using the adapter plate, the interconnection of the acceleration units across the board is achieved using multiple serial transceiver links in the adapter plate, avoiding long-distance wiring, reducing the design difficulty of the computing node and improving reliability.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to computing nodes, computing node clusters, supernode servers, and power-on control methods. Background Technology

[0002] In Artificial Intelligence (AI) nodes based on the Open Compute Project (OCP), the Universal Baseband Board (UBB) typically carries multiple OCP Accelerator Modules (OAMs) and multiple physical layer retimers (PHY Retimers). As system complexity increases, the architecture of the UBB with multiple OAMs and PHY Retimers becomes unusable if a single OAM connector to the UBB fails or a single PHY Retimer malfunctions, resulting in poor maintainability. Furthermore, the configuration and management of multiple OAMs and PHY Retimers on the UBB, as well as the transmission of serializer / deserializer (SerDes) signals, involve long-distance wiring, significantly increasing the design complexity of AI nodes and reducing reliability. Summary of the Invention

[0003] This application provides a computing node, a computing node cluster, a supernode server, and a power-on control method to at least solve the problems of poor maintainability, high design difficulty of AI nodes, and low reliability in related technologies.

[0004] This application provides a computing node, including: an adapter board and multiple baseband boards; a first end of the adapter board is connected to the motherboard side, and a second end of the adapter board is connected to the multiple baseband boards; each baseband board includes an acceleration unit and a re-timer; The adapter board is used to distribute the management bus and data bus from the motherboard to each baseband board; The adapter board includes multiple serial transceiver links, which are used to interconnect the first serial transceiver buses of the acceleration units in multiple baseband boards, so as to realize the interconnection of the acceleration units in multiple baseband boards. For any one of the multiple baseband boards, the second serial transceiver bus of the acceleration unit in that baseband board is connected to the retimer in that baseband board. The retimer is used to condition the signals on the second serial transceiver bus and output the conditioned signals to the switch.

[0005] This application also provides a computing node cluster, including: multiple computing nodes and switches of any of the above types; Multiple computing nodes communicate with each other via a switch.

[0006] This application also provides a supernode server, including: multiple computing nodes of any of the above types.

[0007] This application also provides a power-on control method, applied to a transition board in any of the above-described computing nodes, comprising: Receive the power-on command from the motherboard; In response to a power-on command, if any baseband board is detected to be in place, the acceleration unit power supply module in that baseband board is triggered to supply power to the acceleration unit in that baseband board. Upon receiving a power-ready signal from the acceleration unit in any baseband board, the power supply to the retimer in that baseband board is triggered. When the acceleration units and retimers in multiple baseband boards meet the power-on conditions, a power-ready signal is sent to the motherboard so that the motherboard can perform software-level initialization and low-level driver loading for the acceleration units of each baseband board.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described power-on control methods when executing the computer program.

[0009] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described power-on control methods.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described power-on control methods.

[0011] The computing node provided in this application includes an adapter board and multiple baseband cards. The first end of the adapter board is connected to the motherboard, and the second end is connected to the multiple baseband cards. Each baseband card includes an acceleration unit and a re-timer. This architecture reduces maintenance costs in the event of a single acceleration unit or a single re-timer failure. The adapter board distributes the management bus and data bus from the motherboard to each baseband card. The adapter board utilizes multiple serial transceiver links to interconnect the first serial transceiver buses of the acceleration units in the multiple baseband cards, thus achieving interconnection of the acceleration units in the multiple baseband cards and avoiding the need for separate management buses on the baseband cards. The data bus has long interconnections, avoiding long-distance traces for signal transmission between acceleration units. For any baseband board among multiple baseband boards, the second serial transceiver bus of the acceleration unit in that baseband board is connected to the retimer in that baseband board. The retimer is used to condition the signals on the second serial transceiver bus and output the conditioned signals to the switch. The architecture of the baseband board avoids long-distance traces between the acceleration unit and the retimer in a single baseband board. This achieves the technical effect of reducing the design difficulty of computing nodes and improving the reliability of computing nodes. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This application provides a schematic diagram of the structure of a computing node. Figure 2 This is a schematic diagram of the structure of another computing node provided in an embodiment of this application; Figure 3 A flowchart illustrating a power-on control method provided in an embodiment of this application; Figure 4 Power-on timing diagram of the baseband board provided in the embodiments of this application; Figure 5 A flowchart illustrating yet another power-on control method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The rapid development of large language models has led to an exponential increase in the demand for underlying computing power for model training. The traditional node architecture, which is based on a central processing unit (CPU) and connects a small number of graphics processing units (GPUs) through a peripheral component interconnect express (PCIe) bus, faces physical bottlenecks in terms of computing power density, interconnect bandwidth, and system scalability.

[0018] To break down hardware design barriers among manufacturers, the Open Compute Project (OCP) released the OAM specification, which provides a unified and open interface and interconnection standard for AI accelerators and has become a core reference for mainstream AI computing hardware design.

[0019] Meanwhile, the surge in single-node computing power density places stringent demands on the signal integrity of high-speed data interconnects within the system. When ultra-high-speed signals are transmitted over ordinary flame-retardant epoxy glass cloth laminate (Flame Retardant Type 4, FR4) substrates, they are highly susceptible to severe signal attenuation and jitter due to factors such as dielectric loss, switching power supply noise, and channel crosstalk, leading to a deterioration in the bit error rate at the receiver. To overcome the physical limitations of the transmission link, physical layer retimers are widely introduced into high-speed interconnect buses. Through their built-in clock and data recovery (CDR) circuitry, they effectively eliminate signal jitter and compensate for channel loss, regenerating high-quality high-speed signals, thereby ensuring high-bandwidth, low-latency, and low-bit-error-rate interconnect communication within AI nodes.

[0020] In the AI ​​node architecture based on the OCP specification in related technologies, the UBB (User Bundle) can host up to eight OAMs in a pluggable form. The interconnection topology between multiple OAMs is defined by the configuration pin (STRAP PIN) on the UBB. On the data path, this architecture is mainly divided into internal interconnection and external expansion: some high-speed SerDes ports of the OAMs are routed internally through the UBB to achieve a full interconnection topology between multiple OAMs; the remaining high-speed SerDes ports of the OAMs are connected to the corresponding physical layer retimers. The physical layer retimers condition the SerDes signals output from the SerDes ports and send the conditioned SerDes signals to the switch to achieve large-scale cluster expansion across nodes. On the management path, the CPU on the motherboard side transmits PCIe signals through high-density connectors to configure and manage the OAMs, while the out-of-band monitoring and dynamic configuration of the PHY Retimer are independently handled by the Baseboard Management Controller (BMC) on the motherboard side.

[0021] However, as system complexity continues to increase, the architecture of UBB with multiple OAM and multiple PHY Retimers has the following drawbacks: High manufacturing costs and poor maintainability: The architecture of integrating multiple OAM and PHY Retimers onto a single UBB substrate directly leads to a surge in the number of printed circuit board (PCB) layers and a significant increase in manufacturing specifications. During the manufacturing process, yield issues can easily result in substantial cost losses. Furthermore, the OAM interfaces on the UBB typically use high-density crimp connectors. Physical damage to these connectors during production assembly or later maintenance often leads to the scrapping of the entire UBB board or incurring extremely high return-to-factory repair costs. Additionally, PHY Retimer chips generally use Ball Grid Array (BGA) packaging. A single point of failure in a PHY Retimer chip (such as a cold solder joint or short circuit) is not only extremely difficult to repair on-site, but may even require replacing the entire UBB board, resulting in extremely poor maintainability.

[0022] Signal integrity bottleneck caused by long-link traces: Due to the mechanical architecture and physical size of the OAM standard, the management bus and SerDes signals on the UBB board inevitably have long-distance traces. In other words, the configuration and management of multiple OAM and PHY Retimers on the UBB, as well as the transmission of SerDes signals, involve long-distance traces. To compensate for this physical loss, related technologies have to use more expensive ultra-low loss PCB materials and more complex signal conditioning mechanisms. This not only further increases hardware costs, but also greatly increases the design difficulty and uncertainty of AI nodes.

[0023] It should be noted that an AI node can be an AI server, and an AI server can be a graphics processing unit server (GPUBOX).

[0024] To address the aforementioned technical problems, embodiments of this application provide a computing node, which may be a GPUBOX. Figure 1 This is a schematic diagram of the structure of a computing node provided in an embodiment of this application, as shown below. Figure 1 As shown, the computing node includes an adapter board and multiple baseband boards; the first end of the adapter board is connected to the motherboard, and the second end of the adapter board is connected to the multiple baseband boards; each baseband board includes an acceleration unit and a retimer. The baseband board is a UBB. The acceleration unit is an OAM. The retimer is a PHY Retimer.

[0025] The adapter board distributes the management bus and data bus from the motherboard to each baseband board. The management bus includes the System Management Bus (SMBus). The data bus includes the peripheral interconnect bus. The system management bus is implemented based on the Inter-Integrated Circuit Bus (I2C). The system management bus is used for addressing, status acquisition, and parallel management of multiple different baseband boards. Specifically, it is used for out-of-band acquisition of status information such as temperature of the OAM and PHY Retimer, and supports software configuration of related devices, such as initializing the PHY Retimer, including configuring the transmitter equalization (Txeq) parameters. The peripheral interconnect bus is used for data transmission, such as data transfer between the motherboard and the OAM.

[0026] The main function of the adapter board is to enable high-speed expansion of uplink resources and centralized distribution of underlying control signals.

[0027] The adapter board includes multiple serial transceiver links, which are used to interconnect the first serial transceiver buses of the acceleration units in multiple baseband boards, so as to realize the interconnection of the acceleration units in multiple baseband boards.

[0028] Among them, multiple serial transceiver links are high-speed traces used to interconnect the first serial transceiver buses of acceleration units in multiple baseband boards, thereby realizing the interconnection of acceleration units in multiple baseband boards and providing a direct data interaction channel for acceleration units in different baseband boards to transmit SerDes signals between multiple acceleration units. The serial transceiver bus is also known as the SerDes bus.

[0029] For any one of the multiple baseband boards, the second serial transceiver bus of the acceleration unit in that baseband board is connected to the retimer in that baseband board.

[0030] The second serial transceiver bus is used for the transmission of SerDes signals between the acceleration unit and the retimer.

[0031] The motherboard sends the model training task to the adapter board, which then sends it to the target acceleration unit. The target acceleration unit processes the model training task. During this process, the target acceleration unit typically needs to interact with other acceleration units to obtain collaborative service data, which is represented by SerDes signals. These other acceleration units can be located on the same compute node as the target acceleration unit or not. When other acceleration units are not on the same compute node as the target acceleration unit, data interaction requires retimer and switch connections. When other acceleration units are on the same compute node as the target acceleration unit, data interaction is achieved through multiple serial transceiver links on the adapter board.

[0032] The retimer is used to condition the signals on the second serial transceiver bus and output the conditioned signals to the switch.

[0033] Specifically, the retimer performs jitter cancellation and channel loss compensation on the SerDes signal on the second serial transceiver bus to regenerate a high-quality, high-speed signal. The conditioned SerDes signal is then output to the switch via an eight-channel Octal Small Form-factor Pluggable (OSFP) interface or a four-channel Quad Small Form-factor Pluggable (QSFP) interface, and then transmitted by the switch to the acceleration units in other computing nodes.

[0034] Understandably, the baseband board communicates directly with the switch via an OSFP or QSFP interface.

[0035] The computing node provided in this embodiment includes an adapter board and multiple baseband boards. The first end of the adapter board is connected to the motherboard, and the second end is connected to the multiple baseband boards. Each baseband board includes an acceleration unit and a re-timer. This architecture reduces maintenance costs and manufacturing costs in the event of a single acceleration unit or re-timer failure. The adapter board distributes the management bus and data bus from the motherboard to each baseband board. The adapter board uses multiple serial transceiver links to interconnect the first serial transceiver buses of the acceleration units in the multiple baseband boards, thus achieving interconnection of the acceleration units in the multiple baseband boards and avoiding the need for baseband board interconnection. The management bus and data bus have long interconnections, avoiding long-distance traces for signal transmission between acceleration units. For any baseband board among multiple baseband boards, the second serial transceiver bus of the acceleration unit in that baseband board is connected to the retimer in that baseband board. The retimer is used to condition the signal on the second serial transceiver bus and output the conditioned signal to the switch. The architecture of the baseband board avoids long-distance traces between the acceleration unit and the retimer within a single baseband board, achieving the technical effect of reducing the design difficulty of computing nodes and improving the reliability of computing nodes. The baseband board architecture provided in this embodiment realizes the physical isolation and collaborative operation of high-density computing power and high-speed signal compensation.

[0036] In some alternative implementations, for any one of a plurality of baseband boards, the baseband board includes a first mezzanine connector and a second mezzanine connector, and the acceleration unit in the baseband board is connected to the baseband board through the first mezzanine connector and the second mezzanine connector.

[0037] Figure 2 This is a schematic diagram of the structure of a computing node provided in an embodiment of this application, as shown below. Figure 2 As shown, the baseband board includes a first mezzanine connector and a second mezzanine connector. The first mezzanine connector and the second mezzanine connector (Mezzanine, abbreviated as Mezz) are used for physical carrying and electrical connection of the acceleration unit. Figure 2 The example assumes that a computing node includes two baseband boards, but in practice, a computing node may include more baseband boards and is not limited to this.

[0038] To ensure system standard compatibility and connectivity, the OAM interface network on the baseband board strictly adheres to OAM2.0 and subsequent specifications. In other words, the first and second mezzanine connectors conform to a preset interface specification, which is OAM2.0 and subsequent specifications.

[0039] The computing node provided in this embodiment carries the acceleration unit by using a first mezzanine connector and a second mezzanine connector that conform to OAM2.0 and subsequent specifications. While ensuring standard compatibility and system connectivity, it realizes the pluggable, maintainable and high-density integration of the acceleration unit on the baseband board.

[0040] In some alternative implementations, such as Figure 2 As shown, the adapter board also includes a first connector and a switching module. The first end of the first connector is connected to the motherboard side, and the second end of the first connector is connected to the first end of the switching module. The first connector is a high-speed connector, and the switching module is a PCIe switch.

[0041] The first connector is used to receive peripheral interconnect bus resources on the motherboard side.

[0042] The peripheral interconnect bus resource is the fifth-generation high-speed peripheral interconnect bus (PCIe Gen5) resource. This peripheral interconnect bus resource can be PCIe bus bandwidth resource.

[0043] The switching module is used to expand the peripheral interconnect bus resources received by the first connector into multiple peripheral interconnect bus resources, and to transmit the multiple peripheral interconnect bus resources to multiple baseband boards respectively.

[0044] Each baseband board is used to transmit received peripheral interconnect bus resources to the acceleration unit within that baseband board.

[0045] The computing node provided in this embodiment receives PCIe Gen5 resources from the motherboard through the first connector on the adapter board, expands them into multiple PCIe resources using a PCIe Switch, and then sends them to multiple baseband cards. Each baseband card then supplies its acceleration unit with these resources. Thus, a single set of motherboard-side PCIe resources enables the PCIe connection and configuration management of multiple baseband cards and acceleration units, improving the expansion capability of the PCIe bus resources.

[0046] In some alternative implementations, such as Figure 2 As shown, the adapter board also includes multiple second connectors. The second end of the switching module connects to the first ends of the multiple second connectors. Specifically, the switching module is used to transmit multiple peripheral interconnect bus resources to multiple baseband boards via the multiple second connectors. The second connectors are high-speed connectors.

[0047] In other words, the adapter board receives PCIe Gen5 resources from the motherboard through the high-speed connector at the front end, and uses the onboard PCIe switch module to exchange and expand the bus channels downwards. Then, it transmits the resources to multiple baseband cards through multiple high-speed connectors at the rear end.

[0048] The baseband board includes a third connector. The second ends of multiple second connectors on the adapter board are respectively connected to the first ends of the third connectors on the multiple baseband boards. The third connector is a high-speed connector. It can be understood that the first connector is connected to the switching module via a PCIe bus, the switching module is connected to the multiple second connectors via a PCIe bus, and the third connector in any baseband board is connected to the acceleration unit in that baseband board via a PCIe bus, for configuration and management of the acceleration unit on the motherboard side.

[0049] The computing node provided in this embodiment establishes multiple PCIe physical connections between the switching module and each baseband board by setting multiple second connectors on the adapter board and a third connector on the baseband board. This enables the PCIe resources on the motherboard side to be allocated to each acceleration unit via the path of "first connector → switching module → multiple second connectors → multiple third connectors → acceleration unit", thereby realizing the configuration and management of acceleration units in multiple baseband boards on the motherboard side.

[0050] In some alternative implementations, the third connector is a high-speed connector.

[0051] For any baseband board, the second end of the third connector of the baseband board is connected to the first serial transceiver bus of the acceleration unit in the baseband board.

[0052] Multiple serial transceiver links are specifically used to connect multiple second connectors to interconnect the first serial transceiver buses of acceleration units in multiple baseband boards, thereby realizing the interconnection of acceleration units in multiple baseband boards.

[0053] Understandably, a serial transceiver link is connected to two different second connectors to enable the connection of the first serial transceiver bus of the acceleration unit in the baseband board to which these two second connectors are connected.

[0054] The computing node provided in this embodiment sets a high-speed third connector on the baseband board, leads the first serial transceiver bus of the acceleration unit to the third connector, and uses multiple serial transceiver links inside the adapter board to interconnect multiple second connectors, thereby establishing a high-speed serial transceiver interconnection channel between acceleration units of multiple baseband boards and realizing the interconnection of acceleration units across baseband boards.

[0055] In some alternative implementations, the second end of the first connector is connected to the first end of a plurality of second connectors.

[0056] The first connector is used to receive the system management bus from the motherboard side and fan out the received system management bus into multiple system management buses; through multiple second connectors, the multiple system management buses are routed to multiple baseband cards respectively.

[0057] Each baseband board is used to route the received system management bus to the acceleration unit and retimer within that baseband board.

[0058] Understandably, the first connector is connected to multiple second connectors via a system management bus. For any given baseband board, the third connector of that baseband board is connected to the acceleration unit and retimer of that baseband board via the system management bus.

[0059] The computing node provided in this embodiment receives the system management bus from the motherboard side through the first connector and fans it out into multiple paths. These paths are then routed to multiple baseband boards through multiple second connectors. Each baseband board then routes the system management bus to its internal acceleration unit and PHYRetimer, thereby enabling unified out-of-band management of the acceleration units and PHYRetimer in multiple baseband boards from the motherboard side.

[0060] In some alternative implementations, such as Figure 2 As shown, the adapter board also includes a first logic unit; the first end of the first connector is connected to the second logic unit on the motherboard side. The logic unit is a Complex Programmable Logic Device (CPLD).

[0061] The second end of the first connector is connected to the first end of the first logic unit via a serial input / output bus, and the second end of the first logic unit is connected to the first ends of multiple second connectors.

[0062] Among them, the serial input / output bus is the Serial General Purpose Input / Output (SGPIO) bus.

[0063] The CPLD on the motherboard and the CPLD on the adapter board are deeply integrated using the SGPIO bus to achieve low-latency state synchronization and control signal pass-through across boards.

[0064] The second logic unit is used to acquire the status information of each baseband board sent by the first logic unit and to send control signals of each baseband board to the first logic unit.

[0065] The first logic unit is used to receive control signals for each baseband board sent by the second logic unit, and to output control signals to each baseband board in parallel.

[0066] Understandably, the adapter board is equipped with an independent CPLD device, namely the first logic unit. This first logic unit acts as the logic control center, used to output a group of control signals (CPLD_Signals) of uniform specifications to each baseband board in parallel, and to coordinate the execution of baseband board presence identification, power-on / off timing management and status monitoring.

[0067] The computing node provided in this embodiment uses a first logic unit on an adapter board and a serial input / output bus between the first connector and the second logic unit on the motherboard side to communicate. The second logic unit obtains the status information of each baseband board and sends control signals, while the first logic unit outputs control signals to multiple baseband boards in parallel, thereby realizing centralized status monitoring and parallel logic control of multiple baseband boards on the motherboard side.

[0068] In some alternative implementations, the second end of the first connector is connected to the first end of the first logic device via input / output pins, so that the second logic device can perform low-level logic debugging and status monitoring on the first logic device.

[0069] The input / output pins are general purpose input / output (GPIO) pins. The second end of the first connector is also connected to the first end of the first logic device via input / output pins, allowing the second logic device on the motherboard side to perform low-level logic debugging and status monitoring of the first logic device.

[0070] In some alternative implementations, the second end of the first connector is connected to the first end of the first logic device via an integrated circuit bus, so that the second logic device can address, acquire and manage the status of the first logic device.

[0071] The second end of the first connector is also connected to the first end of the first logic device via an I2C bus, so that the second logic device on the motherboard side can address, acquire and manage the status of the first logic device.

[0072] In some alternative implementations, such as Figure 2 As shown, for any one of the multiple baseband boards, the baseband board also includes an acceleration unit power supply module and a retimer power supply module.

[0073] The acceleration unit power supply module in the baseband board is connected to the acceleration unit in the baseband board and is used to supply power to the acceleration unit in the baseband board.

[0074] The retimer power supply module in the baseband board is connected to the retimer in the baseband board and is used to supply power to the retimer in the baseband board.

[0075] In some alternative implementations, such as Figure 2 As shown, for any one of multiple baseband boards, the baseband board also includes a flash memory module, which is connected to the retimer in the baseband board. The flash memory module is connected to the retimer in the baseband board via a Serial Peripheral Interface (SPI).

[0076] The flash memory module is used to store the optimal link tuning parameters for the retimers in this baseband board. These optimal link tuning parameters include low-level analog parameters, such as transmitter equalization parameters.

[0077] During the engineering verification and system debugging phase, the system dynamically issues commands through the BMC's I2C management interface to fine-tune the underlying analog parameters of the PHY Retimer, such as the transmitter equalization, to compensate for physical link losses and achieve zero-error (BER=0) transmission between the OAM and PHY Retimer under extreme conditions. Once the optimal link tuning parameter combination between the OAM and PHY Retimer has been verified through a long series of tests, the system can permanently burn this optimal link tuning parameter combination into the firmware of the PHY Retimer's external flash memory. After this, the physical layer retimer can achieve fully autonomous, high-quality initialization upon each power-on, relying on the firmware. The BMC can then smoothly exit the underlying physical layer retimer initialization process, significantly reducing the resource overhead of the management bus and overcoming the error challenge caused by channel insertion loss at ultra-high speeds.

[0078] The retimer is used to retrieve the optimal link tuning parameters from the flash module each time power is applied, and to complete the initialization based on the optimal link tuning parameters.

[0079] During system power-up, the PHY Retimer proactively reads the underlying firmware and basic initialization configuration from the external Flash memory via the SPI protocol. This firmware and basic initialization configuration includes optimal link tuning parameters. Simultaneously, the BMC connects via the I2C bus, facilitating link training between the OAM and the PHY Retimer at the SerDes physical layer, thereby completing the PHY Retimer's initialization.

[0080] In some optional implementations, the voltage levels of the configuration pins on the baseband board conform to a preset configuration pin specification. The voltage level combinations of the configuration pins are used to characterize the acceleration unit identifier, enabling the motherboard to accurately identify the acceleration unit. The preset configuration pin specification is OAM2.0 and later specifications.

[0081] In addition, OAM's Universal Asynchronous Receiver / Transmitter (UART) diagnostic interface performs protocol conversion through the first logic unit, bridges to the Universal Serial Bus (USB) protocol, and leads out to the MicroUSB physical interface reserved on the adapter board, providing a convenient channel for obtaining the underlying log and out-of-band diagnostics.

[0082] In some alternative implementations, the second serial transceiver bus includes multiple serial transceiver channels corresponding to multiple target serial transceiver ports in the acceleration unit.

[0083] To address the massive data interaction requests, this application plans for full utilization of the OAM network interface resources. Specifically, the two sets of ports output by OAM are aggregated into 16 high-speed data channels directly connected to the PHY Retimer. After signal debouncing and clock recovery, the data is transmitted to the OSFP interface. The other ports output by OAM transmit data back to the uplink adapter board via high-density connectors. Using the direct-connection traces within the adapter board, cross-board interaction with other computing nodes is achieved, i.e., cross-board interaction with acceleration units in other baseband boards.

[0084] This data network topology perfectly balances the need for full interconnection between nodes in the horizontal (Scale-Out) direction while satisfying the vertical (Scale-Up) cluster expansion requirements.

[0085] To address the issues of severe signal attenuation and high maintenance costs in related technologies, this application proposes a novel architecture for a mini-UBB (mini-UBB) that integrates a single OAM module and a single PHY Retimer. This architecture highly integrates a high-density OAM mezzanine connector, a dedicated OAM power supply module, and a PHY Retimer chip with a matching power supply, significantly shortening high-speed signal traces. For external interconnection, the UBB front end interconnects with a high-speed adapter board via a high-density connector, while the back end communicates directly with external switching networks via OSFP or QSFP interfaces. Furthermore, this application decouples and centrally deploys management bus peripheral devices on the adapter board, significantly reducing PCB routing complexity while physically ensuring that all control signals of the miniUBBs in the system originate from the same source, greatly optimizing signal integrity and overcoming the bottleneck of high-speed physical links.

[0086] Based on this highly integrated architecture, this application further designs a comprehensive intelligent identification, hot-swapping, and dynamic link re-establishment mechanism. When the CPLD in the adapter board detects that the UBB board is physically present, it will first output standby power to read the UBB board's identification code for compatibility verification. After the compatibility verification is passed, the corresponding voltage regulator enable signal will be output strictly according to the preset timing sequence to ensure the safe and smooth power-on of the UBB board.

[0087] Furthermore, the embodiments of this application can quickly realize the underlying handshake and protocol reconstruction of high-speed data links and management buses when UBB boards are hot-swapped or power states are switched, effectively avoiding service interruptions, improving system security and hot-swappable fault tolerance, and significantly improving the operational reliability and subsequent maintenance efficiency of AI server clusters.

[0088] The technical solution provided in this application can be applied across different fields to baseband processing (BBU) or edge computing devices for 5G / 6G mobile communications.

[0089] Embodiments of this application also provide a computing node cluster, including multiple computing nodes and switches. The computing nodes are the computing nodes in any of the above embodiments.

[0090] Multiple computing nodes communicate with each other via a switch.

[0091] In other words, for any baseband board, the SerDes signal output by the acceleration unit in the baseband board is conditioned by the re-timer in the baseband board and then output to the switch through the OSFP interface, and then transmitted to other computing nodes through the switch.

[0092] Embodiments of this application also provide a supernode server, including multiple computing nodes. The computing nodes are the computing nodes in any of the above embodiments.

[0093] A supernode server is a computing system that is physically composed of multiple computing nodes tightly connected by an efficient interconnect protocol, possesses unified memory addressing capabilities across physical nodes, and logically appears as a single computing system to upper-layer software and users. The efficient interconnect protocol may include a memory coherent interconnect protocol bus, which is a high-speed interconnect protocol that can achieve cache coherency and support memory sharing among multiple devices. It may include, but is not limited to, the Compute Express Link (CXL) bus and the Cache Coherent Interconnect for Accelerators (CCIX) bus.

[0094] The embodiments of this application also provide a power-on control method, applied to a transition board in the computing node provided in any of the above embodiments, specifically applied to a first logic unit in the transition board. Figure 3 This is a flowchart illustrating the power-on control method provided in an embodiment of this application, as shown below. Figure 3 As shown, the power-on control method includes the following steps: Step S301: Receive the power-on command sent from the motherboard side.

[0095] Step S302: In response to the power-on command, if any baseband board is detected to be in place, the acceleration unit power supply module in the baseband board is triggered to supply power to the acceleration unit in the baseband board.

[0096] Step S303: After receiving a power-on-ready signal from the acceleration unit in any baseband board, the power supply of the retimer in the baseband board is triggered.

[0097] In step S304, when the acceleration units and retimers in multiple baseband boards meet the power-on conditions, a power-on ready signal is sent to the motherboard side so that the motherboard side performs software-level initialization and low-level driver loading for the acceleration units of each baseband board.

[0098] The power-on conditions are that the power supply status of the acceleration unit is stable and the power supply status of the retimer is stable.

[0099] For intelligent power-on control of UBB, this application designs a cascaded hardware power-on state machine based on the CPLD of the adapter board. When the motherboard issues a power-on command and the CPLD of the adapter board physically detects that the board is in place, the system first prioritizes powering the OAM module by triggering the corresponding electronic fuse (eFuse). Only after receiving the power-good signal from the OAM module will the CPLD trigger the PHYRetimer according to logical dependencies. After the power supply of each high-power hardware module reaches a stable state and the state closed loop is confirmed, the physical layer power-on sequence safely ends, the uplink is then established and handed over to the motherboard CPU, and the OAM software-level initialization and underlying driver loading are officially started, thereby realizing an efficient power-on process that takes into account both transient surge protection and safe link establishment.

[0100] To make the power-on control method clearer, combined with Figure 4 Describe, Figure 4 The power-on timing diagram of the baseband board provided in the embodiments of this application is as follows: Figure 4 As shown, the mainboard CPLD starts first, controlling the power switch of the baseband board to turn on via the adapter board CPLD. The adapter board CPLD continues to operate, first enabling the baseband board power protection, then enabling the acceleration unit power protection. After the baseband board power protection is ready, power is supplied to the acceleration unit on the baseband board. The adapter board CPLD confirms whether the acceleration unit is power-ready. If the acceleration unit is power-ready, the adapter board CPLD enables the power supply of the retimer. Power is supplied to the retimer on the general-purpose board. The adapter board CPLD confirms whether the retimer is power-ready.

[0101] In some optional implementations, the power-on control method described above further includes: If the acceleration unit or retimer in any baseband board fails to meet the power-on conditions, an abnormal message is sent to the motherboard so that the motherboard can perform abnormal troubleshooting and handling.

[0102] Embodiments of this application also provide a power-on control method. Figure 5 This is a flowchart illustrating the power-on control method provided in an embodiment of this application, as shown below. Figure 5 As shown, the power-on control method includes the following steps: The baseband board is inserted into the adapter board.

[0103] The CPLD in the adapter board detects a low in-situ signal from the baseband board via its in-situ detection pin and begins outputting enable signals for each voltage regulator according to a preset timing sequence. The voltage regulators include a power supply module for the acceleration unit and a power supply module for the retimer.

[0104] The CPLD in the adapter board receives the power-on ready signal returned by each voltage regulator and determines whether the power-on conditions are met. If not, the engineer adjusts the system according to the status register of the CPLD in the adapter board until the power-on conditions are met. Then, the CPLD in the adapter board notifies the CPLD on the main board that the baseband board has been powered on.

[0105] If the conditions are met, the CPLD in the adapter board notifies the CPLD on the main board that the baseband board has been powered on.

[0106] Determine if the CPU has successfully initialized OAM. If successful, it will work normally. If it fails, the engineer will troubleshoot according to the status register of the CPLD in the adapter board.

[0107] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, it includes a processor 601 and a memory 602, in which a computer program is stored. The processor 601 is configured to run the computer program to perform the steps in any of the above-described power-on control method embodiments.

[0108] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described power-on control method embodiments when it is run.

[0109] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0110] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described power-on control method embodiments.

[0111] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described power-on control method embodiments.

[0112] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0113] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] The foregoing has provided a detailed description of a computing node, computing node cluster, supernode server, and power-on control method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A computing node, characterized in that, include: An adapter board and multiple baseband boards; a first end of the adapter board is connected to the motherboard side, and a second end of the adapter board is connected to the multiple baseband boards; each baseband board includes an acceleration unit and a re-timer; The adapter board is used to distribute the management bus and data bus on the motherboard side to each of the baseband boards; The adapter board includes multiple serial transceiver links, which are used to interconnect the first serial transceiver buses of the acceleration units in the multiple baseband boards, so as to realize the interconnection of the acceleration units in the multiple baseband boards. For any one of the plurality of baseband boards, the second serial transceiver bus of the acceleration unit in the baseband board is connected to the retimer in the baseband board; The retimer is used to condition the signals on the second serial transceiver bus and output the conditioned signals to the switch.

2. The computing node according to claim 1, characterized in that, For any one of the plurality of baseband boards, the baseband board includes a first mezzanine connector and a second mezzanine connector, and the acceleration unit in the baseband board is connected to the baseband board through the first mezzanine connector and the second mezzanine connector.

3. The computing node according to claim 2, characterized in that, The first mezzanine connector and the second mezzanine connector conform to a preset interface specification.

4. The computing node according to claim 1, characterized in that, The adapter board also includes a first connector and a switching module, wherein a first end of the first connector is connected to the motherboard side, and a second end of the first connector is connected to the first end of the switching module. The first connector is used to receive peripheral interconnect bus resources on the motherboard side; The switching module is used to expand the peripheral interconnect bus resources received by the first connector into multiple peripheral interconnect bus resources, and to transmit the multiple peripheral interconnect bus resources to the multiple baseband boards respectively; Each of the baseband boards is used to deliver received peripheral interconnect bus resources to the acceleration unit in the baseband board.

5. The computing node according to claim 4, characterized in that, The adapter board also includes multiple second connectors; The second end of the switching module is connected to the first end of the plurality of second connectors. Specifically, the switching module is used to transmit the multi-channel peripheral interconnect bus resources to the plurality of baseband boards through the plurality of second connectors.

6. The computing node according to claim 1, characterized in that, The adapter board also includes multiple second connectors, and the baseband board includes a third connector; The second ends of the multiple second connectors of the adapter board are respectively connected to the first ends of the third connectors of multiple baseband boards; For any baseband board, the second end of the third connector of the baseband board is connected to the first serial transceiver bus of the acceleration unit in the baseband board; The multiple serial transceiver links are specifically used to connect the multiple second connectors to interconnect the first serial transceiver buses of the acceleration units in the multiple baseband boards, thereby realizing the interconnection of the acceleration units in the multiple baseband boards.

7. The computing node according to claim 1, characterized in that, The adapter board further includes a first connector and a plurality of second connectors; a first end of the first connector is connected to the motherboard side, and a second end of the first connector is connected to the first end of the plurality of second connectors. The first connector is used to receive the system management bus on the motherboard side and fan out the received system management bus into multiple system management buses; The multiple system management buses are routed to the multiple baseband boards via the multiple second connectors. Each of the baseband boards is used to route the received system management bus to the acceleration unit and retimer in that baseband board.

8. The computing node according to claim 1, characterized in that, The adapter board further includes a first connector, a first logic unit, and multiple second connectors; the first end of the first connector is connected to the second logic unit on the motherboard side. The second end of the first connector is connected to the first end of the first logic device via a serial input / output bus, and the second end of the first logic device is connected to the first end of the plurality of second connectors; The second logic unit is used to acquire the status information of each baseband board sent by the first logic unit and to send control signals of each baseband board to the first logic unit. The first logic unit is used to receive control signals sent by the second logic unit to each of the baseband boards, and to output the control signals to each of the baseband boards in parallel.

9. The computing node according to claim 1, characterized in that, The adapter board further includes a first connector and a first logic device; a first end of the first connector is connected to a second logic device on the motherboard side. The second end of the first connector is connected to the first end of the first logic device via input / output pins, so that the second logic device can perform low-level logic debugging and status monitoring on the first logic device.

10. The computing node according to claim 1, characterized in that, The adapter board further includes a first connector and a first logic device; a first end of the first connector is connected to a second logic device on the motherboard side. The second end of the first connector is connected to the first end of the first logic device via an integrated circuit bus, so that the second logic device can address, acquire and manage the status of the first logic device.

11. The computing node according to claim 1, characterized in that, For any one of the plurality of baseband boards, the baseband board further includes an acceleration unit power supply module and a re-timer power supply module; The acceleration unit power supply module in the baseband board is connected to the acceleration unit in the baseband board and is used to supply power to the acceleration unit in the baseband board. The retimer power supply module in the baseband board is connected to the retimer in the baseband board and is used to supply power to the retimer in the baseband board.

12. The computing node according to claim 1, characterized in that, For any one of the plurality of baseband boards, the baseband board further includes a flash memory module, which is connected to the retimer in the baseband board; The flash memory module is used to store the optimal link tuning parameters of the retimer in the baseband board. The retimer is used to obtain the optimal link tuning parameters from the flash memory module each time power is supplied, and to complete the initialization based on the optimal link tuning parameters.

13. The computing node according to claim 1, characterized in that, The level definitions of the configuration pins in the baseband board conform to the preset configuration pin specifications. The level combinations of the configuration pins are used to characterize the acceleration unit identifier, so that the motherboard can accurately identify the acceleration unit.

14. The computing node according to claim 1, characterized in that, The second serial transceiver bus includes multiple serial transceiver channels corresponding to multiple target serial transceiver ports in the acceleration unit.

15. A computing node cluster, characterized in that, Includes multiple computing nodes and switches as described in any one of claims 1 to 14; The multiple computing nodes communicate with each other through the switch.

16. A supernode server, characterized in that, It includes multiple computing nodes as described in any one of claims 1 to 14.

17. A power-on control method, characterized in that, A adapter board used in a computing node as described in any one of claims 1 to 14, comprising: Receive the power-on command from the motherboard; In response to the power-on command, if any baseband board is detected to be in place, the acceleration unit power supply module in the baseband board is triggered to supply power to the acceleration unit in the baseband board. Upon receiving a power-ready signal from the acceleration unit in any baseband board, the power supply to the retimer in that baseband board is triggered. When the acceleration units and retimers in multiple baseband boards meet the power-on conditions, a power-ready signal is sent to the motherboard side so that the motherboard side can perform software-level initialization and low-level driver loading for the acceleration units of each baseband board.

18. The method according to claim 17, characterized in that, The method further includes: If the acceleration unit or retimer in any baseband board fails to meet the power-on conditions, an abnormal signal is sent to the motherboard so that the motherboard can perform abnormal troubleshooting and handling.

19. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the power-on control method as described in any one of claims 17 to 18.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the power-on control method as described in any one of claims 17 to 18.

21. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the power-on control method as described in any one of claims 17 to 18.

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