Prefetch read method, electronic device, and storage medium

Abstract

The application discloses a prefetch read method, an electronic device and a storage medium, relates to the technical field of multi-core particle architecture optimization, and comprises the following steps: in response to a read operation request, target data is inquired in a local cache, and a query result is determined; if the query result meets a preset prefetch condition, the read operation request is sent to a D2D interface; according to the read operation request, a consistency check request is sent to a consistency point, and a prefetch read request is sent to a memory controller; the consistency check request is processed by the consistency point, a consistency check result is obtained and sent to the D2D interface, the prefetch read request is processed by the memory controller, prefetch read data is obtained and sent to the D2D interface; and according to the consistency check result and the prefetch read data, the target data is determined and sent to a central processing unit core. The application effectively reduces the overall delay of the read operation and improves the memory access performance of the Chiplet architecture processor system.

Description

Technical Field

[0001] This application relates to the field of multi-core architecture optimization technology, and in particular to a prefetching method, electronic device and storage medium. Background Technology

[0002] In the current field of processor chip design, with the continuous growth of computing demands, the traditional monolithic architecture, which integrates all functional modules on a single chip, faces challenges such as declining yield, rising costs, and limited design flexibility. Chiplet architecture has emerged to address this challenge. It breaks down the traditional monolithic chip into multiple functionally independent chips, interconnected via a die-to-die (D2D) interface, to achieve higher manufacturing yields, lower development costs, and more flexible design combinations. (See reference...) Figure 1 In a typical Chiplet processor architecture, there are usually core complex dies (CCDs) that carry the central processing unit (CPU) core and level 3 (L3) cache, and I / O dies (IODs) that carry the point of coherence (PoC) and double data rate (DDR) memory controllers. The CCD and I / O dies are physically connected and transfer data through a D2D interface.

[0003] Currently, when the CPU core initiates a read operation, the read request first accesses the L3 cache. If the L3 cache is missed, the read request needs to be forwarded to the Point of Consistency (PoC) on the I / O chip via the D2D interface. The PoC performs a cache consistency check to determine the consistency status of the target cache line in other core composite chips. After the consistency check is completed, the consistency point forwards the read request to the memory controller, which reads the target data from external DDR memory. The read data is then returned to the CPU core along the original path. The overall latency of the above read operation process is relatively large, limiting the memory access performance of the processor system.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a prefetch method, electronic device, and storage medium that effectively reduces the overall latency of read operations and significantly improves the memory access performance of Chiplet architecture processor systems.

[0006] To achieve the above objectives, this application proposes a prefetching method, comprising: In response to a read operation request sent by the CPU core of the current chip, the target data is retrieved from the local cache and the query result is determined; If the query results meet the preset prefetch conditions, a read operation request is sent to the D2D interface; Based on the read operation request, a consistency check request is sent to the consistency point via the D2D interface, and a prefetch read request is sent to the memory controller. Consistency check requests are processed through consistency points, consistency check results are obtained and sent to the D2D interface, and prefetch requests are processed through the memory controller, prefetch data is obtained and sent to the D2D interface. Based on the consistency check results and prefetched data, the target data is determined through the D2D interface and then sent to the central processing unit core.

[0007] In one embodiment, the D2D interface includes a prefetch logic module. The steps of sending a consistency check request to the consistency point and a prefetch read request to the memory controller through the D2D interface according to the read operation request include: The prefetch logic module parses the read operation request to obtain the target cache line address. Based on the target cache line address, a consistency check request and a prefetch read request are generated according to the preset D2D interface protocol. The consistency check request includes an opcode to indicate the execution of a cache consistency check, and the prefetch read request includes a command identifier to indicate the execution of a prefetch read operation. A consistency check request is sent to the consistency point, and a prefetch request is sent to the memory controller.

[0008] In one embodiment, the step of processing a consistency check request through a consistency point, obtaining a consistency check result, and sending it to the D2D interface includes: The consistency check request is parsed through the consistency point to obtain the target cache line address. Based on the opcode, the cache state of the target cache line address in each core except the current core is determined. Based on the cache state, the consistency check result is generated. Send the consistency check results to the D2D interface.

[0009] In one embodiment, the D2D interface includes a prefetch buffer. The steps of processing prefetch requests through a memory controller, obtaining prefetch data, and sending it to the D2D interface include: The memory controller parses the prefetch request to obtain the target cache line address. Based on the command identifier, the cache line data corresponding to the target cache line address is determined to be the prefetch data. Send the prefetched data to the prefetch buffer.

[0010] In one embodiment, the step of determining the target data through the D2D interface based on the consistency check results and prefetched data includes: The consistency check results are parsed using the D2D interface to obtain the cache state; When the cache state indicates that the target cache line address does not exist in the first chip, or the target cache line address is in a read-only state in each of the first chips, the prefetched data is determined as the target data. Here, the first chip is the chip in the chip system other than the current chip.

[0011] In one embodiment, after parsing the consistency check result through the D2D interface to obtain the cache state, the method further includes: When the cache state indicates that the target cache line address is in an exclusive state or a modified state in any first core, the prefetched data is marked as invalid; Based on the target cache line address, a data retrieval request is generated and sent to the first core corresponding to the target cache line address. The target data is then queried and sent to the central processing unit core.

[0012] In one embodiment, after the steps of sending a consistency check request to the consistency point and a prefetch read request to the memory controller according to the read operation request via the D2D interface, the method further includes: Dynamically monitor the consistency check results and the return order of the pre-fetched data; If the consistency check result arrives at the D2D interface before the prefetched data, the consistency check result is parsed through the D2D interface to obtain the cache state. When the target cache line address in the cache state characterization consistency check result does not exist in the first core, or the target cache line address is in a read-only state in each first core, the receive data path of the D2D interface is configured to bypass mode. In bypass mode, when the prefetch data arrives at the D2D interface, the prefetch data is sent to the central processing unit core as the target data through the D2D interface.

[0013] In one embodiment, after the step of sending a read operation request to the D2D interface, the method further includes: The read operation request is parsed using the D2D interface to obtain the target cache line address; Match the target cache line address with the address labels of each valid entry in the prefetch buffer of the D2D interface; When the target cache line address matches the address label of any valid entry, the corresponding cache line data is read from the matched valid entry and sent to the central processing unit core as the target data.

[0014] In addition, to achieve the above objectives, this application also proposes an electronic device, including: a memory and a processor, the processor being capable of executing the steps of the prefetch method as described above.

[0015] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the prefetch method described above.

[0016] The one or more technical solutions proposed in this application have at least the following technical effects: By responding to a read operation request sent by the CPU core of the current core, the target data is queried in the local cache and the query result is determined. The fast access characteristics of the local cache are utilized to avoid unnecessary cross-core access. If the query result meets the preset prefetch conditions, a read operation request is sent to the D2D interface, triggering the cross-core prefetch read process. According to the read operation request, the D2D interface sends a consistency check request to the consistency point and a prefetch read request to the memory controller, so that the consistency check at the consistency point no longer blocks the data reading of the memory controller, and the DDR memory access can be initiated in advance, thereby effectively shortening the read operation path. The consistency check request is processed by the consistency point, the consistency check result is obtained and sent to the D2D interface, and the prefetch read request is processed by the memory controller, the prefetch read data is obtained and sent to the D2D interface. According to the consistency check result and the prefetch read data, the target data is determined by the D2D interface and sent to the CPU core. This ensures that the system can return the correct target data to the CPU core regardless of the consistency check result, while taking into account both the correctness of the read operation and performance optimization. This application effectively reduces the overall latency of read operations and significantly improves the memory access performance of Chiplet architecture processor systems. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a typical Chiplet processor architecture; Figure 2 This is a schematic diagram of the traditional read request processing flow; Figure 3This is a flowchart illustrating the prefetching method in an embodiment of this application. Figure 1 ; Figure 4 This is a schematic diagram of the Chiplet processor architecture for the prefetch method in an embodiment of this application; Figure 5 This is a flowchart illustrating the prefetching method in an embodiment of this application. Figure 2 ; Figure 6 This is a timing comparison diagram of the prefetch read operation path and the traditional read operation path in the embodiments of this application; Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the prefetching method in the embodiments of this application.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] Currently, referring to Figure 1 and Figure 2 When the CPU core initiates a read request, it first queries the L3 cache. If the L3 cache misses, the read request needs to be sent to the Proof-of-Concept (PoC) via the D2D interface. The PoC performs a cache consistency check to determine the consistency status of the target cache line in other CCDs. After the consistency check is completed, the PoC forwards the read request to the DDR memory controller, which reads the data from external DDR memory and returns the read data to the CPU core. In the above read operation process, the consistency check and DDR memory read are executed in a strictly serial order. The read operation can only be initiated after the consistency point has completed the consistency check and confirmed the data status. This delays DDR memory access, resulting in a significant overall latency for the read operation and limiting the memory access performance of the processor system.

[0024] This application provides a solution that, in response to a read operation request sent by the CPU core of the current core, queries the target data in the local cache and determines the query result, leveraging the fast access characteristics of the local cache to avoid unnecessary cross-core access. If the query result meets the preset prefetch conditions, a read operation request is sent to the D2D interface, triggering a cross-core prefetch read process. The D2D interface, based on the read operation request, sends a consistency check request to the consistency point and a prefetch read request to the memory controller, ensuring that the consistency check at the consistency point no longer blocks data reading from the memory controller, allowing memory access to be initiated earlier, thus effectively shortening the read operation path. The consistency check request is processed at the consistency point, obtaining the consistency check result and sending it to the D2D interface. The prefetch read request is processed by the memory controller, obtaining the prefetch read data and sending it to the D2D interface. The D2D interface, based on the consistency check result and the prefetch read data, determines the target data and sends it to the CPU core, ensuring that regardless of the consistency check result, the system can return the correct target data to the CPU core, while simultaneously balancing the correctness of the read operation and performance optimization. This application effectively reduces the overall latency of read operations and significantly improves the memory access performance of Chiplet architecture processor systems.

[0025] It should be noted that the executing entity of this embodiment can be an electronic device, chip system, or the like capable of implementing the above functions. The following description uses a chip system as an example to illustrate this embodiment and the subsequent embodiments.

[0026] Based on this, the first aspect of the embodiments of this application provides a prefetching method, referring to... Figure 3 The prefetching method includes steps S10 to S50: Step S10: In response to the read operation request sent by the central processing unit core of the current chip, query the target data in the local cache and determine the query result; Optionally, the central processing unit (CPU core) is the core unit in the chip system responsible for instruction execution and computation, and it is connected to the local cache via an internal bus. The local cache includes multiple levels of cache; taking the L3 cache as an example, the L3 cache is the last level of cache on the chip, located between the CPU core and main memory. It provides a shared data cache for multiple CPU cores, and its access speed is much higher than that of main memory. A read request is an access request issued by the CPU core when it needs to read data from memory during instruction execution. The target data is the data content that the CPU core requests to read.

[0027] In one feasible embodiment, when the CPU core needs to read data, it first sends a read operation request to the L3 cache. After receiving the request, the L3 cache checks its storage space for the existence of the corresponding target data based on the address information carried in the request, and determines the query result, i.e., whether the target data is hit in the L3 cache. By prioritizing the query of the L3 cache before accessing main memory, the fast access characteristics of the L3 cache can be utilized, and data can be returned directly when a cache hit occurs, thereby avoiding unnecessary cross-core access and main memory access, and reducing read operation latency.

[0028] Step S20: If the query result meets the preset prefetching conditions, a read operation request is sent to the D2D interface; Optionally, the preset prefetch condition is the basis for determining whether a prefetch read process needs to be initiated for the current read operation. The preset prefetch condition includes, but is not limited to: the target data is not found in the local cache; the target data is found in the local cache but has been marked as a prefetch candidate (e.g., predicted to be accessed based on historical access patterns). This embodiment does not limit the specific content of the preset prefetch condition.

[0029] Optionally, the D2D interface is the physical layer and data link layer interface connecting the CCD and the I / O core, responsible for request forwarding, data transmission, and response return.

[0030] In one feasible embodiment, when the query result in step S10 meets the preset prefetching conditions, such as the target data not being hit in the last level cache (e.g., L3 cache), it indicates that the target data is not in the L3 cache of the current core and needs to be obtained from other storage levels. At this time, a read operation request is sent to the D2D interface to trigger the cross-core data acquisition process.

[0031] Step S30: Based on the read operation request, send a consistency check request to the consistency point and a prefetch read request to the memory controller through the D2D interface; Optionally, a consistency check request is a message used to request the execution of a cache consistency check, the purpose of which is to determine the consistency status of target data in the caches of other cores. A prefetch request is a special type of read request command used to instruct the memory controller to prefetch target data from external memory and return the data to the D2D interface for temporary storage, rather than directly returning it to the CPU core. The memory controller can be a DDR memory controller, a High Bandwidth Memory (HBM) memory controller, a Low Power Double Data Rate (LPDDR) memory controller, or a Compute Express Link (CXL) memory controller; this embodiment does not limit this to any particular type.

[0032] In one feasible embodiment, taking a DDR memory controller as an example, the D2D interface does not simply forward read operation requests to a single target. Instead, based on the received read operation requests, it simultaneously generates and sends requests to two different targets: on the one hand, it sends a consistency check request to the consistency point to trigger the cache consistency check process; on the other hand, it sends a prefetch read request to the DDR memory controller to trigger the DDR memory prefetch read process. Through this method, consistency checks and DDR memory reads are transformed from serial execution to parallel execution. DDR memory access can be initiated in advance without waiting for the consistency check to complete, thereby effectively shortening the read operation path.

[0033] Step S40: Process the consistency check request through the consistency point, obtain the consistency check result and send it to the D2D interface; process the prefetch request through the memory controller, obtain the prefetch data and send it to the D2D interface. Optionally, a point of consistency (PoC) is the management unit of the cache consistency protocol, responsible for maintaining the consistency state between caches in each die of the entire chip system and between the cache and main memory. The consistency check result is the information returned by the consistency point after performing a cache consistency check, which includes the cache state of the target cache line in other dies. Prefetch data is the cache line data read from external memory by the memory controller in response to a prefetch request.

[0034] In one feasible embodiment, the two requests issued in step S30 are processed separately. After receiving the consistency check request, the consistency point performs a cache consistency check, obtains the consistency check result, and sends the result back to the D2D interface. After receiving the prefetch request, the DDR memory controller reads the corresponding cache line data from the external DDR memory as prefetch data and sends the data to the D2D interface. The two processes are independent and executed in parallel, further improving the parallelism of the read operation.

[0035] In step S50, the target data is determined based on the consistency check results and prefetch data through the D2D interface, and the target data is sent to the central processing unit core.

[0036] Optionally, the target data is the data content that is ultimately returned to the CPU core.

[0037] In one feasible embodiment, after receiving the consistency check result from the consistency point and the prefetch data from the memory controller, the D2D interface determines the validity of the prefetch data based on the cache state indicated by the consistency check result: if the consistency check result indicates that the prefetch data is consistent with the latest data in the system, the prefetch data is determined as the target data; if the consistency check result indicates that the prefetch data is outdated, the latest data is obtained through other paths as the target data. Through this method, the D2D interface can ensure that regardless of the consistency check result, the target data ultimately returned to the CPU core is correct and valid, while simultaneously considering both the correctness of the read operation and performance optimization. Subsequently, the D2D interface sends the determined target data to the CPU core, completing the read operation.

[0038] In one feasible implementation, the D2D interface includes a prefetch logic module. Step S30, which involves sending a consistency check request to the consistency point and a prefetch read request to the memory controller based on the read operation request via the D2D interface, may include steps S31-S32: Step S31: The read operation request is parsed by the prefetch logic module to obtain the target cache line address. Based on the target cache line address, a consistency check request and a prefetch read request are generated according to the preset D2D interface protocol. The consistency check request includes an opcode for indicating the execution of a cache consistency check, and the prefetch read request includes a command identifier for indicating the execution of a prefetch read operation. Optionally, the prefetch logic module is a newly added functional submodule in the D2D interface. It is responsible for intercepting read requests from the local cache, managing the initiation of prefetch requests, the determination of consistency results, and the validity control of prefetched data. A cache line is the basic unit of data exchange between the cache and main memory, and each cache line has a unique address identifier. The target cache line address is the address information of the cache line containing the target data accessed by the read operation request.

[0039] Optionally, the D2D interface protocol is the communication protocol specification followed by the D2D interface, defining the message format, command type, and transmission rules for requests and responses. The opcode is a command encoding used to indicate what operation the receiving end should perform; in this step, the opcode is used to instruct the consistency point to perform a cache consistency check. The command identifier is a flag used to distinguish different read request types; in this step, the command identifier indicates that the memory controller is performing a prefetch read operation rather than a normal read operation, and is a command type added to the command field of the D2D interface protocol in this embodiment of the application.

[0040] In one feasible embodiment, after receiving a read operation request, the prefetch logic module parses the request, extracts the target cache line address, and generates two requests according to a preset D2D interface protocol. When generating a consistency check request, the target cache line address and an opcode indicating the execution of a cache consistency check are included in the request, enabling the consistency point to identify the type of the request and perform the corresponding check operation. When generating a prefetch read request, the target cache line address and a command identifier indicating the execution of a prefetch read operation are included in the request, enabling the memory controller to distinguish between normal read requests and prefetch read requests, and to route the read data to the prefetch buffer instead of the normal return path based on the command identifier.

[0041] Step S32: Send the consistency check request to the consistency point and the prefetch request to the memory controller.

[0042] In one feasible embodiment, the consistency check request generated in step S32 is sent to the consistency point via the physical link of the D2D interface, while the prefetch request is sent to the memory controller via the physical link of the D2D interface. The two requests are issued through their respective transmission paths, enabling the consistency point and the memory controller to process their respective received requests in parallel.

[0043] In steps S31-S32 above, the prefetch logic module obtains the target cache line address by parsing the read operation request once, and generates two independent requests—a consistency check request and a prefetch read request—based on the same address, enabling the consistency check and memory read to be executed in parallel. Compared to the current scheme that must wait for the consistency check to complete before initiating a memory read, this embodiment advances memory access to be performed simultaneously with the consistency check, eliminating the serial blocking of memory read by the consistency check, effectively shortening the path length of the read operation, and reducing the overall latency of the read operation.

[0044] In one feasible implementation, step S40, which involves processing the consistency check request through a consistency point, obtaining the consistency check result, and sending it to the D2D interface, includes steps S41-S42: Step S41: Parse the consistency check request through the consistency point to obtain the target cache line address. Based on the opcode, determine the cache state of the target cache line address in each core except the current core. Based on the cache state, generate the consistency check result. Optionally, cache state is used to characterize the existence and read / write permissions of the target cache line in the caches of other cores. Cache states include, but are not limited to: the target cache line does not exist in other cores (i.e., no copy of the cache line is stored in the cache of other cores), the target cache line is in a read-only state in other cores (i.e., other cores hold a read-only copy of the cache line, and the copy is consistent with the data in main memory), and the target cache line is in an exclusive state or a modified state in other cores (i.e., a certain other core holds an exclusive copy of the cache line, and the copy has been modified and is inconsistent with the data in main memory). This embodiment does not limit the specific classification and naming of cache states.

[0045] In one feasible embodiment, after receiving a consistency check request from the D2D interface, the point of consensus (PoC) parses the request and extracts the target cache line address to determine the specific cache line location targeted by this consistency check. After identifying that this is a cache consistency check operation based on the opcode in the consistency check request, it determines the cache state of the cache line corresponding to the target cache line address in all kernels except the current kernel by querying the consistency directory or using other consistency check methods, and generates a consistency check result carrying this cache state information.

[0046] Step S42: Send the consistency check result to the D2D interface.

[0047] In one feasible embodiment, the consistency check result is sent to the D2D interface through a preset feedback signal path so that the D2D interface can subsequently determine the validity of the pre-fetched data.

[0048] In steps S41-S42 above, the target cache line address is obtained by parsing the consistency check request using PoC, and a cache consistency check is performed according to the opcode. After determining the cache status of the target cache line in other cores, the result is fed back to the D2D interface. Through this method, the D2D interface can obtain the consistency check result in real time, providing a basis for subsequently determining the validity of prefetched data and ensuring the completeness of the correctness of the prefetch read operation.

[0049] In one feasible implementation, the D2D interface includes a prefetch buffer. Step S40, which involves processing the prefetch request through the memory controller, obtaining the prefetch data, and sending it to the D2D interface, includes steps S401-S402: Step S401: The prefetch request is parsed by the memory controller to obtain the target cache line address. Based on the command identifier, the cache line data corresponding to the target cache line address is determined to be the prefetch data. Optionally, the memory controller is a hardware module responsible for managing data read and write interactions with external memory.

[0050] In one feasible embodiment, after receiving a prefetch request from the D2D interface, the memory controller parses the request and extracts the target cache line address to determine which address of data needs to be read from memory. Based on the command identifier in the prefetch request, it identifies that this operation is a prefetch operation rather than a normal read operation. Then, based on the target cache line address, it reads the corresponding complete cache line data from external memory and uses this data as the prefetch data. Since the goal of the prefetch operation is to obtain data in advance for subsequent use, the reading granularity is a complete cache line, consistent with the reading granularity of a normal read operation.

[0051] Step S402: Send the prefetch data to the prefetch buffer.

[0052] Optionally, the prefetch buffer is a new hardware structure added to the D2D interface, used to temporarily store prefetched data returned by the memory controller. The prefetch buffer can adopt a set-associative or fully associative structure, containing multiple entries. Each entry stores the data of a cache line, its corresponding address label, and validity flag. The prefetch buffer manages its storage space using a preset replacement strategy. When the number of stored entries reaches its capacity limit, if new prefetched data needs to be written to the prefetch buffer, the least recently used or earliest stored entry is selected from the prefetch buffer and replaced according to a least recently used or first-in-first-out strategy to free up storage space for the new prefetched data. Furthermore, entries marked as invalid can be replaced preferentially to improve storage space utilization efficiency.

[0053] In one feasible embodiment, after identifying the current operation as a prefetch read based on the command identifier, the prefetch read data read in step S401 is sent to the prefetch buffer for temporary storage through the physical link of the D2D interface, instead of being sent directly to the local cache or CPU core on the CCD side. This allows the D2D interface to quickly determine the validity of the data and perform corresponding processing based on the result after the consistency check is returned. At the same time, the valid data in the prefetch buffer can be reused by subsequent read requests, further improving system performance.

[0054] The improvements in this application's embodiments focus on the D2D interface module. These improvements are achieved by adding a prefetch logic module and a prefetch buffer to this module and extending the D2D interface protocol. Other aspects require little or no modification. The extension of the D2D interface protocol is implemented by adding a prefetch read command type, which is compatible with the current protocol command format. Therefore, the changes to the protocol stack are limited, resulting in good backward compatibility. Furthermore, the prefetch buffer, as a newly added hardware storage structure, only needs to store a small number of cache line entries (e.g., 4-16 cache line entries). Its hardware area overhead is approximately 0.1% to 0.5% of the local cache area, having a minimal impact on the overall chip area, demonstrating good feasibility and cost-effectiveness.

[0055] In steps S401-S402 above, the memory controller parses the prefetch request to obtain the target cache line address, identifies the prefetch operation based on the command identifier, and reads the complete cache line data from external memory as prefetch data. This data is then sent to the prefetch buffer for temporary storage. Through this method, the prefetch data is read from memory in advance and temporarily stored in the D2D interface. This allows the data to be immediately retrieved from the prefetch buffer and returned to the CPU core when the consistency check result is returned and the data is deemed valid, without waiting for memory read latency, effectively reducing the overall latency of the read operation.

[0056] Alternatively, in addition to being independently configured in the D2D interface, the prefetch buffer can also be implemented in conjunction with the last-level cache. In this implementation, the prefetch buffer is configured as a special storage area or reserved path within the last-level cache. Prefetched data is stored in the reserved path in the same manner as regular cache lines, and its lifecycle is managed uniformly by the local cache's inherent replacement strategy (such as the least recently used strategy). Address tag matching also reuses the existing comparator of the last-level cache. This implementation reduces the overhead of additional independent storage hardware.

[0057] Optionally, the prefetch buffer can also be implemented using a multi-level configuration. In this implementation, prefetch buffers are set on both the CCD side and the I / O side of the D2D interface, forming a two-level prefetch structure. The I / O-side prefetch buffer receives and temporarily stores the prefetched read data returned by the memory controller; the CCD-side prefetch buffer is used to respond to data returns with a shorter distance and faster speed when subsequent read requests are hit. This two-level prefetch structure shortens both the write path latency of prefetched data from the memory controller to the D2D interface and the read path latency of prefetched data from the D2D interface to the CPU core, further optimizing the system's memory access performance.

[0058] In one feasible implementation, step S50, which involves determining the target data based on the consistency check result and the prefetched data via the D2D interface, includes steps S51-S52: Step S51: Parse the consistency check results through the D2D interface to obtain the cache status; In one feasible embodiment, after receiving the consistency check result from the consistency point, the D2D interface parses the result and extracts the cache status information of the target cache line address in other cores. The cache status is the basis for the D2D interface to determine whether the prefetched data is valid. By parsing the consistency check result to obtain the cache status, the D2D interface can know the distribution of the target data among the cores in the system and the freshness of the data, providing a decision-making basis for subsequently determining the validity of the prefetched data.

[0059] Step S52: When the cache state indicates that the target cache line address does not exist in the first chip, or the target cache line address is in a read-only state in each of the first chips, the prefetch data is determined as the target data, wherein the first chip is a chip in the chip system other than the current chip.

[0060] In one feasible embodiment, the determination is performed based on the cache status parsed in step S51. When the cache status indicates that the target cache line address does not exist in the first core (other cores), it means that the caches of other cores do not store a copy of the cache line, and the data in main memory is the latest valid data. When the cache status indicates that the target cache line address is in a read-only state in other cores, it means that although other cores hold copies of the cache line, they have not modified the data, and the data in main memory is consistent with the data in the caches of each core, which is also the latest valid data. In both of the above cases, the prefetched data temporarily stored in the prefetch buffer is marked as valid, and the prefetched data is directly determined as the target data.

[0061] In steps S51-S52 above, the cache state is obtained by parsing the consistency check result. When the cache state indicates that the target cache line does not exist in other cores or only exists in other cores and is in a read-only state, the prefetched data is determined as the target data. Through this method, when the consistency check result indicates that the prefetched data is valid, the D2D interface can directly use the data pre-read from external memory as the target data and return it to the CPU core without waiting for additional data fetching operations. This allows the latency optimization brought by parallel prefetching to be fully realized, effectively reducing the overall latency of read operations.

[0062] In one feasible implementation, after step S51, where the consistency check result is parsed through the D2D interface to obtain the cache state, steps S53-S54 are further included: Step S53: When the cache state characterizes the target cache line address as either exclusive or modified in any first core, mark the prefetched data as invalid. Optionally, the exclusive state means that a copy of the target cache line exists only in the cache of another kernel, and that kernel has exclusive access to the cache line. The modified state means that the copy of the target cache line in the cache of another kernel has been modified, but the modification has not yet been written back to main memory, so the data in main memory is outdated.

[0063] In one feasible embodiment, when the cache state indicates that the target cache line is in an exclusive or modified state in any other core, it means that the data in main memory may not be the latest data, and the prefetch data temporarily stored in the prefetch buffer is inconsistent with the latest data in the system. The D2D interface marks the corresponding prefetch data in the prefetch buffer as invalid to avoid incorrectly returning outdated data to the CPU core.

[0064] Step S54: Based on the target cache line address, generate a data retrieval request and send it to the first core corresponding to the target cache line address; query the target data and send it to the central processing unit core.

[0065] In one feasible embodiment, since the prefetched data has been marked as invalid, the correct target data needs to be obtained from the core holding the latest data. A data retrieval request is generated based on the target cache line address and sent to the CPU core of the target core holding the latest data. Upon receiving the data retrieval request, the CPU core of the target core reads the corresponding latest data from its cache and sends the data back to the CPU core of the current core that initiated the request via the appropriate return path, thus completing the read operation.

[0066] In steps S53-S54 above, when the cache state indicates that the target cache line is in an exclusive or modified state in any other kernel, the prefetched data is marked as invalid, and the target data is retrieved again from the kernel holding the latest data. This ensures that even if the prefetched data is outdated, the system can still obtain the latest valid data through the correct path of the consistency protocol, guaranteeing that read operations will never return outdated data under any circumstances. This achieves performance optimization while maintaining the correctness and completeness of cache consistency semantics.

[0067] In one feasible implementation, after step S30, which involves sending a consistency check request to the consistency point and a prefetch read request to the memory controller via the D2D interface based on the read operation request, the method further includes steps A10 to A30: Step A10: Dynamically monitor the consistency check results and the return order of the prefetched data; In one feasible embodiment, since the consistency check request and the prefetch request are issued in parallel, and the processing latency of the consistency check (typically 10~20 ns) differs significantly from the read latency of external memory (typically 50~80 ns), the timing of the two responses returning to the D2D interface may vary depending on the specific processing situation. In this step, after the D2D interface issues two requests, its receiving channel is continuously monitored to dynamically detect which one arrives at the D2D interface first: the consistency check result or the prefetch data.

[0068] Step A20: If the consistency check result arrives at the D2D interface before the prefetched data, then the consistency check result is parsed through the D2D interface to obtain the cache state. In one feasible embodiment, when the D2D interface detects that the consistency check result is returned before the prefetched data, the D2D interface immediately parses the consistency check result and extracts the cache state information so as to know the determination result of the data validity in advance before the prefetched data arrives.

[0069] Step A30: When the target cache line address in the cache state characterization consistency check result does not exist in the first core, or the target cache line address is in read-only state in each first core, the receive data path of the D2D interface is configured to bypass mode, so that in bypass mode, when the prefetch data arrives at the D2D interface, the prefetch data is sent to the central processing unit core as target data through the D2D interface.

[0070] Optionally, bypass mode is a data transmission mode of the D2D interface. In bypass mode, the receiving data path of the D2D interface is configured to be pass-through, and when data arrives, it is directly forwarded to the target end without additional temporary storage and reading operations.

[0071] In one feasible embodiment, when the cache state obtained in step A20 indicates that the prefetched data is valid (i.e., the target cache line does not exist in other cores, and / or is only in read-only state in other cores), its receiving data path is pre-configured to bypass mode, so that when the prefetched read data arrives at the D2D interface, the data is no longer written to the prefetch buffer and then read, but the prefetched read data is directly sent to the CPU core of the current core through the D2D interface as the target data, thereby further reducing the first-level pipeline latency.

[0072] In steps A10-A30 above, the return order of consistency check results and prefetched data is dynamically monitored. When the consistency check result returns before the prefetched data and indicates that the prefetched data is valid, the receiving data path is pre-configured to bypass mode. This allows the prefetched data to be directly forwarded to the CPU core upon arrival, without needing to go through the two steps of writing to the prefetch buffer and subsequent reading. By using this method, under the condition that the consistency check result returns earlier, the data return latency of read operations can be further reduced, improving system performance.

[0073] In one feasible implementation, after step S20, which involves sending a read operation request to the D2D interface, steps B10 to B30 are further included: Step B10: Parse the read operation request through the D2D interface to obtain the target cache line address; In one feasible embodiment, the data temporarily stored in the prefetch buffer can not only serve the original read request that triggered the prefetch, but can also be reused by other subsequent read requests. When the D2D interface receives a read operation request, the D2D interface parses the request and extracts the target cache line address so that it can subsequently query whether valid data corresponding to that address already exists in the prefetch buffer.

[0074] Step B20: Match the target cache line address with the address labels of each valid entry in the prefetch buffer of the D2D interface; In one feasible embodiment, each valid entry in the prefetch buffer includes an address tag field to record the address information corresponding to the cache line data stored in that entry. A valid entry refers to a prefetch buffer entry that has been marked as valid (i.e., the consistency check result has been returned and the data has been determined to be valid). In this step, the target cache line address parsed in step B10 is compared and matched one by one with the address tags of each valid entry in the prefetch buffer.

[0075] Step B30: When the target cache line address matches the address label of any valid entry, the corresponding cache line data is read from the matched valid entry, and the cache line data is sent to the central processing unit core as the target data.

[0076] In one feasible embodiment, when the match is successful in step B20, it indicates that the data corresponding to the target cache line address already exists in the prefetch buffer and is valid data. The corresponding cache line data can be directly read from the valid entry that has been successfully matched, and the data can be sent to the CPU core as the target data to complete the read operation. There is no need to send a consistency check request to the consistency point, nor is it necessary to send a prefetch read request or a normal read request to the memory controller.

[0077] In steps B10-B30 above, after parsing the read operation request to obtain the target cache line address, this address is matched with the address tags of each valid entry in the prefetch buffer. When a match is successful, the cache line data is directly read from the prefetch buffer as the target data and returned to the CPU core. Through this method, subsequent read requests can directly hit the valid data already temporarily stored in the prefetch buffer, eliminating the need to perform cross-core consistency checks and DDR memory access procedures again. This further reduces the average memory access latency and achieves a cumulative optimization effect of one prefetch, multiple benefits.

[0078] For example, refer to Figure 4 and Figure 5The prefetch process in this application operates within a Chiplet processor architecture that includes a CCD and I / O chips. The CCD integrates the CPU core and L3 cache, the D2D interface integrates prefetch logic and a prefetch buffer, and the I / O chips integrate a PoC and a DDR memory controller. The DDR memory is externally connected to the DDR memory controller. First, the CPU core initiates a read request, which is sent to the L3 cache. The L3 cache is queried to determine the query result. If the query result is a hit, the data is directly returned to the CPU core, completing the read request. If the query result is a miss, two requests are sent via the D2D interface: one is a prefetch read request to the DDR memory controller, and the other is a consistency check request to the PoC. Upon receiving the prefetch read request, the DDR memory controller reads the corresponding data from the DDR memory and temporarily stores the data in the prefetch buffer. Upon receiving the consistency check request, the PoC performs a cache consistency check to determine the cache state corresponding to the target data. When PoC determines that the cache status is non-existent / read-only, the prefetched data in the prefetch buffer is valid, and the data in the prefetch buffer is returned to the CPU core to complete the read request; when PoC determines that the cache status is exclusive / modified, the prefetched data is invalid, the request is resent, the target data is queried in the corresponding core cache, and the data is returned to the CPU core.

[0079] To verify the effectiveness of the prefetch method in the embodiments of this application, refer to Figure 6 , Figure 6 The memory access timings of the traditional read operation path and the prefetch read operation path of this application are compared: In the traditional read operation path, the CPU core sends a read request to the L3 cache. If the L3 cache misses, the request is forwarded to the Proof-of-Concept (PoC) via the D2D interface. The PoC first performs a cache consistency check. After the PoC completes the consistency check, the request is forwarded to the DDR memory controller, which reads the data from DDR memory. The data returns along the original path, eventually reaching the CPU core. The PoC consistency check and DDR memory read are executed strictly serially. The total latency of the traditional read operation is: T_total = 2×Td + Tp + Tdram; Where Td is the single-transmission latency across the D2D interface, Tp is the latency of performing cache consistency checks during PoC execution, and Tdram is the latency of the DDR memory controller accessing DDR memory and reading data.

[0080] In the prefetch read operation path of this application, the CPU core sends a read request to the L3 cache; after an L3 cache miss, a consistency request is simultaneously sent to the PoC and a prefetch read request is sent to the DDR memory controller via the D2D interface. The PoC cache consistency check process and the DDR memory data read process are executed in parallel; the DDR memory controller reads the prefetched data and writes it to the prefetch buffer, the PoC obtains the consistency check result and shares it with the D2D interface; the D2D interface determines the validity of the prefetched data based on the consistency check result, and if the prefetched data is valid, the data in the prefetch buffer is returned to the CPU core via the L3 cache. The total latency in parallel execution mode depends on the longer operation in the two parallel branches, and the total latency is: T_total' = Td + max(Tp, Tdram) + Td = 2×Td + max(Tp, Tdram); Since the DDR read latency Tdram (approximately 50~80ns) is much greater than the consistency check latency Tp (approximately 10~20ns), max(Tp, Tdram) = Tdram, and the total latency simplifies to: T_total' = 2×Td + Tdram ≈ 60~110ns; Compared with the traditional read operation path, the prefetch read operation path of this application eliminates the serial superimposed consistency check latency Tp (about 10~20ns), and the latency is reduced by about 12%~25% compared with the traditional read operation path.

[0081] In this embodiment, in response to a read operation request sent by the CPU core of the current DRAM, the target data is queried in the local cache and the query result is determined. The fast access characteristic of the local cache avoids unnecessary cross-DRAM access. If the query result meets the preset prefetch conditions, a read operation request is sent to the D2D interface, triggering a cross-DRAM prefetch read process. Based on the read operation request, the D2D interface sends a consistency check request to the consistency point and a prefetch read request to the memory controller. This prevents the consistency check at the consistency point from blocking data reading from the memory controller, allowing DDR memory access to be initiated earlier, effectively shortening the read operation path. The consistency check request is processed at the consistency point, and the consistency check result is obtained and sent to the D2D interface. The prefetch read request is processed by the memory controller, and the prefetch read data is obtained and sent to the D2D interface. Based on the consistency check result and the prefetch read data, the D2D interface determines the target data and sends it to the CPU core. This ensures that regardless of the consistency check result, the system can return the correct target data to the CPU core, balancing read operation correctness and performance optimization. This application effectively reduces the overall latency of read operations and significantly improves the memory access performance of Chiplet architecture processor systems.

[0082] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the prefetching method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0083] A second aspect of this application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the processor is capable of performing the prefetching method as described above.

[0084] The following is for reference. Figure 7 The diagram illustrates a structural schematic of an electronic device suitable for implementing embodiments of this application. The electronic devices in these embodiments may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0085] like Figure 7As shown, the electronic device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. While electronic devices with various systems are shown in the figures, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0086] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0087] The electronic device provided in this application adopts the prefetching method in the above embodiments. Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as the beneficial effects of the prefetching method provided in the above embodiments. Moreover, the other technical features of the electronic device are the same as the features disclosed in the method of the previous embodiment, and will not be repeated here.

[0088] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0089] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0090] A third aspect of this application provides a storage medium that is a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the prefetching method in the above embodiments.

[0091] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0092] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0093] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by an electronic device, the electronic device: responds to a read operation request sent by the central processing unit core of the current chip, queries the target data in the local cache and determines the query result; if the query result meets a preset prefetch condition, it sends a read operation request to the D2D interface; through the D2D interface, based on the read operation request, it sends a consistency check request to the consistency point and a prefetch read request to the memory controller; through the consistency point, it processes the consistency check request, obtains the consistency check result and sends it to the D2D interface; through the memory controller, it processes the prefetch read request, obtains the prefetch read data and sends it to the D2D interface; through the D2D interface, based on the consistency check result and the prefetch read data, it determines the target data and sends the target data to the central processing unit core.

[0094] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0095] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0096] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0097] The readable storage medium provided in this application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for performing the above-described prefetching method. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the prefetching method provided in the above embodiments, and will not be repeated here.

[0098] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A prefetching method, characterized in that, The prefetching method includes: In response to a read operation request sent by the CPU core of the current chip, the target data is retrieved from the local cache and the query result is determined; If the query result meets the preset prefetching conditions, then send the read operation request to the D2D interface; Based on the read operation request, the D2D interface sends a consistency check request to the consistency point and a prefetch read request to the memory controller. The consistency check request is processed through the consistency point to obtain the consistency check result and send it to the D2D interface. The prefetch request is processed through the memory controller to obtain the prefetch data and send it to the D2D interface. The target data is determined through the D2D interface based on the consistency check result and the prefetch data, and then the target data is sent to the central processing unit core.

2. The prefetching method as described in claim 1, characterized in that, The D2D interface includes a prefetch logic module. The step of sending a consistency check request to the consistency point and a prefetch read request to the memory controller through the D2D interface according to the read operation request includes: The read operation request is parsed by the prefetch logic module to obtain the target cache line address. Based on the target cache line address, the consistency check request and the prefetch read request are generated according to the preset D2D interface protocol. The consistency check request includes an opcode for indicating the execution of a cache consistency check, and the prefetch read request includes a command identifier for indicating the execution of a prefetch read operation. The consistency check request is sent to the consistency point, and the prefetch request is sent to the memory controller.

3. The prefetching method as described in claim 2, characterized in that, The step of processing the consistency check request through the consistency point, obtaining the consistency check result, and sending it to the D2D interface includes: The consistency check request is parsed through the consistency point to obtain the target cache line address. Based on the opcode, the cache state of the target cache line address in each core except the current core is determined. Based on the cache state, the consistency check result is generated. The consistency check result is sent to the D2D interface.

4. The prefetching method as described in claim 2, characterized in that, The D2D interface includes a prefetch buffer, and the step of processing the prefetch request through the memory controller, obtaining the prefetch data, and sending it to the D2D interface includes: The memory controller parses the prefetch request to obtain the target cache line address, and determines the cache line data corresponding to the target cache line address as the prefetch data based on the command identifier. The prefetch data is sent to the prefetch buffer.

5. The prefetching method as described in claim 2, characterized in that, The step of determining the target data through the D2D interface based on the consistency check result and the prefetched data includes: The consistency check result is parsed through the D2D interface to obtain the cache state; When the cache state indicates that the target cache line address does not exist in the first chip, or the target cache line address is in a read-only state in each of the first chips, the prefetch data is determined as the target data, wherein the first chip is a chip in the chip system other than the current chip.

6. The prefetching method as described in claim 5, characterized in that, After the step of parsing the consistency check result through the D2D interface to obtain the cache state, the method further includes: When the cache state indicates that the target cache line address is in an exclusive state or a modified state in any of the first cores, the prefetched data is marked as invalid; Based on the target cache line address, a data retrieval request is generated and sent to the first core corresponding to the target cache line address, and the target data is queried and sent to the central processing unit core.

7. The prefetching method as described in claim 5, characterized in that, After the steps of sending a consistency check request to the consistency point and a prefetch read request to the memory controller via the D2D interface according to the read operation request, the method further includes: Dynamically monitor the consistency check results and the return order of the prefetched data; If the consistency check result arrives at the D2D interface before the prefetched data, the consistency check result is parsed through the D2D interface to obtain the cache state. When the cache state indicates that the target cache line address in the consistency check result does not exist in the first core, or the target cache line address is in a read-only state in each of the first cores, the receive data path of the D2D interface is configured to bypass mode, so that in the bypass mode, when the prefetch data arrives at the D2D interface, the prefetch data is sent to the central processing unit core as the target data through the D2D interface.

8. The prefetching method as described in any one of claims 2 to 7, characterized in that, Following the step of sending the read operation request to the D2D interface, the method further includes: The read operation request is parsed through the D2D interface to obtain the target cache line address; Match the target cache line address with the address labels of each valid entry in the prefetch buffer of the D2D interface; When the target cache line address matches the address tag of any of the valid entries, the corresponding cache line data is read from the matched valid entries, and the cache line data is sent to the central processing unit core as the target data.

9. An electronic device, characterized in that, The device includes a memory and a processor, the processor being capable of performing the steps of the prefetch method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the prefetch method as described in any one of claims 1 to 8.

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