Circuit, system and method for large scale parallel matrix multiplication in transmission based on capacitance calculation

Abstract

A method for transmitting large-scale parallel matrix multiplication (A x B) in a capacitance-based computation is provided. The method includes generating a series of analog spike signals by applying an amplitude-time dual encoding scheme, where spike amplitudes correspond to row elements of matrix A and spike timing corresponds to column elements of matrix B; applying the analog spike signals to analog computation cores; in response to the analog spike signals, accumulating and releasing charges in capacitors of the analog computation cores, thereby generating time-varying voltages corresponding to dot product results; detecting time intervals required for the voltages of the capacitors to return to equilibrium levels; and decoding the time intervals into digital results using a time-based decoding scheme, where the time-based decoding scheme is based on the number of clock cycles elapsed during convergence of the capacitor voltages to the equilibrium levels.

Description

Technical Field

[0001] This invention generally relates to hardware acceleration of artificial intelligence (AI). More specifically, this invention relates to a mixed-signal capacitive in-memory (CIM) architecture that uses amplitude-time coding and time-based decoding for in-transmission parallel matrix multiplication. Background Technology

[0002] The rapid development of artificial intelligence has exacerbated the demand for energy-efficient hardware accelerators, as deep learning algorithms present computational challenges and traditional von Neumann architectures have inherent limitations. While digital accelerators have evolved through dedicated processing units and dataflow optimization, they still face inherent constraints such as high data migration costs and CMOS scaling limits. Analog in-memory (CIM) solutions utilize novel non-volatile devices such as memristors, memcells, and phase-change memory (PCM) devices, offering higher energy efficiency by performing computations directly within the memory array. However, these analog solutions suffer from device non-ideals, such as conductance drift and randomness, as well as peripheral circuit overhead, particularly high-power analog-to-digital converters (ADCs) and IR drop issues.

[0003] Therefore, there is a need for a capacitive computing accelerator that can utilize passive charge dynamics to perform low-power, high-throughput matrix computations while reducing reliance on analog-to-digital conversion. Summary of the Invention

[0004] One object of the present invention is to solve the above-mentioned technical problems.

[0005] This invention proposes a capacitance-based matrix multiplication accelerator called WireLightning. WireLightning is a mixed-signal architecture that utilizes the inherent charge dynamics of capacitors to achieve analog acceleration. Unlike analog cross arrays that encode weights in programmable devices, this invention represents matrix elements through precisely controlled spike amplitudes and utilizes the charge accumulation and predictable decay of passive capacitors to perform analog multiply-accumulate (MAC) operations. The proposed architecture addresses two key challenges of existing analog accelerators:

[0006] (1) Device non-ideality: In the technical solution of the present invention, by encoding the weight transiently in the peak timing instead of in the persistent device state, the weight drift and random switching can be reduced, and the range normalized root mean square error (RMSE) and normalized error are reduced to 69.2% and 77.1% of those of memristor-based and PCM-based accelerators, respectively.

[0007] (2) ADC bottleneck: The present invention adopts a time-based decoding scheme to replace the traditional high-power ADC with a high-efficiency clock-driven threshold detection. Compared with other architectures, the ADC power consumption is reduced by 98.8% and 99.9% respectively.

[0008] Key innovations in this invention include amplitude-time dual encoding. Amplitude-time dual encoding utilizes the dynamic charge of capacitors to achieve constant-time dot product operations. This invention also provides row-parallel passive computation using scalable capacitor arrays. The scalable capacitor array concurrently processes rows of the matrix on a dedicated core, enabling simultaneous dot product calculations to improve throughput. Furthermore, this invention provides common value reuse in low-bit quantization vectors. Common value reuse reduces multiplication complexity independent of matrix size, while also reducing spikes and computational errors.

[0009] In existing technologies, matrix-vector multiplication (MVM) calculations have been implemented using memristors, memcells, and PCM devices. This invention, however, utilizes standard CMOS capacitors and practically deployable circuitry to achieve MVM. When implemented in a 40nm CMOS process node, WireLightning achieves 465.47 TOPS / W with 4-bit precision, representing a power efficiency improvement of over 2.9 times compared to analog cross-array accelerators of equivalent precision. Despite the inherent precision limitations of analog computation, the prototype demonstrated a range-normalized RMSE of 1.80% and a normalization error of 9.18% in PCB experiments. By combining capacitance calculation with circuit-level co-design, the capacitance calculation using the WireLightning approach provides a practical solution for energy-efficient edge AI applications.

[0010] According to a first aspect of the invention, a method for performing massively parallel matrix multiplication in transit via capacitance-based computation is provided. Capacitors possess inherent charge accumulation capabilities and predictable discharge behavior, thus providing a solution for performing matrix multiplication. By utilizing charge accumulation during charging to represent accumulation and predictable decay during discharging to represent multiplication, capacitors can realize the dot product of vectors, which is the core operation of MVM operations. The proposed MVM method includes the following steps: generating a series of analog spike signals by applying an amplitude-time dual encoding scheme, wherein the spike amplitude represents matrix row elements and the spike timing represents matrix column elements; applying the analog spike signals to multiple analog computing cores; accumulating and releasing charge in the capacitors of each analog computing core in response to the analog spike signals, thereby generating a time-varying voltage corresponding to the dot product result; detecting the time interval associated with the return of the time-varying voltage of the capacitors toward a balance level using a comparator circuit; and decoding the time interval into a digital result using a time-based decoding scheme, wherein the decoding is based on the number of clock cycles elapsed during the convergence of the capacitor voltage to the balance level.

[0011] According to a second aspect of the invention, a core circuit for calculating vector dot products is provided. The core circuit comprises three components: a DAC, a capacitor (CAP), and a comparator circuit (COMP). The DAC can be implemented using an R-2R trapezoidal DAC, which regulates the charging and discharging of the capacitor by generating an analog spike sequence. When the DAC output is equal to half the source voltage, i.e., VDD / 2, the capacitor voltage begins to decay towards an equilibrium state. A DAC output higher than VDD / 2 causes the capacitor to charge rapidly and gradually discharge back to an equilibrium state after the DAC output returns to VDD / 2; a DAC output lower than VDD / 2 causes the capacitor to discharge rapidly and slowly charge back to an equilibrium state after the DAC output returns to VDD / 2. A grounded capacitor (CAP) can be positioned between the DAC output and the COMP input as the primary component for vector multiplication. Since the COMP input is directly connected to the transistor gate, the DAC can exclusively control the charge injection and release of the capacitor. The proposed design reduces charge leakage, thereby maintaining computational accuracy and signal integrity. The comparator circuit (COMP) comprises two distinct paths: a positive result path (OUTP) containing an even number of inverters, and a negative result path (OUTN) containing an odd number of inverters. OUTP outputs logic 1 when the capacitor voltage is above the equilibrium state (VDD / 2), and OUTN outputs logic 1 when the capacitor voltage is below the equilibrium state. Thus, the voltage deviation from the equilibrium state is converted into a digital signal. An increase in capacitor voltage on the positive path or a decrease in voltage on the negative path prolongs the duration of the high-level output. Therefore, the analog result can be decoded into a digital value based on the number of clock cycles required for the capacitor voltage to return to the equilibrium state. In summary, once all spike signals have been transmitted to the capacitor and the decoding of the calculation result is completed by measuring the clock cycles required for the capacitor voltage to stably return to the equilibrium state, the computational core can perform vector multiplication. The proposed method integrates analog-to-digital conversion into the capacitor reset process, thereby eliminating the need for traditional high-power, large-area ADCs and improving scalability.

[0012] According to a third aspect of the invention, a system for performing large-scale parallel matrix multiplication (A*B) in transmission via capacitance-based computation is provided. The system includes a controller, multiple analog computing cores, a reader, and a scheduler. The controller is configured to: generate a series of analog spike signals based on matrix data using an amplitude-time dual encoding scheme, wherein the spike amplitudes correspond to row elements of matrix A, and the spike timings correspond to column elements of matrix B; and simplify the columns of matrix A by identifying recurring absolute values ​​in the quantized column vectors of matrix B, and group corresponding elements in matrix A and pre-accumulate the grouped values ​​to reduce the number of multiplications to a constant count. The analog computing cores receive the analog spike signals from the controller, wherein each analog computing core includes a resistive trapezoidal digital-to-analog converter (DAC), a capacitor, and a comparator circuit. The resistive trapezoidal DAC is configured to receive digital signals from the controller and generate analog voltage pulses based on the digital signals to drive the capacitor to charge and discharge. The capacitor is electrically connected to the resistive trapezoidal DAC and is configured to accumulate and release charge in response to the voltage pulses, thereby generating a time-varying voltage representing the simulation result of the dot product operation. The comparator circuit is electrically connected to a capacitor and configured to monitor the capacitor's voltage, detect deviations from the equilibrium level, and generate a signal indicating the time interval required for the voltage to return towards the equilibrium level. The reader is electrically connected to each comparator circuit and configured to determine the digital result of the dot product operation by measuring the time interval and converting it into a quantized value using a time-based decoding scheme. The scheduler is configured to coordinate data transmission and timing control between the controller, analog computing cores, and readers during matrix-vector multiplication. The analog computing cores are arranged in a row-parallel architecture, and each analog computing core is configured to concurrently and independently compute the dot product between a row of matrix A and a column vector of matrix B. Attached Figure Description

[0013] The embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, wherein:

[0014] Figure 1 The operational principle of capacitance calculation for the dot product of two vectors is demonstrated.

[0015] Figure 2 An amplitude-time dual encoding scheme was demonstrated;

[0016] Figure 3 A time-based decoding scheme was demonstrated;

[0017] Figure 4 This paper demonstrates a row-by-row parallel computation of matrix A according to an embodiment of the present invention, wherein each row of matrix A is concurrently multiplied with a column vector b from matrix B;

[0018] Figure 5This demonstrates how multiplication can be simplified by grouping corresponding columns of matrix A using the repeated absolute values ​​in the columns of matrix B.

[0019] Figure 6 An overall system architecture of WireLightning according to an embodiment of the present invention is shown, which includes eight unit blocks interconnected with a memory controller;

[0020] Figure 7 A schematic diagram of an analog computing core according to an embodiment of the present invention is shown, wherein the analog computing core includes a resistive trapezoidal DAC, a capacitor (CAP), and a greater than comparator and a less than comparator (COMP).

[0021] Figure 8 The response of the analog computing core to digital signals (I<3:0>) is demonstrated, including capacitor voltage, greater than comparator output (OUTP), and less than comparator output (OUTN).

[0022] Figure 9 The process of generating positive and negative spikes based on register values ​​is demonstrated.

[0023] Figure 10 The workflow of WireLightning is demonstrated, showing the pipelined processing stages including loading vectors, simplifying matrices, generating spikes, and decoding results;

[0024] Figure 11 A schematic experimental setup for PCB-level verification is shown, comprising two parts (a) and (b). Part (a) schematically shows a host computer, a controller FPGA board, a test board carrying analog computing cores, a power supply, and an oscilloscope, while part (b) schematically shows the test board, which includes multiple computing cores, each of which includes a resistive trapezoidal DAC, a capacitor, and a greater than and less than comparator.

[0025] Figure 12 The oscilloscope waveforms shown are divided into two parts, (a) and (b), which show the capacitor voltage and comparator output. Part (a) shows the positive calculation result, and part (b) shows the negative calculation result. In each part (a) and (b), the first trace (A) represents the capacitor voltage, the second trace (B) represents the comparator output (positive / negative result path), the third trace (C) represents the decoding result start signal, and the fourth trace (D) represents the completion signal.

[0026] Figure 13 The frequency distribution of 560,000 vector multiplication results from PCB experiments is shown.

[0027] Figure 14The results show chip simulation from Virtuoso, illustrating the operation of WireLightning and the resulting capacitor voltages across the compute cores.

[0028] Figure 15 The chip layout at different levels is shown in four parts: (a), (b), (c), and (d). Part (a) shows the overall architecture, part (b) shows the cell blocks, part (c) shows the computing engine, and part (d) shows the computing cores, with dimensions of 5920.31 µm × 2166.81 µm, 1469.08 µm × 1071.40 µm, 146.34 µm × 929.06 µm, and 45.22 µm × 33.16 µm, respectively.

[0029] Figure 16 This demonstrates a single vector multiplication in the core of the simulation computation;

[0030] Figure 17 A table is shown for comparing the architecture of the present invention with prior art designs in terms of throughput, area efficiency, and power efficiency;

[0031] Figure 18 A block diagram of a capacitance-based matrix multiplication system according to an embodiment of the present invention is shown; and

[0032] Figure 19 A block diagram of the simulation computing core according to an embodiment of the present invention is shown. Detailed Implementation

[0033] In the following description, apparatus, systems, and / or methods for performing large-scale parallel matrix multiplication in transmission via capacitance-based computation are described as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Certain specific details may be omitted to avoid obscuring the invention; however, this disclosure is intended to enable those skilled in the art to implement the teachings herein without undue experimentation.

[0034] To facilitate a clear understanding of the technical solutions disclosed herein, the following section first provides background information on AI accelerators.

[0035] I. Background of AI Accelerators

[0036] A. Digital accelerator

[0037] Digital accelerator design has evolved significantly to improve performance and resource utilization. Early designs were primarily optimized for dense models, becoming inefficient when handling sparse models due to redundant computations on zero operands. While weighted dataflow methods addressed the sparsity problem, they introduced load imbalance, leading to idle processing cycles. One related study mitigated load imbalance by introducing weight reordering algorithms and hybrid parallel dataflow, but this increased memory overhead for storing non-zero weight locations. Another related work introduced mixed-precision computation through memory adaptive pruning and quantization algorithms, thereby improving processing unit utilization and addressing memory constraints. However, its reliance on neural architecture search increased computational overhead.

[0038] Digital accelerator design has evolved from sparsity-focused approaches to more sophisticated architectures incorporating adaptive data flow, load balancing, and mixed-precision techniques. Nevertheless, data movement and memory access remain critical factors impacting power efficiency. Since maximizing data reuse and minimizing memory accesses are essential for achieving system-level efficiency, the industry has been exploring alternatives. Against this backdrop, analog accelerators, leveraging analog computing, in-memory processing, and mixed-signal techniques, offer a path to improved power efficiency.

[0039] B. Simulated cross-array accelerator

[0040] Regardless of whether they are based on memristors, PCM, or memcapacitors, analog cross-array accelerators can perform in-situ MVM operations, reducing data movement and computational costs compared to digital architectures. Early designs utilized resistive random access memory (RRAM) and PCM cross-arrays to perform parallel dot product operations, using Ohm's law to perform multiplication at each cross-point and Kirchhoff's laws to perform current summation in each column. However, these initial designs lacked full support for complex neural networks such as convolutional neural networks (CNNs). Subsequent developments introduced in-situ CNN processing, pipelined execution, flexible memory configuration, and general-purpose units for various inference workloads. In recent designs, PCM-based architectures have achieved large-scale integration; for example, a 64-core mixed-signal chip can support high-throughput CNN and Long Short-Term Memory (LSTM) inference with minimal off-chip interaction. Another subsequent PCM study implemented four-quadrant analog multiplication and conductance calibration, thereby improving accuracy and performance.

[0041] Memcapacitor-based accelerators encode weights as capacitance values ​​and perform MVM through voltage multiplication and charge accumulation. Early work highlighted their energy efficiency, non-volatility, and scalability at both the device and array levels, but neglected the circuit-level details for practical system implementation. Subsequent research addresses this issue by demonstrating an in-memory computation macrocell based on a ferroelectric capacitor array and its optimized analog multiply-accumulate circuit.

[0042] While analog accelerators offer advantages in computational parallelism and energy efficiency, they still face limitations such as weight drift caused by material instabilities, polarization fatigue, and non-ideal programming characteristics. In this invention, inputs and weights are encoded as controlled spike signals instead of being directly stored in programmable cells. This signal-based approach eliminates device state programming, mitigates weight drift and stochastic behavior, and leverages the inherent charge dynamics of passive capacitors to achieve massively parallel computation, thereby minimizing energy overhead and improving MVM accuracy. Furthermore, the operational amplifier-free ADC design further improves energy efficiency compared to existing analog cross-array accelerators.

[0043] The following sections describe the theoretical principles, operational configurations, and verification results related to capacitance calculation according to the present invention. Based on these principles, configurations, and verification results, the present invention further provides specific hardware architectures, circuit layouts, and system implementations for performing matrix multiplication. Transforming these theoretical and operational aspects into physical hardware components and a coordinated hardware structure constitutes a technical contribution of the present invention.

[0044] II. Principles of Capacitance Calculation

[0045] A. Theoretical Framework

[0046] Matrix multiplication fundamentally involves two operations: multiplication and accumulation. Capacitors possess an inherent ability to accumulate charge and predictable discharge behavior, providing a promising approach to performing matrix multiplication. By using the charge accumulation during charging to represent accumulation and the predictable decay during discharging to represent multiplication, capacitors have the potential to implement the core operations of MVM operations, such as... Figure 1 As shown.

[0047] Figure 1 This demonstrates the operational principle of capacitance calculation for the dot product of two vectors. It is based on events occurring at discrete time points. , and The instantaneous changes in capacitor voltage caused by the input spikes are denoted as X1, X2, and X3, respectively. Each of these changes occurs within its respective decay time interval. , and Subsequently, these initial voltage changes decay into X1*W1, X2*W2, and X3*W3, each determined by its corresponding attenuation factor W. i Scaling is applied. At a specified measurement time, the accumulated capacitor voltage corresponds to the sum of these decaying voltages. Therefore, by applying spikes to the capacitor sequentially at discrete time points, the resulting measured voltage can be represented as the dot product of the instantaneous voltage change vector after each spike and the decay factor vector at the measurement time.

[0048] Assuming the capacitor is initially uncharged and receives a series of discrete, short-duration charging spikes, the voltage across the capacitor at a given moment can be characterized as:

[0049] in, , . This represents the instantaneous voltage of the capacitor. Indicates the first The amplitude of the peak, Indicates the time width of the spike. Indicates the first The area beneath each peak Indicates from the first The decay time since the peak It represents the time constant of a capacitor circuit (i.e., the product of capacitance and resistance). Indicates the first The instantaneous voltage change across the capacitor after a spike, and Indicates the first The attenuation factor of each spike. According to equation (1), by sequentially applying a series of amplitude-modulated spikes to the capacitor at discrete time points, the voltage obtained by the capacitor can represent the dot product of two vectors. Therefore, the voltage across the capacitor after these spikes are applied can effectively encode the vector represented by the spike amplitude. and the vector represented by its decay over time The inner product of the vectors. In practical applications, vector multiplication can be achieved by encoding one vector as peak amplitude and another vector as peak timing. When the peak sequence is received, the capacitor naturally integrates the input signal, thereby generating a voltage that directly represents the inner product of the vectors. Since this calculation occurs simultaneously with the peak transmission, this method is referred to as "computation in transmission" in this paper.

[0050] B. Element Encoding and Result Decoding

[0051] In physical implementation, matrix multiplication of matrix A and matrix B is accomplished by encoding their elements as discrete spike features. Specifically, according to equation (2), the element a of matrix A... iEncoded as peak amplitude y i Amplitude encoding is achieved through the power supply voltage V. DD It is implemented using discrete levels, where N1 represents the number of amplitude levels.

[0052] At the same time, the elements of matrix B It is encoded as spike timing. Equation (3) defines the timing encoding, where, Indicates from the first The peak distribution time The decay time since then, and N2 represents The discrete level number.

[0053] This dual encoding of amplitude and time effectively embeds the elements of matrices A and B into a sequence of spikes. Therefore, by applying a series of spikes with specific amplitudes at specific times, matrix multiplication at the capacitor can be triggered. Subsequently, the instantaneous voltage V of the capacitor is measured. t The dot product of two vectors can be obtained as shown in equation (4) (combining equations (1), (2) and (3)), where K represents a constant scaling factor. Therefore, this spike-based method provides a framework for high-energy-efficiency and high-performance matrix multiplication in neuromorphic computing systems.

[0054] III. Implementation Technology

[0055] A. Element encoding

[0056] Encoding a row of matrix A as spike amplitude requires a digital-to-analog converter (DAC) to convert the digital data into an analog signal. A 4-bit signed encoding scheme quantizes these row elements into 15 discrete amplitude levels to represent integer values ​​from -7 to +7, where zero is mapped to a reference voltage (VDD / 2). The amplitudes of positive spikes (+1 to +7) are scaled from 9 / 16 VDD to 15 / 16 VDD, while the amplitudes of negative spikes (-1 to -7) are scaled from 7 / 16 VDD to 1 / 16 VDD. A column of matrix B is encoded using a 4-bit signed scheme with spike timing controlled by a digital clock. In time encoding, the sign of the negative element in matrix B is transferred to the corresponding element in matrix A. Therefore, the spike occurrence time is quantized into 7 discrete time levels (1 to 7), which can be calculated using equation (3b). When a column of matrix B contains repeating elements, consecutive spikes can be generated in time slots to represent accumulation, such as... Figure 2 As shown. Figure 2 This demonstrates a dual amplitude-time encoding scheme. The peak amplitude represents the row vector 'a' of matrix A, while the peak time represents the column vector 'b' of matrix B. This scheme increases the duration of the peaks (…). This is achieved by using spike width modulation to encode amplitude values ​​that exceed the highest discrete level.

[0057] B. Result Decoding

[0058] The calculation result derived from the instantaneous voltage of the capacitor (Equation 4b) needs to be converted from analog to digital representation. This paper avoids using a traditional ADC because its high power consumption and area overhead limit the scalability of large-scale computations. Instead, it utilizes the inherent decay behavior of the capacitor to digitize its voltage: as shown in the figure. Figure 3 As shown, the decoding of the calculated output is based on the number of clock cycles that the voltage takes to converge to the equilibrium state after the input spike triggers charging and discharging. Figure 3 A time-based decoding scheme is illustrated. The analog capacitor voltage is converted into a digital clock cycle count based on the time required for it to converge to an equilibrium state. The clock cycle count can be used as an address to access the ROM module, thereby retrieving the corresponding digital calculation result. Considering the large matrix size (e.g., 5120×5120), the calculation output is encoded using a 12-bit signed scheme, thus providing a numerical range from -2047 to +2047.

[0059] This time-based decoding method offers several advantages: it eliminates the need for traditional high-power, large-area ADCs and effectively utilizes the inherent reset phase of capacitors to achieve analog-to-digital conversion. Furthermore, by using clock cycle counts as ROM addresses, it improves fault tolerance to result variations. Multiple ROM addresses can be mapped to the same output value, ensuring reliable computation even if manufacturing process variations affect decay time. Therefore, this decoding strategy improves accuracy, scalability, and energy efficiency in large-scale computing systems.

[0060] C. Parallelization of matrix multiplication

[0061] In matrix-vector multiplication (A×b), each result is derived from the dot product of a row of matrix A and vector b. These dot products are essentially independent of each other and can therefore be computed in parallel, meaning each row can be assigned to an independent computational core. Distributing N rows in parallel across N cores can significantly speed up computation.

[0062] Parallel processing by row: Figure 4 This demonstrates the parallel computation of matrix A by row: each row of A is multiplied concurrently with the column vector b from matrix B. Figure 4The diagram illustrates this concept: by assigning each row of the matrix to a separate core, simultaneous dot product calculations with vector b are achieved. The proposed method leverages inherent parallelism, significantly improving computational efficiency as the matrix size increases. In the example shown, a five-row matrix uses five cores, each integrating a capacitor that accumulates a charge proportional to the calculated dot product. Unlike traditional analog cross arrays that perform vector-matrix multiplication by sequentially activating rows, the architecture of this invention can process multiple input vectors concurrently across multiple rows. This parallelization is particularly advantageous for the large-scale matrix multiplications required by long-context Transformer architectures in modern large-scale language models.

[0063] Matrix A is encoded as peak amplitudes: the elements of each row in matrix A are encoded as the amplitudes of the time-stack sequences generated by each core. Peak amplitudes are expressed using a reference voltage V. DD Centered on 2 / 2, positive matrix elements increase the amplitude above the baseline, while negative matrix elements decrease the amplitude below the baseline. Each column of matrix A corresponds to the spike emitted by each independent core at a specific time. For example, in Figure 4 In the matrix, at time τ*ln(4), all cores produce spikes, the amplitude of which corresponds to the elements in the first column of matrix A. Therefore, one row of matrix A determines the spike amplitude of a single core, while one column of matrix A defines the spike amplitude of all cores at a specific time.

[0064] Encode vector b as peak timing: vector b determines the peak timing of each column of matrix A. Specifically, the peak generation time of the i-th column is determined by the corresponding element b. i The absolute value is used to control it. For example, regardless of b i Whether it equals -5 or +5, the spike associated with the i-th column occurs at time τ*ln(5). i The negative sign is used to invert the corresponding column elements of matrix A. In other words, b i The absolute value of vector b defines the timing of the spikes, while its negative sign handles the sign adjustment of the relevant columns in matrix A. Therefore, vector b establishes the temporal order of the spikes, while matrix A determines the amplitude of the spikes.

[0065] In summary, the proposed method achieves parallel matrix-vector multiplication by distributing row-wise dot product computation across multiple cores; each core performs independent computation using matrix and vector values ​​based on spike encoding. The final result is represented as the accumulated measurable voltage within each core. The proposed parallel method provides enhanced computational performance for large-scale matrices.

[0066] D. Simplification of matrix multiplication

[0067] To efficiently compute the dot product of two n-dimensional vectors a and b, the numerical repetition in the quantized vector b can be used to reduce the number of multiplication operations. When vector b is quantized to low bit precision (e.g., 4 bits), many elements become identical, allowing common values ​​to be extracted. Specifically, elements in vector a can be grouped based on the unique absolute value in vector b, and then multiplied according to the corresponding values ​​in b. i The symbols are used to adjust each a. i The sign is used, and these grouping elements are accumulated before performing a multiplication on each unique value.

[0068] Formally, let v represent the distinct quantization values ​​in |b|. Define the index set I. pv ={i|b i =+v} and I nv ={i|b i =-v}. Then the dot product can be rewritten as:

[0069] The method employed reduces the time complexity of multiplication to constant level because the number of multiplications depends only on the number of non-repeating quantized values ​​in |b|, and for k-bit quantization, the upper limit of the number of multiplications is 2. k-1 For example, with 4-bit quantization, regardless of the vector length n, at most 8 multiplications are required, and the remaining operations are simple additions. Therefore, when vector b exhibits low entropy characteristics, the method used can bring significant efficiency improvements compared to traditional methods, thus achieving constant time complexity in simulation computation.

[0070] Extending the optimization to matrix-vector multiplication, consider an n×n matrix A and an n-dimensional vector b. By simultaneously applying the same grouping and sign adjustment strategy to each row of matrix A, a simplified matrix A can be formed. s ,like Figure 5 The diagram illustrates how to simplify multiplication by grouping corresponding columns of matrix A using the repeated absolute values ​​in the columns of matrix B. Specifically, the signs of the columns in matrix A are first adjusted according to the sign of vector b, and then columns corresponding to the same values ​​in vector b are aggregated into a new matrix A. s Therefore, the matrix-vector product A·b can be efficiently computed as A s The product of the multiplication with a fixed-length vector containing unique values ​​in |b| is calculated. Since the physical multiplication is performed in parallel across all capacitor cells, the time required for the multiplication is independent of the dimension of the original matrix. This again reduces the time complexity of the multiplication operation to constant level, resulting in a significant efficiency improvement, especially for vectors with low bit quantization.

[0071] In addition to improving computational efficiency, the method reduces the overall number of spike events (i.e., the number of physical simulation multiplications) by grouping and aggregating positive and negative contributions before triggering independent spike events, thereby mitigating the cumulative error caused by repeated capacitor charging and discharging. Furthermore, the method relaxes the timing constraints discussed in Section IV-B below. Ultimately, these optimizations simultaneously improve the reliability and scalability of matrix multiplication operations in the simulation core.

[0072] IV. Theoretical Constraints of the Computation

[0073] A. Amplitude Constraint

[0074] The result of vector multiplication is obtained by measuring the capacitor voltage from the initial voltage (V). t The decay time is determined by the number of clock cycles required for the voltage to decay to its equilibrium voltage. To ensure accurate measurement of the decay time corresponding to the minimum product magnitude (i.e., 1; unity), the initial capacitor voltage (V) corresponding to the minimum magnitude is used. t It should be higher than a minimum measurable threshold voltage (V). th The threshold represents the minimum voltage offset that can be detected relative to the equilibrium state. This requirement is formally expressed as an “amplitude constraint” (Equation (6)) to ensure the validity and quantizability of the measurement results. In these formulas, N1 represents the discrete quantization level of the peak amplitude, N2 represents the discrete quantization level of the peak timing, and V DD This is the source voltage.

[0075] B. Timing Constraints

[0076] When a column of matrix B contains duplicate elements, consecutive spikes may appear within the same allocated time slot. In this case, spike width modulation can be used to represent the cumulative value (see [link to relevant documentation]). Figure 2 To prevent signal misalignment or overlap, these modulated spikes ( The time interval between adjacent peaks should not exceed the duration of the allocated time slot. This requirement, known as the "timing constraint," ensures that sufficient intervals are provided to reliably accommodate the width-modulated spikes within their respective time slots, as formally expressed in equation (7). Specifically, the minimum time interval between adjacent peaks (denoted as...) (As given by equation (7a)) should be greater than the maximum possible width of the modulation spike (as shown in equation (7b)). Wherein, Represents the simplified matrix A s The maximum cumulative amplitude, where 7 represents the maximum peak amplitude:

[0077] C. Result sensitivity

[0078] During the decoding phase, the capacitor voltage changes from the initial peak or valley voltage (V). t Decay to the threshold voltage (V) th The required decay time (t) follows a logarithmic function, as shown in Equation (8a). This characteristic means that for larger initial voltages, the decay time tends to saturate, resulting in reduced sensitivity to changes in the initial voltage. Conversely, lower initial voltages provide higher sensitivity; in this case, small voltage differences significantly affect the decay time, thereby improving measurement accuracy. Equation (8b) explicitly describes the sensitivity of decay time measurement relative to the initial voltage. This equation shows that the sensitivity of decay time is inversely proportional to the initial voltage: higher initial voltages lead to decreased sensitivity and accuracy, while lower initial voltages provide higher sensitivity and accuracy. This relationship explains the error distribution observed in prototype experiments (see [reference]). Figure 13 (See Section VI). Larger calculated outputs corresponding to higher initial voltages will exhibit greater measurement errors, while smaller outputs corresponding to lower initial voltages will produce smaller errors.

[0079] V. System Architecture

[0080] A. Overall Architecture

[0081] The proposed WireLightning architecture can efficiently perform matrix multiplication between matrix A and matrix B, where each matrix element is represented as a 4-bit integer. Figure 6 This demonstrates WireLightning's overall system architecture, which comprises eight unit blocks interconnected with the memory controller. Each unit block contains a scheduler and ten compute engines. Each compute engine further consists of a controller, 64 emulation cores, and a reader module. Figure 6 As shown, the proposed architecture comprises eight parallel cell blocks coordinated by a memory controller for performing the multiplication of two 5120×5120 matrices. Each cell block concurrently multiplies 640 rows of matrix A with a column vector of matrix B, thereby achieving simultaneous computation on all 5120 rows. The memory controller manages data transfer, loading matrices A and B from off-chip DRAM to on-chip memory and subsequently transferring the computation results back to DRAM.

[0082] Within each unit block, the hierarchical structure contains a scheduler and 10 computation engines. Each engine is responsible for calculating the product of 64 row vectors of matrix A and a column vector of matrix B. The scheduler manages the addresses, data, and control signals of each engine. Each computation engine contains a controller, 64 computation cores, and a read module. Driven by a sequence of spike signals generated by the controller, each computation core calculates the dot product between a row vector of matrix A and a column vector of matrix B. The read module retrieves the results from these cores. Therefore, each scheduler coordinates 10 controllers, collectively managing 640 cores performing parallel vector multiplication. Thus, all eight unit blocks can collectively perform 5120 concurrent multiplications between row vectors and a single column vector. Detailed descriptions of each module will be provided in subsequent sections.

[0083] B. Computing Core

[0084] The computing core primarily performs vector multiplication through controlled charging and discharging of capacitors driven by spike signals. Figure 7 A schematic diagram of the core of the analog computing is shown, which includes three main components: a resistive trapezoidal DAC, a capacitor (CAP), and a greater than / less than comparator (COMP).

[0085] DAC: The DACs in each computing core must meet requirements such as high energy efficiency, a simple architecture suitable for large-scale integration, and high dynamic response. This architecture uses an R-2R ladder DAC, a passive resistor network that can directly divide the reference voltage based on the digital input, thereby achieving a theoretically instantaneous analog output after the input stabilizes. Its purely passive nature eliminates active power-consuming components, thus achieving low power consumption. Furthermore, the ladder structure uses only two repeating resistor values, thus minimizing process mismatch errors, simplifying the manufacturing process, and improving scalability. Additionally, the R-2R ladder network itself can provide the necessary resistance for the core's RC circuitry, which facilitates component reuse and eliminates the need for additional resistors. Therefore, the analog computing core uses an R-2R ladder DAC.

[0086] The R-2R trapezoidal DAC regulates the charging and discharging of the capacitor by generating an analog spike sequence. When the DAC output equals V... DD When the input value is / 2 (corresponding to a digital input I<3:0> value of 8), the capacitor voltage begins to decay towards the equilibrium state. Inputs higher than this value cause the capacitor to charge rapidly and gradually discharge back to the equilibrium state after the input value returns to 8; while inputs lower than this value cause rapid discharge and slow charging back to the equilibrium state after the input value returns to 8, such as... Figure 8 As shown. Figure 8This demonstrates the analog computing core's response to digital signals (I<3:0>), including capacitor voltage, values ​​greater than the comparator output (OUTP), and values ​​less than the comparator output (OUTN). When the digital input value varies between 1 and 15, the DAC produces spikes ranging from 1 / 16 V. DD Up to 15 / 16 V DD , which corresponds to matrix elements from -7 to +7.

[0087] CAP: A grounded capacitor is placed between the DAC output and the COMP input as a key component in vector multiplication. Since the COMP input is directly connected to the transistor gate, the DAC exclusively controls the charge injection and release of the capacitor. This design minimizes charge leakage, thus maintaining computational accuracy and signal integrity.

[0088] COMP: The comparator contains two distinct paths: a positive result path (OUTP) containing two inverters, and a negative result path (OUTN) containing a single inverter (e.g., ...). Figure 7 As shown). When the capacitor voltage is higher than the equilibrium state (V... DD When the capacitor voltage is below the equilibrium state ( / 2), OUTP outputs logic 1; when the capacitor voltage is below the equilibrium state, OUTN outputs logic 1 (as shown in Figure 8). Thus, the voltage offset relative to the equilibrium state is converted into a digital signal. An increase in capacitor voltage on the positive path or a decrease in voltage on the negative path will prolong the duration of the high-level output. Therefore, the analog result can be decoded into a digital value based on the number of clock cycles required for the capacitor voltage to return to the equilibrium state.

[0089] In summary, once all spike signals have been transmitted to the capacitor and the decoding of the calculation results has been completed by measuring the clock cycles required for the capacitor voltage to stabilize and return to equilibrium, the computational core has completed the vector multiplication. The proposed method integrates the analog-to-digital conversion process into the capacitor's reset phase, thereby eliminating the need for traditional high-power, large-area ADCs and improving the system's scalability.

[0090] C. Controller

[0091] The controller consists of 64 identical modules, each connected to a computing core. These modules run concurrently and are synchronized by a common clock to ensure coordinated execution across all cores. Each module contains three key components: an arithmetic logic unit (ALU) that supports addition and subtraction; a storage unit for raw row vectors and simplified row vectors (A1 and A2); and a storage unit for raw and simplified row vectors (A1 and A2). s The register file (RF) for spikes; and the temporary register (Reg) for storing spike amplitude data during spike generation.

[0092] The controller operates primarily in two phases: a matrix simplification phase and a spike generation phase. In the matrix simplification phase, each of the 64 identical modules independently transforms its stored matrix row vectors from A into a simplified form Asimplified. s Upon receiving the enable signal and register file address signal, each module performs the following operations: (1) loads the original row vector from its register file; (2) uses the ALU to iterate and accumulate each element; (3) converts the simplified row vector A... s Save back to the register file.

[0093] During the spike generation phase, each module concurrently generates discrete spike signals for its corresponding computing core, synchronized by a common clock. Upon receiving the spike generation enable signal and the register file address signal, each module performs the following operations: (1) Convert the simplified vector A s Transfer from the register file to a temporary register. (2) Issue an analog spike signal in each clock cycle, the spike amplitude of which is set by the current register value. Positive values ​​generate values ​​higher than the equilibrium level (V). DD / 2) The spike is negative and generates a spike below the equilibrium level. (3) After each spike is emitted, the register value is adjusted to zero (increment or decrement) until it returns to zero, thus ending the spike emission.

[0094] Figure 9 This demonstrates the generation process of positive and negative spikes based on register values. When spike enable is activated, a negative value (-30) in register M0 generates an input signal (I<3:0>) for core 0, thus producing a negative spike. Conversely, a positive value (+17) in register M1 generates an input signal (I<3:0>) for core 1, thus producing a positive spike. An illustrative example (see...) Figure 9 The diagram illustrates the dynamic process of the spikes: Module 0 (M0) is initially loaded with -30 and emits negative spikes that gradually approach zero; Module 1 (M1) is loaded with +17 and emits positive spikes that gradually decrease to zero. The spike generation ends when all modules return to zero simultaneously.

[0095] D. Reader

[0096] The read module monitors 64 computation cores and collects their computation results. Specifically, it detects when a balanced state (i.e., computation completion) is reached by checking the positive and negative result ports of each core. The module contains 64 identical sub-modules, each responsible for a single core and including a sign checking unit and a result acquisition unit. The sign checking unit samples the positive and negative result ports before they return low and stores the output in a two-bit sign register. This sign register determines whether the balanced state was achieved through charging or discharging by recording the last port to return low. If the positive result port returns low (indicating the balanced state was achieved during discharging), the computation result is positive. Conversely, if the negative result port returns low (indicating the balanced state was achieved during charging), the computation result is negative. The result acquisition unit stores the final computational value. It uses the information in the two-bit sign register to select the correct positive or negative computation result broadcast by the scheduler and corresponding to the current decay time, and stores it.

[0097] E. Scheduler

[0098] The scheduler manages the matrix-vector multiplication pipeline by generating address, data, and control signals to ensure efficient computation. It mainly includes SRAM (used to cache a column vector of matrix B), spike ROM (used to store clock cycles of spike events), positive result ROM and negative result ROM (containing the calculation results corresponding to each clock cycle during decoding), and control logic circuitry responsible for generating synchronization and operation signals. Detailed explanations of the signals generated at each pipeline stage will be provided in the next section.

[0099] F. Workflow

[0100] Figure 10 This demonstrates the WireLightning workflow, including pipelined processing stages such as loading vectors, simplifying matrices, generating spikes, and decoding results. The scheduler performs matrix-vector multiplication using a four-stage pipeline architecture designed for optimal computational efficiency (see [link to documentation]). Figure 10Phase 1: Load Vector (LV). The scheduler loads a column vector of matrix B from off-chip DRAM into SRAM. Phase 2: Simplify Matrix (SM). The scheduler provides address and control signals instructing the controller to simplify matrix A based on the loaded vector. These signals include a simplification enable signal, an address for data accumulation, and an address for storing the simplification result. Phase 3: Generate Spike (GS). The controller generates spikes synchronized by scheduler signals derived from the timing of the spike ROM, ensuring accurate execution of spike events. Phase 4: Decode Result (DR). The analog calculation result is digitized in this phase. In each clock cycle, the scheduler extracts the corresponding positive and negative values ​​from the ROM and forwards them to the read modules. Subsequently, each read module determines the final digital result by selecting the correct signed value. This pipelined architecture significantly improves the throughput of matrix-vector multiplication. Experimental results regarding the performance improvement will be described in subsequent sections.

[0101] Considering the dependencies in the pipeline, i.e., each stage can only execute when adjacent stages are idle, the theoretical execution time of matrix-matrix multiplication can be expressed as: t total = (t LV + t SM + t GS + t DR ) + (n - 1) × (t GS + t DR (9)

[0102] Where n is the number of columns in matrix B, and t LV t SM t GS and t DR These represent the execution times for vector loading, matrix simplification, spike generation, and result decoding, respectively. The expressions also reflect the latency of individual stages as well as the dependencies between pipelines.

[0103] VI. Experimental Results

[0104] A. PCB-level experimental results

[0105] Figure 11 A schematic diagram of the experimental setup for PCB-level verification is shown, comprising two parts: (a) and (b). Part (a) illustrates the host computer, the controller FPGA development board, the test board with analog computing cores, the power supply, and the oscilloscope. Part (b) shows the details of the test board, which includes multiple computing cores, each comprising a resistive trapezoidal DAC, a capacitor, and a greater than / less than comparator. It should be noted that... Figure 11This is an illustrative diagram for purposes of illustration only; the relative dimensions and proportions of the components shown do not represent the precise proportions or physical dimensions in the actual implementation of the integrated circuit. Figure 11 The experimental setup included a host computer, a PYNQ Z2 FPGA control board, a custom analog test board, a power supply, and an oscilloscope. The custom test board, powered by the power supply, housed seven computational cores, enabling the concurrent execution of seven vector-vector multiplications. Each computational core included an R-2R ladder network, a computational capacitor with a time constant (τ) of 55µs (implemented through an 11nF capacitor and the equivalent 5kΩ resistor of the R-2R ladder network), and a greater than / less than comparator. The oscilloscope was used to monitor the capacitor voltage and the voltages on the positive and negative result paths. Internally, the PYNQ Z2 utilized programmable logic (PL) to implement the scheduler, controller, and readout module. The FPGA I / O ports operated at 3.3V logic levels, providing a DAC output range between 1 / 16 × 3.3V and 15 / 16 × 3.3V. The digital circuitry within the programmable logic operated at a 1 MHz clock frequency, generating a width T... w The DAC output spike is 1 µs.

[0106] In the matrix multiplication test, the host computer generates two random matrices A (7 × 8) and B (8 × 8), whose elements are 4-bit signed integers uniformly distributed between -7 and +7. Matrix A is transferred to the register of the controller module, while matrix B is sent to the scheduler's memory via the PYNQ Z2 processing system (PS) through the AXI4-Stream protocol. The scheduler initiates the multiplication operation after receiving the "Start" signal from the host via the AXI4-Lite protocol. After the calculation is completed, the result is transmitted from the read module back to the host computer via the PS through AXI4-Stream.

[0107] Figure 12 The oscilloscope waveforms of the capacitor voltage and comparator output are shown in two parts, (a) and (b). Part (a) shows the positive calculation result, and part (b) shows the negative calculation result. In parts (a) and (b), the first trace (A) represents the capacitor voltage, the second trace (B) represents the comparator output (positive / negative result path), the third trace (C) represents the decoding result start signal, and the fourth trace (D) represents the calculation completion signal.

[0108] Figure 12 The waveforms demonstrate the experimental results of a single computational core performing two vector multiplications: one generates... Figure 12 The positive result in part (a) produces another result. Figure 12The negative result in part (b). Trace (A) represents the capacitor voltage; trace (B) in Figure 12 Part (a) represents the positive result path output, in Figure 12 Part (b) represents the negative result path output; trace (C) marks the start of the decoding result stage; trace (D) indicates that the voltage has returned to equilibrium, i.e., the calculation is complete. Therefore, the time interval between trace (C) and trace (D) reflects the decoding time of the capacitor voltage. Figure 12 In part (a), the capacitor discharges back to equilibrium, and the positive result path only returns to a low level at the end, thus confirming that the calculation result is positive. Figure 12 In part (b), the capacitor charges to equilibrium, and the negative result path only returns to a low level at the end, indicating that the calculation result is negative. Each capacitor voltage trace exhibits 5 spike signals, which correspond to 5 non-repeating absolute values ​​in vector b.

[0109] Figure 13 This figure shows the frequency distribution of 560,000 vector multiplication results from PCB experiments. Each data point in the figure represents a single vector-vector multiplication result within the range of -127 to +127, and the shaded density represents the measured frequency. The figure also illustrates the probability density function of the error between the experimental and theoretical results.

[0110] Figure 13 The graph shows the distribution after 560,000 vector multiplications (10,000 matrix multiplications performed across 7 cores), with a comparison of theoretical results (-127 to +127) with experimental measurements. Each data point represents the result of a single vector multiplication. Shading density indicates the measurement frequency, and the graph details the error distribution between experimental and theoretical values.

[0111] Sensitivity analysis of results: Figure 13 This indicates a positive correlation between larger experimental errors and larger absolute values ​​of theoretical results. Within the range [-50, +50], the experimental results are in high agreement with the theoretical values, with a root mean square error (RMSE) of 2.95. However, over the entire range [-127, +127], the RMSE increases to 4.58 (range-normalized RMSE is 1.80%). This phenomenon is consistent with equation (8b): a smaller initial capacitor voltage (V... t This will result in higher sensitivity for decay time measurement, thereby improving accuracy; while a larger V t This will reduce sensitivity and increase error.

[0112] Amplitude constraint analysis: Given PCB parameters (τ = 55 µs, T... w =1 µs, V DDIn the case of (=3.3 V, N1=15, N2=7), the actual comparator threshold used to detect the minimum voltage offset is slightly higher than the theoretical threshold (i.e., V in equation (6b)). th This causes theoretical results in the range [-3, +1] to show as zero because the comparator is not triggered.

[0113] Timing Constraint Analysis: The timing constraints specified in Equation (7c) were satisfied in the experiment. Given the PCB parameters, the constraint requirement simplifies to the matrix (A). s The value of ) should not exceed 59 to prevent peak overlap. A s The theoretical maximum value is 56, which only occurs when all 8 elements of the input vector have the same extreme value (maximum value +7 or minimum value -7).

[0114] Overall, PCB-level experiments verified the accuracy and practicality of the proposed analog matrix multiplication paradigm and confirmed the relevant theoretical calculations and constraint formulas. The next section will discuss the evaluation of this paradigm in integrated chip implementation.

[0115] B. System configuration for chip design and evaluation

[0116] Digital components, including the controller, reader, and scheduler, were implemented in Verilog HDL at register-transfer level (RTL). Functional simulation and debugging were performed using Synopsys VCS and Verdi. After RTL verification, the design was synthesized into a gate-level netlist using Synopsys Design Compiler with a 40-nm standard cell library. Physical implementation (including placement, routing, and power analysis) was performed using Cadence Innovus, with the digital modules configured to operate at a 1GHz clock frequency.

[0117] The simulation computing core was designed using a 40-nm process design kit (PDK), with schematic design and transient simulation completed using Cadence Virtuoso Spectre. Power consumption parameters for each component were then extracted from Virtuoso.

[0118] Mixed-signal co-verification was performed using Cadence Virtuoso AMS, which integrates digital Verilog models and analog SPICE models. Custom analog layouts were drawn in Virtuoso, while digital layouts were generated by Innovus. The final chip integration was completed and passed design rule checking (DRC) in Calibre, as well as layout and schematic verification. Figure 1Layout-versus-schematic (LVS) verification.

[0119] C. Chip delay

[0120] Section VF details the computational workflow of matrix multiplication A × B, where both matrices are 5120 × 5120. The multiplication is performed column-wise: each column vector of matrix B is loaded into the scheduler one by one and multiplied in parallel with the row vectors of matrix A, until all columns of matrix B have been processed. Table I Time consumption of each pipeline task

[0121] Table I summarizes the average execution time for each stage. Stage 1 (LV) loads 8 elements from one column of matrix B per cycle, consuming a total of 640 cycles. Stage 2 (SM) sums 4 columns of matrix A per cycle, requiring 1280 cycles. Stage 3 (GS) generates all 7 spikes, requiring a total of 533 cycles. Stage 4 (DR) decodes the analog signal using the natural decay of capacitors, requiring an average of 2529 cycles.

[0122] Combining Table I and Equation (9), the total delay for the complete multiplication of matrix A and matrix B is 15.6794 ms, calculated as follows: 640 ns + 1280 ns + 533 ns + 2529 ns + (533 ns + 2529 ns) × 5119. The first four terms represent the processing time for the initial columns of matrix B, while the last term corresponds to the time for iteratively executing stages 3 and 4 on the remaining 5119 columns. Figure 14 The Virtuoso chip simulation results demonstrate the pipelined processing stages and the corresponding capacitor voltages across each compute core. The upper panel displays the four digital enable signals corresponding to the pipelined processing stages (i.e., load vector, simplification matrix, spike generation, and decoding result); the lower panel shows the corresponding analog capacitor voltages for each compute core. Notably, capacitor voltage decoding (stage 4) accounts for approximately 82.6% of the total processing time.

[0123] The computational efficiency and accuracy are significantly affected by the capacitor circuit time constant (τ). A smaller τ shortens the spike generation time (Equation (3b)) and reduces the time required to recover to the equilibrium voltage (Equation (8a)), thereby increasing throughput. However, decreasing τ reduces the decoding sensitivity to the initial voltage (Equation (8b)), thus reducing measurement accuracy. The optimal τ is 256 ns (C = 500 fF and R = 512 kΩ), which achieves the best balance between efficiency and accuracy.

[0124] D. Chip power consumption and area

[0125] The chip's power consumption and area consumption (Tables II and III) were evaluated using post-layout simulations with Cadence Virtuoso AMS and Cadence Innovus at a 40-nm process node and a nominal 0.9-V power supply. Digital components operated at a 1 GHz clock frequency. The power consumption of the simulated cores was determined by simulating a 64-core computing engine performing 3,200 [64,5120] × [5120, 128] matrix multiplications (approximately 393.86 µs per multiplication); the simulation covered vector loading, matrix simplification, spike generation, and result decoding stages. The input matrix (4-bit signed integers) was uniformly randomly distributed to reflect power consumption under real-world and average conditions. Instantaneous power consumption of the DAC, CAP, and COMP components was tracked during all 3,200 multiplications. For each multiplication, the energy consumption of each component on each core was determined by integrating the instantaneous power during the multiplication period (approximately 393.86 µs). Subsequently, the total energy of all components across the 64 cores was divided by the multiplication duration to calculate the average power, and then further divided by 64 to normalize it to a single-core value. The final reported average value is based on all 3,200 multiplications and represents the true sustained power consumption after considering inter-core differences. As shown in Table II, the single-core summary results indicate that the average power consumption of the DAC is 0.84µW per core; the power consumption of the capacitors is negligible at 2.4pW per core; while the comparator dominates the overall power consumption, with an average power consumption of 4.02µW per core, accounting for 82.7% of the total single-core power consumption (4.86µW). Table II Power consumption and area composition of a computing core Table III WireLightning chip features (40 nm process) † Both the cell block area and the overall area include the area occupied by the interconnect wiring between cell blocks.

[0126] The power consumption of the digital modules (controllers, readers, and schedulers) was extracted using the Innovus power analysis tool after placement and routing were completed. Each unit block contains 640 analog computing cores and their digital units: 10 controllers, 10 readers, and 1 scheduler. The total power consumption of a single unit block is obtained by summing the power consumption of these digital modules with the power consumption of the 640 analog computing cores. As summarized in Table III, the complete chip consists of eight parallel unit blocks with a total power consumption of 1252.1880 mW and a total area of ​​12.8282 mm²; each unit block has a power consumption of 156.5235 mW and occupies an area of ​​1.5740 mm².

[0127] The analog core accounts for a relatively low percentage of power consumption, only 1.99%, thanks to its simplified structure, passive high-efficiency components, and operational amplifier-free ADC design; however, due to its large number, it still dominates the area share (60.97%). The digital units contribute significantly more power consumption, primarily due to the controller managing spike signals and register arrays, and the scheduler handling large-scale pipelines and intermediate memory. The reader, with its relatively simple logic, has a smaller impact on power consumption and area.

[0128] E. Chip Layout

[0129] Figure 15 The chip layout at different levels is shown, comprising four parts: (a), (b), (c), and (d). Figure 15 Part (a) shows the overall architecture layout of the chip, which consists of 8 unit blocks with a total size of 5920.31 µm × 2166.81 µm (scale bar: 100 µm). Figure 15 Part (b) is an enlarged view of the unit block hierarchy (1469.08 µm × 1071.40 µm; scale bar: 50 µm), showing the digital scheduler (1454.93 × 117.45 µm) and 10 computing engine modules arranged in parallel. Figure 15 Part (c) details the internal configuration of the computing engine (146.34 µm × 929.06 µm; scale bar: 30 µm), including the controller module (117.45 µm × 143.74 µm), an array of 64 analog computing cores (single core size 45.22 µm × 33.16 µm), and a reader module (117.45 µm × 13.78 µm). Figure 15 Part (d) further showcases the microarchitecture of the analog computing core (scale bar: 2 µm), which includes a resistor-trapezoidal DAC, a metal-insulator-metal (MIM) capacitor implemented using four metal layers, and a comparator module consisting of cascaded inverters.

[0130] F. Overall Assessment

[0131] Figure 16 The Cadence Spectre AMS mixed-signal simulation results of a single vector multiplication in the core of the simulation are presented. Waveforms 1-4 in the figure represent the input spike signal (I<3:0>); waveform 5 represents the voltage response of the capacitor; waveforms 6 and 7 represent the outputs of the greater than and less than comparators, respectively. The main plot shows the frequency distribution of the results of 26.21 million 5120-dimensional vector multiplications (represented by shaded density, ranging from -2047 to +2047), while the subplots depict the probability density function of the error distribution between the experimental and theoretical results.

[0132] Specifically, in Figure 16 In the diagram, waveform 5 shows the capacitor discharging and returning to equilibrium, indicating a positive calculation result. The final result is obtained by quantizing a high-level duration (in clock cycles) longer than the comparator output. The quantized value is then used as a ROM address to retrieve and output the final digital calculation result. Figure 16 The figure summarizes the statistical characteristics of these 26.21 million 5120-dimensional vector multiplications, where each vector consists of uniformly distributed 4-bit signed integers (-7 to +7). The data distribution shows that when the theoretical value is in the range [-1023, +1023], the RMSE is 6.40; when the range is extended to the full [-2047, +2047], the RMSE rises to 9.27 (range-normalized RMSE is 0.23%). This trend conforms to the result sensitivity constraint: that is, as the calculated amplitude increases, the measurement accuracy decreases accordingly.

[0133] Table IV compares the simulation results of the PCB prototype and the ASIC. Here, the normalized error is defined as the 2-norm of the difference between the experimental and theoretical results, normalized using the 2-norm of the theoretical results. The range-normalized RMSE represents the root mean square error divided by the output range. The PCB prototype, operating at 3.3 V (τ = 55 µs), achieved a range-normalized RMSE of 1.80% and a normalized error of 9.18% in the range [-127, +127]. In contrast, the 40-nm ASIC solution, operating at 0.9 V (τ = 256 ns), achieved significantly higher accuracy in the range [-2047, +2047] thanks to its higher clock frequency, lower comparator threshold, and lower system noise (range-normalized RMSE reduced to 0.23%, normalized error reduced to 0.96%). Both implementations effectively validate the capacitance calculation principle and, as described in Section IV-C, demonstrate that the relative error increases with the increase of the calculated amplitude. The shorter time constant τ in ASICs effectively improves system throughput by reducing spike generation time and result decoding time (refer to Equations (3b) and (8b)). Overall, this comparison highlights the excellent scalability of the WireLightning architecture, which has successfully scaled from initial proof-of-concept to high-performance integrated circuit solutions. Table IV Comparison of PCB Prototype and ASIC Simulation

[0134] G. Comparison

[0135] 1) MVM Accuracy: The computational paradigm of this invention effectively mitigates the inherent randomness and inter-device variability in analog programmable devices by encoding the elements of matrix B transiently as peak timing sequences rather than static device states. The elements of matrix A are represented by peak amplitudes, and vector multiplication is performed through the accumulation and decay of charge within the capacitor. Although the analog capacitance calculation method of this invention does not completely eliminate noise, it still achieves significantly higher computational accuracy thanks to its non-random characteristics.

[0136] Table V compares the accuracy of the PCB prototype of this invention with existing RRAM and PCM cross array implementations reported in the literature. MVM accuracy is evaluated using two metrics: normalized error and range normalized RMSE. Equation (10) defines the normalized error as the 2-norm of the difference between the experimental result and the theoretical result, which is then normalized by dividing by the 2-norm of the theoretical result. The range normalized RMSE is calculated by dividing the root mean square of the error by the output range. As shown in Table V, the normalized error of the PCB prototype of this invention is only 77.1% of that of existing PCM cross array implementations, while the range normalized RMSE is only 69.2% of that of existing RRAM cross array implementations. These results highlight the significant effect of this scheme in reducing errors and verify the robustness of the proposed capacitance calculation method; the proposed method effectively avoids the inherent conductance drift or stochastic switching problems in memristors and PCM cross arrays. error = y exp - y theo (10a) norm. error = ∥error∥2 / ∥y theo ∥2(10b) Table V Accuracy comparison of matrix-vector multiplication

[0137] 2) ADC Power Consumption: The ADC significantly impacts the overall power consumption of the analog in-memory computing architecture. Therefore, minimizing ADC power consumption is crucial for improving the power efficiency of MVM operations. The method of this invention employs an op-amp-free ADC design based on time-domain conversion. A comparator module composed of cascaded inverters converts the analog capacitor voltage into a digital level signal, and the readout module performs the digital conversion by measuring the duration of these signals. By eliminating the high-power operational amplifier, the architecture of this invention significantly reduces overall power consumption.

[0138] Table VI compares the ADC power consumption during MVM operations. When implemented using a 40-nm CMOS process, the total power consumption of the comparator module in the 64-core computing engine of this invention is 0.2573 mW, equivalent to approximately 0.0040 mW per core. The readout module, responsible for processing all 64 core digital signals, has a total power consumption of 0.1486 mW, equivalent to approximately 0.0023 mW per core. Therefore, the equivalent power consumption of a single ADC is approximately 0.0063 mW. Compared to existing ADC implementations (including 8-bit ADCs using 28-nm and 32-nm CMOS processes), the design of this invention achieves power consumption reductions of 98.8% and 99.9%, respectively. These results demonstrate that the operational amplifier-less, time-domain-based ADC employed in this invention significantly improves the power efficiency of analog in-memory computing systems. Table VI Comparison of ADC power consumption in matrix-vector multiplication

[0139] 3) Throughput: The architecture of this invention utilizes a single capacitor to perform vector multiplication, arranged as a unit block containing 640 capacitors for highly parallel processing. The analog-to-digital conversion of the computed output is performed simultaneously with the voltage decay of the capacitors. By leveraging numerical repeatability, row-by-row parallel computation, and a four-stage pipeline design, matrix multiplication is simplified and scalability is significantly improved, thereby substantially increasing throughput. Regarding power efficiency, unlike memristor- and PCM-based architectures that rely on high-energy-consuming current summation for addition, the architecture of this invention achieves addition through charge accumulation, thus completely avoiding current summation and its associated IR voltage drop problems. Furthermore, the use of narrow voltage spike signals for charge control, combined with a unique operational amplifier-less time-domain ADC design, further enhances power efficiency.

[0140] Figure 17Table VII compares the architecture of this invention with state-of-the-art designs in terms of throughput, area efficiency, and power efficiency. In terms of throughput, the multiplication of two 5120 × 5120 matrices (approximately 0.2684 trillion operations per second) is completed within a 15.68 ms delay (see Section VI-C), achieving a raw throughput of 17.12 TOPS. Regarding power efficiency, considering only the MVM operating power (3.1115 × 8 mW for the compute core and 1.4860 × 8 mW for the read module), the architecture of this invention achieves a raw power efficiency of 465.47 TOPS / W at 4-bit precision using a 40-nm CMOS process and a 0.9-V supply voltage. Consistent with previous work in this field, this evaluation excludes energy overhead associated with intermediate data buffering and movement. To ensure a fair comparison of architectures at different precisions, all throughput values ​​have been normalized to 8-bit arithmetic operations. The architecture of this invention achieves an equivalent power efficiency 2.9 times higher than state-of-the-art analog in-memory computing accelerators. This significant power efficiency gain stems primarily from three core innovations: narrow voltage spike signal representation, analog computing based on charge accumulation and decay, and an operational amplifier-free time-domain ADC design.

[0141] VII. Conclusion

[0142] This disclosure proposes a capacitance-based computation architecture that leverages the inherent charge dynamics of capacitors to achieve a design for high-efficiency matrix multiplication. Matrix elements are encoded as spike amplitudes and spike timings, enabling analog dot product calculations directly from the charging and discharging behavior of capacitors. Key innovations include: a dual amplitude-time encoding scheme for constant-time analog dot product calculations; a capacitor attenuation-based decoding strategy to reduce reliance on high-power ADCs; a row-parallel computation architecture for concurrently performing dot product calculations across multiple rows to maximize throughput; and a multiplication simplification scheme that reduces the multiplication operation to constant-time complexity by utilizing the numerical repeatability in low-bit quantization vectors. Furthermore, this invention overcomes key constraints in current MVM computation paradigms. PCB-level experiments achieved a range-normalized RMSE of 1.80% (only 69.2% of the error of state-of-the-art RRAM cross-array designs) and a normalized error of 9.18% (only 77.1% of the error of leading PCM cross-array solutions). Furthermore, chip-level simulation achieved a range-normalized RMSE as low as 0.23% in large-scale vector multiplication. Using a 40-nm CMOS process, a single 5120 × 5120 matrix multiplication was completed within 15.68 ms under 4-bit arithmetic conditions, achieving a power efficiency of 465.47 TOPS / W. Compared to existing accelerators based on memristors, memcapacitors, and PCM, the power efficiency of this invention's architecture is improved by 2.9 times; this improvement is attributed to narrow voltage spikes, analog computation based on charge accumulation and decay, and an operational amplifier-free ADC design based on time-domain transformation. This work demonstrates that capacitive computing is a promising low-power and highly scalable approach, well-suited for neuromorphic systems and edge AI systems, and provides a compatible foundation for future technological developments.

[0143] The foregoing description primarily elucidates the theoretical principles, computational mechanisms, and performance characteristics related to capacitance-based matrix multiplication. Based on these principles and mechanisms, this invention further provides physical circuit structures, hardware components, and a cooperative system architecture for implementing the disclosed matrix multiplication operations. Specifically, the following description introduces hardware-level configuration methods through which the aforementioned computational principles are implemented in interconnected functional units and physical computational structures.

[0144] Figure 18A block diagram of a capacitance-based matrix multiplication system 1800 according to an embodiment of the present invention is shown. The capacitance-based matrix multiplication system 1800 may include a memory controller 1810, a memory circuit 1820, a controller circuit 1830, an analog computing core array 1840, a reader circuit 1850, and a scheduler circuit 1860. These components may be connected or coupled to each other to transmit signals, exchange data, and coordinate operations. The capacitance-based matrix multiplication system 1800 is configured to perform matrix multiplication by simulating the charge accumulation and discharge behavior of one or more capacitors in the analog computing core array 1840, thereby providing a hardware-based computing architecture for artificial intelligence applications.

[0145] The memory controller 1810 is configured to transfer matrix data to and retrieve matrix data from the storage circuit 1820. The memory controller 1810 may further manage data transfer between the capacitor-based matrix multiplication system 1800 and one or more external storage resources. In some embodiments, the memory controller 1810 may control the loading of matrix data into the storage circuit 1820 and the output of calculation results from the storage circuit 1820. In some embodiments, the memory controller 1810 may correspond to... Figure 6 The memory controller shown is 1810. The memory controller 1810 can be implemented using dedicated control logic, interface circuitry, one or more bus controllers, and / or other data transmission circuitry to support the transfer of matrix data and computation results.

[0146] Storage circuit 1820 is configured to store matrix data, intermediate data, and / or calculation results used by capacitance-based matrix multiplication system 1800. Storage circuit 1820 may provide the stored matrix data to controller circuit 1830 to generate analog spike signals and may receive digital results from reader circuit 1850 after the capacitance-based calculation is completed. In some embodiments, storage circuit 1820 may include one or more on-chip memory resources, buffer circuits, register resources, SRAM resources, and / or other data storage circuits. In some embodiments, storage circuit 1820 may correspond to... Figure 6 The scheduler and related system components shown are associated with one or more storage resources.

[0147] Controller circuit 1830 is configured to acquire matrix data from storage circuit 1820 and generate an analog spike signal based on the matrix data. Analog computing core array 1840 is configured to receive the analog spike signal from controller circuit 1830 and generate an analog calculation result corresponding to the dot product operation. Reader circuit 1850 is configured to receive the signal from analog computing core array 1840 and determine the digital result of the dot product operation. Scheduler circuit 1860 is configured to coordinate data transmission and timing control among controller circuit 1830, analog computing core array 1840, and reader circuit 1850; and the digital result determined by reader circuit 1850 can be stored in storage circuit 1820. This architectural arrangement corresponds to the system hierarchy relationship between the controller, multiple analog computing cores, reader, and scheduler mentioned in the foregoing aspects of the present invention.

[0148] The following paragraphs further describe the functionality and exemplary implementation of the controller circuit 1830, the analog computing core array 1840, the reader circuit 1850, and the scheduler circuit 1860. In some embodiments, these components may correspond to... Figure 6 The relevant system hierarchical functional structure is shown.

[0149] The controller circuit 1830 may include an encoding unit 1832, a matrix simplification unit 1834, and a spike generation unit 1836. The matrix simplification unit 1834 is configured to identify repeated absolute values ​​in the quantized column vector, group the corresponding matrix elements, and pre-accumulate the grouped values ​​to reduce the number of multiplication operations. The encoding unit 1832 is configured to apply an amplitude encoding scheme to the matrix data, where the spike amplitude corresponds to the matrix row elements; and the spike timing is determined by the scheduler circuit 1860 based on the matrix column elements. The spike generation unit 1836 is configured to generate an analog spike signal based on the outputs of the encoding unit 1832 and the matrix simplification unit 1834, and provide the analog spike signal to the analog computing core array 1840. In some embodiments, the controller circuit 1830 may correspond to... Figure 6 The controller shown; and the encoding unit 1832, matrix simplification unit 1834, and spike generation unit 1836 can correspond to Figure 6 The functional parts implemented by the controller module and related sub-components shown (including parts corresponding to arithmetic processing, data storage, and temporary peak holding).

[0150] The analog computing core array 1840 may include multiple analog computing cores arranged in a row-parallel architecture. Each analog computing core is configured to compute the dot product between a matrix row and a column vector concurrently and independently relative to the other cores. In some embodiments, the analog computing core array 1840 may correspond to Figure 6Multiple cores are shown within one or more computing engines; and each analog computing core included in the array may further include digital-to-analog converter circuitry, capacitors, and comparator circuitry (such as...). Figure 7 (As further shown). The digital-to-analog converter circuit is configured to convert the analog spike signal into a voltage pulse, the capacitor is configured to accumulate and release charge in response to the voltage pulse to generate a time-varying voltage corresponding to the analog dot product result, and the comparator circuit is configured to detect the deviation of the time-varying voltage from the equilibrium level.

[0151] The reader circuit 1850 is electrically connected to the analog computing core array 1840 and is configured to determine the digital result of each dot product operation by measuring the time interval required for the time-varying voltage to return to (or toward) a balance level and converting that time interval into a quantized value using a time-based decoding scheme. In some embodiments, the reader circuit 1850 may receive signals output from comparator circuits within each core of the analog computing core array 1840. In some embodiments, the reader circuit 1850 may correspond to... Figure 6 The reader module shown may include a combination of Figure 6 The functions described herein correspond to symbol checking and result collection. Therefore, the reader circuit 1850 can determine whether the corresponding calculation result is positive or negative, and can store or output the corresponding decoding result.

[0152] Scheduler circuit 1860 is configured to provide scheduling signals, control signals, address signals, and / or timing coordination signals to controller circuit 1830, analog computing core array 1840, and reader circuit 1850. In some embodiments, scheduler circuit 1860 may correspond to Figure 6 The scheduler shown may include control logic and storage resources (or cooperate with it) for scheduling matrix-vector multiplication operations, for example, corresponding to Figure 6 The storage resources shown include SRAM, spike ROM, positive result ROM, and negative result ROM. Furthermore, the scheduler circuit 1860 can also obtain matrix B data from the storage circuit 1820 to generate timing control signals. The storage circuit 1820 may correspond to data storage resources used for temporary storage of matrix data and / or calculation results, and in some embodiments, may correspond to... Figure 6 The on-chip memory resources associated with the scheduler and / or other system components are shown. The memory controller 1810 may correspond to... Figure 6 The memory controller shown is configured to manage data transfer between the memory circuitry 1820 and external memory. Therefore, Figure 18 Provided Figure 6 The system hierarchy representation of the architecture shown is as follows, and Figure 6The specific module implementation methods and additional sub-features shown may be selectively incorporated into system 1800 in some embodiments.

[0153] Through the coordinated operation of the memory controller 1810, storage circuitry 1820, controller circuitry 1830, analog computing core array 1840, reader circuitry 1850, and scheduler circuitry 1860, the capacitor-based matrix multiplication system 1800 provides a complete hardware architecture for receiving matrix data, generating analog spike signals, performing row-parallel capacitor-based computations, decoding analog computation results, and storing digital results. By distributing these functions to mutually coordinated system-level components, the capacitor-based matrix multiplication system 1800 strongly supports efficient matrix multiplication while reducing reliance on traditional current-based summation architectures and high-power analog-to-digital converter arrangements. Therefore, the capacitor-based matrix multiplication system 1800 provides a physically implemented computing architecture suitable for accelerating artificial intelligence.

[0154] Although Figure 18 The system-level component arrangement for implementing capacitance matrix multiplication is shown, but additional details regarding the computation process within a single analog computing core will be further described below in conjunction with the core-level architecture. The following description will focus on the circuit-level configuration corresponding to the analog computing cores in the analog computing core array 1840 to illustrate how analog spike signals are converted into voltage-based dot product calculations, and how these results are detected and decoded.

[0155] Figure 19 A block diagram of an analog computing core 1900 according to an embodiment of the present invention is shown. The analog computing core 1900 may include a spike signal input terminal 1902, a resistive trapezoidal DAC 1910, a DAC output node 1912, a capacitor 1920, a comparator circuit 1930, a positive output path 1932, and a negative output path 1934. These components may be connected or coupled to each other to transmit signals and support capacitance-based dot product calculations. In some embodiments, Figure 19 The simulation computing core 1900 shown can correspond to Figure 18 The circuit hierarchy representation of the cores contained in the 1840 analog computing core array can be further corresponding to... Figure 7 The relevant circuit structure is shown.

[0156] Spike signal input 1902 is configured to receive a spike signal for capacitance-based calculations. In some embodiments, the signal received at spike signal input 1902 is a combination of... Figure 18The described controller circuit 1830 is triggered. The analog spike signal can be encoded with matrix-related information according to an amplitude-time encoding scheme and provided to the resistive trapezoidal DAC 1910 to subsequently generate a voltage signal for dot product operations.

[0157] The resistive trapezoidal DAC 1910 is configured to convert a digital spike signal into an analog voltage signal for capacitance-based calculations. In some embodiments, the resistive trapezoidal DAC 1910 may include a passive resistor network configured to generate multiple voltage levels corresponding to different spike amplitudes. The resistive trapezoidal DAC 1910 provides an output signal to DAC output node 1912; and DAC output node 1912 provides a voltage node through which the calculation-related signal is provided to capacitor 1920 and monitored by comparator circuit 1930.

[0158] Capacitor 1920 (also referred to as CAP) is electrically connected to DAC output node 1912 and is configured to accumulate and release charge in response to a voltage signal generated by the resistive trapezoidal DAC 1910. Through this charging and discharging behavior, capacitor 1920 can generate a time-varying voltage corresponding to the simulation result of a dot product operation. In some embodiments, capacitor 1920 corresponds to a computational capacitor for implementing capacitance-based multiplication and accumulation behavior. Therefore, capacitor 1920 provides a physical computational element through which analog spike signals are converted into capacitance-based dot product results.

[0159] Comparator circuit 1930 (also referred to as COMP) is electrically connected to DAC output node 1912 and is configured to monitor the voltage associated with capacitor 1920. Comparator circuit 1930 can detect deviations of the monitored voltage from a balance level and can generate one or more output signals to indicate the behavior of the monitored voltage falling back towards the balance level. In some embodiments, comparator circuit 1930 corresponds to a circuit structure specifically designed to detect the time interval associated with the convergence of the time-varying voltage generated by capacitor 1920. Therefore, comparator circuit 1930 works in conjunction with capacitor 1920 to convert the analog dot product result into a form suitable for time-based decoding.

[0160] Positive output path 1932 and negative output path 1934 are configured to output signals corresponding to different voltage conditions detected by comparator circuit 1930. In some embodiments, positive output path 1932 is associated with a condition where the monitored voltage is above the equilibrium level, while negative output path 1934 is associated with a condition where the monitored voltage is below the equilibrium level. Therefore, the two output paths provide output signals that can be used to derive information related to the dot product operator and time interval information. In some embodiments, the output signals of positive output path 1932 and negative output path 1934 are provided to... Figure 18 The reader circuit 1850 in the middle is used to determine the result of the digital calculation.

[0161] The resistive trapezoidal DAC 1910, DAC output node 1912, capacitor 1920, comparator circuit 1930, positive output path 1932, and negative output path 1934 work together to implement capacitance-based dot product calculations within the analog computing core 1900. More specifically, the resistive trapezoidal DAC 1910 converts the received analog spike signal into a voltage signal, the capacitor 1920 generates a time-varying voltage through charge accumulation and release, and the comparator circuit 1930 detects the fading behavior of this time-varying voltage and generates corresponding output signals on the positive and negative output paths. Through this collaboration, the analog computing core 1900 provides a circuit-level architecture for implementing analog calculations and outputting result signals within the capacitance-based matrix multiplication system 1800.

[0162] In some embodiments, the resistive trapezoidal DAC 1910 includes a passive resistor network having a plurality of resistive elements arranged in a trapezoidal configuration. For example, the network may include a first resistive element having a first resistance value and a second resistive element having a second resistance value greater than the first resistance value (e.g., a repeating R / 2R relationship). The resistive trapezoidal DAC 1910 also includes a plurality of digital inputs corresponding to each bit of the input signal; the passive resistor network can divide the power supply voltage into a plurality of discrete voltage levels according to the state of these digital inputs. In this way, the resistive trapezoidal DAC 1910 generates voltage signals of different amplitudes for capacitance-based calculations.

[0163] In some embodiments, the DAC output node 1912 corresponds to an internal computation node where a resistive trapezoidal DAC 1910 provides its output, and the computation-related voltage is thus supplied to a capacitor 1920 and a comparator circuit 1930. The capacitor 1920 is connected between the DAC output node 1912 and a reference node, such as a lower power supply node or a ground node. For example, the capacitor 1920 may be implemented as a ground capacitor connected to a grounded capacitor corresponding to the VSS reference potential. With this arrangement, the capacitor 1920 accumulates charge when the resistive trapezoidal DAC 1910 drives the DAC output node 1912 to a first voltage range; and releases charge when the DAC output node 1912 falls back towards a balance level, thereby generating a time-varying voltage suitable for dot product calculations.

[0164] In some embodiments, comparator circuit 1930 includes one or more inverter-based comparator stages coupled to power supply nodes, such as an upper power supply node corresponding to VDD and a lower power supply node corresponding to VSS. Comparator circuit 1930 receives a voltage associated with DAC output node 1912 and / or capacitor 1920 and compares it to a balance level. Positive output path 1932 includes a first inverter path associated with a voltage above the balance level condition, and negative output path 1934 includes a second inverter path associated with a voltage below the balance level condition. In some embodiments, positive output path 1932 includes an even number of inverter stages, while negative output path 1934 includes an odd number of inverter stages.

[0165] In some embodiments, when the voltage at DAC output node 1912 is driven above the equilibrium level, capacitor 1920 is charged, and comparator circuit 1930 triggers positive output path 1932 to output a corresponding signal. When the voltage at DAC output node 1912 is driven below the equilibrium level, capacitor 1920 is discharged, and comparator circuit 1930 triggers negative output path 1934 to output a corresponding signal. The duration and / or sequence of the output signals via these two paths are used to determine the sign-related and amplitude-related information of the dot product result.

[0166] In some embodiments, the arrangement of the resistive trapezoidal DAC 1910, DAC output node 1912, capacitor 1920, and comparator circuit 1930 tightly integrates the analog-to-digital conversion process with the process of calculating the voltage drop back to a balanced level. Therefore, the analog computing core 1900 provides a highly energy-efficient circuit configuration: voltage generation, capacitor-based computation, and result signal output are all performed collaboratively without relying on a separate and high-power analog-to-digital conversion module.

[0167] During operation, matrix data associated with matrices A and B are transferred by the memory controller 1810 and stored in the storage circuit 1820 to perform large-scale parallel matrix multiplication in transit via capacitance calculation. In some embodiments, matrices A and B may each be represented as 4-bit signed data. The controller circuit 1830 obtains matrix A data from the storage circuit 1820 and processes it through the matrix simplification unit 1834, the encoding unit 1832, and the spike generation unit 1836; simultaneously, the scheduler circuit 1860 also obtains matrix B data from the storage circuit 1820 to generate timing control signals. More specifically, the matrix simplification unit 1834 identifies repeated absolute values ​​in the quantized column vectors of matrix B, groups corresponding elements in matrix A, and pre-accumulates the grouped values ​​to reduce the number of multiplication operations to a constant level. The encoding unit 1832 applies an amplitude encoding scheme to the matrix data, with spike amplitudes corresponding to the row elements of matrix A; while the spike timing is determined by the scheduler circuit 1860 based on the column elements of matrix B. Based on this processing, the spike generation unit 1836 generates a series of analog spike signals and provides them to the individual cores arranged in a row-parallel architecture in the analog computing core array 1840.

[0168] Within each analog computing core 1900, the input signal is received at the spike signal input terminal 1902 and provided to the resistive trapezoidal DAC 1910. In some embodiments, this input signal comprises a 4-bit signed digital input corresponding to the row element of matrix A and associated with the generation of the analog spike. The resistive trapezoidal DAC 1910 may be implemented as an R-2R trapezoidal DAC, comprising a passive resistor network configured to divide a reference voltage into multiple discrete voltage levels selected by the digital input signal. Based on the received input signal, the resistive trapezoidal DAC 1910 generates an analog spike signal with an amplitude corresponding to one of the discrete voltage levels and provides the corresponding voltage signal to the DAC output node 1912. A capacitor 1920 is electrically connected to the DAC output node 1912 and accumulates and releases charge in response to the voltage signal to generate a time-varying voltage corresponding to the simulation result of the dot product operation. In some embodiments, the time-varying voltage falls back toward a balance voltage level corresponding to VDD / 2; thus, fast charging behavior above VDD / 2 and fast discharging behavior below VDD / 2 are used for capacitance-based calculations, with capacitor 1920 thus serving as the primary component for vector multiplication.

[0169] Comparator circuit 1930 is electrically connected to capacitor 1920 and / or DAC output node 1912, and monitors the voltage associated with capacitor 1920. Because the input of comparator circuit 1930 is directly connected to the transistor gate, the resistive ladder DAC 1910 can exclusively control the charge injection and release of capacitor 1920, thereby minimizing charge leakage and maintaining computational accuracy and signal integrity. Comparator circuit 1930 detects the deviation of the monitored voltage from the equilibrium voltage level and generates a signal indicating the time interval required for the voltage to fall back to the equilibrium level. In some embodiments, comparator circuit 1930 includes a positive output path 1932, such as a "greater than" path corresponding to OUTP containing an even number of inverters, and a negative output path 1934, such as a "less than" path corresponding to OUTN containing an odd number of inverters. When the monitored voltage is higher than the equilibrium voltage level, positive output path 1932 outputs logic 1; when the monitored voltage is lower than the equilibrium voltage level, negative output path 1934 outputs logic 1. Therefore, the order and duration of the signals on OUTP and OUTN indicate the sign-related and amplitude-related information of the dot product operation. The reader circuit 1850 receives the signals output from the comparator circuits of each core in the array, determines the digital result by measuring the time interval and converting it into a quantized value using a time-based decoding scheme (decoding is based on the number of clock cycles elapsed during the convergence of the capacitor voltage to the equilibrium level). During matrix-vector multiplication, the scheduler circuit 1860 coordinates data transmission and timing control throughout the process between the controller, the computing core array, and the reader.

[0170] The digital result determined by the reader circuit 1850 can be stored in the storage circuit 1820 (e.g., in the output register corresponding to the dot product result). In some embodiments, the digital results generated by multiple analog computing cores can collectively constitute the result vector of matrix A multiplication by matrix B (or other matrix multiplication outputs). The result vector or matrix multiplication output can be transferred via the memory controller 1810, output to other processing resources, and / or provided as input to subsequent stages of the neural network model to perform artificial intelligence inference tasks. Therefore, the capacitor-based matrix multiplication system 1800 works closely with the analog computing core 1900 to provide an end-to-end hardware architecture that supports matrix data loading, signal generation, row-parallel capacitor-based dot product calculation, result decoding, result storage, and subsequent utilization of the results. By cleverly integrating analog-to-digital conversion into the capacitor reset process, this architecture effectively reduces or eliminates reliance on traditional high-power, large-area ADCs, thereby significantly improving overall system scalability.

[0171] In summary, this invention provides a capacitor-based matrix multiplication architecture, WireLightning, encompassing circuits, systems, and methods for performing massively parallel matrix multiplication in transit. This invention utilizes the inherent charge accumulation and discharge behavior of passive capacitors to perform dot product calculations and employs a dual amplitude-time encoding scheme (where matrix elements are represented by both peak amplitude and peak timing). Furthermore, this invention employs a time-based decoding scheme to convert analog calculation results into digital results and uses a row-parallel architecture to concurrently process multiple matrix rows.

[0172] Compared to traditional analog and digital matrix multiplication methods, this invention overcomes several limitations associated with weight drift, randomness, IR drop, peripheral circuit overhead, and high-power analog-to-digital conversion. By using transient spike encoding instead of persistent programmable device states to represent matrix-related data, this invention reduces sensitivity to device non-ideal characteristics. By utilizing capacitance-based charge behavior to perform accumulation instead of current summation along shared interconnects, this invention alleviates limitations associated with high-current summation and IR drop. Furthermore, by utilizing repetitive values ​​in low-bit quantization vectors, this invention reduces multiplication complexity to constant levels, thereby significantly improving computational efficiency.

[0173] Experimental and simulation results demonstrate that this invention possesses high precision and high power efficiency. PCB-level experiments achieved a range-normalized RMSE of 1.80% and a normalized error of 9.18%, which are only 69.2% and 77.1% of the errors of comparable RRAM and PCM cross-array implementations reported in the literature, respectively. Chip-level simulation further achieved a range-normalized RMSE of 0.23%. For matrix multiplication of two 5120×5120 matrices, the disclosed architecture achieved a power efficiency of 465.47 TOPS / W in a 40-nm CMOS process with 4-bit precision, representing a 2.9-fold improvement in equivalent power efficiency compared to state-of-the-art analog in-memory computing accelerators.

[0174] Therefore, this invention provides a hardware architecture with extremely high practical value and scalability for accelerating artificial intelligence. By combining passive capacitor computation, time-domain result decoding, row-by-row parallel processing, and multiplication simplification techniques based on repeated quantization values, this invention can support efficient matrix multiplication while significantly reducing reliance on traditional high-power, large-area ADC structures. Thus, the disclosed architecture provides a hardware-level solution highly suitable for neuromorphic computing, edge AI systems, and other applications involving large-scale matrix operations.

[0175] The functional units and modules in the apparatuses and methods disclosed herein can be implemented using computing devices, computer processors, or electronic circuits, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, and other programmable logic devices configured or programmed according to the teachings of this disclosure. The computer instructions or software code running in the computing device, computer processor, or programmable logic device can be readily obtained by those skilled in the art of software or electronics based on the teachings of this disclosure.

[0176] All or part of the methods according to the embodiments can be executed in one or more computing devices, including server computers, personal computers, laptop computers, and mobile computing devices such as smartphones and tablet computers.

[0177] These embodiments may include computer storage media, transient and non-transient storage devices storing computer instructions or software code, which can be used to program or configure a computing device, computer processor, or electronic circuit to perform any of the processes of the present invention. The storage media, transient and non-transient storage devices may include, but are not limited to, floppy disks, optical disks, Blu-ray discs, DVDs, CD-ROMs, magneto-optical disks, ROMs, RAMs, flash memory devices, or any medium or device suitable for storing instructions, code, and / or data.

[0178] The functional units and modules according to various embodiments can also be implemented in distributed computing environments and / or cloud computing environments. In these environments, all or part of the machine instructions are executed in a distributed manner by one or more processing devices interconnected through communication networks, such as intranets, wide area networks (WANs), local area networks (LANs), the Internet, and other forms of data transmission media.

[0179] The foregoing description of the invention is provided for purposes of illustration and description. It is not intended to be exhaustive, nor is it intended to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to those skilled in the art.

[0180] These embodiments were chosen and described in order to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to understand and utilize the various embodiments of the invention, as well as various modifications suitable for a particular intended use.

Claims

1. A simulation computing core for capacitance-based dot product calculation, characterized in that, include: A digital-to-analog converter circuit is configured to receive an input signal associated with spike generation and generate a voltage signal; A capacitor, electrically connected to the digital-to-analog converter circuit, is configured to accumulate and release charge in response to the voltage signal to generate a time-varying voltage corresponding to a dot product operation; as well as A comparator circuit, electrically connected to the capacitor, is configured to monitor the time-varying voltage and generate one or more output signals indicating the time interval associated with the time-varying voltage returning toward a balance level.

2. The simulation computing core according to claim 1, characterized in that, The digital-to-analog conversion circuit includes a resistive trapezoidal digital-to-analog converter.

3. The simulation computing core according to claim 2, characterized in that, The resistive trapezoidal digital-to-analog converter includes an R-2R trapezoidal DAC, wherein the R-2R trapezoidal DAC includes a passive resistor network, and the passive resistor network is configured to divide a reference voltage into multiple selectable discrete voltage levels according to a digital input signal.

4. The simulation computing core according to claim 3, characterized in that, The resistive trapezoidal digital-to-analog converter is configured to receive a 4-bit signed digital input corresponding to a matrix element and output a spike signal, wherein the spike signal has an amplitude corresponding to one of the plurality of discrete voltage levels.

5. The simulation computing core according to claim 1, characterized in that, It also includes a DAC output node, which electrically connects the digital-to-analog converter circuit to the capacitor and the comparator circuit, wherein the input terminal of the comparator circuit is directly connected to the transistor gate, so that the digital-to-analog converter circuit can exclusively control the charge injection and charge release of the capacitor, thereby minimizing charge leakage.

6. The simulation computing core according to claim 1, characterized in that, The comparator circuit includes a positive output path corresponding to OUTP and a negative output path corresponding to OUTN. The positive output path includes an even number of inverters, and the negative output path includes an odd number of inverters. When the time-varying voltage is higher than the equilibrium level, the positive output path is configured to output a high-level signal, and when the time-varying voltage is lower than the equilibrium level, the negative output path is configured to output a high-level signal.

7. The simulation computing core according to claim 6, characterized in that, The comparator circuit is configured such that the order and duration of the signals on OUTP and OUTN indicate sign-related and amplitude-related information corresponding to the digital result of the dot product operation, and wherein the balanced level corresponds to half of the power supply voltage, i.e., VDD / 2.

8. A system for large-scale parallel matrix multiplication in transmission via capacitance-based computation, characterized in that, include: The storage circuit is configured to store matrix data associated with the first matrix and the second matrix; The controller circuit is configured to acquire data of the first matrix from the storage circuit and generate a spike signal according to an amplitude encoding scheme, wherein the spike amplitude corresponds to a matrix element of the first matrix; An analog computing core array comprising a plurality of analog computing cores as claimed in claim 1, the plurality of analog computing cores being arranged in a row-parallel architecture, and each of the analog computing cores being configured to receive the spike signal and generate a time-varying voltage corresponding to a dot product operation between at least a portion of the first matrix and at least a portion of the second matrix. The reader circuit is configured to determine the digital result of the dot product operation based on the time interval associated with the time-varying voltage returning toward the equilibrium level; as well as A scheduler circuit is configured to coordinate timing and data transmission between the controller circuit, the analog computing core array, and the reader circuit, wherein the scheduler circuit determines peak timing based on the matrix elements of the second matrix, and wherein the digital result can be stored in the storage circuit as at least a portion of the matrix multiplication output.

9. The system according to claim 8, characterized in that, The controller circuit includes: An encoding unit is configured to apply the amplitude encoding scheme to the data of the first matrix; A matrix simplification unit is configured to identify repeated absolute values ​​in the quantized column vectors of the second matrix, group corresponding matrix elements in the first matrix, and pre-accumulate the grouped values ​​to reduce the number of multiplication operations; and The spike generation unit is configured to generate the spike signal based on the outputs of the encoding unit and the matrix simplification unit.

10. The system according to claim 9, characterized in that, The encoding scheme is an amplitude-time dual encoding scheme.

11. The system according to claim 8, characterized in that, The reader circuit is configured to determine the digital result by measuring the time interval and converting it into a quantized value using a time-based decoding scheme.

12. The system according to claim 11, characterized in that, The time-based decoding scheme is based on the number of clock cycles that elapse during the time-varying voltage converges to the equilibrium level.

13. The system according to claim 8, characterized in that, The storage circuit includes an output register configured to store the numerical result corresponding to the dot product operation.

14. The system according to claim 8, characterized in that, The digital results generated by the multiple simulation computing cores together form a result vector corresponding to the matrix multiplication of the first matrix and the second matrix.

15. The system according to claim 14, characterized in that, The resulting vector serves as input to subsequent stages of the neural network model to perform artificial intelligence inference tasks.

16. A method for large-scale parallel matrix multiplication in transmission via capacitance-based computation, characterized in that, include: Retrieve the matrix data associated with the first and second matrices; Based on the matrix data, a spike signal is generated according to the encoding scheme, wherein the spike amplitude corresponds to the matrix element of the first matrix, and the spike timing corresponds to the matrix element of the second matrix; The spike signal is provided to multiple analog computing cores arranged in a row-parallel architecture; In each of the aforementioned analog computing cores, a time-varying voltage is generated by accumulating and releasing charge in a capacitor in response to the spike signal, thereby performing a dot product operation; The time interval associated with the return of the time-varying voltage toward the equilibrium level is detected by a comparator circuit; and The numerical result of the dot product operation is determined based on the time interval.

17. The method according to claim 16, characterized in that, Also includes: Before generating the spike signal, identify the repeated absolute values ​​in the quantization column vectors of the second matrix; Group the corresponding matrix elements in the first matrix; as well as Pre-accumulate the grouped values ​​to reduce the number of multiplication operations.

18. The method according to claim 16, characterized in that, Generating the spike signal involves applying an amplitude-time dual encoding scheme to the matrix data.

19. The method according to claim 16, characterized in that, It also includes using a time-based decoding scheme to convert the time interval into a quantized value, the time-based decoding scheme being based on the number of clock cycles elapsed during the convergence of the time-varying voltage toward the equilibrium level.

20. The method according to claim 16, characterized in that, Also includes: The numerical result is stored in the output register corresponding to the dot product result; as well as A result vector is formed based on the digital results generated by the plurality of simulation computing cores. The result vector corresponds to the matrix multiplication of the first matrix and the second matrix. The result vector is used as input to the subsequent stage of the neural network model to perform artificial intelligence inference tasks.

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