A parallelization node admittance matrix solving method and system based on field programmable logic gate array

Abstract

The embodiment of the application provides a parallelization node admittance matrix solving method and system based on a field programmable logic gate array, the method utilizes the natural parallelism of the FPGA, realizes large-scale parallel construction and solving of the node admittance matrix through a distributed processing unit array, compared with traditional central processing unit serial computation, significantly improves the calculation speed, meets the real-time analysis demand of the nuclear power plant, and breaks through the serial computation bottleneck; meanwhile, through the CSR / ELL sparse compression format, the occupation of the on-chip block random access memory resource of the FPGA is greatly reduced, the problem that a large-scale matrix cannot be stored on the chip is solved, meanwhile, through the sparse processing, a large amount of invalid zero element calculation is avoided, the energy efficiency ratio is improved, and the resource utilization ratio is optimized; in addition, the flexible switching of the direct method and the iterative method is supported under the same hardware architecture, the calculation time is shortened, high-speed bottom layer data support is provided for the steady-state, transient-state simulation and fault simulation of the power system of the nuclear power plant, and the real-time requirement is met.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and in particular to a parallelized node admittance matrix solution method and system based on field-programmable gate arrays. Background Technology

[0002] In nuclear power plants, the stability and reliability of the power system are paramount. To ensure effective management and maintenance, detailed analysis and simulation of the system are necessary. The Y-Bus matrix is ​​a fundamental tool in power system analysis, used to describe the electrical connections between nodes in the power system. Traditional methods for solving the Y-Bus matrix primarily rely on serial computation by the Central Processing Unit (CPU), resulting in large computational loads and long processing times, which cannot meet the demands of real-time analysis of large-scale power systems.

[0003] In recent years, with the development of Field-Programmable Gate Array (FPGA) technology, optimizing the node admittance matrix solution process through parallel computing has become a new solution. FPGAs possess high parallel processing capabilities and flexible programmability, which can significantly improve computational speed and efficiency. However, existing FPGA parallelization methods still have some problems when dealing with large-scale power systems, such as low resource utilization and large communication latency.

[0004] Therefore, there is an urgent need for a new FPGA-based parallel node admittance matrix solution method and system to improve computational efficiency and resource utilization, and meet the needs of real-time analysis of nuclear power plant power systems. Summary of the Invention

[0005] This invention provides a parallel node admittance matrix solution method and system based on field-programmable gate arrays, which significantly improves the calculation speed, meets the real-time analysis needs of nuclear power plants, and optimizes resource utilization.

[0006] Firstly, this embodiment provides a parallelized node admittance matrix solution method based on field-programmable gate arrays, including: The main control system divides the power network topology into multiple subnets and maps each subnet to an independent processing unit on a field-programmable gate array (FPGA). Each processing unit is used to independently calculate the node admittance matrix of the corresponding subnet. Within each processing unit, the node admittance matrix of the corresponding subnet is compressed and encoded using a sparse compressed matrix storage format and stored in the on-chip block memory of the FPGA. The sparse compressed matrix storage format includes a compressed row storage format or a fixed-length row storage format. Within each processing unit, a target solution mode is determined based on the solution requirements of the power network topology, and the node admittance matrix is ​​solved based on the target solution mode. The target solution mode is one of the following: a direct solution mode using a parallel triangular decomposer or a Cholisky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication accelerator.

[0007] Secondly, this embodiment provides a parallel node admittance matrix solving system based on a field-programmable gate array (FPGA), including a main control system and a FPGA, wherein the FPGA is configured with multiple processing units: The main control system is used to divide the power network topology into multiple subnets and map each subnet to an independent processing unit on the FPGA, wherein each processing unit is used to independently process the node admittance matrix calculation of the corresponding subnet; The processing unit is used to compress and encode the node admittance matrix of the corresponding subnet using a sparse compressed matrix storage format and store it in the on-chip block memory of the FPGA. The sparse compressed matrix storage format includes a compressed row storage format or a fixed-length row storage format. The processing unit is further configured to determine the target solution mode according to the solution requirements of the power network topology, and solve the node admittance matrix based on the target solution mode, wherein the target solution mode is one of the following: a direct solution mode using a parallel triangular decomposer or a Cholisky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication accelerator.

[0008] This invention provides a parallel node admittance matrix solution method and system based on a field-programmable gate array (FPGA). The method includes: dividing a power network topology into multiple subnets using a main control system, and mapping each subnet to an independent processing unit on an FPGA, wherein each processing unit independently processes the node admittance matrix calculation for its corresponding subnet; within each processing unit, compressing and encoding the node admittance matrix of the corresponding subnet using a sparse compressed matrix storage format, and storing it in the on-chip block memory of the FPGA, wherein the sparse compressed matrix storage format includes a compressed row storage format or a fixed-length row storage format; within each processing unit, determining a target solution mode according to the solution requirements of the power network topology, and solving the node admittance matrix based on the target solution mode, wherein the target solution mode is one of the following: a direct solution mode using a parallel triangular decomposer or a Chorisky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication accelerator. The aforementioned technical solution leverages the inherent parallelism of FPGAs to achieve large-scale parallel construction and solution of node admittance matrices through a distributed processing unit array. Compared to traditional serial computation by a central processing unit, this significantly improves computation speed, meets the real-time analysis needs of nuclear power plants, and breaks through the bottleneck of serial computation. Simultaneously, by using a compressed row storage format or a sparse compression format with a fixed-length row storage format, the occupancy of on-chip block random access memory resources on the FPGA is greatly reduced, solving the problem of large-scale matrices not being able to be stored on-chip. Furthermore, sparsification avoids a large number of invalid zero-element calculations, improving energy efficiency and optimizing resource utilization. In addition, by integrating a parallel triangular decomposer or a Chorisky decomposer with a sparse matrix-vector multiplication accelerator within the same hardware architecture, it supports flexible switching between direct and iterative methods, reducing computation time from seconds to milliseconds. This provides high-speed underlying data support for steady-state, transient, and fault simulation of nuclear power plant power systems, meeting real-time requirements.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1This is a flowchart illustrating a parallelized node admittance matrix solution method based on field-programmable gate arrays provided in Embodiment 1 of the present invention. Figure 2 This is a schematic diagram of a parallel node admittance matrix solving system based on field-programmable gate arrays provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "currently," "preceding," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0014] It should be noted that existing technologies have the following drawbacks: 1) Insufficient sparsity handling: While hardware mapping is primarily used for relatively conventional matrix operations and pipelined parallelism is utilized, specific storage optimizations are not implemented for the highly sparse nature of power system matrices. This results in significant waste of zero-element computation and storage, leading to low resource utilization. Communication bottleneck: Reliance on off-chip storage for large-scale matrix operations results in substantial data interaction latency. 2) Lack of direct decomposition support: The focus is mainly on hardware implementation of iterative methods. Although sparse matrix-vector multiplication (SpMV) accelerators offer excellent performance, convergence and accuracy are poor in certain scenarios. 3) Lack of domain-specific optimization: General-purpose mathematical solvers do not incorporate the topological characteristics of power systems for "network partitioning" and "distributed construction," nor do they address the specific real-time simulation interface design for nuclear power plants, making it difficult to directly meet the millisecond-level online update requirements of power systems. Therefore, a method is needed to address these issues.

[0015] Example 1 Figure 1 This is a flowchart illustrating a parallel node admittance matrix solution method based on field-programmable gate arrays (FPGAs) provided in Embodiment 1 of the present invention. This method is applicable to the case of solving parallel node admittance matrices based on FPGAs. This method can be executed by a parallel node admittance matrix solution system based on FPGAs. This parallel node admittance matrix solution system based on FPGAs can be implemented in hardware and / or software and is generally integrated into electronic devices.

[0016] like Figure 1 As shown, the parallelized node admittance matrix solution method based on field-programmable gate arrays provided in this embodiment may specifically include the following steps: S101. The power network topology is divided into multiple subnets by the main control system, and each subnet is mapped to an independent processing unit on a field programmable gate array (FPGA). Each processing unit is used to independently process the node admittance matrix calculation of the corresponding subnet.

[0017] Preferably, the main control system and the FPGA communicate and control data through a high-speed interface.

[0018] It should be noted that, since the power system of nuclear power plants often exhibits a network topology characterized by local density and global sparseness, the method provided in this embodiment can be adapted to various nuclear power plant grid structures by configuring different compression strategies and processing unit partitioning methods, such as single-unit power supply islands, dual-unit interconnection structures, and nuclear power plant external transmission main transformer systems.

[0019] In this embodiment, the main control system can be understood as a system that sends instructions to the FPGA and receives feedback data from the FPGA. For example, the main control system can be a processor (Advanced RISC Machine, ARM), PowerPC, or a Linux embedded application. PowerPC is a central processing unit with a reduced instruction set architecture. A low-latency external high-speed serial expansion bus standard (PCIe) / system-on-chip interconnect protocol (Avalon) interface is designed for high-speed data interaction and instruction control between the FPGA and the main control system. The main control program implements dynamic reconstruction and solution process management after network topology changes.

[0020] Based on the above description, and according to common combinations of FPGA platforms and main control systems, two complementary interface structures are adopted: 1) PCIe interface (such as PCI Express Gen3 / Gen4): suitable for x86 or high-performance ARM main control systems; 2) Avalon-MM interface: suitable for soft-core main control systems or Nios II embedded systems. The PCIe interface uses a multi-channel PCIe interface core based on Direct Memory Access (DMA), with the following functions: supports high-bandwidth transmission: Gen3 x8 bandwidth up to 6.4 GB / s; configured with two DMA engines: a transmit (TX) channel (main control system → FPGA): used for writing Y matrices, input vectors, and solving control parameters; and a receive (RX) channel (FPGA → main control system): used for reading calculation results (such as voltage vectors); supports burst transmission and linked list-style packet scheduling to improve the efficiency of continuous memory block processing; and can be connected to an Advanced eXtensible Interface (AXI) or Avalon bus to bridge and control internal FPGA modules.

[0021] Then, internal bus protocol adaptation is performed. After receiving data via PCIe, it is automatically mapped to the FPGA's internal AXI-Lite bus or Avalon-MM control channel. Read and write status buffers are set up to support asynchronous transmission and reception and instruction queues. The instruction format can be configured to facilitate the unified issuance of "calculation-write-reconstruction" control flow by the main control system. Among them, AXI-Lite or Avalon-MM are the memory-mapped bus protocols of the FPGA.

[0022] The above-mentioned efficient interface collaborative design and chained DMA transfer reduce data transfer overhead, ensure high system response speed, and reduce communication latency.

[0023] In this embodiment, an FPGA distributed construction mechanism based on node admittance matrices is employed to partition the power network topology of the entire nuclear power plant to minimize the coupling between nodes. Each subnet is designated as a subnet, and each subnet corresponds to an independent processing element (PE) on the FPGA chip. Specifically, the power network topology can be viewed as a set containing multiple nodes. The entire nuclear power plant's power network topology is partitioned into graphs using multi-level graph partitioning algorithms (such as Metis and SCOTCH). Each subdomain has tightly connected nodes, while inter-domain connections are minimal, facilitating distributed execution on the hardware platform and reducing inter-chip communication. Each subdomain is designated as a subnet. Metis and SCOTCH are two graph partitioning tools. For example, by using a graph partitioning algorithm (such as Metis) to divide the nuclear power plant's power network topology into multiple subnets and independently mapping each subnet to a processing element on the FPGA chip, a distributed processing element array structure is formed, achieving a distributed parallel architecture.

[0024] Each subnet is assigned to an independent processing unit on the FPGA. The processing unit contains the following modules: node admittance information receiving module; sparse matrix compression and storage module; local matrix construction and update unit; and boundary node processing module (used to handle coupled nodes across subnets).

[0025] Understandably, when the power network topology is adjusted (such as line access / exit), the main control system can send a topology update command. After receiving the command, the FPGA only modifies the sparse structure of the corresponding subnet without shutting down the entire system, thus realizing hot-swapping and dynamic topology adaptation.

[0026] S102. Within each processing unit, the node admittance matrix of the corresponding subnet is compressed and encoded using a sparse compressed matrix storage format and stored in the on-chip block memory of the FPGA.

[0027] The sparse compressed matrix storage format includes compressed sparse row storage format (CSR) or fixed-length row storage format (ELL).

[0028] In this embodiment, considering the limited on-chip resources of the FPGA, a sparse compressed matrix storage format is used inside the processing unit to compress, store, and encode the node admittance matrix, replacing the traditional dense matrix storage. Since the FPGA has limited on-chip resources, dense matrix storage cannot be used directly. Therefore, this embodiment uses a sparse matrix compression structure to efficiently encode the node admittance matrix. It mainly supports the following two formats: Compressed SparseRow (CSR) format: val[]: array of non-zero elements; col_ind[]: column index of each non-zero element; row_ptr[]: starting position of the first non-zero element in each row within the val array. In the FPGA logic, these three arrays are stored in block RAM (BRAM) and solved row by row through a finite state machine scheduling. Fixed-length row storage format (ELLPACK, ELL): Suitable for more regular networks, it uses two two-dimensional arrays: val[i][j]: the j-th non-zero element value in the i-th row; col[i][j]: the corresponding column index. The ELL structure facilitates parallel processing, adapts to concurrent operations of multiple computing units in FPGAs, and is beneficial for pipelined architecture construction.

[0029] In this embodiment, the main control system or external data bus writes the original network topology, branch parameters, and other information into the FPGA cache via DMA. The matrix construction unit inside the FPGA automatically inserts non-zero elements into the CSR or ELL structure based on the branch admittance and node connection relationship, and executes the following rules: for each branch, update; if the connection topology or component parameters change, incremental updates to the sparse matrix structure are supported to avoid full matrix reconstruction.

[0030] Each processing unit employs the following internal structure: Branch receiving and transformation module: receives branch parameters and calculates the corresponding admittance; Sparse matrix encoding unit: implements CSR / ELL structure filling; Node accumulator module: used to aggregate multiple branch admittances to the same node; Output buffer controller: sends the constructed Y matrix fragments to the decomposer.

[0031] In this embodiment, considering the limited on-chip resources of the FPGA, the following optimization strategies are adopted: using a hybrid storage of BRAM and Look-UpTable Random Access Memory (LUTRAM) to store the sparse matrix; using dual-port RAM to achieve parallel matrix reading and writing; using polling clock scheduling in the multi-processing unit structure to avoid write conflicts; and using fixed-point representation for small-scale branch admittance to save resources.

[0032] As described above, for the inter-chip communication mechanism, processing units communicate via a shared boundary node buffer, using a First-In, First-Out (FIFO) structure for data exchange. For subnetting across FPGA chips, a high-bandwidth AXI bus or fiber optic communication interface is used for synchronous updates of admittance values.

[0033] Specifically, a sparse matrix compression storage structure (such as CSR or ELL format) is used to optimize and compress the node admittance matrix (i.e., the Y matrix) to adapt to the limited on-chip storage resources of the FPGA.

[0034] S103. Within each processing unit, a target solution mode is determined according to the solution requirements of the power network topology, and the node admittance matrix is ​​solved based on the target solution mode.

[0035] The objective solution mode is one of the following: a direct solution mode using a parallel triangular (LU) decomposer or a Cholesky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication (SpMV) accelerator.

[0036] In this embodiment, for the parallel LU / Cholesky decomposer: a set of hardware pipeline circuits is constructed to support the parallel execution of LU decomposition or Cholesky decomposition, which is suitable for the efficient solution of symmetric positive definite Y matrices (i.e., nodal admittance matrices) and improves the computational throughput on causal dependency chains. For the hardware-level SpMV: a custom SpMV module is implemented inside the FPGA, combined with on-chip block memory and a data access scheduler, to achieve parallel memory access and computation, thereby improving the performance of iterative solutions.

[0037] In this embodiment, within each processing unit, based on the solution requirements of the power network topology, a solution mode is selected as the target solution mode from either a parallel LU / Cholesky decomposer or a SpMV accelerator, and the node admittance matrix is ​​solved based on the target solution mode. The parallel LU / Cholesky decomposer and SpMV accelerator are integrated under the same hardware architecture, supporting flexible switching between direct and iterative methods.

[0038] Understandably, the entire process of the parallelized node admittance matrix solution method can be described as follows: the main control system controls the operation of each computation module within the FPGA through a command queue, including: 1) loading new Y matrix data; 2) starting SpMV iterative computation; 3) starting the LU / Cholesky solution; 4) returning the computation results to the main control system; and 5) resetting the CSR index and task scheduling table according to topology changes. These commands are sent to the FPGA via PCIe chained DMA or Avalon command buffer FIFO.

[0039] Furthermore, a two-way status synchronization mechanism is established between the main control system and the FPGA: the FPGA reports computation completion interruptions, abnormal status codes, and matrix dimension mismatch warnings to the main control system; the main control system updates the scheduling status table and decides whether to proceed to the next stage of computation, wait for new data, or reconstruct the matrix; optional soft interrupt or polling mechanisms can be used to ensure the timely response of the main control system's decisions.

[0040] The aforementioned technical solution leverages the inherent parallelism of FPGAs to achieve large-scale parallel construction and solution of node admittance matrices through a distributed processing unit array. Compared to traditional serial computation by a central processing unit, this significantly improves computation speed, meets the real-time analysis needs of nuclear power plants, and breaks through the bottleneck of serial computation. Simultaneously, by using a compressed row storage format or a sparse compression format with a fixed-length row storage format, the occupancy of on-chip block random access memory resources on the FPGA is greatly reduced, solving the problem of large-scale matrices not being able to be stored on-chip. Furthermore, sparsification avoids a large number of invalid zero-element calculations, improving energy efficiency and optimizing resource utilization. In addition, by integrating a parallel triangular decomposer or a Chorisky decomposer with a sparse matrix-vector multiplication accelerator within the same hardware architecture, it supports flexible switching between direct and iterative methods, reducing computation time from seconds to milliseconds. This provides high-speed underlying data support for steady-state, transient, and fault simulation of nuclear power plant power systems, meeting real-time requirements.

[0041] As an optional embodiment of the present invention, based on the above embodiments, this optional embodiment can further optimize the method by including: a1) When the main control system detects a change in the power network topology, it determines the affected updated subnet and the updated node admittance matrix, and transmits the updated node admittance matrix to the target processing unit corresponding to the updated subnet to replace the node admittance matrix of the previous moment.

[0042] In this embodiment, for power network topology changes during nuclear power plant operation (such as switch changes, line commissioning / decommissioning), incremental updates are supported only for the affected subnets and matrix elements, rather than full matrix reconstruction. The subnets affected by the power network topology change are denoted as the updated subnets, the corresponding affected node admittance matrices are denoted as the updated node admittance matrices, and the FPGA processing units allocated to the updated subnets are denoted as the target processing units.

[0043] Specifically, when the main control system detects a change in the power network topology, it determines the updated subnet and the updated node admittance matrix affected by the topology change, identifies the target processing unit corresponding to the updated subnet, and transmits the updated node admittance matrix to the target processing unit to replace the node admittance matrix from the previous moment. The target processing unit is used to process the updated subnet.

[0044] As a specific implementation, when the main control system detects a change in the power network topology, determining the affected updated subnet and the updated node admittance matrix includes: a11) By comparing the power network topology at the current moment with that at the previous moment in real time through the main control system, the changed branches or nodes can be identified.

[0045] In this embodiment, the main control system monitors the network topology data, compares the current node-branch connection relationships with the previous state in real time, and identifies branches or nodes that have changed. It also identifies topology change events, such as bus isolation and load shedding. For example, the power network topology can be the topology data of a Supervisory Control and Data Acquisition (SCADA) / Energy Management System (EMS) system or simulation model. When a topology change event occurs, a sparse structure reconstruction procedure for the node admittance matrix (such as CSR format reconstruction) is automatically triggered, outputting the latest matrix structure and non-zero element indices, which are then transmitted to the FPGA.

[0046] a12) The subnet to which the changed branch or node belongs is the updated subnet.

[0047] Specifically, the subnet to which the branch or node that will change belongs is called the updated subnet.

[0048] a13) For the updated subnet, recalculate and update the non-zero element values ​​and index information in the corresponding compressed storage structure as the updated node admittance matrix.

[0049] Specifically, for the updated subnet, the non-zero element values ​​and index information in the corresponding compressed storage structure are recalculated and updated, and denoted as the updated node admittance matrix.

[0050] b1) Inside the target processing unit, a target solution mode is determined according to the solution requirements of the power network topology, and the updated node admittance matrix is ​​solved based on the target solution mode.

[0051] Specifically, after the updated node admittance matrix is ​​transmitted to the target processing unit corresponding to the updated subnet, the target processing unit determines the target solution mode based on the solution requirements of the power network topology corresponding to the updated subnet, and solves for the updated node admittance matrix corresponding to the updated coupled subnet based on the target solution mode corresponding to the updated coupled subnet. The solution method is the same as before and will not be repeated here.

[0052] The above technical solution addresses the changes in power network topology during nuclear power plant operation, supporting incremental updates only for affected subnets and matrix elements, rather than full matrix reconstruction. It can flexibly respond to changes in the operation mode of nuclear power plant grids, supports hot-swapping and dynamic reconstruction, and can complete system updates without system downtime, thus improving the robustness and adaptability of the system.

[0053] As an optional embodiment of the present invention, based on the above embodiments, this optional embodiment can optimize the steps of the parallel triangular decomposer or the Chorisky decomposer in solving the nodal admittance matrix, including: a2) Read the node admittance matrix from the on-chip block memory, construct the dependency graph of the node admittance matrix, and identify the rows without dependencies in the dependency graph.

[0054] In this embodiment, the parallel LU / Cholesky decomposer supports mode selection. By configuring and switching between LU and Cholesky modes, it adapts to different matrix structures (symmetric / asymmetric), improving versatility. The overall decomposer consists of multiple hardware sub-modules, constructed into a multi-stage pipeline structure, supplemented by a scheduler, an index decoder, and a numerical computation unit. Specifically, it includes an index parsing module, a division unit, a multiply-accumulate array, a cache register and on-chip sparse memory unit, and a forward elimination scheduler.

[0055] The system includes the following modules: Index parsing module: Reads the non-zero column index of the current processing row from the CSR structure; constructs a "non-zero mask" to guide subsequent computation paths; supports matrix row and column transformations to adapt to sparse strip structures. Division unit: Calculates the quotient in Cholesky or LU; uses a fixed-point divider to optimize accuracy and resource consumption; has pipeline depth control logic to support high-concurrency input. Multiply-accumulate array: Implements vector inner product and forward elimination; multiple multiply-accumulate units are configured per row, activated by sparse indexing; supports dynamic path selection to skip invalid products. Cache register and on-chip sparse memory unit: Stores the computed L or U matrix; uses dual-port BRAM to support concurrent read / write; maintains alignment with the pipeline to avoid read / write conflicts. Forward elimination scheduler: Tracks whether all dependencies (L_ik or U_ki) of each row have been computed; schedules the current row into the pipeline after dependencies are satisfied; achieves "causal dependency chain scheduling decoupling".

[0056] In this embodiment, a parallel and pipeline mechanism is adopted to achieve decoupling of causal dependency chain scheduling. A dependency scheduler is used in the LU / Cholesky decomposer to construct a dependency graph to identify inter-row dependencies. Rows without dependencies are dynamically scheduled to enter the pipeline for parallel execution, breaking the serial waiting.

[0057] In this embodiment, during the decomposition process, dependencies exist between different rows, but not all rows are mutually dependent. Based on this, a dependency graph is constructed, and rows without dependencies in the dependency graph are identified as rows that can be executed in parallel.

[0058] b2) A ready line queue is dynamically maintained by the scheduler, wherein the ready line queue contains the lines in the dependency graph that are currently available for execution in the multi-level pipeline.

[0059] In this embodiment, a scheduler is used to dynamically maintain a ready line queue, which is used to store the lines that are currently available for execution in the multi-level pipeline and have no dependencies as determined above.

[0060] c2) Multiple independent rows in the ready row queue are simultaneously scheduled to the multi-stage pipeline of the parallel triangular decomposer or the Cholisky decomposer for concurrent execution.

[0061] In this embodiment, multiple pipelines of the LU / Cholesky decomposer are allowed to process multiple ready lines concurrently, maximizing hardware utilization.

[0062] It should be noted that this embodiment employs data reuse and memory access optimization, uses a block caching mechanism for the L matrix, and organizes it by column blocks; introduces an L2 cache controller to reduce on-chip BRAM access conflicts; and allows multiple rows to share a set of memory access ports, with access priorities scheduled through an arbitrator.

[0063] The multi-stage pipeline includes, in sequence, an index decoding stage, an existing decomposition item query stage, a multiply-accumulate unit accumulation stage, a division or square root operation stage, and a result write-back and update stage; the multi-stage pipeline adopts a structure that combines forward channels and feedback paths.

[0064] In this embodiment, a multi-stage pipeline is introduced for single-row decomposition: Stage 1: Index decoding stage; Stage 2: Existing decomposition item (L / U) lookup; Stage 3: Multiply-accumulate unit accumulation stage; Stage 4: Division / square root operation stage; Stage 5: Result write-back and update stage. The multi-stage pipeline adopts a "forward path + feedback path" structure, allowing for partial advance scheduling of subsequent stages, thereby improving throughput.

[0065] The above technical solution relies on decoupling technology to maximize the fill rate of the hardware pipeline, reduce the idle cycle of computing units, significantly improve the actual running efficiency of the decomposition algorithm, and increase the computing throughput.

[0066] As an optional embodiment of the present invention, based on the above embodiments, this optional embodiment can optimize the steps of the sparse matrix-vector multiplication accelerator in solving the nodal admittance matrix, including: a3) After reading the elements of the node admittance matrix from the on-chip block memory once, broadcast them to multiple multiply-accumulate units to achieve the reuse of the elements in the node admittance matrix.

[0067] In this embodiment, a "read once, broadcast multiple times" vector broadcasting mechanism is introduced in the sparse matrix vector multiplication (SpMV) accelerator. Combined with on-chip block RAM (BRAM) and a data access scheduler, the pipeline overlap of data reading and multiplication-addition operations is realized, thus parallelizing memory access and computation.

[0068] In this embodiment, the overall sparse matrix-vector multiplication accelerator consists of the following key sub-modules: CSR data cache and parser, vector buffer and broadcast module, sparse multiply-accumulate array, row-level pipeline scheduler, and output write-back and accumulation module.

[0069] The CSR data buffer and parser are as follows: The input sparse matrix uses the CSR format: row pointer array: row_ptr[n+1]; column index array: col_idx[nnz]; non-zero value array: val[nnz]. It is preloaded into the BRAM on the FPGA chip and organized in blocks: each BRAM block corresponds to several rows of data; row pointers are independently buffered for easy indexing; the CSR parser reads row_ptr[i] ~ row_ptr[i+1] of a row to obtain the range of non-zero elements and initiates multiple sets of multiplication operations.

[0070] Vector Buffer and Broadcast Module: Input vectors are stored in a multi-port accessible BRAM buffer; supports vector element queries based on col_idx[]; sets up a local cache (L1-like) to store recently accessed vectors, and supports: recently accessed vector index prediction; read / write conflict arbitration; multiple access reuse (broadcast mode).

[0071] Specifically, after reading the elements of the node admittance matrix from the on-chip block memory once, they are broadcast to multiple multiply-accumulate units to achieve the reuse of elements in the node admittance matrix.

[0072] b3) Using a row-level pipeline scheduler, the multiply-accumulate channel resources are dynamically allocated based on the number of non-zero elements in each row of the node admittance matrix, and dense rows with more non-zero elements are prioritized for pipeline execution.

[0073] In this embodiment, the sparse multiply-add array comprises multiple multiply-add (MAC) units arranged in parallel; each MAC unit performs processing; rows with varying numbers of non-zero elements are dynamically allocated MAC channels; pipelined scheduling is supported, allowing multiple row-level computations to be executed in parallel. The row-level pipeline scheduler monitors the MAC array status to determine which rows can proceed; it determines the processing order based on sparsity (e.g., dense rows first); and supports the following scheduling modes: static priority queue and dynamic row load-aware scheduling. The output write-back and accumulation module writes the output vector to an on-chip buffer; it can directly interface with the next iteration (e.g., residual calculation in the generalized minimum residual method); and supports intermediate result caching, data format conversion, and normalization operations.

[0074] Specifically, the row-level pipeline scheduler dynamically allocates multiply-accumulate channel resources based on the number of non-zero elements in each row of the node admittance matrix, and prioritizes scheduling dense rows with more non-zero elements into the pipeline for execution.

[0075] The above technical solution uses a vector broadcast mechanism to reduce the number of repeated reads from external storage and on-chip bus, solves the "memory wall" problem in sparse matrix vector multiplication accelerator operations, significantly improves data supply efficiency, and alleviates memory access bottlenecks.

[0076] As an optional embodiment of the present invention, based on the above embodiments, this optional embodiment can optimize the mapping of each subnet to an independent processing unit on a field-programmable gate array (FPGA), including: a4) Real-time acquisition of the number of nodes and branch connection density of the subnet corresponding to each processing unit.

[0077] In this embodiment, to prevent some processing units from becoming performance bottlenecks due to excessive workload, a hardware-level load monitoring mechanism is introduced. A real-time scheduler runs in the main control system, dynamically adjusting the load distribution of processing units based on the number of nodes and connection density of each subnet, achieving system-level load balancing optimization. This step is used to collect the number of nodes and branch connection density of the subnet corresponding to each processing unit in real time, to assess the load status of the processing unit. For example, the complexity of the processing unit can be assessed based on the number of non-zero elements in each row of the node admittance matrix, i.e., the sparsity of the nodes.

[0078] b4) Based on the number of nodes and branch connection density of each subnet, dynamically adjust the subnet tasks allocated to each processing unit to ensure load balancing of each processing unit.

[0079] In this embodiment, based on the number of nodes and branch connection density of each subnet, it can be determined whether the load on the corresponding processing unit is too light or too heavy, and the subnet tasks allocated to each processing unit can be dynamically adjusted to ensure load balance among the processing units. For example, based on the number of non-zero elements in each row of the node admittance matrix, i.e., the sparsity, penalty accumulation units are dynamically allocated, prioritizing dense rows or balancing the load.

[0080] The above technical solution, by introducing load balancing and dynamic scheduling mechanisms, solves the problem of uneven computing load among processing units caused by uneven power grid topology, prevents overall system performance degradation caused by individual heavily loaded processing units, and achieves load balancing optimization.

[0081] As an optional embodiment of the present invention, based on the above embodiments, this optional embodiment can optimize the method by further including: using a double buffer mechanism to manage the node admittance matrix, so that while the FPGA is performing the node admittance matrix calculation at the current moment, the main control system or the internal logic of the FPGA prepares the updated node admittance matrix for the next moment, thereby realizing asynchronous pipelined operation of calculation and data update.

[0082] In this embodiment, to prevent computational blocking, a double-buffering mechanism is employed at the application layer to implement asynchronous pipelined computation and data updates, supporting real-time solution process switching based on events (such as fault triggering). Specifically, the Y-matrix solution uses a double-buffering mechanism, meaning that the next Y-matrix is ​​prepared simultaneously during the current solution. Furthermore, an event-triggered model can be used to asynchronously trigger re-solution under conditions such as topology changes, load disturbances, and scheduling plan changes. In addition, the control system can invoke multiple FPGA task queues to improve instantaneous throughput.

[0083] The above technical solution uses a double buffer and asynchronous mechanism to eliminate computational blocking caused by data updates, ensuring stable solution results are continuously output within millisecond cycles, supporting the implementation of advanced protection and control functions, and guaranteeing solution continuity.

[0084] It should be noted that a parameterized configuration mechanism can be introduced in this embodiment, allowing for scalability and adaptability settings at the application layer. For example, through the human-computer interaction interface provided by the system, the system supports configuring the following parameters via the register interface: number of subnets and partitioning method; CSR or ELL structure selection; maximum number of supported non-zero elements; threshold judgment criteria (for sparsity control), thus realizing the scalability and adaptability of the application layer.

[0085] To more clearly illustrate the parallel node admittance matrix solving method based on field-programmable gate arrays (FPGAs) provided in this embodiment of the invention, a practical application scenario is used as an example. For instance, the application layer supports real-time power system simulation. The method provided in this embodiment is embedded in a nuclear power plant real-time dispatch simulation platform, running collaboratively with steady-state analysis and transient response simulation modules to achieve millisecond-level online admittance matrix updates and solutions, supporting advanced functions such as fault location, optimized power flow regulation, and dynamic reconfiguration. The hardware real-time computing layer (FPGA) implements modules such as parallel node admittance matrix solving, LU / Cholesky, and SpMV, providing millisecond-level response. The intermediate control layer (master / dispatch server) runs the simulation master control program, data scheduling module, and state synchronization module, communicating with the FPGA and coordinating model reconfiguration and solution calls. The application layer (simulation system platform) is embedded in a nuclear power plant-specific real-time simulation system, connecting to the admittance matrix solving module through an application programming interface (API), supporting functions such as visualization, alarms, and trend prediction.

[0086] As described above, the steady-state simulation module uses the Y matrix solution updated every millisecond by the FPGA module as input to drive state estimation and power flow solution; after a disturbance occurs (such as a sudden load drop or bus short circuit), the transient simulation module calls the high-frequency admittance matrix solution to adjust the voltage and current vectors in real time and feed them back to the protection logic; the fault simulation module can simulate the disconnection of a specific line or equipment failure, triggering a change in the Y matrix structure, and the system completes the structural reconstruction and solution path switching within 10 ms.

[0087] The method provided in this embodiment has an automatic data stream cyclic update mechanism. To ensure real-time performance, the following data cycle is set in the simulation platform: 1) Topology data update (1ms) → Y matrix construction → FPGA parallel solution (1~2ms) → voltage / current solution write-back → used by each simulation module; 2) The main control scheduling system performs periodic scanning of the topology database (real-time acquisition or simulation disturbance); 3) If structural changes or node attribute changes occur, the sparse Y matrix (CSR / ELL format) is reconstructed and uploaded to the FPGA; 4) The FPGA completes the LU / Cholesky solution or SpMV iteration within 1~2 milliseconds to solve for the new voltage vector; 5) The main control program pushes the results to the transient simulation module and the control and protection module.

[0088] Example 2 Figure 2 This is a schematic diagram of a parallel node admittance matrix solving system based on a field-programmable gate array (FPGA) according to Embodiment 2 of the present invention. This device is applicable to solving parallel node admittance matrices based on FPGAs. This parallel node admittance matrix solving system based on FPGAs can be implemented in hardware and / or software and is generally integrated into electronic devices. Figure 2 As shown, the system includes: a main control system 21 and a field-programmable gate array (FPGA) 22, wherein the FPGA 22 is configured with multiple processing units 221: The main control system 21 is used to divide the power network topology into multiple subnets and map each subnet to an independent processing unit 221 on the FPGA 22, wherein each processing unit 221 is used to independently process the node admittance matrix calculation of the corresponding subnet; The processing unit 221 is used to compress and encode the node admittance matrix of the corresponding subnet using a sparse compressed matrix storage format and store it in the on-chip block memory of the FPGA 22. The sparse compressed matrix storage format includes a compressed row storage format or a fixed-length row storage format. The processing unit 221 is further configured to determine the target solution mode according to the solution requirements of the power network topology, and solve the node admittance matrix based on the target solution mode, wherein the target solution mode is one of the following: a direct solution mode using a parallel triangular decomposer or a Cholisky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication accelerator.

[0089] The aforementioned technical solution leverages the inherent parallelism of FPGAs to achieve large-scale parallel construction and solution of node admittance matrices through a distributed processing unit array. Compared to traditional serial computation by a central processing unit, this significantly improves computation speed, meets the real-time analysis needs of nuclear power plants, and breaks through the bottleneck of serial computation. Simultaneously, by using a compressed row storage format or a sparse compression format with a fixed-length row storage format, the occupancy of on-chip block random access memory resources on the FPGA is greatly reduced, solving the problem of large-scale matrices not being able to be stored on-chip. Furthermore, sparsification avoids a large number of invalid zero-element calculations, improving energy efficiency and optimizing resource utilization. In addition, by integrating a parallel triangular decomposer or a Chorisky decomposer with a sparse matrix-vector multiplication accelerator within the same hardware architecture, it supports flexible switching between direct and iterative methods, reducing computation time from seconds to milliseconds. This provides high-speed underlying data support for steady-state, transient, and fault simulation of nuclear power plant power systems, meeting real-time requirements.

[0090] Optionally, the main control system 21 also includes a power grid monitoring module. The power grid monitoring module is used to determine the affected updated subnet and the updated node admittance matrix when a change in the power network topology is detected, and to transmit the updated node admittance matrix to the target processing unit corresponding to the updated subnet to replace the node admittance matrix at the previous moment. The target processing unit is used to determine the target solution mode according to the solution requirements of the power network topology, and solve the updated node admittance matrix based on the target solution mode.

[0091] Optionally, the power grid monitoring module is specifically used for: By comparing the power network topology at the current moment with that at the previous moment in real time through the main control system, the changed branches or nodes can be identified. The subnet to which the changed branch or node belongs is the updated subnet; For the updated subnet, the non-zero element values ​​and index information in the corresponding compressed storage structure are recalculated and updated as the admittance matrix of the updated node.

[0092] Optionally, the processing unit 221 includes a decomposition module for: Read the node admittance matrix from the on-chip block memory, construct the dependency graph of the node admittance matrix, and identify the rows without dependencies in the dependency graph; A ready line queue is dynamically maintained by the scheduler, wherein the ready line queue contains the lines in the dependency graph that are currently available for execution in the multi-stage pipeline. Multiple independent rows in the ready row queue are simultaneously scheduled to the multi-stage pipeline of the parallel triangular decomposer or the Cholisky decomposer for concurrent execution.

[0093] Optionally, the multi-stage pipeline sequentially includes an index decoding stage, an existing decomposition item query stage, a multiply-accumulate unit accumulation stage, a division or square root operation stage, and a result write-back and update stage; the multi-stage pipeline adopts a structure combining forward channels and feedback paths.

[0094] Optionally, the decomposition module is further configured to: After reading the elements of the node admittance matrix from the on-chip block memory once, they are broadcast to multiple multiply-accumulate units to achieve the reuse of elements in the node admittance matrix; The row-level pipeline scheduler dynamically allocates multiply-accumulate channel resources based on the number of non-zero elements in each row of the node admittance matrix, and prioritizes scheduling dense rows with more non-zero elements into the pipeline for execution.

[0095] Optionally, the main control system 21 is specifically used for: The number of nodes and branch connection density of the subnet corresponding to each processing unit are collected in real time. The subnet tasks allocated to each processing unit are dynamically adjusted based on the number of nodes and branch connection density of each subnet to ensure load balancing of each processing unit.

[0096] Optionally, the system also includes a double buffer management module for: The node admittance matrix is ​​managed by a double buffering mechanism, which enables the main control system or the internal logic of the FPGA to prepare the updated node admittance matrix for the next moment while the FPGA is performing the calculation of the node admittance matrix at the current moment, thereby realizing asynchronous pipelined operation of calculation and data update.

[0097] Optionally, the main control system and the FPGA exchange data and control commands through a high-speed interface.

[0098] The parallel node admittance matrix solving system based on field-programmable gate arrays provided in this invention can execute the parallel node admittance matrix solving method based on field-programmable gate arrays provided in any embodiment of this invention, and has the corresponding functional modules and beneficial effects of the method.

[0099] Example 3 Figure 3 This is a schematic diagram of an electronic device provided in Embodiment 3 of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0100] like Figure 3 As shown, the electronic device 30 includes at least one processor 31 and a memory, such as a read-only memory (ROM) 32 or a random access memory (RAM) 33, communicatively connected to the at least one processor 31. The memory stores computer programs executable by the at least one processor. The processor 31 can perform various appropriate actions and processes based on the computer program stored in the ROM 32 or loaded from storage unit 38 into the RAM 33. The RAM 33 can also store various programs and data required for the operation of the electronic device 30. The processor 31, ROM 32, and RAM 33 are interconnected via a bus 34. An input / output (I / O) interface 35 is also connected to the bus 34.

[0101] Multiple components in electronic device 30 are connected to I / O interface 35, including: input unit 36, such as keyboard, mouse, etc.; output unit 37, such as various types of monitors, speakers, etc.; storage unit 38, such as disk, optical disk, etc.; and communication unit 39, such as network card, modem, wireless transceiver, etc. Communication unit 39 allows electronic device 30 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0102] Processor 31 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 31 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 31 performs the various methods and processes described above, such as parallelized node admittance matrix solving methods based on field-programmable gate arrays.

[0103] In some embodiments, the parallelized node admittance matrix solving method based on field-programmable gate arrays (FPGAs) can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 38. In some embodiments, part or all of the computer program can be loaded and / or mounted on electronic device 30 via ROM 32 and / or communication unit 39. When the computer program is loaded into RAM 33 and executed by processor 31, one or more steps of the parallelized node admittance matrix solving method based on FPGAs described above can be performed. Alternatively, in other embodiments, processor 31 can be configured to execute the parallelized node admittance matrix solving method based on FPGAs by any other suitable means (e.g., by means of firmware).

[0104] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0105] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0106] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0107] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0108] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0109] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0110] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the parallelized node admittance matrix solution method based on field-programmable gate arrays provided in any embodiment of this invention.

[0111] In implementing a computer program product, computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include, but are not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0112] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0113] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A parallelized method for solving the node admittance matrix based on field-programmable gate arrays, characterized in that, include: The main control system divides the power network topology into multiple subnets and maps each subnet to an independent processing unit on a field-programmable gate array (FPGA). Each processing unit is used to independently calculate the node admittance matrix of the corresponding subnet. Within each processing unit, the node admittance matrix of the corresponding subnet is compressed and encoded using a sparse compressed matrix storage format and stored in the on-chip block memory of the FPGA. The sparse compressed matrix storage format includes a compressed row storage format or a fixed-length row storage format. Within each processing unit, a target solution mode is determined based on the solution requirements of the power network topology, and the node admittance matrix is ​​solved based on the target solution mode. The target solution mode is one of the following: a direct solution mode using a parallel triangular decomposer or a Cholisky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication accelerator.

2. The method according to claim 1, characterized in that, Also includes: When the main control system detects a change in the power network topology, it determines the affected updated subnet and the updated node admittance matrix, and transmits the updated node admittance matrix to the target processing unit corresponding to the updated subnet to replace the node admittance matrix of the previous moment. Within the target processing unit, a target solution mode is determined based on the solution requirements of the power network topology, and the updated node admittance matrix is ​​solved based on the target solution mode.

3. The method according to claim 2, characterized in that, When the main control system detects a change in the power network topology, it determines the affected updated subnet and the updated node admittance matrix, including: By comparing the power network topology at the current moment with that at the previous moment in real time through the main control system, the changed branches or nodes can be identified. The subnet to which the changed branch or node belongs is the updated subnet; For the updated subnet, the non-zero element values ​​and index information in the corresponding compressed storage structure are recalculated and updated as the admittance matrix of the updated node.

4. The method according to claim 1, characterized in that, The steps of the parallel triangular decomposer or the Cholisky decomposer to solve for the nodal admittance matrix include: Read the node admittance matrix from the on-chip block memory, construct the dependency graph of the node admittance matrix, and identify the rows without dependencies in the dependency graph; A ready line queue is dynamically maintained by the scheduler, wherein the ready line queue contains the lines in the dependency graph that are currently available for execution in the multi-stage pipeline. Multiple independent rows in the ready row queue are simultaneously scheduled to the multi-stage pipeline of the parallel triangular decomposer or the Cholisky decomposer for concurrent execution.

5. The method according to claim 4, characterized in that, The multi-stage pipeline sequentially includes an index decoding stage, an existing decomposition item query stage, a multiply-accumulate unit stage, a division or square root operation stage, and a result write-back and update stage; the multi-stage pipeline adopts a structure that combines forward channels and feedback paths.

6. The method according to claim 1, characterized in that, The steps of the sparse matrix-vector multiplication accelerator to solve for the nodal admittance matrix include: After reading the elements of the node admittance matrix from the on-chip block memory once, they are broadcast to multiple multiply-accumulate units to achieve the reuse of the elements in the node admittance matrix; The row-level pipeline scheduler dynamically allocates multiply-accumulate channel resources based on the number of non-zero elements in each row of the node admittance matrix, and prioritizes scheduling dense rows with more non-zero elements into the pipeline for execution.

7. The method according to claim 1, characterized in that, The step of mapping each subnet to an independent processing unit on a Field Programmable Gate Array (FPGA) includes: The number of nodes and branch connection density of the subnet corresponding to each processing unit are collected in real time. The subnet tasks allocated to each processing unit are dynamically adjusted based on the number of nodes and branch connection density of each subnet to ensure load balancing of each processing unit.

8. The method according to claim 1, characterized in that, Also includes: The node admittance matrix is ​​managed by a double buffering mechanism, which enables the main control system or the internal logic of the FPGA to prepare the updated node admittance matrix for the next moment while the FPGA is performing the calculation of the node admittance matrix at the current moment, thereby realizing asynchronous pipelined operation of calculation and data update.

9. The method according to claim 1, characterized in that, The main control system and the FPGA communicate and control each other via a high-speed interface.

10. A parallelized nodal admittance matrix solving system based on field-programmable gate arrays, characterized in that, It includes a main control system and a field-programmable gate array (FPGA), wherein the FPGA is configured with multiple processing units: The main control system is used to divide the power network topology into multiple subnets and map each subnet to an independent processing unit on the FPGA, wherein each processing unit is used to independently process the node admittance matrix calculation of the corresponding subnet; The processing unit is used to compress and encode the node admittance matrix of the corresponding subnet using a sparse compressed matrix storage format and store it in the on-chip block memory of the FPGA. The sparse compressed matrix storage format includes a compressed row storage format or a fixed-length row storage format. The processing unit is further configured to determine the target solution mode according to the solution requirements of the power network topology, and solve the node admittance matrix based on the target solution mode, wherein the target solution mode is one of the following: a direct solution mode using a parallel triangular decomposer or a Cholisky decomposer, or an iterative solution mode using a sparse matrix-vector multiplication accelerator.

Images