Method and device for identifying a direct current series arc

Abstract

The application discloses a kind of identification method and device of direct current series arc, it is related to direct current energy detection technical field, main purpose is to realize the identification of direct current series arc of efficient, low-power consumption, meet the real-time requirement of direct current system to arc fault fast cut-off.The main technical scheme of the present application is: obtaining convolutional neural network, and the pulse neural network with the same hierarchical topology structure as the convolutional neural network;The parameters of the convolutional neural network are mapped layer by layer into the pulse neural network to obtain a target direct current series arc identification model;Obtain the time-domain discrete signal of the target direct current loop, and encode the time-domain discrete signal into a pulse signal;The pulse signal is processed using the target direct current series arc identification model to obtain the arc identification result of the target direct current loop.

Description

Technical Field

[0001] This invention relates to the field of technology, and in particular to a method and apparatus for identifying DC series electric arcs. Background Technology

[0002] A DC series arc refers to a continuous high-temperature plasma discharge phenomenon in a DC circuit, caused by a small gap formed between conductors due to loose wiring connections, insulation aging, or mechanical damage, which then allows current to break down the air dielectric. Because DC current does not have a natural zero-crossing point, once ignited, it can burn stably and continuously release a large amount of energy, threatening both personal safety and the safe operation of the DC system. Therefore, accurately identifying DC series arcs is of great significance for ensuring the safety of DC systems.

[0003] Currently, deep learning-based intelligent detection methods have become the mainstream approach for DC series arc detection. For example, an architecture combining Convolutional Neural Networks (CNNs) and Long Short-Term Memory (LSTM) leverages the advantages of CNNs in feature extraction and LSTMs in temporal modeling to achieve arc detection. However, when this method is applied to hardware terminals (such as smart circuit breakers), the dense convolutional operations of CNNs and the complex temporal recursion of LSTMs involve massive floating-point multiplication and addition operations, severely impacting computational power consumption and significantly increasing model inference latency. This makes it impossible to meet the real-time requirements of DC systems for rapid arc fault interruption. Summary of the Invention

[0004] In view of the above problems, the present invention provides a method and apparatus for identifying DC series arcs, the main purpose of which is to achieve efficient and low-power DC series arc identification and meet the real-time requirements of DC systems for rapid arc fault cutoff.

[0005] To solve the above-mentioned technical problems, the present invention proposes the following solution: In a first aspect, the present invention provides a method for identifying DC series electric arcs, the method comprising: Obtain a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The convolutional neural network is used to process the time-frequency characteristics of the time-domain discrete signal after transformation to identify DC series arcs in a DC circuit. The parameters of the convolutional neural network are mapped layer by layer into the spiking neural network to obtain the target DC series arc identification model; Acquire the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal; The pulse signal is processed using the target DC series arc identification model to obtain the arc identification result of the target DC circuit.

[0006] Secondly, the present invention provides a device for identifying DC series electric arcs, the device comprising: The network acquisition unit is used to acquire a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The convolutional neural network is used to process the time-frequency characteristics of the time-domain discrete signal after transformation to identify DC series arcs in a DC circuit. The parameter mapping unit is used to map the parameters of the convolutional neural network obtained by the network acquisition unit to the spiking neural network layer by layer to obtain the target DC series arc recognition model. The signal processing unit is used to acquire the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal; An arc identification unit is used to process the pulse signal obtained by the signal processing unit using the target DC series arc identification model obtained by the parameter mapping unit, so as to obtain the arc identification result of the target DC circuit.

[0007] To achieve the above objectives, according to a third aspect of the present invention, a storage medium is provided, the storage medium including a stored program, wherein, when the program is executed, the device on which the storage medium is located is controlled to perform the DC series arc identification method of the first aspect.

[0008] To achieve the above objectives, according to a fourth aspect of the present invention, a processor is provided for running a program, wherein the program executes the method for identifying DC series arcs described in the first aspect.

[0009] By employing the above technical solution, the present invention provides a method and apparatus for identifying DC series arcs. This method acquires a convolutional neural network (CNN) and a spiking neural network (SNN) with the same hierarchical topology. The consistent hierarchical topology of both provides a structural matching prerequisite for subsequent parameter mapping, avoiding feature extraction capability attenuation caused by topological differences. The CNN is used to process the time-frequency features after time-domain discrete signal transformation to identify DC series arcs in a DC circuit. Subsequently, the parameters of the CNN are mapped layer by layer to the SNN to obtain the target DC series arc identification model. This method, while fully inheriting the arc feature extraction capability of the CNN, transforms the model's computation mechanism from the dense floating-point multiplication and addition operations of the traditional CNN to the event-driven pulse operations of the SNN, significantly reducing the computational complexity at the model architecture level. The computational overhead is adapted to the computational constraints of hardware deployment. Then, by acquiring the time-domain discrete signal of the target DC circuit and encoding it into a pulse signal, the original DC circuit's time-domain sampling signal can be converted into a pulse sequence compatible with the input format of the spiking neural network, ensuring the input compatibility and processing feasibility of the target DC series arc identification model. Finally, the target DC series arc identification model is used to process the pulse signal to obtain the DC series arc identification result. This effectively solves the technical problem of excessive computational consumption in hardware interruption scenarios caused by massive floating-point multiplication and addition operations, which is a problem in existing detection methods based on convolutional neural networks and long short-term memory networks, while ensuring the accuracy of DC series arc identification. It enables efficient and low-power DC series arc identification in resource-constrained hardware environments, meeting the real-time requirements of DC systems for rapid arc fault disconnection.

[0010] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart of a method for identifying a DC series electric arc provided by an embodiment of the present invention is shown; Figure 2 A flowchart of another method for identifying DC series arcs provided by an embodiment of the present invention is shown; Figure 3A block diagram of a DC series arc identification device provided in an embodiment of the present invention is shown; Figure 4 A block diagram of another DC series arc identification device provided in an embodiment of the present invention is shown. Detailed Implementation

[0012] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0013] To address the technical pain points of existing DC series arc detection methods based on Convolutional Neural Networks (CNNs) and Long Short-Term Memory (LSTMs) when deployed on hardware terminals, which result in excessive computing power consumption and large inference delays due to massive floating-point multiplication and addition operations and complex time-series recursion, thus failing to meet the real-time requirements for rapid arc fault cutoff, a recognition scheme based on spiking neural networks is proposed.

[0014] Specifically, this invention abandons the mechanism of traditional CNNs and LSTMs that rely on dense floating-point operations, and introduces a Spiking Neural Network (SNN) that uses event-driven pulse operations to significantly reduce computational overhead. To overcome the problems of high training difficulty and difficulty in guaranteeing accuracy of SNNs directly, this invention adopts a parameter mapping strategy. First, a pre-trained high-precision CNN is obtained, and an SNN with the exact same hierarchical topology is pre-constructed. This isomorphic design provides a perfect structural matching premise for subsequent parameter mapping, avoiding the attenuation of feature extraction ability due to differences in network topology.

[0015] Subsequently, the parameters of the pre-trained CNN are directly mapped layer by layer into the SNN to obtain the target DC series arc recognition model. While fully inheriting the powerful arc feature extraction capability of CNN, the underlying computation mechanism is completely transformed into event-driven pulse accumulation operation. In the inference stage, the time-domain discrete signal of the target DC circuit is acquired and encoded into a pulse sequence, which is then processed using the target model.

[0016] The present invention provides a method for identifying DC series arcs, the execution subject of which can be an edge computing unit deployed in the hardware terminal of the DC system (such as a smart circuit breaker, a DC fault arc detection device, or an edge computing gateway), such as a microcontroller unit (MCU), an embedded neural network processor (NPU), or a field programmable gate array (FPGA).

[0017] Because this invention transforms intensive floating-point multiply-accumulate operations into event-driven pulse operations, it greatly reduces the requirements for hardware computing power and memory bandwidth. Therefore, this method is particularly suitable for deployment in the end-of-line hardware protection equipment of DC systems with limited resources and extremely high requirements for power consumption and real-time cutoff. It can directly complete efficient and low-latency edge-side inference at the fault location.

[0018] Next, combined Figure 1 This invention provides a method for identifying DC series arcs, and its specific execution steps are as follows: Figure 1 As shown, it includes: 101. Obtain convolutional neural networks and spiking neural networks with the same hierarchical topology as convolutional neural networks.

[0019] In this embodiment of the invention, model training can be performed in advance on a cloud server with sufficient computing power, or it can be performed on the hardware terminal of the DC system. This is because model training is an offline, one-time process, and compared to continuous real-time inference during long-term device operation, its computational resources and time overhead are phased and limited.

[0020] During the training preparation phase, the training dataset of the DC system is first obtained. This dataset can be obtained by retrieving a publicly available arc fault dataset that has been annotated, or by collecting and preprocessing the actual historical operating electrical signals of the DC system.

[0021] In the specific training process, the time-domain signal in the training dataset is first extracted through sliding frame division and short-time fourier transform (STFT), and then frequency domain enhancement is performed using the flipped Gaussian function to convert it into time-frequency features.

[0022] Subsequently, the time-frequency features can be input into the convolutional layer of a Convolutional Neural Network (CNN) to extract static spatial features representing the arc fault state. Next, the static feature sequence output by the CNN is input into a Long Short-Term Memory (LSTM) network to capture the dynamic evolution features of the time-frequency slice sequence along the time dimension, thereby forming a joint static-dynamic feature representation. Finally, this joint feature representation is input into the fully connected layer of the CNN to output the prediction result, and the model is trained in a supervised iterative manner using the backpropagation algorithm based on the prediction error until the model converges.

[0023] As can be seen, the above approach essentially embeds a Long Short-Term Memory (LSTM) network between the front-end convolutional layers and the back-end fully connected layers of a Convolutional Neural Network (CNN). During the training phase, this design leverages the temporal processing capabilities of the LSTM network to perform temporal processing on the feature sequences output by the CNN convolutional layers, forming a static-dynamic joint feature representation. This joint feature representation, after being used by the fully connected layers to output prediction results, has its prediction error backpropagated to the convolutional layers. This causes the error gradient used to update the convolutional layer parameters to include temporal dependency information, thereby introducing additional temporal optimization constraints to the convolutional layers. This prompts the convolutional layers to learn a feature representation with temporal discriminative power, ultimately improving the accuracy of CNN feature extraction.

[0024] During the model deployment to the hardware terminal, a pre-trained joint model containing cascaded convolutional neural networks and long short-term memory networks can be obtained first. Then, during parameter mapping, the long short-term memory network is removed, and only the parameters of the convolutional neural networks are mapped layer by layer to the spiking neural network. This completely eliminates the complex temporal recursive operations of the long short-term memory network, achieving extreme lightweighting and low power consumption of the model on the hardware terminal side. It can be seen that the final convolutional neural network can be used to process the time-frequency characteristics of discrete-time signals to identify DC series arcs in DC circuits.

[0025] In some optional implementations, embodiments of the present invention may also perform a sequence-to-sequence load-side time-frequency domain amplitude prediction task during the training process; the predicted load-side time-frequency domain sequence is reconstructed into a time-domain signal through inverse short-time Fourier transform, thereby realizing the prediction of the electromagnetic interference effect generated by the series arc fault on the load side.

[0026] This is because the nonlinear volt-ampere characteristics of DC series arc faults can induce broadband electromagnetic interference in the circuit. The attenuation and distortion of the interference signal when it is transmitted to the load side through the impedance of the distribution line are affected by multiple factors such as line parameters and load type, making it difficult to accurately characterize using traditional physical models. By combining the main task of fault identification with the task of predicting the time-frequency amplitude of the load side during the training phase, multi-task learning can be carried out, which can enhance the model's ability to extract features of the frequency domain propagation law of arc interference and simultaneously improve the identification accuracy of the main task and the restoration accuracy of the prediction task.

[0027] Furthermore, by converting the frequency domain prediction results into time domain waveforms through inverse short-time Fourier transform, the time domain form of electromagnetic interference on the load side can be intuitively restored under the premise of only collecting power supply side signals. Real-time prediction of interference effects can be completed without the need to deploy additional acquisition devices on the load side, providing data basis for electromagnetic protection of sensitive electrical equipment on the load side.

[0028] 102. The parameters of the convolutional neural network are mapped layer by layer to the spiking neural network to obtain the target DC series arc recognition model.

[0029] In this step, a pre-built spiking neural network with a network structure completely identical to the convolutional neural network described above can be constructed, with the number of network layers, the number of channels per layer, and the inter-layer connections corresponding one-to-one. All network parameters of the initial convolutional neural network model are transferred and assigned to the corresponding structure of the spiking neural network layer by layer according to the correspondence between layers. The parameter mapping process does not require secondary training of the spiking neural network. After all parameters are mapped, a target DC series arc recognition model with feature extraction logic equivalent to that of the convolutional neural network is obtained.

[0030] The parameter mapping process can be as follows: The channel weights of each layer in the convolutional neural network are mapped to the synaptic weights of the corresponding channels in the corresponding layers of the spiking neural network. Each layer in the spiking neural network includes at least one channel, and each channel includes multiple in-slot firing neurons. The synaptic weights are used to control the intensity of the pulse signal transmitted between connected in-slot firing neurons in adjacent layers. The bias terms of each layer in the convolutional neural network are mapped to the bias parameters of each in-slot firing neuron in the corresponding channel of the corresponding layer in the spiking neural network. The bias parameters are used to provide a constant potential accumulation value when the in-slot firing neurons in the current layer accumulate membrane potential. Finally, the spiking neural network with the mapped synaptic weights and bias parameters is determined as the target DC series arc recognition model.

[0031] In another parallel implementation, the channel weights and bias terms of each layer of the convolutional neural network can be normalized and scaled layer by layer. Then, the scaled channel weights are mapped to the synaptic weights of the same layer and the same number channel in the spiking neural network, and the scaled bias terms are mapped to the bias parameters of each Leaky Integrate-and-Fire (LIF) neuron in the same channel. The pulse firing threshold of each LIF neuron in the corresponding layer of the spiking neural network is adjusted synchronously so that the pulse firing frequency of the neuron can linearly approximate the real activation value of the corresponding position in the original convolutional neural network. Finally, the configuration of the spiking neural network is completed based on the mapped synaptic weights, bias parameters, and adjusted pulse firing thresholds to obtain the target DC series arc recognition model.

[0032] 103. Obtain the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal.

[0033] In this embodiment of the invention, step 103 first acquires the time-domain discrete signal of the target DC circuit, and performs sliding frame division according to a preset frame length and a preset sliding step size to obtain multiple time-domain signal frames. The preset sliding step size is equal to the time step size of the pulse neural network membrane potential update to ensure timing synchronization. Then, a short-time Fourier transform is performed on each time-domain signal frame and the amplitude information in the positive frequency range is extracted to obtain the initial frequency domain features. Next, the weight of each frequency point is determined by using the flipped Gaussian function and multiplied with the amplitude to obtain enhanced frequency domain features to highlight the high-frequency arc features. Finally, each enhanced frequency domain feature is encoded as binary pulse data and combined in chronological order to generate a pulse signal, thereby converting the original time-domain signal into a spatiotemporal pulse sequence adapted to the network input.

[0034] In another parallel implementation, to further simplify the front-end preprocessing process and reduce the computing power overhead of the hardware terminal, step 103 can also directly encode the acquired time-domain discrete signal of the target DC circuit into a pulse signal. Specifically, firstly, the acquired time-domain discrete signal is normalized; then, a pulse frequency encoding mechanism is used to directly map the normalized amplitude of each sampling point in the time-domain discrete signal to the pulse firing probability or pulse firing frequency within the corresponding time step. That is, the larger the signal amplitude, the higher the probability or frequency of generating a pulse within that time step, thereby generating single-point pulse data; finally, the single-point pulse data corresponding to each sampling point are combined in chronological order to generate a pulse signal.

[0035] The difference between the two encoding methods is as follows: In the first method, the original one-dimensional time-domain signal is converted into two-dimensional time-frequency features through short-time Fourier transform, and the amplitude energy of the signal is expanded and distributed to the spatial dimension of frequency. Within a single time step, each frequency point only needs to express the corresponding feature through a binary pulse state of 0 or 1. The pulse neural network can complete the arc feature recognition by combining the spatial pulse distribution of the frequency dimension with the accumulation of the temporal membrane potential. Therefore, binary pulse coding is adopted.

[0036] The second approach skips frequency domain transformation and directly encodes the one-dimensional time-domain discrete signal. Since the frequency dimension lacks spatial feature information, the continuous amplitude information of the original signal will be lost if only single-step binary threshold encoding is used. Therefore, a pulse frequency encoding mechanism is adopted to map the normalized amplitude of the sampling point to the pulse firing probability of the corresponding time step. The amplitude is characterized by the pulse firing density within the time window, and the continuous amplitude information is retained by the pulse sequence in the time dimension.

[0037] 104. The pulse signal is processed using the target DC series arc identification model to obtain the arc identification result of the target DC circuit.

[0038] In this embodiment of the invention, step 104 is implemented as follows: The encoded pulse signal is input into the target DC series arc identification model (i.e., the configured spiking neural network). During the forward inference process of the model, the spiking neural network uses its internal leak-integral ignition neurons to perform event-driven membrane potential accumulation and pulse firing processing on the input pulse signal based on the mapped synaptic weights, thereby extracting the spatiotemporal features in the pulse signal layer by layer. Since the spiking neural network only triggers the accumulation operation when a pulse is received, and does not perform calculations when there is no pulse input, the traditional dense floating-point multiply-accumulate operation is converted into sparse pulse event operation, which greatly reduces the computing power and power consumption of the hardware terminal inference process. Finally, the response state of the output layer neurons of the spiking neural network (such as the pulse firing frequency or the final accumulated membrane potential value) is decoded to determine whether the target DC circuit is in a normal operating state or a DC series arc fault state, thereby obtaining the final arc identification result of the target DC circuit.

[0039] Specifically, the arc identification result can be represented as a state category label, that is, directly outputting a discrete identifier that represents the current circuit state (for example, outputting "0" to represent the normal operation state and outputting "1" to represent the DC series arc fault state), which is used for the most direct fault identification. It can also be expressed as fault confidence (or probability distribution value), that is, the specific percentage probability that the current circuit belongs to the normal operation state or the arc fault state, so that the back-end system can make more flexible secondary judgments to prevent false alarms by combining the preset probability threshold. It can also be a hardware control command (or trigger signal). When the identification result clearly determines that it is an arc fault and the action conditions are met, the model output terminal directly generates and outputs the underlying electrical signal (such as a high / low level switching signal or a PWM wave with a specific duty cycle) to drive the intelligent circuit breaker, trip unit or relay to perform the disconnection action. This achieves physical isolation of the arc fault within milliseconds and ensures the safety of personnel and equipment in the DC system.

[0040] It should be noted that, to balance identification sensitivity and false alarm resistance, the fault confidence level output by the model can be divided into three intervals. Specifically, a safety threshold and a danger threshold are preset, with the safety threshold being lower than the danger threshold. When the confidence level is lower than the safety threshold, it is determined to be a normal state, and no action is required; when the confidence level is higher than the danger threshold, it is determined to be an arc fault, and a cut-off command is immediately output; when the confidence level falls within the fuzzy interval between the safety threshold and the danger threshold, it indicates that the certainty of a single inference result is insufficient. In this case, a cut-off decision is not made immediately, but an observation window is activated to continue collecting subsequent results and performing inference. A comprehensive judgment is made based on the multiple inference results within the observation window. The comprehensive judgment method can include: The system counts the number of times the confidence level exceeds a preset intermediate threshold within the observation window. A fault is identified when this number reaches the preset confirmation threshold. Alternatively, the system calculates the weighted average of the confidence levels within the window; a fault is identified when this weighted average exceeds the preset confirmation threshold. If the observation window reaches the threshold but the fault confirmation condition is not met, the system is considered normal and the observation period ends.

[0041] Based on the above Figure 1As can be seen from the implementation method, the DC series arc identification method provided by the present invention obtains a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The consistent hierarchical topology of the two provides a structural matching premise for subsequent parameter mapping, avoiding the attenuation of feature extraction ability caused by topological differences. The convolutional neural network is used to process the time-frequency features after the transformation of the time-domain discrete signal to identify the DC series arc in the DC circuit. Then, the parameters of the convolutional neural network are mapped to the spiking neural network layer by layer to obtain the target DC series arc identification model. While fully inheriting the arc feature extraction ability of the convolutional neural network, the model operation mechanism is changed from the dense floating-point multiplication and addition operation of the traditional convolutional neural network to the event-driven pulse operation of the spiking neural network, which greatly reduces the computational complexity of the operation process at the model architecture level. This approach addresses the computational constraints of hardware deployment by reducing computational overhead. It then acquires the discrete-time signal of the target DC circuit and encodes it into a pulse signal, converting the original DC circuit's time-domain sampling signal into a pulse sequence compatible with the input format of the pulse neural network. This ensures the input compatibility and processing feasibility of the target DC series arc identification model. Finally, the target DC series arc identification model processes the pulse signal to obtain the DC series arc identification result. This effectively solves the technical problem of excessive computational consumption in hardware interruption scenarios caused by massive floating-point multiplication and addition operations, which is inherent to existing detection methods based on convolutional neural networks and long short-term memory networks, while maintaining accuracy in DC series arc identification. It enables efficient and low-power DC series arc identification in resource-constrained hardware environments, meeting the real-time requirements of DC systems for rapid arc fault disconnection.

[0042] Next, combined Figure 2 This invention describes a method for identifying DC series arcs, the specific steps of which are as follows: Figure 2 As shown, it includes: 201. Obtain the joint model, which consists of a convolutional neural network and a long short-term memory network cascaded in sequence.

[0043] 202. Remove the Long Short-Term Memory network from the joint model to obtain the convolutional neural network.

[0044] 203. Obtain a spiking neural network with the same hierarchical topology as the convolutional neural network.

[0045] The implementation methods of steps 201-203 are the same as those of step 101, and can achieve the same technical effect and solve the same technical problem, so they will not be repeated here.

[0046] It should be noted that introducing a Long Short-Term Memory (LSTM) network during the training phase can fully exploit the dynamic evolution dependency of DC arc faults along the time dimension, thereby assisting and improving the front-end convolutional neural network's ability to extract static spatial features under complex operating conditions. This ensures that the pre-trained convolutional neural network parameters have high feature representation quality. In other words, the LSM network is used during the training phase to apply temporal constraints to the output of the convolutional neural network using its temporal processing capabilities, thereby optimizing the parameters of the convolutional neural network. The present invention allows the implementation of a method that can directly strip and discard all recurrent connection weight matrices within a Long Short-Term Memory (LSTM) network, involving input gates, forget gates, output gates, and cell state updates. It then directly bridges the output tensor of the feature extraction layer in a convolutional neural network to the backend fully connected classification layer. This operation completely eliminates the massive floating-point multiplication and addition operations caused by the complex gating mechanism and temporal recursion of LSM networks, significantly reducing computational power consumption and inference latency on resource-constrained hardware terminals (such as smart circuit breakers), thus meeting the real-time requirements for rapid arc fault disconnection.

[0047] Furthermore, the activation mechanism of the spiking neural network adopts the standard modified linear unit (ReLU). This is to better match the discrete characteristics of the binarization (0 or 1) of the pulse signal; at the same time, since the leakage coefficient of the leakage integral ignition neuron in the spiking neural network already provides a complete membrane potential decay mechanism, there is no need to introduce a negative slope in the activation function, thereby further simplifying the computational logic and resource overhead on the hardware side.

[0048] 204. The parameters of the convolutional neural network are mapped layer by layer to the spiking neural network to obtain the target DC series arc recognition model.

[0049] In this embodiment, it is preferable to map the channel weights of each network layer in the convolutional neural network to the synaptic weights of the corresponding channels in the corresponding network layer of the spiking neural network. Each network layer in the spiking neural network includes at least one channel, and each channel includes multiple leaky integrators. The synaptic weights are used to control the intensity of the pulse signal transmitted between the leaky integrators connected in adjacent network layers. Simultaneously, the bias terms of each network layer in the convolutional neural network are mapped to the bias parameters of each leak-integration ignition neuron in the corresponding channel of the corresponding network layer of the spiking neural network. The bias parameters are used to provide a constant potential accumulation value when the leak-integration ignition neuron in the current network layer accumulates the membrane potential. Finally, the spiking neural network mapped with synaptic weights and bias parameters is used as the target DC series arc recognition model.

[0050] This invention preferably adopts this direct layer-by-layer parameter mapping implementation method. In terms of deployment efficiency, it eliminates the need for any lightweight compression that would damage the feature representation capabilities of the pre-trained convolutional neural network, and also eliminates the need for time-consuming secondary retraining and fine-tuning that would consume a lot of computing power, thus greatly improving efficiency. Secondly, in terms of recognition accuracy, through the strict isomorphic lossless mapping from channel weights to synaptic weights and from bias terms to bias parameters, it can fully inherit the powerful arc feature extraction capabilities learned by the pre-trained convolutional neural network under complex DC operating conditions, fundamentally avoiding the accuracy attenuation caused by traditional model compression and conversion, and ensuring a high accuracy rate for fault identification.

[0051] 205. Obtain the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal.

[0052] In this embodiment, the time-domain discrete signal of the acquired target DC circuit is preferably divided into multiple time-domain signal frames by sliding frames according to a preset frame length and a preset sliding step size. During this process, the time length corresponding to the preset sliding step size is specifically set to be strictly equal to the time step size for updating the membrane potential inside the spiking neural network. Subsequently, a short-time Fourier transform is performed on each time-domain signal frame to obtain a complex spectrum, and the amplitude information of the complex spectrum in the positive frequency range is extracted using the conjugate symmetry of the spectrum to obtain the initial frequency domain features corresponding to each time-domain signal frame.

[0053] Next, the weights of each frequency point within the positive frequency range are determined using the flipped Gaussian function, and the amplitude of each frequency point in the initial frequency domain feature is multiplied by the corresponding weight to obtain the enhanced frequency domain feature corresponding to each time domain signal frame; each enhanced frequency domain feature is encoded into corresponding binary pulse data; the binary pulse data are combined in chronological order to generate a pulse signal.

[0054] By setting the preset sliding step size to be equal to the time step size of the spiking neural network membrane potential update, the temporal resolution of the input pulse sequence is perfectly synchronized with the temporal resolution of the neuron state update within the network. This avoids feature loss or phase shift caused by temporal misalignment and ensures the accuracy of temporal feature extraction.

[0055] Furthermore, by extracting only the amplitude information within the positive frequency range through short-time Fourier transform, redundant negative frequency components are effectively eliminated. This significantly reduces the input dimension of the spiking neural network without losing core features, thereby reducing the computational and storage overhead during model inference.

[0056] Finally, the enhanced frequency domain features are encoded into binary pulse data, perfectly matching the sparse computation characteristics of event-driven spiking neural networks. The binarized pulse input completely eliminates complex floating-point multiplication operations when the hardware terminal performs synaptic weight accumulation, further reducing computing power consumption from the underlying data format, and greatly meeting the low power consumption and millisecond-level real-time disconnection requirements of resource-constrained hardware terminals such as smart circuit breakers.

[0057] In determining the weight of each frequency point using the inverted Gaussian function, the squared value of the frequency value and the squared value of the preset Gaussian standard deviation of each frequency point can be calculated separately. Then, the ratio of the squared value of the frequency value to twice the squared value of the preset Gaussian standard deviation is calculated. Next, the negative value of this ratio is taken as the exponent, and the exponent of the natural constant is calculated to obtain the intermediate calculated value. Finally, the weight value of the corresponding frequency point is determined based on the intermediate calculated value (which can be 1 minus the intermediate calculated value).

[0058] Through the above operational logic, the calculated weight values ​​monotonically increase with increasing frequency, exhibiting a distribution characteristic of low weight for low frequencies and high weight for high frequencies. This can specifically amplify the weight ratio of high-frequency arc fault characteristics while effectively suppressing the interference of low-frequency steady-state load components in the DC system, thereby enhancing the model's ability to identify weak DC series arc fault characteristics and significantly reducing the probability of misjudgment and missed judgment under complex operating conditions.

[0059] The formula for flipping the Gaussian function is: (Formula 1) in, To preset the Gaussian standard deviation, The frequency value at the frequency point. It is a natural constant. The weights are the corresponding frequency points.

[0060] 206. The pulse signal is processed using the target DC series arc identification model to obtain the arc identification result of the target DC circuit.

[0061] In this embodiment of the invention, the specific implementation process of step 206 is as follows: The network layer in the target DC series arc identification model (i.e., the configured pulse neural network) includes an input layer, at least one hidden layer and an output layer.

[0062] First, the input layer receives the encoded pulse signal and transmits it to the first hidden layer. In the hidden layer, the leaky integrator neurons accumulate the membrane potential based on the received pulse signal from the previous network layer (which can be either a hidden layer or the input layer), obtaining an updated membrane potential. If the updated membrane potential of the leaky integrator neurons reaches the pulse firing threshold, a pulse signal is fired to the leaky integrator neurons connected to the next network layer, and the updated membrane potential is reset by subtracting the pulse firing threshold to retain any residual membrane potential exceeding the threshold. Based on the received pulse signal from the previous network layer, the leaky integrator neurons in the output layer perform membrane potential accumulation, pulse signal firing, and membrane potential reset operations. Finally, based on the pulse signal firing status of the leaky integrator neurons in the output layer (such as the pulse firing frequency or the final accumulated membrane potential value), the arc recognition result of the target DC circuit is decoded.

[0063] Through the above implementation method, the mechanism of resetting by subtracting the pulse firing threshold from the updated membrane potential (i.e., the soft reset mechanism) can retain the residual membrane potential exceeding the threshold after the neuron fires a pulse, avoiding the problem of high-frequency pulse information loss caused by the traditional hard reset (directly returning to zero), and significantly improving the accuracy of DC series arc recognition; at the same time, the layer-by-layer event-driven pulse transmission and firing mechanism ensures that the model triggers calculation only when a pulse is received, realizing extreme sparse computing and low-power operation from the underlying logic.

[0064] Furthermore, the specific process of accumulating membrane potential using leak-integration ignition neurons in the hidden layer is as follows: First, the ratio of the membrane potential update time step to the leakage time constant is calculated, and the membrane potential decay coefficient (which can be 1 minus the ratio) is determined based on this ratio. Then, the membrane potential at the current moment is multiplied by the membrane potential decay coefficient to obtain the remaining membrane potential after leakage decay. Next, for each leakage integrator ignition neuron, the pulse signals transmitted by the leakage integrator ignition neurons connected in the previous network layer are obtained, and each pulse signal is multiplied by the corresponding synaptic weight and summed to obtain the input excitation accumulation value. Finally, the remaining membrane potential, the input excitation accumulation value, and the bias parameter of the leakage integrator ignition neuron are added together, and the sum is taken as the membrane potential updated by the leakage integrator ignition neuron.

[0065] The formula is: (Formula 2) In the formula, This represents the membrane potential of the neuron at the current moment. For time step, The leakage time constant, The input pulse sequence (with values ​​of 0 or 1). This corresponds to the synaptic weights; when the membrane potential exceeds a preset threshold... At this time, the neuron triggers an output pulse and performs a membrane potential reset.

[0066] It should be noted that in classic spiking neural network theoretical models, the membrane potential update formula usually does not explicitly include bias parameters. This is because biophysical models often ignore background current, or conventional software frameworks tend to achieve an equivalent bias effect by modifying the pulse firing threshold. However, in this invention, since the target DC series arc recognition model is derived layer by layer losslessly from a pre-trained convolutional neural network, and each layer of the convolutional neural network necessarily contains bias terms for adjusting the basic activation level.

[0067] In order to achieve complete inheritance of feature extraction capabilities and avoid accuracy decay, this invention explicitly maps the bias term of the convolutional neural network to the bias parameter of the leaky integral ignition neuron, and uses it as a constant background excitation current, which is directly added to the residual membrane potential and the accumulated value of the input excitation in each time step.

[0068] This approach not only perfectly equips the bias activation logic of the original convolutional neural network mathematically, but also requires only one low-overhead constant addition operation when implemented at the underlying hardware level of microcontrollers and other hardware terminals. This avoids the complex logical judgments caused by modifying the dynamic threshold, thereby maximizing the execution efficiency and low power consumption advantages of hardware inference while ensuring the high recognition accuracy of the model.

[0069] By introducing a membrane potential decay mechanism based on the leakage time constant, the physical characteristics of charge leakage in biological neurons are simulated. This gives the network a natural short-term memory and time decay capability, effectively filtering out occasional transient noise interference in the DC loop and preventing false triggering of the membrane potential due to noise accumulation, thus improving the model's anti-interference capability. At the same time, the pulse signal of the previous layer is multiplied and summed with the synaptic weights, and then combined with the bias parameters and the decayed remaining membrane potential for comprehensive accumulation. This perfectly replicates the weighted summation and bias activation logic in the original convolutional neural network, ensuring the lossless inheritance of feature extraction capability after parameter mapping. High-precision spatiotemporal feature fusion is achieved in extremely simple addition and multiplication operations.

[0070] In this embodiment of the invention, neurons in each layer of the spiking neural network are connected via synapses. Specifically, there are connection channels between neurons in the previous layer and neurons in the next layer, and each connection channel corresponds to a synaptic weight. When a neuron in the previous layer emits a spiking signal, the spiking signal is transmitted along the synapse to the connected neuron in the next layer. The transmitted signal strength is equal to the product of the spiking signal and the corresponding synaptic weight, thereby achieving weighted control of the spiking signal strength.

[0071] Regarding the way the model receives data, spiking neural networks employ a time-driven or event-driven mechanism, receiving and processing data moment-by-moment. Specifically, although the macroscopic input is a pulse sequence containing multiple time steps, internally, the data is discretized and sliced. At each current time, input layer neurons receive the pulse signal of the current time, while hidden layer neurons, based on the residual membrane potential state of the previous time, receive the pulse signal transmitted from the previous hidden layer and update their current state, thereby achieving frame-by-frame accumulation and extraction of temporal dynamic features.

[0072] The relationship between time step and pulse firing when membrane potential exceeds the threshold constitutes a dynamic collaborative mechanism of periodic checking and conditional triggering. The time step is the smallest discrete-time unit in which the spiking neural network simulates the passage of time and updates its state. Within each time step, the leak-integration firing neuron receives pulse signals from the previous layer, accumulates the membrane potential, and simultaneously performs leakage decay of the membrane potential according to physical characteristics. At the end of the current time step, the neuron checks whether its updated membrane potential has reached the pulse firing threshold. If the updated membrane potential is greater than or equal to the pulse firing threshold, the neuron fires a pulse signal to the next layer and performs a membrane potential reset operation; if the updated membrane potential is less than the pulse firing threshold, the neuron does not fire a pulse signal and carries the current membrane potential into the next time step to continue accumulation and decay.

[0073] Furthermore, to better understand the technical solution of this invention, the following explanations are provided for the core terms involved in spiking neural networks: Spiking neural networks are a third-generation neural network based on the spiking mechanism of biological neurons. The network transmits discrete pulse signals instead of continuous real values, and features event-driven, sparse computation and extremely low power consumption.

[0074] Leakage integral ignition neuron is a commonly used mathematical model of neurons in spiking neural networks. It has the characteristics of integrating and accumulating the input current, naturally leaking and decaying the membrane potential over time, and igniting and firing pulses when a threshold is reached.

[0075] Membrane potential is a state variable inside a leaky integral igniting neuron, representing the current accumulated voltage value of the neuron, and is the core indicator that determines whether the neuron fires a pulse signal.

[0076] Synaptic weights are parameters that characterize the strength of the connection channels between neurons in adjacent network layers. They are mapped from the channel weights of the pre-trained convolutional neural network and determine the contribution of the pulses from the previous layer to the accumulation of the membrane potential of the neurons in the next layer.

[0077] The time step is the smallest time unit in which the time axis is discretized during forward inference in a spiking neural network. The network's state updates and pulse propagation are both progressively advanced in steps based on the time step.

[0078] The leakage time constant is a physical parameter that controls the rate at which the membrane potential decays in the leak-integrated ignition neuron. The larger the constant, the slower the membrane potential decays, and the longer the neuron remembers historical pulse information.

[0079] The membrane potential decay coefficient is a coefficient used to scale the current membrane potential within each time step to achieve leakage decay. It is usually calculated based on the time step and the leakage time constant.

[0080] The pulse firing threshold is the trigger voltage threshold for the leak-integration ignition neuron to fire a pulse signal. When the updated membrane potential reaches or exceeds this threshold, the neuron triggers the ignition operation.

[0081] The bias parameters are mapped from the bias terms of the pre-trained convolutional neural network, providing a constant base accumulated value for the membrane potential of the leak-integration ignition neuron at each time step, which is used to regulate the basic excitability of the neuron.

[0082] Membrane potential reset is a membrane potential recovery mechanism after the leaked integral ignition neuron fires a pulse. It involves subtracting the pulse firing threshold from the updated membrane potential to retain residual membrane potentials that exceed the threshold, thereby avoiding the loss of high-frequency pulse information.

[0083] The input stimulus accumulation value is the total current value obtained by multiplying the pulse signals transmitted from all connected neurons in the previous network layer by their corresponding synaptic weights within the current time step. It is the direct stimulus source that causes the membrane potential of the current neuron to rise.

[0084] Furthermore, as a response to the above Figure 1 In addition to the implementation of the method shown, this embodiment of the invention also provides a DC series arc identification device for identifying the above-mentioned arc. Figure 1 The method shown is implemented accordingly. This device embodiment corresponds to the foregoing method embodiment. For ease of reading, this device embodiment will not repeat the details of the foregoing method embodiment, but it should be clear that the device in this embodiment can implement all the contents of the foregoing method embodiment. Figure 3 As shown, the device includes: The network acquisition unit 301 is used to acquire a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The convolutional neural network is used to process the time-frequency characteristics after the time-domain discrete signal transformation to identify DC series arcs in a DC circuit. The parameter mapping unit 302 is used to map the parameters of the convolutional neural network obtained by the network acquisition unit 301 to the spiking neural network layer by layer to obtain the target DC series arc recognition model. Signal processing unit 303 is used to acquire the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal; The arc identification unit 304 is used to process the pulse signal obtained by the signal processing unit 303 using the target DC series arc identification model obtained by the parameter mapping unit 302, so as to obtain the arc identification result of the target DC circuit.

[0085] Furthermore, as a response to the above Figure 2 In addition to the implementation of the method shown, this embodiment of the invention also provides a DC series arc identification device for identifying the above-mentioned arc. Figure 2 The method shown is implemented accordingly. This device embodiment corresponds to the foregoing method embodiment. For ease of reading, this device embodiment will not repeat the details of the foregoing method embodiment, but it should be clear that the device in this embodiment can implement all the contents of the foregoing method embodiment. Figure 4 As shown, the device includes: The network acquisition unit 301 is used to acquire a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The convolutional neural network is used to process the time-frequency characteristics after the time-domain discrete signal transformation to identify DC series arcs in a DC circuit. The parameter mapping unit 302 is used to map the parameters of the convolutional neural network obtained by the network acquisition unit 301 to the spiking neural network layer by layer to obtain the target DC series arc recognition model. Signal processing unit 303 is used to acquire the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal; The arc identification unit 304 is used to process the pulse signal obtained by the signal processing unit 303 using the target DC series arc identification model obtained by the parameter mapping unit 302, so as to obtain the arc identification result of the target DC circuit.

[0086] In one optional implementation, the network acquisition unit 301 includes: The model acquisition module 3011 is used to acquire a joint model, which includes a convolutional neural network and a long short-term memory network cascaded in sequence. The long short-term memory network is used to apply temporal constraints to the output of the convolutional neural network during the training phase using temporal processing capabilities to optimize the parameters of the convolutional neural network. The network removal module 3012 is used to remove the long short-term memory network from the joint model to obtain the convolutional neural network.

[0087] In one optional implementation, the parameter mapping unit 302 includes: The weight mapping module 3021 is used to map the channel weights of each network layer in the convolutional neural network to the synaptic weights of the corresponding channels in the corresponding network layer of the spiking neural network. Each network layer in the spiking neural network includes at least one channel, and each channel includes multiple leaky integration ignition neurons. The synaptic weights are used to control the intensity of the pulse signal transmitted between the leaky integration ignition neurons connected in adjacent network layers. The bias mapping module 3022 is used to map the bias terms of each network layer in the convolutional neural network to the bias parameters of each leak-integration ignition neuron in the corresponding channel of the corresponding network layer of the spiking neural network. The bias parameters are used to provide a constant potential accumulation value when the leak-integration ignition neuron of the current network layer accumulates the membrane potential. The model configuration module 3023 is used to use the spiking neural network mapped by the weight mapping module 3021 and the bias parameters mapped by the bias mapping module 3022 as the target DC series arc recognition model.

[0088] In one optional implementation, the network layer of the target DC series arc identification model includes an input layer, a hidden layer, and an output layer; the arc identification unit 304 includes: The signal receiving module 3041 is used to send pulse signals to the input layer and transmit them to the hidden layer; The potential update module 3042 is used to accumulate the membrane potential based on the pulse signal emitted by the previous network layer, using the leaked integral ignition neurons in the hidden layer, to obtain the updated membrane potential. The pulse firing module 3043 is used to fire a pulse signal to the leaky integrator connected to the next network layer in response to the membrane potential updated by the potential update module 3042 reaching the pulse firing threshold, and to reset the updated membrane potential by subtracting the pulse firing threshold, so as to retain the residual membrane potential exceeding the pulse firing threshold. The output layer processing module 3044 is used to perform the membrane potential accumulation of the potential update module 3042, the pulse signal emission of the pulse emission module 3043 and the membrane potential reset operation by using the leaked integral ignition neuron in the output layer based on the received pulse signal transmitted from the previous hidden layer. The result output module 3045 is used to obtain the DC series arc identification result of the target DC circuit based on the pulse signal emission of the leaked integration ignition neuron in the output layer of the output layer processing module 3044.

[0089] In one optional implementation, the potential update module 3042 is specifically used for: Calculate the ratio of the membrane potential update time step to the leakage time constant, and determine the membrane potential decay coefficient based on the ratio; Multiply the current membrane potential by the membrane potential decay coefficient to obtain the remaining membrane potential after leakage decay. For each leaking integral ignition neuron, the pulse signal transmitted by the leaking integral ignition neuron connected in the previous network layer is obtained. Each pulse signal is multiplied by the corresponding synaptic weight and then summed to obtain the input excitation accumulation value. The remaining membrane potential, the accumulated input excitation value, and the bias parameter of the leaked integral ignition neuron are added together, and the sum is used as the updated membrane potential of the leaked integral ignition neuron.

[0090] In one optional implementation, the signal processing unit 303 includes: The signal partitioning module 3031 is used to perform sliding frame partitioning on the time-domain discrete signal according to a preset frame length and a preset sliding step length to obtain multiple time-domain signal frames. The time length corresponding to the preset sliding step length is equal to the time step length of the membrane potential update. The spectrum transformation module 3032 is used to perform a short-time Fourier transform on each time-domain signal frame divided by the signal division module 3031 to obtain a complex spectrum, and extract the amplitude information of the complex spectrum in the positive frequency range to obtain the initial frequency domain features corresponding to each time-domain signal frame. The feature enhancement module 3033 is used to determine the weight of each frequency point in the positive frequency range obtained by the spectrum transformation module 3032 using the flipped Gaussian function, and multiply the amplitude of each frequency point in the initial frequency domain feature with the corresponding weight to obtain the enhanced frequency domain feature corresponding to each time domain signal frame. The pulse coding module 3034 is used to encode each enhanced frequency domain feature obtained by the feature enhancement module 3033 into corresponding binary pulse data; The signal organization module 3035 is used to combine the binary pulse data obtained by the pulse encoding module 3034 in chronological order to generate the pulse signal.

[0091] In one optional implementation, when determining the weights of each frequency point using the flipped Gaussian function, the feature enhancement module 3033 is specifically used for: Calculate the squared value of the frequency value and the squared value of the preset Gaussian standard deviation for each frequency point; Calculate the ratio of the squared value of the frequency to the squared value of twice the preset Gaussian standard deviation; The negative value of the ratio is used as the exponent, and the natural constant is calculated to the power of the exponent to obtain an intermediate calculated value; The weight value of the corresponding frequency point is determined based on the intermediate calculated value, and the weight value increases as the frequency increases.

[0092] Furthermore, embodiments of the present invention also provide a storage medium for storing a computer program, wherein the computer program, when running, controls the device where the storage medium is located to execute the above-described... Figure 1-2 The method described in [the document / article].

[0093] Furthermore, embodiments of the present invention also provide a processor for running a program, wherein the program executes the above-described... Figure 1-2 The method described in [the document / article].

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0095] It is understood that the relevant features in the above methods and apparatus can be referenced interchangeably. Furthermore, the terms "first," "second," etc., in the above embodiments are used to distinguish between embodiments and do not represent the superiority or inferiority of any particular embodiment.

[0096] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0097] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0098] In addition, the memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0099] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0100] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0101] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0102] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0103] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0104] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0105] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0106] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0107] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for identifying DC series electric arcs, characterized in that, The method includes: Obtain a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The convolutional neural network is used to process the time-frequency characteristics of the time-domain discrete signal after transformation to identify DC series arcs in a DC circuit. The parameters of the convolutional neural network are mapped layer by layer into the spiking neural network to obtain the target DC series arc identification model; Acquire the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal; The pulse signal is processed using the target DC series arc identification model to obtain the arc identification result of the target DC circuit.

2. The method according to claim 1, characterized in that, Obtaining a convolutional neural network includes: A joint model is obtained, which includes a convolutional neural network and a long short-term memory network cascaded in sequence. The long short-term memory network is used to apply temporal constraints to the output of the convolutional neural network during the training phase using temporal processing capabilities to optimize the parameters of the convolutional neural network. The convolutional neural network is obtained by removing the long short-term memory network from the joint model.

3. The method according to claim 1, characterized in that, The parameters of the convolutional neural network are mapped layer by layer into the spiking neural network to obtain the target DC series arc identification model, including: The channel weights of each network layer in the convolutional neural network are mapped to the synaptic weights of the corresponding channels in the corresponding network layer of the spiking neural network. Each network layer in the spiking neural network includes at least one channel, and each channel includes multiple leaky integrators. The synaptic weights are used to control the intensity of the pulse signal transmitted between the leaky integrators connected in adjacent network layers. The bias terms of each network layer in the convolutional neural network are mapped to the bias parameters of each leak-integration ignition neuron in the corresponding channel of the corresponding network layer of the spiking neural network. The bias parameters are used to provide a constant potential accumulation value when the leak-integration ignition neuron of the current network layer accumulates the membrane potential. The spiking neural network mapped with the synaptic weights and the bias parameters is used as the target DC series arc identification model.

4. The method according to any one of claims 1-3, characterized in that, The network layer of the target DC series arc identification model includes an input layer, a hidden layer, and an output layer; the pulse signal is processed using the target DC series arc identification model to obtain the arc identification result of the target DC circuit, including: The pulse signal is sent to the input layer and then transmitted to the hidden layer; For the hidden layer, the leak-integration ignition neurons in the hidden layer are used to accumulate the membrane potential based on the pulse signal emitted by the previous network layer, so as to obtain the updated membrane potential. In response to the updated membrane potential reaching the pulse firing threshold, a pulse signal is fired to the leaky integral ignition neuron connected to the next network layer, and the updated membrane potential is reset by subtracting the pulse firing threshold to retain the residual membrane potential that exceeds the pulse firing threshold. Based on the received pulse signal transmitted from the previous network layer, the leaky integral firing neurons in the output layer are used to perform the operations of membrane potential accumulation, pulse signal emission, and membrane potential reset. Based on the pulse signal emission of the leaked integral ignition neurons in the output layer, the DC series arc identification result of the target DC circuit is obtained.

5. The method according to claim 4, characterized in that, By utilizing leak-integration ignition neurons in the hidden layer, the membrane potential is accumulated based on the received pulse signals emitted by the previous network layer to obtain the updated membrane potential, including: Calculate the ratio of the membrane potential update time step to the leakage time constant, and determine the membrane potential decay coefficient based on the ratio; Multiply the current membrane potential by the membrane potential decay coefficient to obtain the remaining membrane potential after leakage decay. For each leaking integral ignition neuron, the pulse signal transmitted by the leaking integral ignition neuron connected in the previous network layer is obtained. Each pulse signal is multiplied by the corresponding synaptic weight and then summed to obtain the input excitation accumulation value. The remaining membrane potential, the accumulated input excitation value, and the bias parameter of the leaked integral ignition neuron are added together, and the sum is used as the updated membrane potential of the leaked integral ignition neuron.

6. The method according to claim 1, characterized in that, Encoding the discrete-time signal into a pulse signal includes: According to the preset frame length and preset sliding step length, the time-domain discrete signal is divided into multiple time-domain signal frames by sliding frames. The time length corresponding to the preset sliding step length is equal to the time step length of the membrane potential update. Perform a short-time Fourier transform on each of the time-domain signal frames to obtain a complex spectrum, and extract the amplitude information of the complex spectrum in the positive frequency range to obtain the initial frequency domain features corresponding to each of the time-domain signal frames; The weights of each frequency point within the positive frequency range are determined using the flipped Gaussian function, and the amplitudes of each frequency point in the initial frequency domain features are multiplied by the corresponding weights to obtain the enhanced frequency domain features corresponding to each time domain signal frame. Each of the enhanced frequency domain features is encoded into corresponding binary pulse data; The binary pulse data are combined in chronological order to generate the pulse signal.

7. The method according to claim 6, characterized in that, The weights of each frequency point within the positive frequency range are determined using the flipped Gaussian function, including: Calculate the squared value of the frequency value and the squared value of the preset Gaussian standard deviation for each frequency point; Calculate the ratio of the squared value of the frequency to the squared value of twice the preset Gaussian standard deviation; Taking the negative value of the ratio as the exponent, the natural constant is calculated to the power of the exponent to obtain an intermediate calculated value; The weight value of the corresponding frequency point is determined based on the intermediate calculated value, and the weight value increases as the frequency increases.

8. A device for identifying DC series electric arcs, characterized in that, The device includes: The network acquisition unit is used to acquire a convolutional neural network and a spiking neural network with the same hierarchical topology as the convolutional neural network. The convolutional neural network is used to process the time-frequency characteristics of the time-domain discrete signal after transformation to identify DC series arcs in a DC circuit. The parameter mapping unit is used to map the parameters of the convolutional neural network obtained by the network acquisition unit to the spiking neural network layer by layer to obtain the target DC series arc recognition model. The signal processing unit is used to acquire the time-domain discrete signal of the target DC circuit and encode the time-domain discrete signal into a pulse signal; An arc identification unit is used to process the pulse signal obtained by the signal processing unit using the target DC series arc identification model obtained by the parameter mapping unit, so as to obtain the arc identification result of the target DC circuit.

9. A storage medium, characterized in that, The storage medium includes a stored program, wherein, when the program is executed, it controls the device containing the storage medium to perform the DC series arc identification method as described in any one of claims 1 to 7.

10. A processor, characterized in that, The processor is used to run a program, wherein the program executes the method for identifying DC series arcs as described in any one of claims 1 to 7.

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