Conditional distribution-based logic circuit vulnerability estimation method combining with graph neural network

Abstract

The application relates to a logic circuit vulnerability estimation method combining a conditional distribution and a graph neural network, and relates to the technical field of digital chip anti-radiation. The application is to solve the defects of the existing method for evaluating soft error rate. The application extracts a target combinational logic block with a flip-flop as a boundary in a gate-level netlist of a target logic circuit; circuit graph data of the target combinational logic block is input into a graph neural network model, and an estimation result of vulnerability of the target combinational logic block is output; the graph neural network model performs the following operations: through a neighborhood aggregation mechanism, each node feature and neighbor node features in the circuit graph data are fused to generate a node representation of each node in the graph; global mean pooling processing is performed on all node representations to obtain a graph representation; the graph representation is input into a multilayer perceptron to predict a prediction distribution; the mean value of circuit vulnerability in the prediction distribution is calculated by using the prediction distribution, and the mean value is taken as the output of the graph neural network model.

Description

Technical Field

[0001] This application belongs to the field of digital chip radiation protection technology, and in particular relates to circuit vulnerability estimation. Background Technology

[0002] Single-event effects (SEE) are one of the major faults faced by digital integrated circuits in space radiation environments. In digital circuits, both logic gates and flip-flops can experience SEE: when a flip-flop undergoes a SEE transition, it latches the resulting level state, directly generating a soft error; while a logic gate's SEE transient only causes a soft error if the transient pulse it generates propagates normally to the flip-flop and is latched. This probabilistic characteristic makes accurate assessment of the soft error rate of digital circuits extremely difficult.

[0003] Currently, soft error rate (Soft Error Rate) assessment is mainly achieved through two methods. The first is a fault injection-based approach, essentially a Monte Carlo method, which injects faults into a simulation platform to statistically determine the probability of soft errors. Existing work focuses on implementing fault injection frameworks across different simulation platforms, accelerating the single-simulation process of fault injection by constructing hybrid simulation platforms and mapping basic bits to the design under test, and compressing the required sample size by introducing strategies such as Monte Carlo tree search, Bayesian sampling, and adaptive importance sampling, thus accelerating the overall assessment process. The second method is based on static analysis, which directly calculates the reliability of logic gates and circuits by designing fault models and algorithms. Typical works include the PTM method, SPRA method, PGM method, and the MaskIt method specifically designed for single-event transients. MaskIt employs backpropagation, making the number of algorithm iterations proportional to the number of logic gates, thus reducing computational overhead to some extent. Furthermore, machine learning methods have also seen preliminary applications in circuit soft error rate estimation.

[0004] However, all of the aforementioned existing technologies have their inherent drawbacks. Regarding fault injection-based methods, they face an unacceptable runtime bottleneck. This is because the sampling space for fault injection grows exponentially with the number of circuit input vectors. Even with various sampling strategies and simulation acceleration methods, the number of experiments required for large-scale circuits remains extremely large, making the evaluation time insufficient for practical engineering needs. In terms of static analysis methods, the core challenge lies in the signal correlation problem caused by the re-converging fan-out structure. The re-converging structure causes multiple propagation paths of the same signal to converge again at subsequent logic gates, resulting in complex correlations between signals. Classical methods lack the ability to accurately model these correlations. Although existing technologies attempt to introduce correlation coefficients, binary non-Bernoulli sequences, Bayesian networks, and other methods to more accurately characterize signal correlations during fault propagation, as circuit size increases and re-converging structures become increasingly complex, these accurate modeling methods inevitably and significantly increase the overhead of algorithm traversal and computation, making the balance between runtime and estimation accuracy extremely difficult. Meanwhile, static analysis methods suffer from an inherent drawback: computational accuracy deteriorates as circuit size increases. This is because these methods require multiple complete traversals of the circuit diagram. During the gate-by-gate, level-by-level propagation calculation, a large number of floating-point numbers are involved in multiplication and addition operations. As the circuit size grows, the accumulated floating-point numbers easily exceed the floating-point representation precision of the computer, leading to a significant loss of accuracy in the calculation results. Therefore, the accuracy and speed bottlenecks of static analysis methods become increasingly apparent as circuit size increases. In machine learning, existing attempts are limited by the architectural characteristics of the models themselves. Taking recurrent neural networks as an example, their serialization processing mode struggles to effectively capture the large-scale, non-Euclidean topology of circuit netlists. Therefore, they can only predict extremely small circuits such as full adders, severely restricting their scalability to larger-scale combinational logic circuits.

[0005] In summary, the existing technologies mainly have the following technical problems that urgently need to be solved: the exponential sampling space of fault injection methods leads to unacceptable evaluation efficiency; static analysis methods are caught in a dilemma between accuracy and efficiency due to the difficulty in modeling signal correlation caused by re-converging structures, while the cumulative accuracy loss of floating-point numbers is aggravated as the circuit size increases; and existing machine learning methods cannot be extended to large-scale gate-level netlists due to architectural limitations. Summary of the Invention

[0006] This application addresses the problems of existing methods for assessing soft error rates, such as the time-consuming nature of fault injection methods due to the exponential growth of the sampling space, the difficulty in balancing accuracy and efficiency and the accumulation of floating-point errors in static analysis methods, and the limited scalability of machine learning methods. It provides a logic circuit vulnerability estimation method combining conditional distribution and graph neural networks. Utilizing the inherent graph representation learning capabilities of graph neural networks (GNNs), it models combinational logic blocks as soft error information graphs containing circuit structure information and vulnerability-related initial features. Combining the theoretical advantages of graph isomorphic networks in node representation learning, and introducing conditional distribution learning to replace the traditional end-to-end regression training method, it overcomes the speed bottleneck and scalability limitations in large-scale circuit soft error rate assessment while ensuring estimation accuracy, achieving efficient and accurate estimation of circuit vulnerability.

[0007] The first aspect of this application provides a method for estimating the vulnerability of logic circuits by combining conditional distributions and graph neural networks, including:

[0008] Extract the target combinational logic block with flip-flops as boundaries from the gate-level netlist of the target logic circuit. The target combinational logic block includes logic gates, input nodes, output nodes, and constant nodes.

[0009] The circuit diagram data of the target combinational logic block is input into the graph neural network model, and the vulnerability estimation result of the target combinational logic block is output.

[0010] The circuit diagram data includes circuit nodes and the connections between nodes, and each node contains initial features related to circuit vulnerability.

[0011] The graph neural network model performs the following operations:

[0012] The features of each node and its neighboring nodes in the circuit diagram data are fused using a neighborhood aggregation mechanism to generate a node representation for each node.

[0013] Perform global mean pooling on all node representations to obtain a graph representation;

[0014] The graph representation is input into a multilayer perceptron to predict the distribution.

[0015] The estimated value of the circuit vulnerability is calculated using the predicted distribution and used as the output of the graph neural network model.

[0016] In one possible design, the circuit diagram data is a soft error information graph, which uses the logic gates, input nodes, output nodes, and constant nodes as nodes and the lines between the nodes as edges. Each node contains initial features related to circuit vulnerability.

[0017] In one possible design, the method for obtaining the soft error information graph includes:

[0018] Extract the circuit topology from the gate-level netlist corresponding to the target combinational logic block, and construct a directed topology graph using the logic gates, input nodes, output nodes and constant nodes in the target combinational logic block as nodes and the connections between nodes as edges.

[0019] Assign initial features related to circuit vulnerability to each node;

[0020] The directed topological graph with assigned features is converted into an undirected graph to obtain the soft error information graph.

[0021] In one possible design, the initial features include the node type, signal probability, and logic shielding capability.

[0022] In one possible design, the neighborhood aggregation mechanism includes:

[0023] Node In the The layer's own characteristics multiplied by a coefficient and with the node All neighboring nodes in the 1st The features of the layers are summed and aggregated.

[0024] Input the aggregation result into the first... In a multilayer perceptron of a layered graph isomorphic network model, the output node is... In the Layer node representation;

[0025] This is the layer index for a graph isomorphic network model. For the first Layer diagrams utilize the learnable parameters of the network model.

[0026] In one possible design, inputting the graph representation into a multilayer perceptron to predict the predicted distribution includes:

[0027] The graph representation is input into a multilayer perceptron, which outputs the vulnerability condition distribution of the target combinational logic block. The vulnerability condition distribution is a histogram density, which includes the predicted probability that the vulnerability of the target combinational logic block falls into each sub-interval of the [0,1] interval.

[0028] In one possible design, calculating the mean of the circuit vulnerability in the predicted distribution using the predicted distribution includes:

[0029] Divide the interval [0,1] evenly into For each sub-interval, the estimated value of the circuit vulnerability is calculated using the following formula:

[0030] ,

[0031] in, This represents the mean of circuit vulnerability in the predicted distribution. For the first The center value of each sub-interval The vulnerability of the target logic block falls into the histogram. The probability of each sub-interval.

[0032] In one possible design, the training method for the graph neural network model includes:

[0033] A truncated Gaussian distribution is constructed centered on the actual vulnerability value of the target combinational logic circuit as the target distribution.

[0034] The vulnerability condition distribution output by the graph neural network model is used as the prediction distribution.

[0035] The graph neural network model is updated using the KL divergence between the target distribution and the predicted distribution as the loss function.

[0036] In one possible design, the loss function expression for training the graph neural network model is:

[0037] ,

[0038] in, Represents the target distribution and predicted distribution KL divergence between them For the target distribution and predicted distribution Cross-entropy between For the target distribution Cross-entropy.

[0039] In one possible design, the expression for the target distribution is:

[0040] ,

[0041] in, For position The probability density value at that location. The vulnerability value is assigned to a point on the histogram interval. To truncate the standard deviation of the Gaussian distribution, The mean of a Gaussian distribution, and intermediate variables. , Represents the error function. and These are the lower and upper bounds of the cutoff interval of the truncated Gaussian distribution, respectively.

[0042] A second aspect of this application provides a logic circuit vulnerability estimation apparatus combining conditional distribution and graph neural network, the apparatus comprising a processor and a memory, the memory storing at least one instruction, the at least one instruction being loaded and executed by the processor to implement the logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described above.

[0043] A third aspect of this application provides a computer storage medium storing at least one instruction, which is loaded and executed by a processor to implement the logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described above.

[0044] The beneficial effects of this application are:

[0045] This application models combinational logic blocks as an undirected graph with logic gates, inputs, outputs, and constant nodes as nodes and wires as edges, and assigns initial features to each node to construct a soft error information graph. This graph modeling approach encodes the circuit's topological structure information and vulnerability-related factors into a graph data structure, providing an input foundation for graph neural networks. This enables subsequent models to efficiently learn the intrinsic mapping relationship between circuit structure and vulnerability, ultimately achieving high-precision vulnerability estimation.

[0046] Building upon the aforementioned graph modeling, this application employs a graph isomorphic network as the encoder. Utilizing its neighborhood aggregation mechanism with learnable parameters, iteratively fuses the features of the central node itself with the features of its multi-layered neighbor nodes, generating node representations that fully incorporate local topological context information. Furthermore, this application employs global average pooling as the graph-level readout strategy, using the average of all node representations as the representation of the entire graph. This avoids the biases that might be introduced by complex pooling strategies while leveraging the powerful node representation capabilities of the graph isomorphic network to ensure the quality of the graph representation, thus providing physically meaningful and information-rich graph-level features for subsequent predictions.

[0047] After obtaining the graph representation, this application models the task as a histogram density estimation problem of learning the conditional distribution of vulnerability over the [0,1] interval. The network outputs the density value of each sub-interval in the histogram. During the training phase, a truncated Gaussian distribution is used as the target distribution, and KL divergence is used as the loss function for supervision. During the inference phase, the vulnerability estimate is calculated by weighted summation of the probability of each interval and the interval center value. The inherent advantages of this distribution learning mechanism are: on the one hand, compared with end-to-end regression, distribution learning provides richer supervision signals, increases the hypothesis space and learning difficulty of the model, thereby effectively preventing overfitting and promoting generalization; on the other hand, compared with simple classification tasks, histogram density estimation breaks through the theoretical upper limit of the indiscriminate nature of samples in the same interval in classification patterns, allowing the predicted value to change continuously within the interval, resulting in more refined estimation results. Experimental data show that the MAE and MRE of the distribution modeling method are reduced by approximately 73% and 68% respectively compared with end-to-end regression, verifying the effectiveness of the above mechanism.

[0048] In summary, this application achieves comprehensive performance superiority over existing methods: the mean absolute error is less than 0.02, the mean relative error is approximately 5%, and the Pearson correlation coefficient reaches 0.98, demonstrating a strong correlation with the true value. Regarding inference efficiency, thanks to the undirected graph structure adapted for GPU parallel computing and the computational paradigm of graph neural networks where inference can be completed with a single forward propagation, the inference time for a single circuit is less than 1 second. This fundamentally overcomes the efficiency bottlenecks caused by the need for multiple gate traversals in traditional static analysis methods and the need for massive sampling in fault injection methods. Attached Figure Description

[0049] Figure 1 A flowchart illustrating the logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described in a specific implementation;

[0050] Figure 2 A flowchart for resolving a gate-level netlist into a directed topology graph;

[0051] Figure 3 A flowchart for assigning vulnerability-related features;

[0052] Figure 4 The training flowchart for the GNN4SE model;

[0053] Figure 5 A schematic diagram illustrating the prediction results for different problem modeling methods. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. Specific implementation method one:

[0056] Combinational logic blocks are the processing objects in this implementation method; they refer to the combinational logic circuit section bounded by input nodes, output nodes, and flip-flops. For a given combinational logic block, each logic gate... It can be encoded into a vector ,in, The feature dimensions of the nodes are represented. Next, the combinational logic block can be represented as a matrix. ,in This indicates the number of logic gates within a combinational logic block, and the vulnerability of that combinational logic block is... Consider learning a conditional distribution of vulnerability within the interval [0,1], and then using the average of this conditional distribution as the circuit vulnerability. This approach increases the learning difficulty but effectively prevents overfitting and promotes generalization.

[0057] The Soft Error Information Graph (SEIG) is a graph data obtained after processing combinational logic blocks in this embodiment. The SEIG uses input, output, and constant variables and logic gates in the gate-level netlist as nodes, and wire variables in the gate-level netlist as edges. Nodes in the SEIG contain initial features related to circuit vulnerability.

[0058] Constrained target distribution and predicted distribution Let [0,1] be the histogram density. Assume [0,1] is uniformly divided into... There are 10 sub-intervals, each with a width of 1. ,function coefficient This represents the soft error rate of a given SEIG falling within a certain interval. The probability of the predicted distribution. Corresponding to a normalized histogram density, the density value for each interval is... Finally, circuit vulnerability is the average soft error rate of SEIG across each interval. :

[0059] (1),

[0060] in, For the first The center value of each sub-interval To predict the th in the distribution The probability of each sub-interval.

[0061] Figure 1 This is a flowchart of the logic circuit vulnerability estimation method combining conditional distribution and graph neural networks described in this embodiment. In this embodiment, the gate-level netlist of the target logic circuit is preprocessed to obtain SEIG. A trained GNN4SE (Graph Neural Network for Soft Error Rate Estimation) is used to learn a graph representation that integrates circuit structure and vulnerability information on the SEIG. Then, this graph representation is used to predict the histogram density of the SEIG. Finally, the vulnerability of the gate-level netlist is estimated using the probability of each interval in the histogram density. Specifically:

[0062] 1. Preprocessing: The gate-level netlist (circuit structure description file) of the target circuit is converted into an abstract syntax tree (AST). Then, a depth-first search is performed on the AST to extract the circuit's topology information, constructing a directed topology graph. Vulnerability information is assigned to nodes as initial features on this normal circuit topology graph. This vulnerability information includes node type, signal probability, and logic masking capability. Finally, the directed graph is converted into an undirected graph, and the assigned node features are combined to construct a SEIG (Self-Enhancing Indicator).

[0063] Specifically, the preprocessing stage consists of two parts: graph modeling and feature allocation.

[0064] 1) Graph modeling

[0065] like Figure 2 As shown, the gate-level netlist is first parsed into an abstract syntax tree (AST). In the AST, a wire is also represented as a node, and the child nodes of a logic gate are wire nodes. Therefore, a depth-first search is performed on the AST to form an initial topology graph, during which wires are temporarily represented as nodes in the graph. Thus, when adding a logic gate node, an edge is added between the logic gate and the wire node. In fact, edges in the initial topology graph have no practical meaning, and using wires as nodes increases the memory usage of the circuit graph. Therefore, the initial topology graph is simplified by performing a breadth-first search, directly connecting the predecessor and successor nodes of wire nodes, and removing the wire nodes. This results in a directed circuit topology graph with input, output, logic gates, and constants as nodes and wires as edges.

[0066] 2) Feature allocation

[0067] like Figure 3 As shown, nodes in SEIG possess initial vulnerability-related characteristics, namely node type, logic shielding capability, and signal probability. Signal probability is a prerequisite for vulnerability analysis, and an unbiased estimate is generated using Monte Carlo-based logic simulation. First, a predetermined number of simulations is set. Then, the input vector is initialized, and circuit logic simulation is performed node by node, recording the number of times a node's logic value is 1 during each simulation. When the predetermined number of simulations is reached, the ratio of the number of times each node's logic value is 1 to the number of circuit simulations is used as the signal probability. Since the signal probability is a value obtained through simulation, it implicitly contains the node's topology depth and the circuit's data flow direction.

[0068] Next, the graph is traversed once more, this time assigning node types and logical masking capabilities. Node types are embedded into the initial features as one-hot vectors. Logical masking capability is the ability of a logic gate to mask single-particle transients. For a two-input logic gate, logical masking capability refers to the probability that the logic gate can output correctly when a single-particle transient propagates to it. The logical masking capability is:

[0069] (2),

[0070] in, This indicates the logic shielding capability of a logic gate. and These are the two input signals of a two-input logic gate. The output signal of the logic gate. Indicates the input of the logic gate The probability of being able to output correctly.

[0071] The above formula applies to any two-input logic gate. There are two special cases: for NOT gates, there is only one input signal, and the logic masking probability is always 0. When modeling the topology, it also includes Input, Output, and Const nodes. For these nodes, let... It ignores the actual probability of signal errors and only evaluates the logic gate's logic masking capability when a signal error occurs. This approach allows for characterizing the inherent properties of logic gates, while leaving this hidden information to be learned by the GNN.

[0072] Finally, the directed graph is converted into an undirected graph, resulting in SEIG. The undirected graph form captures the graph's topological relationships and provides complete node context information when generating node representations.

[0073] 2. GNN4SE Model: GNN4SE takes SEIG as input and uses the summation function in the Graph Isomorphism Network (GIN) model to aggregate neighborhood circuit vulnerability messages. It then uses a multilayer perceptron in the GIN model to update the vulnerability-specific node representation. The generated node representation is then processed by a global average pooling function that conforms to the arithmetic mean characteristics of circuit vulnerability to generate a graph representation specifically for circuit vulnerability estimation. Finally, the multilayer perceptron generates the corresponding histogram density from the graph representation.

[0074] GNN4SE is the model architecture used in this implementation. It is trained using a dedicated circuit vulnerability dataset to converge the model parameters. The trained GNN4SE can be used to infer the circuit vulnerability value of a given combinational logic block, such as... Figure 4 As shown.

[0075] 1) Generation of Vulnerability Node Representations

[0076] Graph Isomorphic Networks (GINs) are highly representative encoders in the node feature aggregation stage. Their core advantage lies in their theoretically complete neighborhood aggregation mechanism, which can fully integrate the central node's own attributes with the features of neighboring nodes with multiple hop counts. As shown in Equation (3), GINs introduce learnable parameters... By weighting and scaling the original features of the central node, and then summing and aggregating them with the normalized features of its neighbors, it has been theoretically proven to have a powerful expressive ability to distinguish any non-isomorphic graphs and to capture the feature differences corresponding to different local topologies in a precise manner. GIN is considered to generate node representations that can effectively integrate the features of neighboring nodes and local topological structure information. Through multiple layers of propagation, each node representation contains both local details and implicit contextual information of the node.

[0077] (3),

[0078] in, The current central node to be updated. For nodes The neighboring nodes, For layer index, For nodes In the Layer node representation, For the first Multilayer perceptron, For the first Learnable parameters of the layer For neighboring nodes In the Layer node representation.

[0079] 2) Vulnerability graph representation generation

[0080] As can be seen from formula (1), the overall vulnerability of the circuit is not determined independently by a single logic gate, but is the combined result of the vulnerabilities of all logic gates. From a statistical perspective, it can be equivalently described as the average value of the individual vulnerabilities of all gate-level units. In order to conform to the physical laws of the circuit and rely on the powerful node representation capability of GIN to complete the global graph representation construction, this implementation selects all node representations output by the last layer of GIN to perform global mean pooling as the graph-level readout aggregation strategy. This strategy naturally has the prior constraint of equal weighting of unit contributions.

[0081] (4),

[0082] in, This is a graphical representation of the entire circuit. Indicates global average pooling. This represents a soft error information diagram corresponding to the target combinational logic block. For nodes After all The final node representation generated after layer GIN propagation and update.

[0083] 3) Histogram density estimation

[0084] The graph representation is input into a Multi Layer Perceptron (MLP), which outputs the predicted histogram density (predicted distribution). To fit the true histogram density (target distribution) ).

[0085] GNN4SE employs differentiated computation logic during the training and inference phases. During training, the network outputs the histogram probability distribution corresponding to the entire image, minimizing the predicted histogram density relative to the target distribution. The KL divergence supervised model learning between the constraints allows the network to learn a graph representation that accurately matches the distribution of the real data.

[0086] Consider a truncated Gaussian distribution on the interval [0,1] as the method for generating the density in the histogram. The mean of the Gaussian distribution... It is vulnerability itself, probability density for:

[0087] (5),

[0088] in, The variable represents the range of values ​​on the histogram interval, and the intermediate variable is... Through variance parameter This results in a significant smoothing of the vulnerability value. Represents the error function. and These are the lower and upper bounds of the cutoff interval, respectively.

[0089] Using KL divergence as the loss function, the target distribution... and predicted distribution KL divergence between for:

[0090] (6),

[0091] in, For the target distribution and predicted distribution Cross-entropy between For the target distribution Cross-entropy.

[0092] During the inference phase, the predicted histogram density corresponding to each interval is directly read, and the circuit vulnerability is obtained by using formula (1).

[0093] In this implementation, in addition to commonly used metrics such as MAE (Mean Absolute Error), MRE (Mean Relative Error), RMSE (Root Mean Square Error), and Pearson correlation coefficient, the MAE-TOP5 (top 5% MAE) and MRE-TOP5 (top 5% MRE) metrics are also used. MAE-TOP5 refers to averaging the top 5% of absolute errors obtained during the inference phase, ranked from largest to smallest. MRE-TOP5 has a similar meaning. Such metrics allow for the observation of maximum errors and avoid missing outliers removed by the global mean, which is extremely important for regression prediction.

[0094] Table 1 compares the test results of GNN4SE with other benchmark solutions. This table shows that:

[0095] First, GNN4SE outperforms traditional algorithms across all metrics. GNN4SE achieves a mean absolute error of less than 0.02, a mean relative error of only 5%, a Pearson coefficient of 0.98, and its inference results show a strong correlation with the true value. In contrast, among other benchmark schemes, the best mean relative error, FPM, is only 10.2%, and other schemes have lower Pearson coefficients.

[0096] Secondly, GNN4SE also has a significant advantage in inference time. By leveraging the performance advantages of GPUs and the parallel computing advantages of undirected graphs, the inference time for a single graph is less than 1 second, while the running time of other traditional algorithms increases with the improvement of inference accuracy.

[0097] Third, relying solely on mean absolute error (MAE) or mean relative error (MRE) is not objective in circuit vulnerability estimation and fails to reflect the model's overall performance on the dataset. While different GNN models exhibit good predictive performance when only MAE and RMSE are considered, the task is to predict regression values ​​in the [0,1] interval. Therefore, more metrics are needed to evaluate model performance. MAE provides absolute error, MRE measures relative error, and RMSE is more sensitive to outliers and reflects the distribution of prediction errors. For circuits with low vulnerability, even slight fluctuations can lead to large relative errors. Therefore, even if a model achieves excellent performance on metrics such as MAE, RMSE, MRE, and Pearson's algorithm, its MAE-TOP5 and MRE-TOP5 metrics remain relatively poor, especially MRE-TOP5 at 0.342, which may result in an overestimation of circuit vulnerability when the circuit is small.

[0098] Table 1 Comparison results of GNN4SE and traditional algorithms

[0099]

[0100] Table 2 compares the test results of GNN4SE with other classic GNN schemes. Some classic models do not provide graph representation methods in their design; therefore, for these models, graph representation consistent with this implementation method is used. Examples include GCN, GAT, Deepgate, and PNA. Furthermore, all GNN models in this implementation method are trained using histogram density modeling to obtain objective comparison results under a unified benchmark. These benchmark schemes are tested using five random seeds to generate mean and variance. First, GNN4SE achieves the best prediction accuracy and training time among all models. This is due to optimizations for circuit fragility. Second, both stacked GNNs and recurrent GNNs show excellent results. However, recurrent GNNs clearly have excessively long training times, which is related to their aggregation method, making large-scale parallel training impossible. Similarly, both stacked GNNs and recurrent GNNs show poor results. GAT and DAGNN both use attention aggregation mechanisms when aggregating nodes. Attention mechanisms are prone to weight bipolarity, disrupting continuous feature gradients and amplifying the risk of overfitting during regression.

[0101] Table 2 Comparison results of different GNN models

[0102]

[0103] Instead of end-to-end regression prediction, we chose to learn the conditional distribution of circuit vulnerability. Therefore, it's necessary to discuss whether this problem modeling approach truly improves performance. Three scenarios are discussed: first, learning the conditional distribution (Histogram); second, a classification task (OneBin) using cross-entropy as the loss function for training, where the center value of the output interval is used as the circuit vulnerability after outputting the class in the inference result. OneBin and Histogram are consistent, both using an interval of 40. Third, direct end-to-end regression prediction using L2 loss for training.

[0104] Figure 5 The test results for the three modeling methods are presented directly. The horizontal axis in the graph represents circuits sorted from lowest to highest vulnerability. First, while end-to-end regression training is intuitive and has mature training models, it may result in predicted values ​​converging towards the dataset mean or median. Second, classification models perform better than regression models because classification problems are often easier to train model parameters for than regression problems. Distribution tasks often perform better than regression tasks, but if simply modeling as a classification task, there is a theoretical upper limit to the absolute error of this approach. Furthermore, a drawback of classification problems is that circuits within the same region lack discriminative strength. Histograms, however, demonstrate that they have more room to learn more accurate values, offering a tangible improvement for regression tasks.

[0105] Table 3 provides data support for the above analysis. Under the regression prediction model, the MAE and MRE increased by as much as 268% and 215% respectively, while the Pearson coefficient decreased by 13.68%. Although the distribution model also showed some increases in MAE and MRE, at 20.13% and 17.94% respectively, its Pearson coefficient did not decrease significantly. This indicates that the classification approach effectively improved the performance of regression prediction, and learning the conditional distribution can further increase the theoretical upper limit and improve model accuracy.

[0106] Table 3 Statistical results of model inference for different problem modeling methods

[0107]

[0108] To further illustrate the implementation scheme of this application, this embodiment uses the Nangate 45nm open-source cell library to synthesize a gate-level netlist. Regarding the logic masking capability allocation in feature assignment, taking a 2-input NAND gate as an example, when one signal of the gate is faulty and the other is normal, as long as the normal signal is logic 0, the faulty signal can be masked regardless of its nature. Therefore, using Formula 2, the logic masking capability of the 2-input NAND gate is calculated to be 0.5. The logic masking capability matrix of the logic gates is summarized in Table 4.

[0109] Table 4 Logic shielding capability of logic gates

[0110]

[0111] Specifically, a 12-dimensional vector is assigned to each node based on the gate type, logic shielding capability, and signal probability.

[0112] The node representation dimension is set to 128, the GIN layer is set to 3 layers, and the multilayer perceptron contains a hidden layer with 64 neurons and a ReLU activation function. The number of intervals in the histogram density is set. The variance is 40, truncated in the Gaussian distribution. It is 0.75.

[0113] The model was trained for 140 epochs using an NVIDIA Tesla V100 GPU with a batch size of 128 and an initial learning rate of [missing information]. , and according to attenuation.

[0114] Specific Implementation Method Two: The logic circuit vulnerability estimation device combining conditional distribution and graph neural network described in this implementation method includes a processor and a memory. The memory stores at least one instruction, which is loaded and executed by the processor to implement the logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described in Specific Implementation Method One.

[0115] Specific Implementation Method 3: A computer storage medium as described in this embodiment stores at least one instruction, which is loaded and executed by a processor to implement the logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described in Specific Implementation Method 1.

[0116] While specific embodiments of this application have been described herein with reference to them, it should be understood that these embodiments are merely examples of the principles and applications of this application. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of this application as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A vulnerability estimation method for logic circuits combining conditional distribution and graph neural networks, characterized in that, include: Extract the target combinational logic block with flip-flops as boundaries from the gate-level netlist of the target logic circuit. The target combinational logic block includes logic gates, input nodes, output nodes, and constant nodes. The circuit diagram data of the target combinational logic block is input into the graph neural network model, and the vulnerability estimation result of the target combinational logic block is output. The circuit diagram data includes circuit nodes and the connections between nodes, and each node contains initial features related to circuit vulnerability. The graph neural network model performs the following operations: The features of each node and its neighboring nodes in the circuit diagram data are fused using a neighborhood aggregation mechanism to generate a node representation for each node. Perform global mean pooling on all node representations to obtain a graph representation; The graph representation is input into a multilayer perceptron to predict the distribution. The mean of the circuit vulnerability in the predicted distribution is calculated using the predicted distribution and used as the output of the graph neural network model.

2. The logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described in claim 1, characterized in that, The circuit diagram data is a soft error information graph, which uses the logic gates, input nodes, output nodes, and constant nodes as nodes and the lines between the nodes as edges. Each node contains initial features related to circuit vulnerability.

3. The vulnerability estimation method for logic circuits combining conditional distribution and graph neural networks according to claim 2, characterized in that, The method for obtaining the soft error information map includes: Extract the circuit topology from the gate-level netlist corresponding to the target combinational logic block, and construct a directed topology graph using the logic gates, input nodes, output nodes and constant nodes in the target combinational logic block as nodes and the connections between nodes as edges. Assign initial features related to circuit vulnerability to each node; The directed topological graph with assigned features is converted into an undirected graph to obtain the soft error information graph.

4. The logic circuit vulnerability estimation method combining conditional distribution and graph neural network as described in claim 3, characterized in that, The initial characteristics include the node type, signal probability, and logic shielding capability.

5. The logic circuit vulnerability estimation method combining conditional distribution and graph neural network according to claim 1, characterized in that, The neighborhood aggregation mechanism includes: Node In the The layer's own characteristics multiplied by a coefficient and with the node All neighboring nodes in the 1st The features of the layers are summed and aggregated. Input the aggregation result into the first... In a multilayer perceptron of a layered graph isomorphic network model, the output node is... In the Layer node representation; This is the layer index for a graph isomorphic network model. For the first Layer diagrams utilize the learnable parameters of the network model.

6. The vulnerability estimation method for logic circuits combining conditional distribution and graph neural networks according to claim 1, characterized in that, The step of inputting the graph representation into a multilayer perceptron to predict and obtain a predicted distribution includes: The graph representation is input into a multilayer perceptron, which outputs the vulnerability condition distribution of the target combinational logic block. The vulnerability condition distribution is a histogram density, which includes the predicted probability that the vulnerability of the target combinational logic block falls into each sub-interval of the [0,1] interval.

7. The logic circuit vulnerability estimation method combining conditional distribution and graph neural network according to claim 1, characterized in that, The calculation of the mean of circuit vulnerability in the predicted distribution using the predicted distribution includes: Divide the interval [0,1] evenly into For each sub-interval, the estimated value of the circuit vulnerability is calculated using the following formula: ， in, This represents the mean of circuit vulnerability in the predicted distribution. For the first The center value of each sub-interval The vulnerability of the target logic block falls into the histogram. The probability of each sub-interval.

8. The vulnerability estimation method for logic circuits combining conditional distribution and graph neural networks according to claim 1, characterized in that, The training method for the graph neural network model includes: A truncated Gaussian distribution is constructed centered on the actual vulnerability value of the target combinational logic circuit as the target distribution. The vulnerability condition distribution output by the graph neural network model is used as the prediction distribution. The graph neural network model is updated using the KL divergence between the target distribution and the predicted distribution as the loss function.

9. The vulnerability estimation method for logic circuits combining conditional distribution and graph neural networks according to claim 8, characterized in that, The loss function expression used to train the graph neural network model is: ， in, Represents the target distribution and predicted distribution KL divergence between them For target distribution and predicted distribution Cross-entropy between For target distribution Cross-entropy.

10. The logic circuit vulnerability estimation method combining conditional distribution and graph neural network according to claim 8, characterized in that, The expression for the target distribution is: ， in, For position The probability density value at that location. The vulnerability value is assigned to a point on the histogram interval. To truncate the standard deviation of the Gaussian distribution, The mean of a Gaussian distribution, and intermediate variables. , Represents the error function. and These are the lower and upper bounds of the cutoff interval of the truncated Gaussian distribution, respectively.

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