High isolation zero delay USB to RS485 isolation serial communication module

Abstract

The application discloses a high-isolation zero-delay USB-to-RS485 isolated serial communication module, and particularly relates to the field of industrial serial communication signal conversion equipment, which comprises a PCB, a USB-A sinking plate seat J1, a USB-to-serial communication chip U4, a signal isolation chip U3, an RS485 transceiver U2, a P3.5 press-type wiring terminal J2 and an RS485 port protection matching circuit. USB differential signals connected to the USB-A sinking plate seat J1 are converted into RXD1, TXD1 and TXEN1 through an MS3020, and then are isolated and transmitted into RXD_TTL, TXD_TTL and TXEN by an NIRSP31V. The TXEN is directly used to control the RE pin and the DE pin of a UM13088. Meanwhile, a protection matching circuit is arranged on the side of RS485-A and RS485-B ports, so that data conversion, hardware transceiving switching and port protection under the condition of isolation between the USB side and the RS485 side are realized.

Description

Technical Field

[0001] This invention relates to the field of industrial serial communication signal conversion equipment technology, and more specifically, to a high-isolation, zero-delay USB to RS485 isolated serial communication module. Background Technology

[0002] In the connection of equipment such as industrial automation control, power data acquisition, CNC equipment, building control, and access control, the host computer side usually uses a USB interface to complete data interaction and bus power supply, while the field device side mostly uses an RS485 differential bus to achieve long-distance, multi-node, half-duplex communication. With the increasing deployment of edge computing devices in industrial fields, field controllers, acquisition terminals, and edge computing gateways need to receive device data and issue control commands through local communication interfaces. Therefore, USB to RS485 conversion modules are used to connect the host computer, edge computing gateway, and RS485 fieldbus. Existing USB to RS485 conversion modules generally have a USB to serial port chip after the USB interface to convert the USB differential signal into TTL serial port transmit and receive signals, and then use an RS485 transceiver to convert the TTL signal into RS485-A and RS485-B differential signal output. This type of structure can meet the basic interface conversion requirements, but its circuit design usually focuses on signal format conversion. The electrical isolation between the low-voltage circuit on the USB side and the industrial line on the RS485 side, the discharge path of the RS485 port for static electricity and surge, and the hardware switching relationship of half-duplex transmission and reception are not designed as a coordinating communication link. During field use, the RS485 port needs to be connected to an external communication cable via a terminal block and connected to the acquisition terminal, controller, execution device, or other nodes in the control cabinet. The USB end is directly connected to the host computer or edge computing device port, and the module's operating power is also provided by the USB bus. Since the RS485 line side is directly related to the field equipment, cables, and grounding environment, electrostatic pulses, surge voltages, common-mode interference, and ground potential differences will preferentially affect RS485-A, RS485-B, and their reference ground. If the USB side and RS485 side are connected with a direct common ground or insufficient isolation, the above interference will enter the USB to serial port chip side along the differential signal loop, transceiver power supply loop, or ground loop, which will manifest as conversion chip reset, USB port enumeration abnormality, serial communication interruption, data frame loss, or malfunction of field equipment. For edge computing scenarios that require continuous acquisition of field data and local processing, the above abnormalities will also cause discontinuous data acquisition on the edge side and unstable control command response, affecting the reliable operation of the field communication link. On the other hand, when the RS485 bus uses half-duplex communication, the same pair of differential lines undertakes both transmission and reception. The transceiver needs to switch between transmit drive state and receive listener state through the DE and RE control terminals. If the existing conversion module controls the transmission and reception direction through software delay, main control program judgment, or external control pins, the switching timing will be affected by the program execution cycle, baud rate, data frame length, and bus response time. When the communication rate increases or the response interval of field devices shortens, the delayed release of transmit enable will prolong the bus occupation time, and the untimely activation of receive enable will cause the loss of the leading edge of the returned data. If the delay is increased to avoid frame loss, the bus interaction efficiency will be reduced. Therefore, half-duplex transceiver switching cannot be treated as an auxiliary control action, but needs to form a defined hardware connection relationship with the transceiver enable signal output by the USB to serial port, the isolation transmission path, and the RS485 transceiver control terminal. Therefore, the technical problem to be solved by this application is: how to enable the USB side and the RS485 side to complete data transmission through isolated TTL transmit and receive signals and transmit and receive enable signals in the USB to RS485 isolated serial communication module, so as to avoid the backflow of static electricity, surge and common mode interference from the RS485 field port to the USB side, and enable the RS485 half-duplex transceiver to switch the transmit and receive states in a timely manner according to the isolated hardware transmit and receive enable signals, so as to meet the requirements of isolation security, port protection capability and transmit and receive stability in industrial field and edge computing device access scenarios. Summary of the Invention

[0003] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide a high-isolation, zero-latency USB-to-RS485 isolated serial communication module. This module converts the USB differential signal connected to the USB-A socket J1 into RXD1, TXD1, and TXEN1 via an MS3020. Then, an NIRSP31V isolates and transmits RXD1, TXD1, and TXEN1 as RXD_TTL, TXD_TTL, and TXEN. TXEN is used to directly control the RE and DE pins of the UM13088. Simultaneously, protection matching circuits are set on the RS485-A and RS485-B port sides to achieve data conversion, hardware transmit / receive switching, and port protection under isolated conditions between the USB and RS485 sides, thereby solving the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a high-isolation, zero-delay USB to RS485 isolated serial communication module, comprising a PCB board, a USB-A recessed mounting base J1, a USB to serial communication chip U4, a signal isolation chip U3, an RS485 transceiver U2, a P3.5 push-button terminal J2, and an RS485 port protection matching circuit. The USB-A recessed mounting bracket J1 is located at one end of the PCB board. The VCC pin of the USB-A recessed mounting bracket J1 is connected to VBUS, the D+ pin is connected to the USB to serial communication chip U4 through DP2_P, the D- pin is connected to the USB to serial communication chip U4 through DM2_N, and the GND pin is connected to the USB side ground GND. The USB to serial communication chip U4 is an MS3020 chip. The USB to serial communication chip U4 is connected to RXD1 through the RXD / GPIO11 pin, to TXD1 through the TXD / GPIO8 pin, and to TXEN1 through the GPIO17 / TXEN pin. The signal isolation chip U3 is an NIRSP31V chip. The R pin of the signal isolation chip U3 is connected to RXD1, the D pin is connected to TXD1, and the DE pin is connected to TXEN1. RXD1, TXD1, and TXEN1 are isolated and transmitted as RXD_TTL, TXD_TTL, and TXEN, respectively. The RS485 transceiver U2 is a UM13088 chip. The RO pin of the RS485 transceiver U2 is connected to RXD_TTL, the DI pin is connected to TXD_TTL, the RE pin and the DE pin are both connected to TXEN, the A pin is connected to RS485-A, and the B pin is connected to RS485-B. The P3.5 push-button terminal J2 is located at the other end of the PCB board. The first terminal of the P3.5 push-button terminal J2 is connected to RS485-A, and the second terminal is connected to RS485-B. The RS485 port protection matching circuit is connected between RS485-A and RS485-B, and between RS485-A, RS485-B and the isolation ground GND2.

[0005] In a preferred embodiment, the USB-A socket J1 includes a VCC pin, a D- pin, a D+ pin, and a GND pin; the VCC pin is connected to VBUS via L1, where L1 is an FB600 ferrite bead; the D+ pin forms DP2_P, the D- pin forms DM2_N, and the GND pin is connected to the USB-side ground GND. The input side of the USB-A recessed mounting bracket J1 is equipped with D12, C6, C21, and C22. D12 is an SMFJ28A-E3 / 52 protection device, and D12 is located in the input side protection branch of the USB-A recessed mounting bracket J1. C6 is a 10μF capacitor, and C6 is connected to the power supply filtering branch between VBUS and USB side ground GND. C21 and C22 are both 10pF capacitors, and C21 and C22 are connected to the USB differential signal filtering branch where DP2_P and DM2_N are located.

[0006] In a preferred embodiment, the USB to serial communication chip U4 is model MS3020; the USBDP pin of the USB to serial communication chip U4 is connected to DP2_P, the USBDM pin is connected to DM2_N, the VDD5V pin is connected to VBUS, the VLDO33 pin is connected to the LVDO33 network, and the VSS pin is connected to USB side ground GND. The RXD / GPIO11 pin of the USB to serial communication chip U4 is connected to RXD1, the TXD / GPIO8 pin is connected to TXD1, and the GPIO17 / TXEN pin is connected to TXEN1. This enables the USB to serial communication chip U4 to convert the USB differential signals input via DP2_P and DM2_N into TTL serial port transmit / receive signals corresponding to RXD1 and TXD1, and output the transmit / receive enable signal corresponding to TXEN1. The RSTN pin of the USB-to-serial communication chip U4 is connected to the reset configuration branch, which includes R6, a 100K resistor connected to the reset configuration node where the RSTN pin is located; the GPIO1 / SPISCLK pin of the USB-to-serial communication chip U4 is connected to the RX-LED, and the GPIO0 / SPICS pin is connected to the TX-LED.

[0007] In a preferred embodiment, the signal isolation chip U3 is of model NIRSP31V; the signal isolation chip U3 includes R pin, D pin, DE pin and GND1 pin located on the front side of isolation, and 17 pin R2, 15 pin D2, 16 pin DE2, VISO pin and GND2 pin located on the rear side of isolation; The signal isolation chip U3 has its R pin connected to RXD1, D pin connected to TXD1, DE pin connected to TXEN1, and GND1 pin connected to USB-side ground GND; the signal isolation chip U3 has its 17th pin R2 connected to RXD_TTL, its 15th pin D2 connected to TXD_TTL, its 16th pin DE2 connected to TXEN, its VISO pin connected to 5V_VISO, and its GND2 pin connected to isolation-side ground GND2. The signal isolation chip U3 isolates and transmits RXD1 as RXD_TTL through the isolation channel between pin R and pin 17 R2, isolates and transmits TXD1 as TXD_TTL through the isolation channel between pin D and pin 15 D2, and isolates and transmits TXEN1 as TXEN through the isolation channel between pin DE and pin 16 DE2. This makes RXD1, TXD1, and TXEN1 located on the front isolation side corresponding to USB-side ground GND, and makes RXD_TTL, TXD_TTL, and TXEN located on the back isolation side corresponding to GND2.

[0008] In a preferred embodiment, C13, C14 and C18 are provided on the power supply side before isolation of the signal isolation chip U3, and C15, C16 and C17 are provided on the power supply side after isolation of the signal isolation chip U3; C13 and C16 are both 10μF capacitors, and C14, C15, C17 and C18 are all 0.1μF capacitors. C13, C14, and C18 are connected to the pre-isolation power supply filter branch corresponding to the USB side ground GND, and are used to store energy and perform high-frequency filtering on the pre-isolation power supply of the signal isolation chip U3; C15, C16, and C17 are connected to the post-isolation power supply filter branch corresponding to the post-isolation ground GND2, and are used to store energy and perform high-frequency filtering on the post-isolation power supply where 5V_VISO is located. The signal isolation chip U3 is also connected to R3 and R10, both of which are 0Ω resistors, and are connected to the isolation back-side connection branch of the signal isolation chip U3.

[0009] In a preferred embodiment, the RS485 transceiver U2 is model UM13088; the RS485 transceiver U2 includes RO pin, RE pin, DE pin, DI pin, GND pin, A pin, B pin and VCC pin; The RS485 transceiver U2 has its VCC pin connected to 5V_VISO, its GND pin connected to the isolated ground GND2, its RO pin connected to RXD_TTL, its DI pin connected to TXD_TTL, its RE pin and DE pin both connected to TXEN, its A pin connected to RS485-A, and its B pin connected to RS485-B. The TXEN signal is formed by isolating TXEN1 with signal isolation chip U3 and is simultaneously input to the RE and DE pins of RS485 transceiver U2 as the isolated hardware transmit / receive enable signal. When RS485 transceiver U2 is in transmit mode, TXD_TTL is input to RS485 transceiver U2 via DI pin and output as RS485-A and RS485-B differential signals via A and B pins. When RS485 transceiver U2 is in receive mode, RS485-A and RS485-B are input to RS485 transceiver U2 via A and B pins and output as RXD_TTL via RO pin. The signal side of the RS485 transceiver U2 is equipped with resistors R1, R2, R4, and R5, all of which are 4.7K resistors, used to form the level bias of the relevant signal terminals and the RS485 differential terminals of the RS485 transceiver U2; the power supply side of the RS485 transceiver U2 is equipped with capacitor C5, which is a 0.1μF capacitor connected to the decoupling branch between 5V_VISO and the isolation ground GND2.

[0010] In a preferred embodiment, the RS485 port protection matching circuit includes D1, D2, D8, D9, R12, C19, and C20; D1 and D2 are both SMBJ6.5CA transient suppression devices, D8 and D9 are both GDT gas discharge tubes, R12 is a 120Ω terminating matching resistor, and C19 and C20 are both 100pF capacitors. D1 is connected to the transient voltage suppression branch where RS485-A is located, and D2 is connected to the transient voltage suppression branch where RS485-B is located; D8 is connected to the surge discharge branch between RS485-A and the isolation ground GND2, and D9 is connected to the surge discharge branch between RS485-B and the isolation ground GND2. R12 is connected between RS485-A and RS485-B to form an RS485 differential termination match; C19 is connected between RS485-A and GND2 (the ground after isolation), and C20 is connected between RS485-B and GND2 (the ground after isolation) to filter high-frequency interference on the RS485 port side; RS485-A and RS485-B are connected to P3.5 push-button terminal J2 after passing through the RS485 port protection matching circuit.

[0011] In a preferred embodiment, a status indicator circuit is further included, which includes D3, D4, D5, R7, R8 and R9; D3 is a yellow receive indicator, D4 is a green transmit indicator, D5 is a blue power-on indicator, R7 and R8 are both 499Ω resistors, and R9 is a 1KΩ resistor. D3 is connected to the receive status indication branch of RX-LED via R7, and RX-LED is connected to the GPIO1 / SPISCLK pin of USB to serial communication chip U4; D4 is connected to the transmit status indication branch of TX-LED via R8, and TX-LED is connected to the GPIO0 / SPICS pin of USB to serial communication chip U4; D5 is connected to the power-on status indication branch between VBUS and USB side ground GND via R9, and is used to display the power-on status of USB to RS485 isolated serial communication module.

[0012] In a preferred embodiment, the USB-to-serial communication chip U4 outputs TXEN1 via the GPIO17 / TXEN pin, which changes according to the transmission state of TXD1. When the USB-to-serial communication chip U4 outputs the transmission data corresponding to TXD1 via the TXD / GPIO8 pin, the GPIO17 / TXEN pin outputs TXEN1 in the transmission enable state. TXEN1 is isolated by the signal isolation chip U3 to form TXEN. TXEN is simultaneously input to the RE and DE pins of the RS485 transceiver U2, so that the RS485 transceiver U2 maintains the transmission state during the TXD_TTL input DI pin. When the transmission data corresponding to TXD1 is output, the GPIO17 / TXEN pin switches TXEN1 to the receive enable state. TXEN is synchronously switched via the signal isolation chip U3, causing the RS485 transceiver U2 to exit the transmission state and enter the receiving state. The TXEN1, TXEN, RE, and DE pins form a hardware transmit / receive enable link from the USB to serial communication chip U4 to the RS485 transceiver U2. This hardware transmit / receive enable link does not pass through the delay control branch and external direction control branch formed by the independent main control chip, so that the transmit and receive states of the RS485 transceiver U2 are hardware switched according to the transmit state of TXD1.

[0013] In a preferred embodiment, when RS485-A and RS485-B are subjected to external transient interference, the transient voltage suppression branch containing D1 and D2 clamps the transient voltage on RS485-A and RS485-B, the surge discharge branch containing D8 and D9 discharges the surge energy on RS485-A and RS485-B to the isolation ground GND2, and the high-frequency filtering branch containing C19 and C20 bypasses the high-frequency interference components on RS485-A and RS485-B to the isolation ground GND2. R12 is connected between RS485-A and RS485-B. During the transient voltage suppression, surge discharge, and high-frequency filtering processes performed by D1, D2, D8, D9, C19, and C20, it maintains the differential termination matching between RS485-A and RS485-B, so that when RS485-A and RS485-B are connected to an external RS485 line via the P3.5 push-button terminal J2, port protection and differential signal matching are simultaneously achieved.

[0014] The technical effects and advantages of this invention are as follows: 1. RXD1, TXD1, and TXEN1 are output through U4, and then isolated and transmitted as RXD_TTL, TXD_TTL, and TXEN by U3 respectively. This ensures that the data reception signal, data transmission signal, and transmit / receive enable signal are transmitted across the isolation boundary. At the same time, GND is used as the reference ground on the USB side, and GND2 is used as the reference ground on the RS485 side. This makes it difficult for static electricity, surge, and common-mode interference on the RS485 side to enter the USB side along the data path or ground loop. After isolation, TXEN can still directly control the RE and DE pins of U2. Therefore, while achieving electrical isolation between the USB side and the RS485 side, the hardware control relationship of the RS485 transmit / receive direction can still be maintained, thus balancing isolation safety and half-duplex transmit / receive stability. 2. TXEN is formed by isolating TXEN1 through U3, and TXEN is directly connected to the RE and DE pins of U2, so that the transmit and receive states of RS485 transceiver U2 can be switched by hardware according to the corresponding transmit state of TXD1. Compared with the transmit and receive switching by software delay, main control program judgment or external direction control pin, it can reduce the loss of data leading edge caused by the lag of transmit enable release and the untimely opening of receive enable, and at the same time avoid the reduction of bus interaction efficiency due to manually setting the delay time. 3. The RS485 port protection matching circuit is composed of D1, D2, D8, D9, C19, C20 and R12. Transient voltage clamping, surge discharge, high frequency filtering and differential termination matching are completed in the same RS485 port. When the external line is connected to the industrial site, it can relatively reduce the impact of static electricity, surge, high frequency interference and signal reflection on the communication link. 4. The USB input side protection and filtering structure is formed by L1, D12, C6, C21 and C22, so that the USB power supply and USB differential signal entering U4 are protected and filtered before USB to TTL conversion. This can relatively reduce the impact of power supply fluctuations and high-frequency interference on the stability of USB identification and serial communication. 5. By using D3, D4, and D5 to correspond to the module's receiving status, transmitting status, and power-on status respectively, the module's operating status can be directly observed on-site, which is beneficial for quickly determining the power supply and communication status and reducing the difficulty of on-site maintenance and fault location. Attached Figure Description

[0015] Figure 1 This is the circuit schematic diagram of the present invention.

[0016] Figure 2 This is a schematic diagram of the PCB layout of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Refer to the instruction manual appendix Figure 1-2 The present invention provides a high-isolation, zero-delay USB to RS485 isolated serial communication module, comprising a PCB board, a USB-A recessed mounting base J1, a USB to serial communication chip U4, a signal isolation chip U3, an RS485 transceiver U2, a P3.5 push-button terminal J2, an RS485 port protection matching circuit, and a status indication circuit. The USB-A recessed mounting plate J1 is located at one end of the PCB board, and the P3.5 push-button terminal block J2 is located at the other end of the PCB board. The USB to serial communication chip U4, the signal isolation chip U3, and the RS485 transceiver U2 are arranged between the USB-A recessed mounting plate J1 and the P3.5 push-button terminal block J2, so that the USB side signal enters and passes through the USB to serial port, signal isolation, RS485 transceiver and port protection matching in sequence before being output to the external RS485 line. The purpose of the above arrangement in this embodiment is to form a clear signal transmission path between the USB-side low-voltage interface and the RS485-side industrial field interface on the same PCB board, and to separate different electrical areas. The USB-A recessed mounting bracket J1 is used to connect the USB interface of the host computer or edge computing device, and the P3.5 push-button terminal block J2 is used to connect the external RS485 bus. If the USB side and the RS485 side are directly connected through a common conversion circuit, the electrostatic pulses, surge voltages and common-mode interference generated on the RS485 line side can easily be transmitted to the USB side through the signal line or ground line, causing the USB to serial communication chip U4 to reset, the USB port to malfunction or the data communication to be interrupted. In this embodiment, the USB-side ground GND and the isolated ground GND2 are set separately through the signal isolation chip U3, and the external interference is first discharged and suppressed on the RS485 port side through the RS485 port protection matching circuit, thereby enabling the module to adapt to the long-distance communication environment in the industrial field.

[0019] Description of USB-A recessed mounting J1 and USB input-side protection and filtering structure: The USB-A recessed mounting bracket J1 includes a VCC pin, a D- pin, a D+ pin, and a GND pin. The VCC pin of the USB-A recessed mounting bracket J1 is connected to VBUS via L1, which is an FB600 ferrite bead. The D+ pin of the USB-A recessed mounting bracket J1 forms DP2_P, the D- pin of the USB-A recessed mounting bracket J1 forms DM2_N, and the GND pin of the USB-A recessed mounting bracket J1 is connected to the USB-side ground GND. DP2_P and DM2_N serve as USB differential data lines, VBUS serves as the USB power input, and GND serves as the USB-side ground potential reference. L1 is positioned between the VCC pin and VBUS of the USB-A socket J1. Its purpose is not for electrical isolation, but to suppress high-frequency interference in the USB power supply path. USB interface plugging and unplugging, host computer power supply ripple, and cable coupling interference can all be superimposed on the VBUS path. If filtering is not performed on the USB input side, the VDD5V pin and reset configuration node of the subsequent USB to serial communication chip U4 are easily affected by power supply fluctuations, which may manifest as chip enumeration abnormalities, unstable serial communication, or uncertain module power-on status. L1, together with the subsequent capacitor, can make the power supply path into the module more stable. The input side of the USB-A recessed mounting bracket J1 is equipped with D12, C6, C21, and C22. D12 is an SMFJ28A-E3 / 52 protection device, which is located in the input side protection branch of the USB-A recessed mounting bracket J1 to suppress transient overvoltages on the USB input side. C6 is a 10μF capacitor, which is connected to the power supply filtering branch between VBUS and USB-side ground GND to store and smooth the USB power supply. C21 and C22 are both 10pF capacitors, which are connected to the USB differential signal filtering branch where DP2_P and DM2_N are located to suppress high-frequency spike interference on the USB differential line. The significance of the aforementioned USB input-side protection and filtering structure is to provide preliminary protection for the power supply and differential signals at the USB input end, ensuring that the power supply and data lines entering the USB-to-serial communication chip U4 are in a relatively clean electrical environment. For example, if the USB cable is laid near an industrial control cabinet, the cable may be susceptible to high-frequency interference. If C21 and C22 are missing, spikes on DP2_P and DM2_N may directly enter the USBDP and USBDM pins of U4, causing abnormal USB data recognition. If C6 is missing, VBUS transient fluctuations will directly affect the power supply side of U4, causing the module to reset or disconnect when plugged in or unplugged or when the load changes.

[0020] Explanation of the USB-to-serial communication chip U4 and the signal generation on the TTL side: The USB-to-serial communication chip U4 is model MS3020. The USBDP pin of the USB-to-serial communication chip U4 is connected to DP2_P, the USBDM pin is connected to DM2_N, the VDD5V pin is connected to VBUS, the VLDO33 pin is connected to the LVDO33 network, and the VSS pin is connected to USB-side ground (GND). The USB-to-serial communication chip U4 receives the USB differential signal input from the USB-A socket J1 through the USBDP and USBDM pins, receives USB power through the VDD5V pin, and completes the conversion from USB to TTL serial port signal with USB-side ground (GND) as the reference ground. The USB-to-serial communication chip U4 connects the RXD / GPIO11 pin to RXD1, the TXD / GPIO8 pin to TXD1, and the GPIO17 / TXEN pin to TXEN1. RXD1 and TXD1 correspond to TTL serial port transmit / receive signals, while TXEN1 corresponds to transmit / receive enable signals. It's crucial to distinguish the functions of these three signals: RXD1 receives data returned from the RS485 side and transmitted after isolation; TXD1 outputs data to be sent to the RS485 bus; and TXEN1 is not ordinary serial port data but an enable signal controlling the RS485 half-duplex transmit / receive direction. Outputting TXEN1 as an independent signal is fundamental to implementing subsequent hardware transmit / receive switching. The RSTN pin of the USB-to-serial communication chip U4 is connected to the reset configuration branch. The reset configuration branch includes R6, which is a 100K resistor connected to the reset configuration node where the RSTN pin is located. The purpose of the reset configuration branch is to provide a definite reset state for U4, preventing U4 from entering an abnormal state due to the reset pin being floating or having an uncertain level at the moment of power-on. If the RSTN pin is not stably configured, USB enumeration may fail, the serial port may not respond, or the TXEN1 output state may be abnormal at power-on, which will affect the working state of the subsequent RS485 transceiver U2. The GPIO1 / SPISCLK pins of the USB-to-serial communication chip U4 are connected to the RX-LED, and the GPIO0 / SPICS pins are connected to the TX-LED. The purpose of this connection is to bring out the transmit and receive status of the U4's internal or related outputs to the status indicator circuit, so that the module can reflect the receiving and transmitting actions through the indicator lights when it is working. For field maintenance, without this indicator structure, the staff can only judge the communication status through the host computer software or external instruments, which is less efficient in diagnosing line faults and equipment faults.

[0021] Explanation of signal isolation chip U3 and the signal relationship before and after isolation: The signal isolation chip U3 is model NIRSP31V. Signal isolation chip U3 includes R, D, DE, and GND1 pins on the front side of the isolation layer, and pins 17 (R2), 15 (D2), 16 (DE2), VISO, and GND2 pins on the rear side of the isolation layer. The R pin of signal isolation chip U3 is connected to RXD1, the D pin to TXD1, the DE pin to TXEN1, and the GND1 pin to USB-side ground (GND). Pin 17 (R2) of signal isolation chip U3 is connected to RXD_TTL, pin 15 (D2) to TXD_TTL, pin 16 (DE2) to TXEN, the VISO pin to 5V_VISO, and the GND2 pin to the rear-side ground (GND2). Signal isolation chip U3 forms isolation transmission channels between RXD1 and RXD_TTL, between TXD1 and TXD_TTL, and between TXEN1 and TXEN. Specifically, in the receiving direction, RXD_TTL is transmitted as RXD1 through the isolation channel between pin 17 (R2) and pin R; in the transmitting direction, TXD1 is transmitted as TXD_TTL through the isolation channel between pin D and pin 15 (D2); and in the transmit / receive enable direction, TXEN1 is transmitted as TXEN through the isolation channel between pin DE and pin 16 (DE2). Through these three isolation transmission relationships, RXD1, TXD1, and TXEN1 are located on the front isolation side corresponding to USB ground GND, while RXD_TTL, TXD_TTL, and TXEN are located on the back isolation side corresponding to GND2. In this embodiment, TXEN1, RXD1, and TXD1 are sent together to the signal isolation chip U3 for isolation. This is crucial. If a conventional isolation design only isolates TXD and RXD, leaving the transmit / receive enable control signals on the USB side, the RE and DE pins of the RS485 transceiver U2 cannot be directly and definitively controlled by hardware after isolation. Adding a microcontroller, optocoupler control branch, or manual direction control terminal would increase delay, wiring complexity, and state uncertainty. In this embodiment, TXEN1 is isolated by U3 to form TXEN, and then TXEN directly controls the RE and DE pins of U2. This ensures that the transmit / receive enable signals are associated with the data transmission state on the USB side, while also being able to directly control the RS485 transceiver U2 after isolation, thus simultaneously meeting the requirements of isolation security and half-duplex transmit / receive control. Furthermore, if only TXD1 and RXD1 are isolated through U3, without passing TXEN1 as TXEN, then the DE and RE pins of the RS485 transceiver U2 need to have a separate control source. If this control source comes from the USB side, it will break the isolation boundary; if it comes from an independent host control chip, it will introduce program judgment and control delays; if it comes from a manual jumper or an external direction pin, it is easy to cause a delay in transmission release or untimely reception activation during high-speed communication. This embodiment avoids the above problems by passing TXEN1 to TXEN through isolation.

[0022] Instructions for the isolation power supply filtering and configuration connection of signal isolation chip U3: The power supply side of the signal isolation chip U3 before isolation is equipped with capacitors C13, C14, and C18, and the power supply side after isolation is equipped with capacitors C15, C16, and C17. C13 and C16 are both 10μF capacitors, and C14, C15, C17, and C18 are all 0.1μF capacitors. C13, C14, and C18 are connected to the power supply filtering branch corresponding to the USB side ground GND, which is used to store energy and perform high-frequency filtering on the power supply before isolation of the signal isolation chip U3. C15, C16, and C17 are connected to the power supply filtering branch corresponding to the post-isolation side ground GND2, which is used to store energy and perform high-frequency filtering on the post-isolation power supply where 5V_VISO is located. The purpose of this power supply filtering structure is to ensure that the power supply on both sides of U3 has a stable transient current supply capability. When the signal isolation chip transmits RXD1, TXD1, and TXEN1, both the front and rear sides of the isolation chip will generate switching actions and transient current requirements. If the 5V_VISO filtering on the rear side of the isolation is insufficient, edge jitter or level glitches may occur in TXEN, TXD_TTL, or RXD_TTL. If the filtering on the front side of the isolation is insufficient, the reception of the output signal from U3 to U4 may be affected by power supply noise. The 10μF capacitor is used for energy storage and low-frequency power fluctuation suppression, and the 0.1μF capacitor is used for high-frequency decoupling. The combination of the two makes the isolation transmission process more stable. The signal isolation chip U3 is also connected to R3 and R10, both of which are 0Ω resistors and are connected to the isolation back-side configuration connection branch of the signal isolation chip U3. In this embodiment, the 0Ω resistor is used to form configuration connection and debugging connection points, so that the relevant network on the isolation back side has a definite connection relationship in PCB routing and product debugging. This structure does not change the main signal transmission principle of the signal isolation chip U3, but it is beneficial to PCB routing, testing and configuration management.

[0023] Instructions for RS485 transceiver U2 and TTL to RS485 differential converter: The RS485 transceiver U2 is model UM13088. The RS485 transceiver U2 includes RO, RE, DE, DI, GND, A, B, and VCC pins. The VCC pin is connected to 5V_VISO, the GND pin is connected to the isolated ground GND2, the RO pin is connected to RXD_TTL, the DI pin is connected to TXD_TTL, the RE and DE pins are both connected to TXEN, the A pin is connected to RS485-A, and the B pin is connected to RS485-B. The function of U2 is to convert between TTL single-ended signals and RS485 differential signals. In the transmitting direction, TXD_TTL is input to RS485 transceiver U2 via the DI pin, and U2 converts it into a differential output between pins A and B, forming RS485-A and RS485-B. In the receiving direction, the external RS485 line enters pins A and B of U2 via RS485-A and RS485-B input through J2. U2 converts the differential signal into RXD_TTL output via the RO pin, and then transmits it back to the USB side through isolation via U3. This conversion relationship enables USB devices to perform bidirectional data interaction with RS485 bus devices through a TTL serial port link. The VCC pin of RS485 transceiver U2 is connected to 5V_VISO, and the GND pin is connected to the isolation ground GND2. This ensures that U2 is completely under the power supply and reference of the isolation ground. When the RS485 port is interfered with, the interference mainly affects the isolation ground and will not directly flow back to the USB side where U4 is located through the power supply ground of U2. If the ground of U2 and the GND of U4 are directly shared, the ground potential difference on the RS485 field side may form a return path through the ground wire, which may damage the security and communication stability of the USB side device. On the signal side of RS485 transceiver U2, resistors R1, R2, R4, and R5 are provided. Each of R1, R2, R4, and R5 is a 4.7K resistor, used to form the level bias of the relevant signal terminals and the RS485 differential terminals of RS485 transceiver U2. The purpose of the level bias is to provide a definite default level for the relevant signal lines, avoiding uncertain states when the bus is idle or the input is floating. On the power supply side of RS485 transceiver U2, capacitor C5 is provided. C5 is a 0.1μF capacitor connected to the decoupling branch between 5V_VISO and the isolation ground GND2, used to suppress high-frequency power supply disturbances generated or received by U2 during operation.

[0024] Explanation of hardware transceiver enabled links and zero-latency transceiver handover: TXEN is formed by isolating TXEN1 with signal isolation chip U3, and is simultaneously input to the RE and DE pins of RS485 transceiver U2 as the isolated hardware transmit / receive enable signal. TXEN1, output by USB to serial communication chip U4 through GPIO17 / TXEN pin, changes according to the transmit state of TXD1. When USB to serial communication chip U4 outputs the transmit data corresponding to TXD1 through TXD / GPIO8 pin, GPIO17 / TXEN pin outputs TXEN1 in the transmit enable state. TXEN1 is isolated by signal isolation chip U3 to form TXEN, which is simultaneously input to the RE and DE pins of RS485 transceiver U2, keeping RS485 transceiver U2 in the transmit state during the TXD_TTL input DI pin period. When the transmit data corresponding to TXD1 ends, GPIO17 / TXEN pin switches TXEN1 to the receive enable state. TXEN is synchronously switched by signal isolation chip U3, causing RS485 transceiver U2 to exit the transmit state and enter the receive state. The aforementioned hardware transceiver enable link consists of the GPIO17 / TXEN pins of the USB-to-serial communication chip U4, TXEN1, the signal isolation chip U3, TXEN, and the RE and DE pins of the RS485 transceiver U2. This link does not pass through the delay control branch formed by the independent main control chip, nor does it pass through the external direction control branch. Its purpose is to establish the RS485 half-duplex transceiver direction switching on the hardware transceiver enable signal output by U4, so that the transmitting and receiving states can be hardware switched according to the TXD1 transmitting state. In addition, in this embodiment, "zero delay" does not mean that there is no physical propagation time in the circuit, but rather that the RS485 transmit and receive status is not controlled by microcontroller program delay, software waiting time, or manual direction switching. In conventional solutions, if the RS485 direction is controlled by software delay, a manually set delay time is usually required after transmission before switching to the receiving state. If the delay is too short, the last part of the data will not be completely transmitted before the transmission driver is shut down. If the delay is too long, the RS485 bus will be occupied and the response leading edge of the external device will be missed. In this embodiment, TXEN1 controls the RE and DE pins of U2 directly based on the transmission status change of TXD1 and after isolation by U3, which can reduce the problems of transmission release lag and untimely reception start. For example, when the host computer sends a query frame to the RS485 device, TXD1 outputs the query frame data, TXEN1 enters the transmit enable state, and U2 maintains the transmit state and converts TXD_TTL to RS485-A and RS485-B differential output. After the query frame ends, TXEN1 switches to the receive enable state, TXEN switches synchronously, and U2 enters the receive state to receive the response frame returned by the RS485 device. If this process is controlled by software delay, the delay time needs to be manually set according to the baud rate and frame length. Improper setting can easily lead to frame loss. This embodiment reduces this kind of uncertainty by enabling the hardware transceiver link.

[0025] Description of RS485 port protection matching circuit: The RS485 port protection matching circuit includes D1, D2, D8, D9, R12, C19, and C20; D1 and D2 are both SMBJ6.5CA transient suppression devices, D8 and D9 are both GDT gas discharge tubes, R12 is a 120Ω terminating matching resistor, and C19 and C20 are both 100pF capacitors; D1 is connected to the transient voltage suppression branch where RS485-A is located, and D2 is connected to the transient voltage suppression branch where RS485-B is located; D8 is connected to the surge discharge branch between RS485-A and the isolation ground GND2, and D9 is connected to the surge discharge branch between RS485-B and the isolation ground GND2; R12 is connected between RS485-A and RS485-B; C19 is connected between RS485-A and the isolation ground GND2, and C20 is connected between RS485-B and the isolation ground GND2; The transient voltage suppression branch containing D1 and D2 is used to clamp transient voltages on RS485-A and RS485-B. After the RS485 line is connected to external equipment and long lines, electrostatic discharge, insertion / removal spikes or transient overvoltages will first act on RS485-A and RS485-B. D1 and D2 are used to limit the transient voltage to the range that the subsequent circuit can withstand when the voltage exceeds the device response conditions, so as to prevent the A and B pins of U2 from directly bearing excessive voltage. The surge discharge branch containing D8 and D9 is used to discharge the surge energy on RS485-A and RS485-B to the isolation ground GND2. The GDT gas discharge tube is suitable for handling high-energy surge discharge tasks. Its function is not to filter small high-frequency interference, but to provide a discharge channel when surge energy enters the port, reducing the impact of the surge on U2 and subsequent circuits. If the RS485 port only has a low-power clamping device and lacks a GDT discharge path, the clamping device is prone to overload or damage under high-energy surge impact. The high-frequency filtering branch containing C19 and C20 is used to bypass the high-frequency interference components on RS485-A and RS485-B to the isolated ground GND2. The RS485 bus transmits differential signals, and high-frequency interference in the industrial field may be superimposed on the differential lines and cause waveform edge glitches. C19 and C20 provide a bypass path for high-frequency components, which helps to reduce port high-frequency noise. The function of C19 and C20 is different from that of D8 and D9. D8 and D9 are for high-energy surges, while C19 and C20 are for high-frequency interference components. Together, they form the port's anti-interference capability. R12 is connected between RS485-A and RS485-B to maintain differential termination matching between them. RS485 lines are differential transmission lines; improper termination matching can cause waveform ringing, overshoot, or bit errors due to cable reflection. The significance of R12, along with D1, D2, D8, D9, C19, and C20, is as follows: the protection device limits external interference, the filtering device reduces high-frequency noise, and R12 maintains differential transmission termination matching. If only the protection device is used without R12, the port may have surge protection but insufficient waveform quality; if only R12 is used without the protection device, transmission matching exists but electrostatic discharge and surge protection are insufficient. This embodiment combines clamping, bleeding, filtering, and termination matching to ensure that the RS485 port simultaneously meets interference immunity and differential transmission requirements when connected to external lines. RS485-A and RS485-B are connected to P3.5 push-button terminal J2 after passing through the RS485 port protection matching circuit. The first terminal of P3.5 push-button terminal J2 is connected to RS485-A, and the second terminal is connected to RS485-B. After the external RS485 line is connected to J2, the external interference first acts on the port protection matching circuit, and then enters the A and B pins of U2, thereby reducing the direct impact of the external line on U2.

[0026] Description of the status indicator circuit: The status indicator circuit includes D3, D4, D5, R7, R8, and R9; D3 is a yellow receive indicator, D4 is a green transmit indicator, D5 is a blue power-on indicator, R7 and R8 are both 499Ω resistors, and R9 is a 1KΩ resistor; D3 is connected to the receive status indicator branch containing the RX-LED through R7, and the RX-LED is connected to the GPIO1 / SPISCLK pin of the USB to serial communication chip U4; D4 is connected to the transmit status indicator branch containing the TX-LED through R8, and the TX-LED is connected to the GPIO0 / SPICS pin of the USB to serial communication chip U4; D5 is connected to the power-on status indicator branch between VBUS and USB-side ground GND through R9. The purpose of the status indicator circuit is to provide observable operating status; D5 is used to indicate whether the module is being powered normally from the USB side; D3 is used to display the receiving status; D4 is used to display the transmitting status; R7, R8, and R9 are used as current-limiting resistors for the corresponding indicator lights to limit the current in the indicator light loop and prevent the indicator lights from being directly connected to the signal or power network, causing overcurrent; without the status indicator circuit, field personnel cannot intuitively see whether the module is powered on, transmitting, or receiving when communication is abnormal, and troubleshooting requires relying on host computer software, oscilloscopes, or bus analysis tools, resulting in low maintenance efficiency; It should be noted that R7 and R8 are 499Ω resistors used for current limiting of D3 and D4, and are not used for RS485 differential termination matching; RS485 differential termination matching is achieved by R12 connected between RS485-A and RS485-B; this distinction can prevent the status indicator resistor from being mistaken for the differential matching resistor, and also ensure that the device usage in the instruction manual, schematic diagram and PCB diagram are consistent.

[0027] Overall module operation process description: When the module is powered on, the host computer or edge computing device provides VBUS and USB differential signals to the module through the USB-A socket J1; VBUS enters the power supply side of the USB to serial communication chip U4 after passing through L1, C6 and related input protection filtering structures, and D5 displays the power-on status; DP2_P and DM2_N are input to the USBDP and USBDM pins of U4, and U4 converts the USB differential signal into TTL serial port transmit and receive signals corresponding to RXD1 and TXD1, and outputs the transmit and receive enable signal corresponding to TXEN1; When transmitting data, U4 outputs TXD1 through the TXD / GPIO8 pin and simultaneously outputs TXEN1, which is in the transmit enable state, through the GPIO17 / TXEN pin. TXD1 is isolated by U3 to form TXD_TTL, and TXEN1 is isolated by U3 to form TXEN. TXEN controls the RE and DE pins of U2, putting U2 in the transmit state. TXD_TTL is input through the DI pin of U2 and output as RS485-A and RS485-B differential signals through the A and B pins of U2. RS485-A and RS485-B are output from J2 to the external RS485 line after passing through the RS485 port protection matching circuit. When receiving data, external RS485 devices input differential signals to RS485-A and RS485-B via J2. These differential signals first pass through the RS485 port protection and matching circuit. External transient interference is clamped by D1 and D2, high-energy surges are discharged by D8 and D9, high-frequency interference is filtered by C19 and C20, and the differential lines are terminated and matched by R12. After protection and matching, RS485-A and RS485-B enter pins A and B of U2. U2 outputs RXD_TTL via pin RO. RXD_TTL is isolated by U3 and transmitted as RXD1 before returning to U4. Through this process, the module achieves data return from the RS485 side to the USB side. During the transmission and reception switching process, the TXEN1, TXEN, RE pins and DE pins form a hardware transmit and receive enable link; when the transmit data output corresponding to TXD1 ends, TXEN1 switches to the receive enable state, TXEN is synchronously switched via U3, and U2 exits the transmit state and enters the receive state; this process does not go through the delay control branch formed by the independent main control chip and the external direction control branch, so that the module can still complete the RS485 half-duplex transmit and receive direction switching under high isolation conditions.

[0028] Technical effects of this embodiment: This embodiment establishes an isolation transmission relationship between RXD1 and RXD_TTL, TXD1 and TXD_TTL, and TXEN1 and TXEN through U3, enabling the three signals of receiving data, transmitting data, and transmit / receive enable to be transmitted across the isolation boundaries. The significance of this structure is that the USB side and the RS485 side can maintain separate GND and GND2 settings, while the RS485 transceiver U2 can still obtain the isolated data and transmit / receive enable control. Compared with a structure that only isolates the data lines without isolating the transmit / receive enable signals, this embodiment avoids the need to set additional master control delay control or external direction control on the RS485 side, thereby improving the consistency of half-duplex switching. This embodiment forms a hardware transmit / receive enable link through the TXEN1, TXEN, RE, and DE pins, enabling the RS485 transceiver U2 to switch between transmit and receive states based on the transmit state of TXD1. This structure solves the problems of delayed transmit release, delayed receive response, and inaccurate software delay settings in half-duplex RS485 communication. The technical effect here is not simply to increase communication speed, but to maintain a direct hardware link for transmit / receive direction control while the isolation structure is in place. This embodiment uses D1, D2, D8, D9, C19, C20, and R12 to form an RS485 port protection matching circuit, enabling the RS485 port to simultaneously provide transient voltage clamping, surge discharge, high-frequency filtering, and differential termination matching. This structure addresses the problem of static electricity, surges, high-frequency interference, and signal reflection coexisting after an external RS485 line is connected to an industrial site. If only a single TVS device is configured, it is difficult to withstand high-energy surges; if only a GDT is configured, the response speed and small-amplitude transient suppression are insufficient; if only a termination resistor is configured, port protection cannot be provided. This embodiment arranges different functional devices on the RS485-A and RS485-B port sides, so that external interference is processed before entering U2, while maintaining differential transmission matching. This embodiment displays the receiving, transmitting, and power-on statuses via D3, D4, and D5, respectively, enabling the module to have an observable status during field operation. This structure itself is not the core of communication conversion, but it can reduce the difficulty of troubleshooting and is especially suitable for quickly judging the power supply, transmitting, and receiving statuses in industrial sites or edge computing device access scenarios.

[0029] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-isolation, zero-latency USB to RS485 isolated serial communication module, characterized in that, Includes a PCB board, a USB-A recessed mounting base J1, a USB to serial communication chip U4, a signal isolation chip U3, an RS485 transceiver U2, a P3.5 push-button terminal block J2, and an RS485 port protection and matching circuit. The USB-A recessed mounting bracket J1 is located at one end of the PCB board. The VCC pin of the USB-A recessed mounting bracket J1 is connected to VBUS, the D+ pin is connected to the USB to serial communication chip U4 through DP2_P, the D- pin is connected to the USB to serial communication chip U4 through DM2_N, and the GND pin is connected to the USB side ground GND. The USB to serial communication chip U4 is an MS3020 chip. The USB to serial communication chip U4 is connected to RXD1 through the RXD / GPIO11 pin, to TXD1 through the TXD / GPIO8 pin, and to TXEN1 through the GPIO17 / TXEN pin. The signal isolation chip U3 is an NIRSP31V chip. The R pin of the signal isolation chip U3 is connected to RXD1, the D pin is connected to TXD1, and the DE pin is connected to TXEN1. RXD1, TXD1, and TXEN1 are isolated and transmitted as RXD_TTL, TXD_TTL, and TXEN, respectively. The RS485 transceiver U2 is a UM13088 chip. The RO pin of the RS485 transceiver U2 is connected to RXD_TTL, the DI pin is connected to TXD_TTL, the RE pin and the DE pin are both connected to TXEN, the A pin is connected to RS485-A, and the B pin is connected to RS485-B. The P3.5 push-button terminal J2 is located at the other end of the PCB board. The first terminal of the P3.5 push-button terminal J2 is connected to RS485-A, and the second terminal is connected to RS485-B. The RS485 port protection matching circuit is connected between RS485-A and RS485-B, and between RS485-A, RS485-B and the isolation ground GND2.

2. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 1, characterized in that: The USB-A recessed mounting base J1 includes a VCC pin, a D- pin, a D+ pin, and a GND pin; the VCC pin is connected to VBUS via L1, where L1 is an FB600 ferrite bead; the D+ pin forms DP2_P, the D- pin forms DM2_N, and the GND pin is connected to the USB-side ground GND. The input side of the USB-A recessed mounting bracket J1 is equipped with D12, C6, C21, and C22. D12 is an SMFJ28A-E3 / 52 protection device, and D12 is located in the input side protection branch of the USB-A recessed mounting bracket J1. C6 is a 10μF capacitor, and C6 is connected to the power supply filtering branch between VBUS and USB side ground GND. C21 and C22 are both 10pF capacitors, and C21 and C22 are connected to the USB differential signal filtering branch where DP2_P and DM2_N are located.

3. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 2, characterized in that: The model of the USB to serial communication chip U4 is MS3020; the USBDP pin of the USB to serial communication chip U4 is connected to DP2_P, the USBDM pin is connected to DM2_N, the VDD5V pin is connected to VBUS, the VLDO33 pin is connected to the LVDO33 network, and the VSS pin is connected to USB side ground GND. The RXD / GPIO11 pin of the USB to serial communication chip U4 is connected to RXD1, the TXD / GPIO8 pin is connected to TXD1, and the GPIO17 / TXEN pin is connected to TXEN1. This enables the USB to serial communication chip U4 to convert the USB differential signals input via DP2_P and DM2_N into TTL serial port transmit / receive signals corresponding to RXD1 and TXD1, and output the transmit / receive enable signal corresponding to TXEN1. The RSTN pin of the USB-to-serial communication chip U4 is connected to the reset configuration branch, which includes R6, a 100K resistor connected to the reset configuration node where the RSTN pin is located; the GPIO1 / SPISCLK pin of the USB-to-serial communication chip U4 is connected to the RX-LED, and the GPIO0 / SPICS pin is connected to the TX-LED.

4. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 3, characterized in that: The signal isolation chip U3 is model NIRSP31V; the signal isolation chip U3 includes R pin, D pin, DE pin and GND1 pin located on the front side of isolation, and R2 pin 17, D2 pin 15, DE2 pin 16, VISO pin and GND2 pin located on the rear side of isolation. The signal isolation chip U3 has its R pin connected to RXD1, D pin connected to TXD1, DE pin connected to TXEN1, and GND1 pin connected to USB-side ground GND; the signal isolation chip U3 has its 17th pin R2 connected to RXD_TTL, its 15th pin D2 connected to TXD_TTL, its 16th pin DE2 connected to TXEN, its VISO pin connected to 5V_VISO, and its GND2 pin connected to isolation-side ground GND2. The signal isolation chip U3 isolates and transmits RXD1 as RXD_TTL through the isolation channel between pin R and pin 17 R2, isolates and transmits TXD1 as TXD_TTL through the isolation channel between pin D and pin 15 D2, and isolates and transmits TXEN1 as TXEN through the isolation channel between pin DE and pin 16 DE2. This places RXD1, TXD1, and TXEN1 on the front isolation side corresponding to USB ground GND, and places RXD_TTL, TXD_TTL, and TXEN on the back isolation side corresponding to GND2.

5. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 4, characterized in that: The power supply side of the signal isolation chip U3 before isolation is provided with C13, C14 and C18, and the power supply side of the signal isolation chip U3 after isolation is provided with C15, C16 and C17; C13 and C16 are both 10μF capacitors, and C14, C15, C17 and C18 are all 0.1μF capacitors. C13, C14, and C18 are connected to the pre-isolation power supply filter branch corresponding to the USB side ground GND, and are used to store energy and perform high-frequency filtering on the pre-isolation power supply of the signal isolation chip U3; C15, C16, and C17 are connected to the post-isolation power supply filter branch corresponding to the post-isolation ground GND2, and are used to store energy and perform high-frequency filtering on the post-isolation power supply where 5V_VISO is located. The signal isolation chip U3 is also connected to R3 and R10, both of which are 0Ω resistors, and are connected to the isolation back-side connection branch of the signal isolation chip U3.

6. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 4, characterized in that: The RS485 transceiver U2 is model UM13088; the RS485 transceiver U2 includes RO pin, RE pin, DE pin, DI pin, GND pin, A pin, B pin and VCC pin; The RS485 transceiver U2 has its VCC pin connected to 5V_VISO, its GND pin connected to the isolated ground GND2, its RO pin connected to RXD_TTL, its DI pin connected to TXD_TTL, its RE pin and DE pin both connected to TXEN, its A pin connected to RS485-A, and its B pin connected to RS485-B. The TXEN signal is formed by isolating TXEN1 with signal isolation chip U3 and is simultaneously input to the RE and DE pins of RS485 transceiver U2 as the isolated hardware transmit / receive enable signal. When RS485 transceiver U2 is in transmit mode, TXD_TTL is input to RS485 transceiver U2 via DI pin and output as RS485-A and RS485-B differential signals via A and B pins. When RS485 transceiver U2 is in receive mode, RS485-A and RS485-B are input to RS485 transceiver U2 via A and B pins and output as RXD_TTL via RO pin. The signal side of the RS485 transceiver U2 is equipped with resistors R1, R2, R4, and R5, all of which are 4.7K resistors, used to form the level bias of the relevant signal terminals and the RS485 differential terminals of the RS485 transceiver U2; the power supply side of the RS485 transceiver U2 is equipped with capacitor C5, which is a 0.1μF capacitor connected to the decoupling branch between 5V_VISO and the isolation ground GND2.

7. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 6, characterized in that: The RS485 port protection matching circuit includes D1, D2, D8, D9, R12, C19, and C20; D1 and D2 are both SMBJ6.5CA transient suppression devices, D8 and D9 are both GDT gas discharge tubes, R12 is a 120Ω terminating matching resistor, and C19 and C20 are both 100pF capacitors. D1 is connected to the transient voltage suppression branch where RS485-A is located, and D2 is connected to the transient voltage suppression branch where RS485-B is located; D8 is connected to the surge discharge branch between RS485-A and the isolation ground GND2, and D9 is connected to the surge discharge branch between RS485-B and the isolation ground GND2. R12 is connected between RS485-A and RS485-B to form an RS485 differential termination match; C19 is connected between RS485-A and GND2 (the ground after isolation), and C20 is connected between RS485-B and GND2 (the ground after isolation) to filter high-frequency interference on the RS485 port side; RS485-A and RS485-B are connected to P3.5 push-button terminal J2 after passing through the RS485 port protection matching circuit.

8. The high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 3, characterized in that: It also includes a status indicator circuit, which includes D3, D4, D5, R7, R8 and R9; D3 is a yellow receive indicator, D4 is a green transmit indicator, D5 is a blue power-on indicator, R7 and R8 are both 499Ω resistors, and R9 is a 1KΩ resistor. D3 is connected to the receive status indication branch of RX-LED via R7, and RX-LED is connected to the GPIO1 / SPISCLK pin of USB to serial communication chip U4; D4 is connected to the transmit status indication branch of TX-LED via R8, and TX-LED is connected to the GPIO0 / SPICS pin of USB to serial communication chip U4; D5 is connected to the power-on status indication branch between VBUS and USB side ground GND via R9, and is used to display the power-on status of USB to RS485 isolated serial communication module.

9. A high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 6, characterized in that: The USB-to-serial communication chip U4 outputs TXEN1 via the GPIO17 / TXEN pin, which changes according to the transmission state of TXD1. When the USB-to-serial communication chip U4 outputs the transmission data corresponding to TXD1 via the TXD / GPIO8 pin, the GPIO17 / TXEN pin outputs TXEN1 in the transmission enable state. TXEN1 is isolated by the signal isolation chip U3 to form TXEN. TXEN is simultaneously input to the RE and DE pins of the RS485 transceiver U2, enabling the RS485 transceiver U2 to maintain the transmission state during the TXD_TTL input DI pin period. When the transmission data corresponding to TXD1 ends, the GPIO17 / TXEN pin switches TXEN1 to the receive enable state. TXEN is synchronously switched via the signal isolation chip U3, causing the RS485 transceiver U2 to exit the transmission state and enter the receive state. The TXEN1, TXEN, RE, and DE pins form a hardware transmit / receive enable link from the USB to serial communication chip U4 to the RS485 transceiver U2. This hardware transmit / receive enable link does not pass through the delay control branch and external direction control branch formed by the independent main control chip, so that the transmit and receive states of the RS485 transceiver U2 are hardware switched according to the transmit state of TXD1.

10. A high-isolation, zero-latency USB to RS485 isolated serial communication module according to claim 7, characterized in that: When RS485-A and RS485-B are subjected to external transient interference, the transient voltage suppression branch containing D1 and D2 clamps the transient voltage on RS485-A and RS485-B, the surge discharge branch containing D8 and D9 discharges the surge energy on RS485-A and RS485-B to the isolation ground GND2, and the high-frequency filtering branch containing C19 and C20 bypasses the high-frequency interference components on RS485-A and RS485-B to the isolation ground GND2. R12 is connected between RS485-A and RS485-B. During the transient voltage suppression, surge discharge, and high-frequency filtering processes performed by D1, D2, D8, D9, C19, and C20, it maintains the differential termination matching between RS485-A and RS485-B, so that when RS485-A and RS485-B are connected to an external RS485 line via the P3.5 push-button terminal J2, port protection and differential signal matching are simultaneously achieved.

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