A circuit schematic image visualization method and system based on component retrieval and feedback enhancement

Abstract

A circuit schematic diagram visualization method and system based on component retrieval and feedback enhancement, in view of the low degree of automation of circuit design and the low efficiency of schematic diagram generation in the prior art, the present application constructs an index library of circuit function description-component list and a complete SPICE subcircuit tool library, uses a large language model combined with vector retrieval technology to automatically recall candidate components and generate SPICE netlist code according to the user input task description; the system introduces a feedback enhancement mechanism, checks the generated netlist for requirements and legality, and drives model iteration correction; finally, the verified SPICE netlist is converted into a schematic diagram file format readable by simulation software, realizing efficient and accurate visualization generation of the circuit schematic diagram and improving the intelligent level of circuit design.

Description

[0001] Technology Neighborhood This invention relates to the field of computer large language model retrieval enhancement generation and prompt word engineering design technology, and in particular to a circuit principle image visualization method and system based on component retrieval and feedback enhancement. Background Technology

[0002] Significant breakthroughs have been achieved in the field of artificial intelligence, particularly in text-to-image generation technology, especially in generating natural scenes and real-world images. These technologies have not only driven innovation in visual creation and the media industry but also brought enormous potential and transformation to the education sector. In the educational process, especially in textbook writing and the presentation of teaching content, images serve as a powerful tool that can significantly enhance students' understanding and memory. For abstract and complex theoretical concepts, visual representations are often more intuitive and vivid than textual descriptions. Currently, image generation models perform well in generating natural images of the real world, but their effectiveness remains significantly limited in tasks such as generating highly structured images like circuit diagrams and mechanical diagrams.

[0003] First, from the perspective of data distribution, mainstream image generation models typically rely on large-scale internet image data for pre-training. This data is highly concentrated in natural scenes, portraits, and everyday objects, exhibiting continuous textures, blurred boundaries, and strong statistical redundancy. In contrast, the visual features of circuit diagrams and mechanical diagrams usually exhibit high discreteness, mainly composed of a small number of high-contrast lines, regular geometric shapes, and precisely arranged symbols, lacking obvious texture features. This significant distributional difference makes existing methods based on pixel or latent space statistical modeling difficult to effectively capture the generation patterns of circuit diagrams. For example, the paper "FACTUALITY MATTERS: WHEN IMAGE GENERA-TION AND EDITING MEET STRUCTURED VISUALS" proposes that modern visual generation models excel at creating aesthetically pleasing natural images, but perform poorly in scenarios requiring diagram planning and multimodal reasoning, such as diagram generation. Our proposed method utilizes a large language model, rather than traditional image generation models, to transform the logical structure of the diagram into a netlist structure, and then renders it into a visualized circuit principle image using the .asc file format. Summary of the Invention

[0004] To overcome the problems of the prior art, the present invention aims to propose a circuit principle image visualization method and system based on component retrieval and feedback enhancement. By utilizing the understanding of circuit domain knowledge through a large language model, the positions and connections of circuit components are rationally arranged, and visualization is achieved in the simulation software LTspice by generating SPICE netlists and .asc files. This effectively alleviates the problem of scarce public datasets in this field and significantly reduces the error rate of the large language model in the process of generating circuit description code.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A circuit schematic visualization method based on component retrieval and feedback enhancement includes the following steps: S1: Obtain circuit schematics from electronics textbooks, use a multimodal large language model to identify the schematics and extract corresponding functional descriptive text, and use an object detection model to extract component information from the circuit schematics to construct data pairs of circuit function description and circuit component list; use a text embedding model to convert the circuit function descriptions into vectors and store them in a vector retrieval database to form a circuit component index library; at the same time, construct a circuit tool library containing fully encapsulated SPICE sub-circuit modules. S2: Receive the circuit design task input by the user, and obtain the corresponding list of circuit components by matching the historical circuit data with the highest semantic similarity of functional features in the vector retrieval database through vector retrieval; input the design task and the list of components into the code big language model, and generate SPICE netlist code containing complete connection relationships by combining the task difficulty judgment result; wherein, simple tasks directly use prompt words to generate SPICE netlist, and complex tasks call the sub-circuit module code in the circuit tool library to assist in the generation of SPICE netlist; S3: Perform requirements analysis and legality checks on the generated SPICE netlist. If errors are found, the error information is fed back to the code language model for iterative correction until a compliant SPICE netlist is generated. S4: Use the code big language model to convert compliant SPICE netlists into circuit schematic .asc files that can be read by simulation software, and visualize the circuit schematic in the simulation software.

[0006] The YOLO object detection model is used to train and recognize the circuit schematic, extracting component information and their location information, including resistors, capacitors, power supplies, and transistors, and constructing data pairs of circuit function description and circuit component list; the circuit function description is converted into a vector using a text embedding model and stored in a vector retrieval database. The specific process of building a circuit tool library is as follows: S1.1: Select standardized basic circuits with independent structures and clear functions from electronic textbooks or standard circuit design materials; S1.2: For each selected standardized basic circuit, use the sub-circuit definition instructions in SPICE syntax to encapsulate the code and generate sub-circuit module code with independent input and output ports; S1.3: Extract the functional characteristic description of each standardized basic circuit as the key, and the corresponding sub-circuit module code as the value. Establish the mapping relationship between functional description and sub-circuit code and store it in the sub-circuit code library to form the circuit tool library.

[0007] In step S2, before generating the SPICE netlist code, the difficulty of the circuit design task is determined using the code language model. This includes: if the circuit design task is a single function, has fewer than a set number of components, and does not require calling sub-circuit modules, it is determined to be a simple task; if the circuit design task is a composite function, has a multi-level structure, has more than a set number of components, and requires calling sub-circuit modules from the circuit tool library, it is determined to be a complex task, and the circuit tool library is called to assist in generating the SPICE netlist.

[0008] For the complex task, the specific implementation of generating the SPICE netlist is as follows: PySpice is used as an intermediate interface, and the Python code generation capability of the code big language model is used to convert the circuit structure description into a PySpicePython script. The PySpice Python script uses an object-oriented approach to define circuit element instances and their node connections. Executing the Python script generates SPICE netlist code containing complete connection relationships.

[0009] The specific method of S3 is as follows: Requirements analysis check: Verify whether the generated SPICE netlist meets the basic requirements of the design task, including the naming of input and output nodes, the completeness of necessary components, and whether the circuit topology matches the task description; Netlist validity check: Verify whether the syntax of the SPICE netlist conforms to the syntax specification and whether it can be executed for simulation; If any item is not met, it indicates an error.

[0010] In step S4, when converting the SPICE netlist into an .asc file using a large language model, the coordinates of the circuit elements on the canvas are determined based on the connection relationships in the netlist, generating graphic symbols, precise locations, and visualization information of the connection relationships of all circuit elements in the circuit.

[0011] A circuit diagram image visualization system based on component retrieval and feedback enhancement, used to implement the circuit diagram image visualization method based on component retrieval and feedback enhancement, includes: The data construction module is used to acquire circuit schematics from electronic textbooks, extract component information from the circuit schematics using a target detection model, and extract corresponding circuit function descriptions using a multimodal large language model, constructing data pairs of circuit function descriptions and circuit component lists. A text embedding model is used to convert the circuit function descriptions in the data pairs into vectors, which are then stored in a vector retrieval database to form a circuit index library. Simultaneously, standardized basic circuits are selected from standard circuit design materials, encapsulated into SPICE sub-circuit module codes, and a code resource library is established with the circuit function descriptions as keys and the sub-circuit module codes as values, forming a circuit tool library. The SPICE netlist generation module receives circuit design tasks input by the user, uses them as query vectors to search the vector retrieval database, and obtains a list of similar circuit components. Combining the circuit design task and the obtained list of circuit components, it uses a large language model to generate SPICE netlist code containing complete connection relationships. If the task is determined to be complex, it matches the circuit design task in the code resource library and calls the corresponding sub-circuit module code to assist in generating the SPICE netlist code. The feedback enhancement processing module is used to perform requirements analysis checks and netlist validity checks on the generated SPICE netlist code. If errors are found, the error information is converted into natural language and fed back to the large language model for iterative correction.

[0012] The data construction module includes: The data preparation unit is used to obtain circuit schematics and their corresponding text descriptions from electronic textbooks, extract component information from the schematics using a target detection model, and construct circuit function description-component list data pairs. A vectorized storage unit is used to convert the circuit function description into a vector using an embedding model and store it in a vector index library to support semantic-based fast retrieval. The tool library building unit is used to select structurally independent standardized basic circuits from the pre-set electronic teaching materials, encapsulate the code using SPICE sub-circuit definition instructions, and establish a key-value pair mapping relationship between function description and sub-circuit code.

[0013] When generating a SPICE netlist, the SPICE netlist generation module is configured to use the PySpice syntax interface to transform the SPICE netlist generation task into a Python code generation task, and use the code of the large language model to generate SPICE netlist code containing complete connection relationships.

[0014] The feedback enhancement processing module includes: The requirements analysis and inspection unit is used to verify whether the generated netlist contains the necessary circuit components, whether the input and output node names are correct, and whether the circuit topology matches the task description. The netlist validity check unit is used to verify whether the syntax of the netlist conforms to the requirements of the SPICE simulation tool; The iterative correction unit is used to convert the error information generated during the above inspection process into natural language feedback, which is then input into the large language model for self-correction.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. It realizes intelligent and automated circuit design, improving the accuracy of generation. This invention introduces a retrieval-enhanced generation and feedback-enhanced mechanism. Retrieval enhancement involves searching and obtaining a list of similar circuit components from a vector-based circuit component index library, ensuring the authenticity and standardization of the generated content and avoiding model illusion. Feedback enhancement involves a feedback-enhanced processing module that performs legality checks and requirements analysis on the generated netlist and drives iterative model correction. This significantly improves the accuracy and usability of the final generated SPICE netlist and schematic.

[0016] 2. End-to-end conversion from natural language to visual schematic diagrams has been achieved. This paper utilizes the PySpice syntax interface to transform netlist generation into Python code generation, and finally automatically converts the verified code into .asc schematic files that can be read by simulation software. The generated schematics are physically simulateable. This achievement realizes the transformation from natural language description to structured code to visual graphics, providing a brand-new technical path for automated circuit design.

[0017] 3. Highly modular and scalable The system employs object-oriented design principles and SPICE sub-circuit encapsulation technology, enabling modules in the circuit tool library to be flexibly combined like building blocks. When new components or functions need to be added, simply add new key-value pairs to the library without modifying the core algorithm, resulting in extremely high flexibility and maintainability. Attached Figure Description

[0018] Figure 1 This is a flowchart visualizing the circuit schematic of the present invention.

[0019] Figure 2 This is a flowchart of the SPICE netlist generation process of the present invention.

[0020] Figure 3 Flowchart for constructing the dataset of this invention.

[0021] Figure 4 This is a flowchart illustrating the feedback enhancement process of the present invention.

[0022] Figure 5 This is a performance comparison of the method of this invention with large language model agents and existing work AnologCoder.

[0023] Figure 6 This is an ablation experiment based on the GPT3.5 model.

[0024] Figure 7 This is an ablation experiment based on GPT4o.

[0025] Figure 8 Example of generating a DC rectifier filter circuit.

[0026] Figure 9 This is a case study for generating a two-stage RC bandpass filter.

[0027] Figure 10 Example generation for BJTA class amplifiers. Detailed Implementation

[0028] This example presents a circuit schematic visualization method based on component retrieval and feedback enhancement. The overall process is as follows: Figure 1 As shown, this method first converts the input circuit design task into a SPICE netlist, and then visualizes the circuit image by converting the SPICE netlist into an .asc file. Figure 2 This invention demonstrates the overall process of generating SPICE netlists, collecting text pairs of circuit schematics and functional descriptions, vectorizing the circuit functional descriptions using an embedding model, and storing them in a database to form a circuit component database supporting fast semantic retrieval; and constructing a circuit tool library containing fully encapsulated SPICE sub-circuit modules. The feedback-enhanced process reduces the error rate of the model-generated code.

[0029] The scarcity of publicly available textbook-level circuit schematic image datasets currently hinders circuit image generation to some extent. To support subsequent circuit schematic generation tasks, this invention constructs a dataset that maps circuit schematic descriptions to circuit component-level semantics. Figure 3 The process of building the dataset is shown below: S1. Regarding data source selection, this invention primarily uses electronic textbooks as the data source, systematically selecting representative circuit schematics to construct a high-quality dataset. Compared to circuit diagrams in research papers, circuit schematics in textbooks typically feature standardized structures, standardized symbols, complete annotations, and clear contextual explanations, providing more accurate and stable component-level semantic labels for the model. Functional block diagrams or highly abstract system structure diagrams commonly found in electronic papers often encapsulate or omit multiple components, making their granularity insufficient for component-level detection, annotation, and generation requirements. Therefore, textbook circuit schematics are more suitable as the data foundation for circuit image generation and understanding tasks. In the dataset construction process, this invention employs a combination of automated scripts and a multimodal large language model to improve the efficiency of data collection and annotation. The overall process is as follows: (1) PDF Slicing and Initial Screening of Textbooks: First, the PDF files of electronic textbooks are sliced, and the candidate image regions are input into the multimodal large language model. Under the guidance of prompts and context, the model first determines whether the input image belongs to the circuit schematic diagram, and then automatically locates and extracts the descriptive text corresponding to the circuit schematic diagram.

[0030] (2) Text Simplification and Manual Verification: Considering that the descriptions of circuit schematics in textbooks are usually quite lengthy, often containing a lot of background information or explanations of principles, while such information helps humans understand the working mechanism of the circuit, it is not necessary for model training and may even introduce semantic noise. Therefore, in the data construction process, this invention performs semantic compression on the original descriptive text, retaining only the key information that reflects the core functions and structural features of the circuit. Subsequently, the automatically selected image and text pairs are verified by manual review to ensure that the image is indeed a circuit schematic and that the corresponding simplified description is basically accurate in semantics.

[0031] Taking a circuit schematic from a textbook as an example, its original description is: This diagram shows a large-signal model of a bipolar junction transistor (BJT) in the saturation region, including both NPN and PNP types. Each model includes a collector (C), base (B), and emitter (E), and labels the on-state voltage and saturation voltage drop. These models are used to simplify the behavioral representation of BJTs under specific bias conditions, facilitating circuit analysis and design. The above description contains a lot of background and explanatory information. This invention simplifies it to: a large-signal model of a bipolar junction transistor in the saturation region. This semantic simplification allows the text description to characterize the core functional features of the circuit in a more compact and stable form. On the one hand, the simplified functional description is used to construct a semantic-based component index library as a retrieval condition to match the set of circuit components related to the function, thereby providing structural priors and candidate constraints for the subsequent generation process; on the other hand, the functional description also serves as a conditional input for the diffusion model training stage, guiding the model to generate circuit schematics consistent at both the functional and structural levels. Ultimately, this invention constructs a total of 6403 pairs of circuit schematic-text description image-text pairs.

[0032] One of the primary challenges faced by models in generating SPICE netlists for complex circuits is the generation of missing or fabricated components, known as "phantom components." This is mainly due to the lack of high-quality circuit design data in the pre-training phase of large-scale language models, which prevents them from fully learning the distribution patterns, naming conventions, and structural constraints of circuit components. Relying solely on prompt inputs is insufficient to guarantee that the model can generate SPICE code containing a complete and reasonable list of components. For example, when asking GPT-3.5, "What components make up a series-to-series feedback amplifier composed of three transistors?", the model's typical answer is: A series-to-series feedback amplifier consists of three transistors, several resistors, several capacitors, and one inductor. The transistors are used for signal amplification, the resistors and capacitors form the feedback loop, and the inductor is used to achieve resonance. However, analysis of the actual schematic reveals that the circuit does not contain any inductors or capacitors. This indicates that in complex circuit structure generation tasks, models are prone to generating phantom components that do not conform to the target design based on common circuit priors, resulting in generated results that cannot be directly applied to simulation verification.

[0033] To address the component illusion problem that easily occurs in circuit netlist generation, this project proposes a constraint generation method based on component-level retrieval enhancement. The core idea is to decompose the circuit netlist generation task into a two-stage process of retrieval and generation. First, a list of components that best matches the target circuit description is retrieved to construct a structured prior for the generation process, thereby guiding the language model to generate more accurate SPICE netlists.

[0034] To accurately extract component information from circuit images, this invention employs a deep learning-based object detection method. Specifically, a YOLOv8 model was trained on the v3qwe dataset, which includes common circuit components such as resistors, diodes, power supplies, and capacitors, along with their corresponding bounding boxes. This model achieved excellent detection performance on the test set, with an accuracy of 97.3%. Based on this, the previously processed text descriptions and the circuit component list are combined to construct a "circuit function description – component list" data pair.

[0035] Based on the constructed "circuit function description – component list" data pair, this invention uses OpenAI's text-embedding 3 model to vectorize the circuit description and stores it in a vector index library, forming a knowledge base that supports fast semantic retrieval. During the inference phase, the input circuit function description is used as a query, and vector retrieval recalls the list of circuit components most similar to the description, thereby enhancing the knowledge for the generation task. Subsequently, the retrieved component list and circuit function description are input together into the Prompt of the large language model as supplementary information, constraining the SPICE netlist generated by the model to only include the retrieved component types. This avoids introducing components irrelevant to the retrieval results and ensures that key components are not omitted.

[0036] S2. Receive the circuit design task input by the user, retrieve a list of similar circuit components from the circuit component index library through vector retrieval, and determine the difficulty. For simple tasks, directly generate a netlist using prompt words; if determined to be a complex task, call the circuit tool library and add the encapsulated PySpice sub-circuit code to the prompt word context; combine the retrieved component list and / or sub-circuit code, and use a large language model to generate SPICE netlist code containing complete connection relationships.

[0037] While existing large language models (MLMs) are capable of generating code in multiple programming languages, research has shown that their code generation quality and stability on Python significantly outperform most other programming languages. Furthermore, mainstream code generation models such as CodeLlama are primarily trained on large-scale Python code data for fine-tuning, further contributing to their superior performance on Python tasks. In contrast, most LLM training corpora built on GitHub contain a relatively low proportion of SPICE-related code, thus limiting the model's ability to directly generate high-quality SPICE netlists.

[0038] Therefore, this invention selects PySpice as the intermediate interface for SPICE netlist generation and execution. PySpice deeply integrates traditional SPICE syntax with the Python programming language, describing circuit components and connections in an object-oriented manner. While retaining SPICE simulation capabilities, it significantly improves code readability and scalability. Compared to directly generating pure SPICE netlists, the Python code generation method based on PySpice is more suitable for the modeling capabilities of large language models, effectively mitigating generation errors caused by the lack of contextual semantics and insufficient structured information when directly using SPICE, thereby improving the correctness of circuit generation.

[0039] The specific process of generating SPICE netlist code containing complete connection relationships using the code big language model is as follows: Constructing a system-level prompt (hint word): Inject specific system instructions into the code language model, for example: "You are a professional analog circuit design assistant. Please generate netlist code strictly according to the SPICE syntax specification based on the circuit function description and available component list I provide. Requirements: explicitly declare power nodes, correctly set transistor parameters, and include necessary simulation control instructions." Injecting context information: The list of circuit components retrieved from the "vector retrieval database" in step S2 (e.g., NPN transistor models, resistor value ranges, etc.) is used as a constraint condition, concatenated into the user's natural language task, and then sent to the large model. This effectively prevents the large model from generating illusions (i.e., fabricating non-existent components).

[0040] Structured text decoding and formatting: The code-based language model uses an autoregressive inference architecture based on the Transformer framework, generating a text stream conforming to SPICE syntax on a token-by-token basis. The generated text must adhere to strict formatting specifications; for example, each line represents a component instantiation statement (<component name><positive node><negative node><parameter>), and comments are automatically added to distinguish different functional modules (such as bias networks, amplification stages, etc.). Building upon this foundation, this invention introduces a contextual learning mechanism. Specifically, a two-stage amplifier design example with both active and resistive loads is provided as a one-time learning sample in the prompt. This example not only provides a clear design framework for the model but also standardizes the structure and style of the output code to some extent, thereby helping to reduce syntax errors and circuit connection errors. It is important to emphasize that all test tasks differ from the provided example in circuit topology and design objectives to avoid potential data leakage issues and ensure the fairness of experimental evaluation. Furthermore, this project employs a thought chain strategy, guiding the model to first provide a complete circuit design plan, including the required component types and their connection relationships, before generating specific code. This intermediate planning process, as an explicit reasoning step, effectively reduces the difficulty of generating complex circuit designs and improves the correctness and interpretability of the final generated code.

[0041] S3. Perform requirements analysis and validity checks on the generated SPICE netlist. If errors are found, feed the error information back to the code language model for iterative correction until a compliant SPICE netlist is generated.

[0042] The circuit tool library organizes circuits in key-value pairs. The keys describe the functional characteristics of the circuit. Unlike the original AnalogCoder method, this invention discards some simulation specification parameters, such as voltage gain and phase difference, which are not directly related to circuit structure visualization, making the index information more concise and better suited to the research objectives of this invention. The values ​​store the corresponding executable design content, including PySpice subcircuit definitions and their calling methods, such as the subcircuit instantiation interface. When faced with complex tasks, the code-heavy language model first retrieves the appropriate circuit from the subcircuit library and then adds the corresponding calling code to the context of the prompt words. If the model determines it is a simple task, it will directly execute the feedback enhancement process.

[0043] Code generated by large language models occasionally contains errors; therefore, guiding the model to correct the code based on error information is crucial. Numerous studies have shown that providing relevant error feedback to large language models helps them fix erroneous code. However, in analog circuit design tasks, in addition to handling runtime errors that may occur during SPICE simulation, additional verification of circuit-related information is required to ensure the correctness of the design results.

[0044] The feed enhancement process of this invention is divided into two parts, as follows: Figure 4The process involves two main steps: First, a requirements analysis check. At this stage, the generated netlist is verified to meet the basic requirements of the design task, including: whether the input and output nodes are correctly named and whether necessary circuit components (such as power supplies and loads) are present; whether the circuit topology matches the task description; and whether it matches the input circuit component list. Second, a netlist validity check. This stage focuses on the validity and executability of the netlist, ensuring it complies with the SPICE simulation tool.

[0045] S4. In S4, this invention reuses the code-large language model deployed in phase S2. The model receives the SPICE netlist text verified in S3, and by understanding the component instantiation statements (such as R1 N001 N002 1k) and node connection relationships in the netlist, it automatically calculates the layout coordinates of each component on the canvas according to the LTspice .asc file format specification, and generates corresponding text descriptions of fields such as Version, Symbol, and Wire, and finally outputs a .asc file that can be directly loaded by LTspice.

[0046] To evaluate the code generation performance of this invention, experiments were first conducted on a benchmark proposed by AnalogCoder. This benchmark includes 24 unique circuit design tasks, with the difficulty of the tasks differentiated according to the number of components and connection complexity in the circuit, and divided into basic circuit tasks and complex circuit tasks.

[0047] The specific tasks of benchmark testing are as follows: (1) Basic Circuit Tasks (1-15) These tasks mainly involve single circuit design, such as single-stage amplifiers, inverters, common current sources, etc. These circuits are relatively low in complexity and are suitable for testing the performance of models when designing simple circuits.

[0048] (2) Composite Circuit Tasks (16-24) These tasks involve more complex circuit designs, typically requiring the combination of multiple basic circuit modules into a complete design, such as multi-stage amplifiers and operational amplifiers. The design of composite circuits requires the model to be able to handle the integration of multiple sub-circuit modules, which is quite challenging.

[0049] For these circuit tasks, this invention uses Pass@k as an indicator to evaluate the generated SPICE netlist. See the experimental section below for details, which describes the experiments from both comparative and ablation perspectives.

[0050] Figure 5This paper presents performance comparisons between the proposed method, a large-scale code language model agent, and the existing work AnologCoder. Experiments were conducted using DeepSeek-V2, GPT-3.5, and GPT-4o models under the same prompt word settings. The accuracy of SPICE netlist generation for 24 circuit design tasks was assessed using the pass@k metric. Experimental results show that closed-source models with a larger number of parameters exhibit certain advantages in circuit design tasks. For example, GPT-4o, with its richer training corpus and stronger reasoning ability, performs best overall. This reflects that circuit design not only requires code generation capabilities but also relies on specialized domain knowledge; therefore, models with larger training scales and broader knowledge coverage often have greater potential.

[0051] Further analysis of task complexity shows that GPT-4o can achieve good results in simple circuit design tasks; however, in complex circuit scenarios, the component retrieval and feedback enhancement components introduced in the method of this invention can significantly improve the accuracy and reliability of the generated data, demonstrating the effectiveness of the proposed process.

[0052] In the comparison with the existing work AnologCoder, both were based on the GPT-4o model for fairness. The results show that the proposed method outperforms AnologCoder on multiple task metrics, validating the advancement and practicality of the proposed framework in circuit netlist generation.

[0053] To investigate the impact of the base model and various method components on the generation effect, this invention conducted systematic ablation experiments on GPT-3.5 and GPT4o, respectively.

[0054] First, ablation experiments were conducted using the relatively weaker GPT-3.5 as a base model, and the results are as follows: Figure 6 As shown. "Invention Method (No Context)" refers to removing context examples from the prompts; "Invention Method (No Feedback Enhancement)" indicates that the feedback enhancement process is not used; "Invention Method (No RAG)" indicates that the circuit element index library is not used. Experiments show that context examples have the most significant impact on model inference performance; removing them drastically reduces the pass rate of code generation. The feedback enhancement process also contributes significantly to improving the pass rate. In contrast, the impact of the component index library is relatively small, but a stable improvement in task accuracy can still be observed on GPT-3.5. Ablation experiment results on GPT-4o ( Figure 7The results show different patterns: removing context examples or feedback enhancement processes still leads to a significant drop in accuracy, but removing the component index library has almost no impact on the performance of GPT-4o. This is expected, as GPT-4o already possesses sufficient circuit domain priors thanks to its rich pre-trained knowledge, thus having a low dependence on external component information. For weaker models like GPT-3.5, the component index library can still effectively supplement knowledge.

[0055] After generating the SPICE netlist, this invention will next illustrate this with some visualization examples, such as... Figure 8 Figures 9 and 10 show the proposed method. This invention compares the proposed method with a method that directly generates netlists based on a large language model (GPT-4o). Three typical cases were selected for the experiment: a DC rectifier filter circuit, a two-stage RC bandpass filter, and a BJTA-type amplifier. Figure (a) shows the method for generating SPICE netlists using GPT-4o, (b) shows the method proposed in this invention, and (c) is a reference image. As can be seen from Figure (a), while the traditional large language model can identify component names when processing multi-port components (such as transistors) or multi-stage coupled circuits, it often lacks awareness of spatial layout, leading to chaotic wiring in the generated netlist after conversion. In contrast, although the method of this invention (b) has some components not connected to the circuit, the component arrangement is more neat and aesthetically pleasing.

Claims

1. A circuit principle image visualization method based on component retrieval and feedback enhancement, characterized in that, Includes the following steps: S1: Obtain circuit schematics from electronics textbooks, use a multimodal large language model to identify the schematics and extract corresponding functional descriptive text, and use an object detection model to extract component information from the circuit schematics to construct data pairs of circuit function description and circuit component list; use a text embedding model to convert the circuit function descriptions into vectors and store them in a vector retrieval database to form a circuit component index library; at the same time, construct a circuit tool library containing fully encapsulated SPICE sub-circuit modules. S2: Receive the circuit design task input by the user, and obtain the corresponding list of circuit components by matching the historical circuit data with the highest semantic similarity of functional features in the vector retrieval database through vector retrieval; input the design task and the list of components into the code big language model, and generate SPICE netlist code containing complete connection relationships by combining the task difficulty judgment result; wherein, simple tasks directly use prompt words to generate SPICE netlist, and complex tasks call the sub-circuit module code in the circuit tool library to assist in the generation of SPICE netlist; S3: Perform requirements analysis and legality checks on the generated SPICE netlist. If errors are found, the error information is fed back to the code language model for iterative correction until a compliant SPICE netlist is generated. S4: Use the code big language model to convert compliant SPICE netlists into circuit schematic .asc files that can be read by simulation software, and visualize the circuit schematic in the simulation software.

2. The method according to claim 1, characterized in that, The specific process of constructing the circuit element index library in S1 is as follows: The YOLO object detection model is used to train and recognize the circuit schematic, extracting component information and their location information, including resistors, capacitors, power supplies, and transistors, and constructing data pairs of circuit function description and circuit component list; the circuit function description is converted into a vector using a text embedding model and stored in a vector retrieval database. The specific process of building a circuit tool library is as follows: S1.1: Select standardized basic circuits with independent structures and clear functions from electronic textbooks or standard circuit design materials; S1.2: For each selected standardized basic circuit, use the sub-circuit definition instructions in SPICE syntax to encapsulate the code and generate sub-circuit module code with independent input and output ports; S1.3: Extract the functional characteristic description of each standardized basic circuit as the key, and the corresponding sub-circuit module code as the value. Establish the mapping relationship between functional description and sub-circuit code and store it in the sub-circuit code library to form the circuit tool library.

3. The method according to claim 1, characterized in that, In step S2, before generating the SPICE netlist code, the difficulty of the circuit design task is determined using the code language model. This includes: if the circuit design task is a single function, has fewer than a set number of components, and does not require calling sub-circuit modules, it is determined to be a simple task; if the circuit design task is a composite function, has a multi-level structure, has more than a set number of components, and requires calling sub-circuit modules from the circuit tool library, it is determined to be a complex task, and the circuit tool library is called to assist in generating the SPICE netlist.

4. The method according to claim 2, characterized in that, For the complex task, the specific implementation of generating the SPICE netlist is as follows: PySpice is used as an intermediate interface, and the Python code generation capability of the code big language model is used to convert the circuit structure description into a PySpice Python script. The PySpice Python script uses an object-oriented approach to define circuit element instances and their node connections. Executing the Python script generates SPICE netlist code containing complete connection relationships.

5. The method according to claim 1, characterized in that, The specific method of S3 is as follows: Requirements analysis check: Verify whether the generated SPICE netlist meets the basic requirements of the design task, including the naming of input and output nodes, the completeness of necessary components, and whether the circuit topology matches the task description; Netlist validity check: Verify whether the syntax of the SPICE netlist conforms to the syntax specification and whether it can be executed for simulation; If any item is not met, it indicates an error.

6. The method according to claim 1, characterized in that, In step S4, when converting the SPICE netlist into an .asc file using a large language model, the coordinates of the circuit elements on the canvas are determined based on the connection relationships in the netlist, generating graphic symbols, precise locations, and visualization information of the connection relationships of all circuit elements in the circuit.

7. A circuit principle image visualization system based on component retrieval and feedback enhancement, used to implement the method described in any one of claims 1 to 6, characterized in that, include: The data construction module is used to obtain circuit schematics from electronic textbooks, call a multimodal large language model to extract the corresponding circuit function descriptions, and use an object detection model to extract the component information in the circuit schematics to construct data pairs of circuit function descriptions and circuit component lists. The circuit function descriptions in the data pairs are converted into vectors using a text embedding model and stored in a vector retrieval database to form a circuit component index library. At the same time, a circuit tool library containing fully encapsulated SPICE sub-circuit modules is constructed. The SPICE netlist generation module is used to receive circuit design tasks input by the user, convert the design tasks into query vectors, and retrieve the corresponding list of circuit components from the vector retrieval database. The code big language model is invoked, and its reasoning ability is used to determine the difficulty of the task. The SPICE netlist code containing complete connection relationships is generated by combining the circuit component list. If the task is determined to be complex, the code of the sub-circuit module in the circuit tool library is called to assist in the generation. The feedback enhancement processing module is used to input the netlist code output by the SPICE netlist generation module into the code big language model, and use the code big language model to perform requirement analysis and netlist validity checks on the netlist code. If there are errors, the error information is converted into natural language and fed back to the code big language model for iterative correction. The visualization conversion module is used to call the code language model to parse the finally verified SPICE netlist and convert it into an .asc file format that can be read by simulation software, thereby realizing the visualization of the circuit schematic.

8. The system according to claim 7, characterized in that, The data construction module includes: The data preparation unit is used to obtain circuit schematics and their corresponding text descriptions from electronic textbooks, extract component information from the schematics using a target detection model, and construct circuit function description-component list data pairs. A vectorized storage unit is used to convert the circuit function description into a vector using an embedding model and store it in a vector index library to support semantic-based fast retrieval. The tool library building unit is used to select structurally independent standardized basic circuits from the pre-set electronic teaching materials, encapsulate the code using SPICE sub-circuit definition instructions, and establish a key-value pair mapping relationship between function description and sub-circuit code.

9. The system according to claim 7, characterized in that, When generating a SPICE netlist, the SPICE netlist generation module is configured to use the PySpice syntax interface to transform the SPICE netlist generation task into a Python code generation task, and use the code of the large language model to generate SPICE netlist code containing complete connection relationships.

10. The system according to claim 7, characterized in that, The feedback enhancement processing module includes: The requirements analysis and inspection unit is used to verify whether the generated netlist contains the necessary circuit components, whether the input and output node names are correct, and whether the circuit topology matches the task description. The netlist validity check unit is used to verify whether the syntax of the netlist conforms to the requirements of the SPICE simulation tool; The iterative correction unit is used to convert the error information generated during the above inspection process into natural language feedback, which is then input into the large language model for self-correction.

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