A thermal simulation analysis method of a thermal analysis model and a related device

Abstract

The application provides a thermal simulation analysis method of a thermal analysis model and a related device. The method comprises: obtaining a thermal analysis model; the thermal analysis model comprises boundary conditions, and one or more of geometric model information, heat source position information, and temperature sensing point position information of at least one chip; the boundary conditions comprise a first type of boundary condition, and the first type of boundary condition is used to control a preset boundary of the at least one chip in the thermal analysis model to remain at a preset temperature; and performing thermal simulation analysis on the thermal analysis model to obtain a temperature analysis result of one or more nodes in the at least one chip. The embodiments of the application can cover more application scenarios, and improve the accuracy and practicality of the final thermal simulation analysis result.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a thermal simulation analysis method and related apparatus for thermal analysis models. Background Technology

[0002] In recent decades, with the continuous development and improvement of science and technology, chip design has become increasingly complex to meet people's higher functional demands, such as the emergence of very large-scale integrated circuit design and 3D chip multi-layer stacking design. To ensure that chips or integrated circuits can operate stably under various working conditions and maintain a long service life, thermal simulation can be used to optimize the thermal design of chips or integrated circuits.

[0003] However, due to the increasing complexity of chip and integrated circuit designs, traditional finite element and finite volume methods result in large-scale simulations and long computation times, failing to meet the needs of SPICE-thermal co-simulation analysis. Therefore, a reduction-order approach is needed to accelerate computation and improve simulation efficiency. However, current mainstream reduction-order tools only support thermal simulations in certain scenarios, limiting their applicability. Given the complexity of real-world user scenarios, this can easily lead to poor accuracy and practicality of the final thermal simulation analysis results.

[0004] Therefore, how to provide a thermal simulation analysis scheme that can cover more application scenarios and improve the accuracy and practicality of the final simulation results is an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical issues, this application provides a thermal simulation analysis method and related apparatus for a thermal analysis model. This method can cover simulation scenarios with applied first-type boundary conditions, more closely resembling the complex scenarios encountered by users in actual use, thereby improving the accuracy and practicality of the final thermal simulation analysis results.

[0006] The present application is described below from different aspects. It should be understood that the different implementation methods and beneficial effects described below can be referenced from each other.

[0007] In a first aspect, embodiments of this application provide a thermal simulation analysis method for a thermal analysis model, the method comprising:

[0008] A thermal analysis model is obtained; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a first type of boundary conditions, which are used to control the preset boundary of the at least one chip to be maintained at a preset temperature in the thermal analysis model;

[0009] Thermal simulation analysis is performed on the thermal analysis model to obtain temperature analysis results for one or more nodes in the at least one chip.

[0010] In this embodiment, thermal simulation analysis can be performed on the thermal analysis model with the first type of boundary conditions, that is, the simulation scenario with the first type of boundary conditions applied is covered, which is closer to the complex scenario when the user actually uses it, thereby improving the accuracy and practicality of the final thermal simulation analysis results.

[0011] In one possible implementation, performing thermal simulation analysis on the thermal analysis model includes:

[0012] The thermal analysis model is reduced in order to obtain the order reduction result;

[0013] The reduced-order result is calculated to obtain the temperature analysis results of one or more nodes in the at least one chip.

[0014] In this embodiment of the application, the thermal analysis model can be reduced in order during the thermal simulation analysis process to reduce the computational dimension, thereby speeding up the calculation and meeting the need for rapid prediction of chip temperature.

[0015] In one possible implementation, reducing the order of the thermal analysis model includes:

[0016] The thermal analysis model is reduced in order using the Krylov subspace method; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

[0017] In this embodiment of the application, when reducing the order of the thermal analysis model, the reduction parameters obtained after multiple block classical orthogonalization (BCGS) processes can be used to ensure that the thermal feature matrix of the reduced thermal analysis model is full rank, thereby ensuring the convergence of fast calculation and improving the accuracy of prediction results.

[0018] In one possible implementation, reducing the order of the thermal analysis model includes:

[0019] The thermal analysis model is subjected to data separation based on the first type of boundary conditions to obtain a second processing result; the second processing result includes the thermal capacity and thermal resistance information of each node, the power consumption information of the boundary nodes and heat sources, and the temperature information of the sensing point.

[0020] The order of the second processing result is reduced.

[0021] In one possible implementation, data separation of the thermal analysis model based on the first type of boundary conditions includes:

[0022] Thermal analysis data is extracted from the thermal analysis model; the thermal analysis data includes one or more of the following: heat dissipation capacity information of each node in the at least one chip, location information of each node, boundary node information, temperature sensing point information, and heat source power information; the boundary node is a node in the at least one chip for which boundary conditions are applied.

[0023] The thermal analysis data is reorganized to obtain a first processing result; the first processing result includes one or more of the following: heat dissipation capacity information of boundary nodes, heat dissipation capacity information of non-boundary nodes, and power density information of heat sources.

[0024] Data separation is performed on the first processing result based on the first type of boundary conditions.

[0025] In one possible implementation, the data separation of the first processing result based on the first type of boundary conditions includes:

[0026] Obtain the first power consumption information describing the power consumption of each heat source;

[0027] Determine the isothermal boundary information based on the first type of boundary conditions;

[0028] The isothermal boundary information is fused with the first power consumption information to obtain the second power consumption information;

[0029] The first processing result is separated based on the second power consumption information.

[0030] In one possible implementation, when the first type of boundary condition is empty, all elements in the isothermal boundary information are 0.

[0031] In this embodiment of the application, when the first type of boundary condition is empty, that is, when the thermal analysis model does not apply the first type of boundary condition, all elements in the isothermal boundary information can be set to 0 to avoid errors in the calculation process and prevent the calculation from being performed normally.

[0032] In one possible implementation, the first power consumption information includes a first power consumption vector U, the isothermal boundary information includes an isothermal boundary vector T0, and the second power consumption information includes a second power consumption vector U. new The step of fusing the isothermal boundary information with the first power consumption information to obtain the second power consumption information includes:

[0033] The isothermal boundary vector T0 is used as a pseudo power consumption term and appended to the first power consumption vector U to obtain the second power consumption vector U. new .

[0034] In this embodiment, the first type of boundary condition is used as a pseudo power consumption term and continued to the end of the power consumption term to meet the entry requirements of the order reduction method, while providing a guarantee for supporting thermal simulation analysis of the first type of boundary condition.

[0035] In one possible implementation, the data separation of the first processing result based on the second power consumption information satisfies both the chip steady-state thermal conductivity formula and the chip transient thermal conductivity formula; wherein, the chip steady-state thermal conductivity formula includes:

[0036]

[0037] The transient thermal conductivity formula for chips includes:

[0038]

[0039] Among them, K 11 T is a non-boundary submatrix describing the heat dissipation capability of each non-boundary node; T is a temperature matrix describing each node of the at least one chip in steady state; P density This is a power density matrix describing the power density of each heat source; K 10 The boundary submatrix describes the heat dissipation capability of each boundary node; [P density -K 10 B and B are power consumption boundary matrices describing the thermal impact of boundary nodes and heat sources on the at least one chip; heat dissipation capability includes thermal capacity capability and thermal resistance capability; and U new It is a power vector matrix with pseudo-power consumption terms;

[0040] E is the mass matrix describing the transient thermal capacity of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; A is the stiffness matrix describing the thermal resistance of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; the second processing result includes the mass matrix E, the stiffness matrix A, the power consumption boundary matrix B, and the temperature sensing selection matrix C; the temperature sensing selection matrix C describes one or more temperature sensing points selected for thermal simulation analysis.

[0041] In this embodiment, the data separation process can be performed according to the chip steady-state heat conduction formula and the chip transient heat conduction formula to ensure the effectiveness of data separation.

[0042] In one possible implementation, the Krylov subspace method uses the reduction parameter Q as the reduction matrix; the reduction of the second processing result by the Krylov subspace method satisfies the following formula:

[0043] E r =Q T EQ;

[0044] Ar =Q T AQ;

[0045] B r =Q T B;

[0046]

[0047] Among them, E r Let A be the mass matrix after the order reduction. r B is the reduced stiffness matrix. r This is the power consumption boundary matrix after order reduction. The reduced-order temperature-sensing selection matrix C r The transpose of the matrix; r represents the dimension of the reduced matrix.

[0048] In one possible implementation, calculating the reduced-order result to obtain temperature analysis results for one or more nodes in the at least one chip includes:

[0049] Based on the reduced mass matrix E r Stiffness matrix A r Power consumption boundary matrix B r The transpose of the temperature-sensing selection matrix Perform calculations to determine the temperature set matrix Tr of one or more sensing points.

[0050] In one possible implementation, the temperature set matrix Tr satisfies the following formula:

[0051]

[0052] Where, x r This is the temperature matrix of the subspace after order reduction.

[0053] Secondly, embodiments of this application provide a thermal simulation analysis apparatus for a thermal analysis model, comprising:

[0054] An acquisition unit is used to acquire a thermal analysis model; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a first type of boundary conditions, which are used to control the preset boundary of the at least one chip to be maintained at a preset temperature in the thermal analysis model;

[0055] The processing unit is used to perform thermal simulation analysis on the thermal analysis model to obtain temperature analysis results for one or more nodes in the at least one chip.

[0056] In one possible implementation, performing thermal simulation analysis on the thermal analysis model includes:

[0057] The thermal analysis model is reduced in order to obtain the order reduction result;

[0058] The reduced-order result is calculated to obtain the temperature analysis results of one or more nodes in the at least one chip.

[0059] In one possible implementation, reducing the order of the thermal analysis model includes:

[0060] The thermal analysis model is reduced in order using the Krylov subspace method; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

[0061] In one possible implementation, reducing the order of the thermal analysis model includes:

[0062] The thermal analysis model is subjected to data separation based on the first type of boundary conditions to obtain a second processing result; the second processing result includes the thermal capacity and thermal resistance information of each node, the power consumption information of the boundary nodes and heat sources, and the temperature information of the sensing point.

[0063] The order of the second processing result is reduced.

[0064] In one possible implementation, data separation of the thermal analysis model based on the first type of boundary conditions includes:

[0065] Thermal analysis data is extracted from the thermal analysis model; the thermal analysis data includes one or more of the following: heat dissipation capacity information of each node in the at least one chip, location information of each node, boundary node information, temperature sensing point information, and heat source power information; the boundary node is a node in the at least one chip for which boundary conditions are applied.

[0066] The thermal analysis data is reorganized to obtain a first processing result; the first processing result includes one or more of the following: heat dissipation capacity information of boundary nodes, heat dissipation capacity information of non-boundary nodes, and power density information of heat sources.

[0067] Data separation is performed on the first processing result based on the first type of boundary conditions.

[0068] In one possible implementation, the data separation of the first processing result based on the first type of boundary conditions includes:

[0069] Obtain the first power consumption information describing the power consumption of each heat source;

[0070] Determine the isothermal boundary information based on the first type of boundary conditions;

[0071] The isothermal boundary information is fused with the first power consumption information to obtain the second power consumption information;

[0072] The first processing result is separated based on the second power consumption information.

[0073] In one possible implementation, when the first type of boundary condition is empty, all elements in the isothermal boundary information are 0.

[0074] In one possible implementation, the first power consumption information includes a first power consumption vector U, the isothermal boundary information includes an isothermal boundary vector T0, and the second power consumption information includes a second power consumption vector U. new The step of fusing the isothermal boundary information with the first power consumption information to obtain the second power consumption information includes:

[0075] The isothermal boundary vector T0 is used as a pseudo power consumption term and appended to the first power consumption vector U to obtain the second power consumption vector U. new .

[0076] In one possible implementation, the data separation of the first processing result based on the second power consumption information satisfies both the chip steady-state thermal conductivity formula and the chip transient thermal conductivity formula; wherein, the chip steady-state thermal conductivity formula includes:

[0077]

[0078] The transient thermal conductivity formula for chips includes:

[0079]

[0080] Among them, K 11 T is a non-boundary submatrix describing the heat dissipation capability of each non-boundary node; T is a temperature matrix describing each node of the at least one chip in steady state; P density This is a power density matrix describing the power density of each heat source; K 10 The boundary submatrix describes the heat dissipation capability of each boundary node; [P density -K 10 B and B are power consumption boundary matrices describing the thermal impact of boundary nodes and heat sources on the at least one chip; heat dissipation capability includes thermal capacity capability and thermal resistance capability; and U new It is a power vector matrix with pseudo-power consumption terms;

[0081] E is the mass matrix describing the transient thermal capacity of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; A is the stiffness matrix describing the thermal resistance of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; the second processing result includes the mass matrix E, the stiffness matrix A, the power consumption boundary matrix B, and the temperature sensing selection matrix C; the temperature sensing selection matrix C describes one or more temperature sensing points selected for thermal simulation analysis.

[0082] In one possible implementation, the Krylov subspace method uses the reduction parameter Q as the reduction matrix; the reduction of the second processing result by the Krylov subspace method satisfies the following formula:

[0083] E r =Q T EQ;

[0084] A r =Q T AQ;

[0085] B r =Q T B;

[0086]

[0087] Among them, E r Let A be the mass matrix after the order reduction. r B is the reduced stiffness matrix. r This is the power consumption boundary matrix after order reduction. The reduced-order temperature-sensing selection matrix C r The transpose of the matrix; r represents the dimension of the reduced matrix.

[0088] In one possible implementation, calculating the reduced-order result to obtain temperature analysis results for one or more nodes in the at least one chip includes:

[0089] Based on the reduced mass matrix E r Stiffness matrix A r Power consumption boundary matrix B r The transpose of the temperature-sensing selection matrix Perform calculations to determine the temperature set matrix Tr of one or more sensing points.

[0090] In one possible implementation, the temperature set matrix Tr satisfies the following formula:

[0091]

[0092] Where, x r This is the temperature matrix of the subspace after order reduction.

[0093] Thirdly, embodiments of this application provide a thermal simulation analysis method for a thermal analysis model, the method comprising:

[0094] A thermal analysis model is obtained; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a third type of boundary conditions, which are used to control the heat transfer coefficient and fluid temperature between the preset boundary of the at least one chip and the surrounding fluid in the thermal analysis model.

[0095] After reducing the order of the thermal analysis model using the Krylov subspace method, thermal simulation analysis is performed on the reduced order results to obtain the temperature analysis results of one or more nodes in the at least one chip; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

[0096] Fourthly, embodiments of this application provide a thermal simulation analysis apparatus for a thermal analysis model, comprising:

[0097] An acquisition unit is used to acquire a thermal analysis model; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a third type of boundary conditions, which are used to control the heat transfer coefficient and fluid temperature between the preset boundary of the at least one chip and the surrounding fluid in the thermal analysis model.

[0098] The processing unit is used to reduce the order of the thermal analysis model using the Krylov subspace method, and then perform thermal simulation analysis on the reduced order result to obtain the temperature analysis results of one or more nodes in the at least one chip; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

[0099] Fifthly, embodiments of this application provide a thermal simulation analysis device, which may include a processor and a memory, the memory being used to store a computer program; the processor being used to execute the computer program, causing the thermal simulation analysis device to perform a thermal simulation analysis method of the thermal analysis model in any possible implementation of the first or third aspect described above.

[0100] In a sixth aspect, embodiments of this application provide an electronic device including a processor and an interface circuit. The processor is used to communicate with other devices through the interface circuit, enabling the electronic device to execute the thermal simulation analysis method of the thermal analysis model in any possible implementation of the first or third aspect described above.

[0101] In a seventh aspect, embodiments of this application provide a computer program product, which includes computer program code, and when the computer program product is run on a computer, causes the computer to execute the thermal simulation analysis method of the thermal analysis model in any possible implementation of the first or third aspect described above.

[0102] Eighthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on a computing device, cause the computing device to perform a thermal simulation analysis method of the thermal analysis model in any possible implementation of the first or third aspect described above.

[0103] Ninthly, this application provides a chip system including a processor for supporting a device in implementing the functions involved in any of the possible implementations of the first or third aspect described above, such as generating or processing information involved in the thermal simulation analysis method of the aforementioned thermal analysis model. In one possible design, the chip system further includes a memory for storing necessary program instructions and data for the device. This chip system may be composed of chips or may include chips and other discrete devices.

[0104] Alternatively, the processor and memory can be physically independent units, or the memory can be integrated with the processor.

[0105] The technical effects achieved in the above aspects can be referred to each other or to the beneficial effects in the method embodiments shown below, which will not be repeated here. Attached Figure Description

[0106] The accompanying drawings are provided to more clearly illustrate the technical solutions of the embodiments of this application. The drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0107] Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of this application;

[0108] Figure 2 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0109] Figure 3 This is a flowchart illustrating a thermal simulation analysis method for a thermal analysis model provided in an embodiment of this application.

[0110] Figure 4 This is a flowchart illustrating a thermal simulation analysis scheme provided in an embodiment of this application;

[0111] Figure 5 This is a schematic diagram of a downgrading process provided in an embodiment of this application;

[0112] Figure 6 This is a schematic diagram of a transient temperature rise curve provided in an embodiment of this application;

[0113] Figure 7 This is a schematic diagram of a temperature curve comparison provided in an embodiment of this application;

[0114] Figure 8 This is a flowchart illustrating another thermal simulation analysis method for a thermal analysis model provided in this application embodiment;

[0115] Figure 9 This is a schematic diagram of the structure of a thermal simulation analysis device for a thermal analysis model provided in an embodiment of this application;

[0116] Figure 10 This is a schematic diagram of the structure of a thermal simulation analysis device provided in an embodiment of this application. Detailed Implementation

[0117] The embodiments of this application will now be described with reference to the accompanying drawings.

[0118] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0119] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0120] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0121] To better understand the technical solutions of the embodiments of this application, several terms or nouns related to this application are briefly introduced below so that those skilled in the art can understand them.

[0122] I. First type of boundary conditions

[0123] A boundary condition of the first kind refers to a boundary condition where the temperature on the object's boundary is known and constant. In other words, a boundary condition of the first kind assumes that the temperature distribution on the object's surface is fixed and does not change over time, but rather remains at a constant value. Therefore, a boundary condition of the first kind can also be called an isothermal boundary condition. A boundary condition of the first kind implies that the thermal effect of the external environment on the object is strong enough to force the boundary temperature to be maintained. For example, when the surface of an object is in contact with a phase change substance (such as a boiling liquid or a molten solid), although heat exchange occurs, the surface temperature is fixed by the phase change temperature.

[0124] II. Second type of boundary conditions

[0125] The second type of boundary condition specifies the heat flux density (or heat transfer density) at the boundary of an object. The heat flux density is the same at the boundary, meaning the heat entering a unit area of ​​the object's surface is equal to the heat conducted to a unit area inside the object (within the boundary). Specifically, the second type of boundary condition relates the normal component of the temperature gradient to the given heat flux density via Fourier's law; the negative sign indicates the direction of heat flow.

[0126] III. Third type of boundary conditions

[0127] The third type of boundary condition refers to the convective heat transfer condition between the boundary of an object and the surrounding fluid. Its core is to describe the heat transfer state at the boundary by defining the fluid temperature and the surface heat transfer coefficient of the object. That is to say, the third type of boundary condition specifies the surface heat transfer coefficient (h) and the fluid temperature (tf) between the boundary of the object and the surrounding fluid, and assumes that these parameters are known.

[0128] IV. Error Vector Magnitude (EVM) Characteristics

[0129] Error vector amplitude characteristics (EVMs) are used to quantify the difference between an ideal signal and the actual transmitted signal, and are an important indicator for quantifying vector signal quality. This application can be applied to the thermal simulation analysis of radio frequency power amplifier (PA) chips, and can extract the dynamic thermal network feature matrix of the PA bias circuit in the RF front end, thereby quickly simulating the dynamic junction temperature of the transistors in the chip, optimizing the PA thermal design, and thus improving the dynamic EVM characteristics.

[0130] First, this paper analyzes and proposes some or all of the technical problems that this application aims to solve. Currently, due to the increasing complexity of chip design, thermal analysis simulation using traditional finite element and finite volume methods suffers from large computational scale and long computation time, failing to meet the requirements for rapid chip temperature prediction. Therefore, a model order reduction (MOR) scheme is needed to reduce the computational scale and time. Existing model order reduction (MOR) schemes mainly fall into two categories: one is based on Krylov subspace classes (such as Moments Matching (MM)). MM predefines a series of expansion points 's' and corresponding expansion orders 'moment' based on system characteristics, adapting to high-precision model order reduction for ultra-high-dimensional dynamic systems (millions to tens of millions of dimensions); the other is based on Singular Value Decomposition (SVD) classes (such as balanced truncation and orthogonal decomposition). SVD methods can guarantee the structural characteristics of the model before and after order reduction and truncate the model by the magnitude of the system's singular values, thereby reducing the computational dimensionality.

[0131] The main drawback of the first Krylov subspace-based order reduction technique is that it cannot guarantee the stability of the reduced system, especially the full-rank property before and after the reduction. It is easy for a system that was originally full-rank to become non-full-rank after the reduction, which leads to computational divergence.

[0132] For the second type of singular value decomposition (SVD) order reduction techniques, the orthogonal decomposition method and the balanced truncation method are used. The orthogonal decomposition method requires a large number of training samples. After order reduction, the prediction accuracy is strongly correlated with the number and representativeness of the samples. When the training samples are limited, the prediction accuracy is relatively poor. The balanced truncation method requires solving two high-order Lyapunov equations, which is computationally complex and has a large memory overhead.

[0133] Furthermore, current mainstream thermal model reduction tools only support thermal simulation analysis with third-type boundary conditions, and do not support thermal simulation analysis with first-type boundary conditions. In other words, existing thermal model reduction mainly supports thermal simulation analysis given convective heat transfer coefficients and ambient temperature, and does not support scenarios with first-type boundary conditions, such as simulation scenarios that cannot cover isothermal boundaries like cold plates.

[0134] To this end, this application proposes a thermal simulation analysis method and related apparatus for thermal analysis models, which can perform thermal simulation analysis on thermal analysis models with first-type boundary conditions, that is, cover the simulation scenario with first-type boundary conditions applied, which is closer to the complex scenario when users actually use the model, thereby improving the accuracy and practicality of the final thermal simulation analysis results.

[0135] Furthermore, when performing thermal simulation analysis on the thermal analysis model, the model can first be reduced in order using the Krylov subspace method, and then the reduced order result can be used to calculate the thermal simulation analysis result. The reduction parameters (such as the reduction matrix) used in the Krylov subspace method are determined after multiple block classical orthogonalizations (BCGS) (such as BCGS2, BCGS3, ..., BCGSn), thus ensuring that the reduced-order eigenma matrix is ​​full rank, ultimately guaranteeing the convergence of fast computation.

[0136] To facilitate understanding of the embodiments of this application, the following examples illustrate several scenarios or structures in which the thermal simulation analysis method of the thermal analysis model in this application can be applied. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of a chip structure provided in an embodiment of this application. The chip structure may include a substrate, molding, etc., and transistors, metal electrodes, and metal interconnects are fabricated inside the molding. The transistors can serve as heat sources, the metal electrodes can serve as temperature sensing points, and a first-type boundary condition can be applied to the top of the molding. Optionally, Figure 1 The chip structure shown may include more or fewer components. For example, the above... Figure 1 The chip structure shown can be the structure of a radio frequency chip or a computing chip; no specific limitation is made here.

[0137] See also Figure 2 , Figure 2This is a schematic diagram of another chip structure provided in an embodiment of this application. The chip structure may include a substrate, a base plate, and a metal layer. The base plate and metal layer can be fabricated on the substrate. Transistors and metal electrodes can be fabricated on the base plate. On-chip metal traces can also be fabricated on the base plate. The metal layer on the substrate and the on-chip metal traces on the base plate can be connected by metal jumpers. The transistor can serve as a heat source, the metal electrode can serve as a temperature sensing point, and a first-type boundary condition can be applied to the bottom of the substrate; that is, a cold plate can be disposed at the bottom of the substrate.

[0138] It is understandable that the above Figure 1 or Figure 2 The illustrated application scenarios or structures do not constitute a specific limitation on the application scenarios or structures of the thermal simulation analysis method of the thermal analysis model in this application. The above application scenarios are only an exemplary implementation in the embodiments of this application. The application scenarios in the embodiments of this application include, but are not limited to, the above application scenarios. The thermal simulation analysis method of any thermal analysis model provided in this application can also be applied to the thermal simulation analysis process in other chip structure or circuit structure designs. For example, the target object can be the natural convection heat dissipation of a chip coupled to a mobile phone (or tablet). These are not listed one by one here.

[0139] To better understand the thermal simulation analysis method of the thermal analysis model provided in the embodiments of this application, the technical solution of the thermal simulation analysis method of the thermal analysis model provided in the embodiments of this application will be described below with reference to more accompanying drawings.

[0140] To clearly describe the technical solution of this application, multiple embodiments will be used to illustrate the technical solution of this application, as detailed below. In this application, unless otherwise specified, the same or similar parts between various embodiments or implementations can be referenced mutually. In the various embodiments of this application, and in the various implementation methods / methods / implementations within each embodiment, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments and between the various implementation methods / methods / implementations within each embodiment are consistent and can be mutually referenced. The technical features in different embodiments and the various implementation methods / methods / implementations within each embodiment can be combined according to their inherent logical relationships to form new embodiments, implementation methods, methods, or implementation approaches. The embodiments described below do not constitute a limitation on the scope of protection of this application.

[0141] Please see Figure 3 , Figure 3This is a flowchart illustrating a thermal simulation analysis method for a thermal analysis model provided in this application embodiment. The method can be applied to the thermal simulation analysis process of a chip, or one or more partitions in a chip, or one or more modules in a chip, or one or more unit groups in a chip. The method may include, but is not limited to, the following steps S301-S302.

[0142] S301: Obtain the thermal analysis model.

[0143] Specifically, the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information. The boundary conditions include a first type of boundary condition, which is used to control the preset boundary of the at least one chip to maintain a preset temperature in the thermal analysis model. The geometric model information may include the attribute information and positional relationships of each component in the at least one chip. The attribute information includes information such as the material, shape, heat capacity, and thermal conductivity (or thermal resistance) of each component. Optionally, the above thermal analysis model can be obtained by the user through chip simulation design tools, or it can be obtained by reading existing thermal analysis project files; no specific limitation is made here.

[0144] S302: Perform thermal simulation analysis on the thermal analysis model to obtain the temperature analysis results of one or more nodes in the at least one chip.

[0145] Specifically, after obtaining the thermal analysis model, the thermal analysis data in the thermal analysis model can be calculated, and the thermal simulation analysis process can be executed to finally calculate the temperature analysis results of one or more nodes in the chip, thereby enabling rapid and accurate prediction of the temperature of each node.

[0146] Based on the above steps S301-S302, the embodiments of this application can perform thermal simulation analysis on thermal analysis models with first-type boundary conditions, thereby covering simulation scenarios with applied first-type boundary conditions, which are closer to the complex scenarios in actual use by users, and improving the accuracy and practicality of the final thermal simulation analysis results.

[0147] In one possible implementation, the thermal simulation analysis of the thermal analysis model includes: reducing the order of the thermal analysis model to obtain a reduced-order result; and calculating the reduced-order result to obtain the temperature analysis results of one or more nodes in the at least one chip. Specifically, to accelerate the calculation, during the thermal simulation analysis process, the thermal analysis model can first be reduced in order to decrease the computational dimension, and then the reduced-order result can be calculated to obtain the temperature analysis results of each node, thus meeting the need for rapid chip temperature prediction.

[0148] Optionally, the order reduction scheme for the thermal analysis model can be performed using the Krylov subspace method. For example, the order reduction of the thermal analysis model includes: reducing the order of the thermal analysis model using the Krylov subspace method; the order reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes. The aforementioned order reduction of the thermal analysis model can be performed using the Krylov subspace method. The order reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes, which ensures that the matrix obtained after order reduction is full rank, thereby guaranteeing the convergence of fast computation.

[0149] Optionally, when reducing the order of the thermal analysis model, the model can be first separated into data, and then the separation result can be used to reduce the order. For example, reducing the order of the thermal analysis model includes: separating the data of the thermal analysis model based on the first type of boundary conditions to obtain a second processing result; the second processing result includes the heat capacity and thermal resistance information of each node, the power consumption information of the boundary nodes and heat sources, and the temperature information of the sensing point; and reducing the order of the second processing result. In this embodiment, the data of the thermal analysis model can be separated first according to the first type of boundary conditions to meet the entry requirements of the order reduction method.

[0150] In one possible implementation, thermal analysis data can be extracted from the thermal analysis model first, then the thermal analysis data can be reorganized through matrix row and column transformations, and finally the reorganized result can be separated into data. For example, data separation of the thermal analysis model based on the first type of boundary conditions includes: extracting thermal analysis data from the thermal analysis model; the thermal analysis data includes one or more of the following: heat dissipation capacity information of each node in the at least one chip, location information of each node, boundary node information, temperature sensing point information, and heat source power information; the boundary node is a node in the at least one chip to which boundary conditions are applied; reorganizing the thermal analysis data to obtain a first processing result; the first processing result includes one or more of the following: heat dissipation capacity information of boundary nodes, heat dissipation capacity information of non-boundary nodes, and power density information of heat sources; and separating the first processing result based on the first type of boundary conditions.

[0151] Optionally, the data separation of the first processing result based on the first type of boundary conditions includes: obtaining first power consumption information describing the power consumption of each heat source; determining isothermal boundary information based on the first type of boundary conditions; fusing the isothermal boundary information with the first power consumption information to obtain second power consumption information; and performing data separation on the first processing result based on the second power consumption information. In this embodiment, the boundary temperature and power consumption parameters are reassembled to meet the entry requirements of the order reduction method. Further optionally, when the first type of boundary conditions is empty, all elements in the above isothermal boundary information can be set to 0.

[0152] For ease of understanding, the following will be based on Figure 1 Taking the chip structure shown as an example, a brief explanation of the thermal simulation analysis scheme for the solid-state thermal conductivity physical process of the chip in this application will be given.

[0153] See Figure 4 , Figure 4 This is a flowchart illustrating a thermal simulation analysis scheme provided in an embodiment of this application, including the following steps 1-6:

[0154] 1. Obtain a thermal analysis model (such as a 3D chip thermal analysis model).

[0155] 2. Extract data from the thermal analysis model to obtain thermal analysis data, which includes heat dissipation capacity information of each node (such as thermal resistance matrix R and thermal capacity matrix D), location information of each node (set of node degrees of freedom, such as node coordinates and numbers), boundary node information (such as set of boundary nodes), temperature sensing point information (such as set of temperature sensing points), and heat source power information (such as unit heat source power distribution).

[0156] 3. The thermal analysis data is reorganized through matrix row and column transformations to obtain the reorganized result (i.e., the first processing result); the reorganized result includes the heat dissipation capacity information of the boundary nodes (such as the boundary submatrix K). 10 ), and the heat dissipation capacity information of non-boundary nodes (such as the non-boundary submatrix K). 11 ) and power density information of the heat source (such as the power density matrix P) density )wait.

[0157] 4. Reassemble the boundary temperature and power consumption parameters, and perform data separation on the reorganization result to obtain the separation result (i.e., the second processing result, which can be called the state space model system matrix). The separation result (state space model system matrix) may include the thermal capacity and thermal resistance information of each node (such as the mass matrix E and stiffness matrix A), the power consumption information of the boundary nodes and heat sources (such as the power consumption boundary matrix B), and the temperature information of the sensing point (such as the temperature selection matrix C).

[0158] 5. The separation results are reduced in order using the Krylov subspace moment matching method, resulting in multiple reduced matrices. The reduction parameters (such as the reduced matrix Q) used in the Krylov subspace moment matching method are determined after multiple block classical orthogonalization (BCGS) processes. r Let A be the mass matrix after the order reduction. r B is the reduced stiffness matrix. r This is the power consumption boundary matrix after order reduction. The reduced-order temperature-sensing selection matrix C r The transpose of , where r represents the dimension of the reduced matrix.

[0159] 6. Calculate the reduced-order matrix that describes the thermal characteristics of the thermal analysis model to obtain temperature analysis results for one or more nodes. The calculation process can be performed by loading a fast calculation script.

[0160] Optionally, for step 4 above, first power consumption information (i.e., power consumption parameters) describing the power consumption of each heat source can be obtained, and isothermal boundary information (i.e., boundary temperature) can be determined based on the first type of boundary conditions in the thermal analysis model. Then, the first power consumption information and the isothermal boundary information are fused to obtain second power consumption information. Finally, the data separation of the reshaping result obtained in step 3 is performed based on the second power consumption information. For example, the first power consumption information is a first power consumption vector U (which can be input by the user), the isothermal boundary information is an isothermal boundary vector T0, and the second power consumption information is a second power consumption vector Unnew. The isothermal boundary vector T0 is used as a pseudo power consumption term and appended to the end of the first power consumption vector U to obtain the second power consumption vector Unnew.

[0161] The data separation process satisfies the following chip steady-state heat conduction formula and chip transient heat conduction formula, wherein,

[0162] The steady-state thermal conductivity formula for a chip can be exemplarily expressed as follows:

[0163] The transient thermal conductivity formula for a chip can be exemplarily expressed as follows:

[0164] Among them, K 11 The non-boundary submatrix describing the heat dissipation capability of each non-boundary node can be renormalized based on the thermal resistance matrix, thermal capacity matrix, node information, and boundary node set; T is the temperature matrix describing each node of the at least one chip under steady state; P density The power density matrix describing the power density of each heat source can be determined based on the power distribution per unit heat source; K 10 The boundary submatrix describing the heat dissipation capacity of each boundary node can be determined based on the thermal resistance matrix, thermal capacity matrix, and boundary node set renormalization; [P] density -K10 and B are power consumption boundary matrices describing the thermal effects of boundary nodes and heat sources on the at least one chip; the heat dissipation capability includes heat capacity capability and thermal resistance capability; and U new is a power consumption vector matrix with a dummy power consumption term; E is a mass matrix describing the transient heat capacity capability of each node, which is obtained by separation based on the non-boundary sub-matrix and the boundary sub-matrix; A is a stiffness matrix describing the thermal resistance capability of each node, which is obtained by separation based on the non-boundary sub-matrix and the boundary sub-matrix; the second processing result includes the mass matrix E, the stiffness matrix A, the power consumption boundary matrix B and the temperature sensing selection matrix C; the temperature sensing selection matrix C describes one or more temperature sensing points selected for thermal simulation analysis.

[0165] It should be noted that the introduction of the constant temperature boundary causes the right-hand term of the equal sign to include two terms: the power consumption term and the boundary term, the user-configurable parameter U term cannot be separated and cannot meet the access requirement for the right-hand term of the reduced-order scheme. In the embodiments of the present application, the constant temperature boundary is used as a dummy power consumption term and connected to the rear section of the power consumption term, so that the right-hand term of the equal sign formally only includes the power consumption term, thereby meeting the access requirement for the right-hand term of the reduced-order scheme. Finally, the thermal simulation analysis method provided by the embodiments of the present application can support the reduction of the first-type boundary condition in addition to the third-type boundary condition, and meets the simulation requirements of constant temperature test scenarios such as cold plates.

[0166] Optionally, for the above step 5, the Krylov subspace moment matching method is used for order reduction, the order reduction frequency expansion point s (e.g., s=[0,1]) may be set first, and the expansion order moment (e.g., m=[1,3]) may be set. During order reduction, a krylov subspace is created to match the first r (r<<N) order moments of the original model, so that the dimension of the original model is reduced from order N to order r, and finally the matrix E is obtained r , A r , B r and E r is the reduced-order mass matrix, A r is the reduced-order stiffness matrix, B r is the reduced-order power consumption boundary matrix, is the transpose matrix of the reduced-order temperature sensing selection matrix C r . The frequency expansion point s may be set to different time lengths according to different service scenarios, and the expansion order may be set to different values according to different requirements for accuracy. In addition, the reduced-order matrix Q used in the Krylov subspace moment matching method is determined after multiple block classical orthogonalization BCGS processes, which can ensure that the reduced-order Ar and Er matrices are full rank, and further ensure the convergence of fast calculation.

[0167] For example, the process of order reduction using the Krylov subspace moment matching method may refer to, for example Figure 5 The calculation process shown includes:

[0168] (1) Construct a transient temperature analysis function.

[0169] (2) Perform a Laplace transform on the transient temperature analysis function.

[0170] (3) Create a Krylov subspace to match the first r-th moments of the original model.

[0171] (4) The order reduction is complete, and matrix E is obtained. r A r B r as well as

[0172] Where x represents the temperature set of all nodes, y represents the temperature set of all sensing points, s represents the reduced-order frequency expansion point, I represents the full-order system mass matrix, X represents the temperature matrix of all nodes, and Y represents the temperature matrix of all sensing points. Represents the stiffness matrix of the full-order system. Represents the power consumption boundary matrix. Let x represent the set of Krylov subspaces. r Let y represent the temperature matrix of the reduced subspace. r This represents the final temperature result matrix of the sensing point.

[0173] For example, the reduced-order matrix Q is determined after multiple block classical orthogonalization (BCGS) processes. The calculation process for the multiple block classical orthogonalization (BCGS) scheme can be referenced in the following formula:

[0174] Input: X = (X1, X2)

[0175] output: Q

[0176]

[0177] Y1 = X2 - Q1S1

[0178] Y1 = Q2R2

[0179] if need reorthogonalization

[0180]

[0181] Y2 = Q2 - Q1S2

[0182] Y2=Q3R3

[0183] Q = [Q1, Q2 or Q3].

[0184] Where X represents the two matrices required for the BCGS operation, X1 represents the matrix solution Q0 that satisfies orthogonality in the previous round, X2 represents the solution of the i-th frequency point equation (S[i]*EA)X2=-EX0, X0 is the solution of (S[i]*EA)X0=B, Q1 is equal to X1, S1 represents intermediate matrix 1, Y1 represents intermediate matrix 2, Q2 represents the Q matrix obtained after QR decomposition of Y1, R2 represents the R matrix obtained after QR decomposition of Y1, S2 represents the intermediate matrix after the second orthogonalization, Y2 represents the intermediate matrix after the Q2 matrix is ​​orthogonalized again, Q3 represents the Q matrix obtained after the third orthogonalization, and R3 represents the R matrix obtained after the third orthogonalization.

[0185] For example, the final reduced-order matrix can be represented by the following formula:

[0186] E r =Q T EQ;

[0187] A r =Q T AQ;

[0188] B r =Q T B;

[0189]

[0190] Q∈R m*n , rank(Q) = n.

[0191] Since the stiffness matrix A in the thermal analysis model is a negative definite matrix and the mass matrix E is a positive definite matrix, the reduced-order matrix Q obtained by multiple block classical orthogonalizations (BCGS) is orthogonal and has full column rank, making the reduced-order E... r A r It must be full rank, and subsequent inversion of the matrix yields a unique exact solution, with the calculation results converging. However, for a scheme that does not employ multiple block classical orthogonalizations of the BCGS, the reduced order E... r A r Since it is not full rank, the linear least squares solution can only be obtained through lstsq, which introduces bias, causes the solution to diverge, and results in instability.

[0192] Optionally, for step 6 above, after reducing the order of the thermal analysis model to obtain a matrix E that can describe the thermal characteristics. r A r B r as well as Then, the final temperature set matrix Tr of each sensing point can be calculated.

[0193] For example, the temperature set matrix Tr of each sensing point can satisfy the following formula:

[0194]

[0195] Where, x r This is the temperature matrix of the subspace after order reduction.

[0196] Regarding the effectiveness of the thermal simulation analysis scheme provided in this application's embodiments, please refer to... Figure 6 The transient temperature rise curve, assuming the above Figure 1 The structure shown includes 27 dynamic power consumption heat sources with a power cycle of 1ms. Power consumption P0 occurs during the first 0.5ms cycle, and zero power consumption occurs during the next 0.5ms cycle. Compared to existing finite element or finite volume method thermal simulation analysis schemes, the computational scale is reduced from 3.04 million degrees of freedom to 196 degrees of freedom. The single-step transient calculation time of the reduced-order model is less than 0.1ms, while the existing scheme takes approximately 300s, representing a speedup of more than 3 × 10⁻⁶ seconds. 6 The calculation accuracy is as follows: based on the embodiments of this application, the maximum temperature rise at the sensing point is 3.88℃, while based on the existing scheme, the maximum temperature rise at the sensing point is 4.05℃, with a relative deviation of 4.19%, and the two are in good agreement.

[0197] It should be noted that the thermal simulation analysis scheme provided in this application can be applied not only to a single chip or a module within a chip, but also to devices comprising multiple chips. For example, the thermal simulation analysis scheme provided in this application can be applied to a mobile phone (or tablet) coupled from a chip, with a natural convection cooling scenario, i.e., a third-type boundary condition. The application scenario changes from a single chip to an entire device, multiplying the number of heat sources and temperature sensing points, and making the heat exchange environment more complex. First, fluid-structure conjugate heat transfer calculations can be used to extract the gridded convection heat transfer coefficient and ambient temperature set of the mobile phone's outer surface, and then the thermal analysis model for the solid region can be reduced in order. During the calculation process, since the first-type boundary condition is empty, all elements in the isothermal boundary information can be set to 0.

[0198] The effectiveness of the thermal simulation analysis scheme provided in this application embodiment can be found in [reference]. Figure 7 , Figure 7 The temperature curves obtained based on this scheme and those obtained based on existing finite element or finite volume methods are shown, and the two are basically consistent. However, compared with existing finite element or finite volume method thermal simulation analysis schemes, the computational scale is reduced from 35 million degrees of freedom to a reduced 116 degrees of freedom, and the single-step transient calculation time is 0.01 ms, while the existing scheme takes about 600 s, resulting in a speedup of 6 × 10⁻⁶. 7The thermal simulation analysis scheme provided in this application can quickly complete calculations and analysis, meeting the need for rapid chip temperature prediction while ensuring the accuracy of the prediction.

[0199] Furthermore, this application also provides another thermal simulation analysis method for thermal analysis models, which can be applied to thermal analysis models with third-type boundary conditions, such as... Figure 8 As shown, the method may include, but is not limited to, the following steps: S801, obtaining a thermal analysis model, the thermal analysis model including boundary conditions, and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a third type of boundary condition. The third type of boundary condition is used to control the heat transfer coefficient and fluid temperature between the preset boundary of the at least one chip and the surrounding fluid in the thermal analysis model. S802, after reducing the order of the thermal analysis model using the Krylov subspace method, performing thermal simulation analysis on the reduced order result to obtain the temperature analysis results of one or more nodes in the at least one chip; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes. Figure 8 The method shown can be used as a reference. Figure 3 The relevant descriptions will not be repeated here.

[0200] The foregoing describes the method provided in this application. In order to facilitate the implementation of the above-described solutions in the embodiments of this application, the embodiments of this application also provide corresponding devices or equipment.

[0201] Based on the application scenarios described in this application and the thermal simulation analysis method for the thermal analysis model provided in this application, this application provides a thermal simulation analysis device for a thermal analysis model. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of the structure of a thermal simulation analysis device for a thermal analysis model provided in an embodiment of this application. The thermal simulation analysis device 1900 may include an acquisition unit 1901 and a processing unit 1902. The modules in the thermal simulation analysis device 1900 are communicatively connected. The functions of each unit are as follows:

[0202] The acquisition unit 1901 is used to acquire a thermal analysis model; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a first type of boundary conditions, which are used to control the preset boundary of the at least one chip to be maintained at a preset temperature in the thermal analysis model;

[0203] The processing unit 1902 is used to perform thermal simulation analysis on the thermal analysis model to obtain temperature analysis results of one or more nodes in the at least one chip.

[0204] In one possible implementation, performing thermal simulation analysis on the thermal analysis model includes:

[0205] The thermal analysis model is reduced in order to obtain the order reduction result;

[0206] The reduced-order result is calculated to obtain the temperature analysis results of one or more nodes in the at least one chip.

[0207] In one possible implementation, reducing the order of the thermal analysis model includes:

[0208] The thermal analysis model is reduced in order using the Krylov subspace method; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

[0209] In one possible implementation, reducing the order of the thermal analysis model includes:

[0210] The thermal analysis model is subjected to data separation based on the first type of boundary conditions to obtain a second processing result; the second processing result includes the thermal capacity and thermal resistance information of each node, the power consumption information of the boundary nodes and heat sources, and the temperature information of the sensing point.

[0211] The order of the second processing result is reduced.

[0212] In one possible implementation, data separation of the thermal analysis model based on the first type of boundary conditions includes:

[0213] Thermal analysis data is extracted from the thermal analysis model; the thermal analysis data includes one or more of the following: heat dissipation capacity information of each node in the at least one chip, location information of each node, boundary node information, temperature sensing point information, and heat source power information; the boundary node is a node in the at least one chip for which boundary conditions are applied.

[0214] The thermal analysis data is reorganized to obtain a first processing result; the first processing result includes one or more of the following: heat dissipation capacity information of boundary nodes, heat dissipation capacity information of non-boundary nodes, and power density information of heat sources.

[0215] Data separation is performed on the first processing result based on the first type of boundary conditions.

[0216] In one possible implementation, the data separation of the first processing result based on the first type of boundary conditions includes:

[0217] Obtain the first power consumption information describing the power consumption of each heat source;

[0218] Determine the isothermal boundary information based on the first type of boundary conditions;

[0219] The isothermal boundary information is fused with the first power consumption information to obtain the second power consumption information;

[0220] The first processing result is separated based on the second power consumption information.

[0221] In one possible implementation, when the first type of boundary condition is empty, all elements in the isothermal boundary information are 0.

[0222] In one possible implementation, the first power consumption information includes a first power consumption vector U, the isothermal boundary information includes an isothermal boundary vector T0, and the second power consumption information includes a second power consumption vector U. new The step of fusing the isothermal boundary information with the first power consumption information to obtain the second power consumption information includes:

[0223] The isothermal boundary vector T0 is used as a pseudo power consumption term and appended to the first power consumption vector U to obtain the second power consumption vector U. new .

[0224] In one possible implementation, the data separation of the first processing result based on the second power consumption information satisfies both the chip steady-state thermal conductivity formula and the chip transient thermal conductivity formula; wherein, the chip steady-state thermal conductivity formula includes:

[0225]

[0226] The transient thermal conductivity formula for chips includes:

[0227]

[0228] Among them, K 11 T is a non-boundary submatrix describing the heat dissipation capability of each non-boundary node; T is a temperature matrix describing each node of the at least one chip in steady state; P density This is a power density matrix describing the power density of each heat source; K 10 The boundary submatrix describes the heat dissipation capability of each boundary node; [P density -K 10 B and B are power consumption boundary matrices describing the thermal impact of boundary nodes and heat sources on the at least one chip; heat dissipation capability includes thermal capacity capability and thermal resistance capability; and U new It is a power vector matrix with pseudo-power consumption terms;

[0229] E is the mass matrix describing the transient thermal capacity of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; A is the stiffness matrix describing the thermal resistance of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; the second processing result includes the mass matrix E, the stiffness matrix A, the power consumption boundary matrix B, and the temperature sensing selection matrix C; the temperature sensing selection matrix C describes one or more temperature sensing points selected for thermal simulation analysis.

[0230] In one possible implementation, the Krylov subspace method uses the reduction parameter Q as the reduction matrix; the reduction of the second processing result by the Krylov subspace method satisfies the following formula:

[0231] E r =Q T EQ;

[0232] A r =Q T AQ;

[0233] B r =Q T B;

[0234]

[0235] Among them, E r Let A be the mass matrix after the order reduction. r B is the reduced stiffness matrix. r This is the power consumption boundary matrix after order reduction. The reduced-order temperature-sensing selection matrix C r The transpose of the matrix; r represents the dimension of the reduced matrix.

[0236] In one possible implementation, calculating the reduced-order result to obtain temperature analysis results for one or more nodes in the at least one chip includes:

[0237] Based on the reduced mass matrix E r Stiffness matrix A r Power consumption boundary matrix B r The transpose of the temperature-sensing selection matrix Perform calculations to determine the temperature set matrix Tr of one or more sensing points.

[0238] In one possible implementation, the temperature set matrix Tr satisfies the following formula:

[0239]

[0240] Where, x r This is the temperature matrix of the subspace after order reduction.

[0241] It should be noted that the functions of each functional unit / module in the thermal simulation analysis device of the thermal analysis model described in the embodiments of this application can be found in the relevant descriptions in the above method embodiments, and will not be repeated here.

[0242] Understandably, the specific descriptions of the acquisition unit 1901 and processing unit 1902 shown in the above device embodiments are merely examples. For the specific functions or execution steps of the acquisition unit 1901 and processing unit 1902, please refer to the description of any of the above method embodiments, which will not be detailed here.

[0243] The above describes the thermal simulation analysis device for the thermal analysis model according to embodiments of this application. The following describes the possible product forms of the thermal simulation analysis device for the thermal analysis model. It should be understood that any device possessing the above-described features... Figure 9 Any form of product containing the functional thermal simulation analysis device of the described thermal analysis model falls within the protection scope of the embodiments of this application. It should also be understood that the following description is merely illustrative and does not limit the product form of the thermal simulation analysis device of the thermal analysis model in the embodiments of this application to this extent.

[0244] In one possible implementation, the above Figure 9 In the thermal simulation analysis device of the thermal analysis model shown, the processing unit 1902 can be one or more processors; the acquisition unit 1901 can be a transceiver or a transceiver module. In this embodiment, the processor and the transceiver can be coupled, etc., and the connection method of the processor and the transceiver is not limited in this embodiment.

[0245] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a thermal simulation analysis device provided in an embodiment of this application. The thermal simulation analysis device 2000 includes at least one processor 2001 and at least one memory 2002. Optionally, it may also include at least one communication interface 2003.

[0246] The processor 2001 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.

[0247] The memory 2002 can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited to these. The memory can exist independently and be connected to the processor via a bus. The memory can also be integrated with the processor.

[0248] Communication Interface 2003 is used for communication with other devices or communication networks.

[0249] The memory 2002 can be used to store the application code that executes the above scheme, and its execution is controlled by the processor 2001. The processor 2001 can be used to execute the application code stored in the memory 2002.

[0250] It should be noted that the code stored in memory 2002 can execute the above. Figure 3 or Figure 8 The thermal simulation analysis method of the provided thermal analysis model, and the functions of each functional unit in the thermal simulation analysis equipment 2000 described in this application embodiment, can be found above. Figure 3 or Figure 8 The relevant descriptions in the method embodiments are not repeated here.

[0251] This application also provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, which, when executed by a computer, may implement some or all of the steps of any of the methods described in the above method embodiments.

[0252] This application also provides a computer program product, which includes instructions that, when executed by a computer, enable the computer to perform some or all of the steps of any of the methods described in the above method embodiments.

[0253] This application also provides a chip system including a processor for supporting the device in implementing the functions involved in any of the above embodiments, such as generating or processing information involved in the thermal simulation analysis method of the above thermal analysis model. In one possible design, the chip system further includes a memory for storing necessary program instructions and data of the device. This chip system may be composed of chips or may include chips and other discrete devices.

[0254] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0255] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0256] In the several embodiments provided in this application, it should be understood that the disclosed devices or apparatuses can be implemented in other ways. For example, the device or apparatus embodiments described above are merely illustrative. For instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices, apparatuses, or units may be electrical or other forms.

[0257] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0258] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0259] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory, or random access memory.

[0260] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A thermal simulation analysis method for a thermal analysis model, characterized in that, The method includes: A thermal analysis model is obtained; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a first type of boundary conditions, which are used to control the preset boundary of the at least one chip to be maintained at a preset temperature in the thermal analysis model; Thermal simulation analysis is performed on the thermal analysis model to obtain temperature analysis results for one or more nodes in the at least one chip.

2. The method as described in claim 1, characterized in that, The thermal simulation analysis of the thermal analysis model includes: The thermal analysis model is reduced in order to obtain the order reduction result; The reduced-order result is calculated to obtain the temperature analysis results of one or more nodes in the at least one chip.

3. The method as described in claim 2, characterized in that, The process of reducing the order of the thermal analysis model includes: The thermal analysis model is reduced in order using the Krylov subspace method; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

4. The method as described in claim 2 or 3, characterized in that, The process of reducing the order of the thermal analysis model includes: The thermal analysis model is subjected to data separation based on the first type of boundary conditions to obtain a second processing result; the second processing result includes the thermal capacity and thermal resistance information of each node, the power consumption information of the boundary nodes and heat sources, and the temperature information of the sensing point. The order of the second processing result is reduced.

5. The method as described in claim 4, characterized in that, Data separation of the thermal analysis model based on the first type of boundary conditions includes: Thermal analysis data is extracted from the thermal analysis model; the thermal analysis data includes one or more of the following: heat dissipation capacity information of each node in the at least one chip, location information of each node, boundary node information, temperature sensing point information, and heat source power information; the boundary node is a node in the at least one chip for which boundary conditions are applied. The thermal analysis data is reorganized to obtain a first processing result; the first processing result includes one or more of the following: heat dissipation capacity information of boundary nodes, heat dissipation capacity information of non-boundary nodes, and power density information of heat sources. Data separation is performed on the first processing result based on the first type of boundary conditions.

6. The method as described in claim 5, characterized in that, The step of separating the data from the first processing result based on the first type of boundary conditions includes: Obtain the first power consumption information describing the power consumption of each heat source; Determine the isothermal boundary information based on the first type of boundary conditions; The isothermal boundary information is fused with the first power consumption information to obtain the second power consumption information; The first processing result is separated based on the second power consumption information.

7. The method as described in claim 6, characterized in that, When the first type of boundary condition is empty, all elements in the isothermal boundary information are 0.

8. The method according to any one of claims 6-7, characterized in that, The first power consumption information includes a first power consumption vector U, the isothermal boundary information includes an isothermal boundary vector T0, and the second power consumption information includes a second power consumption vector U. new ; The step of fusing the isothermal boundary information with the first power consumption information to obtain the second power consumption information includes: The isothermal boundary vector T0 is used as a pseudo power consumption term and appended to the first power consumption vector U to obtain the second power consumption vector U. new .

9. The method as described in claim 8, characterized in that, The data separation of the first processing result based on the second power consumption information satisfies both the chip steady-state thermal conductivity formula and the chip transient thermal conductivity formula; wherein, the chip steady-state thermal conductivity formula includes: The transient thermal conductivity formula for chips includes: Among them, K 11 T is a non-boundary submatrix describing the heat dissipation capability of each non-boundary node; T is a temperature matrix describing each node of the at least one chip in steady state; P density This is a power density matrix describing the power density of each heat source; K 10 The boundary submatrix describes the heat dissipation capability of each boundary node; [P density -K 10 B and B are power consumption boundary matrices describing the thermal impact of boundary nodes and heat sources on the at least one chip; heat dissipation capability includes thermal capacity capability and thermal resistance capability; and U new It is a power vector matrix with pseudo-power consumption terms; E is the mass matrix describing the transient thermal capacity of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; A is the stiffness matrix describing the thermal resistance of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; the second processing result includes the mass matrix E, the stiffness matrix A, the power consumption boundary matrix B, and the temperature sensing selection matrix C; the temperature sensing selection matrix C describes one or more temperature sensing points selected for thermal simulation analysis.

10. The method as described in claim 9, characterized in that, The Krylov subspace method uses the reduction parameter Q as the reduction matrix; the reduction of the second processing result by the Krylov subspace method satisfies the following formula: E r =Q T EQ; A r =Q T AQ; B r =Q T B; Among them, E r Let A be the mass matrix after the order reduction. r B is the reduced stiffness matrix. r This is the power consumption boundary matrix after order reduction. The reduced-order temperature-sensing selection matrix C r The transpose of the matrix; r represents the dimension of the reduced matrix.

11. The method as described in claim 10, characterized in that, The calculation of the order reduction result to obtain the temperature analysis results of one or more nodes in the at least one chip includes: Based on the reduced mass matrix E r Stiffness matrix A r Power consumption boundary matrix B r The transpose of the temperature-sensing selection matrix Perform calculations to determine the temperature set matrix Tr of one or more sensing points.

12. The method as described in claim 11, characterized in that, The temperature set matrix Tr satisfies the following formula: Where, x r This is the temperature matrix of the subspace after order reduction.

13. A thermal simulation analysis device for a thermal analysis model, characterized in that, include: An acquisition unit is used to acquire a thermal analysis model; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a first type of boundary conditions, which are used to control the preset boundary of the at least one chip to be maintained at a preset temperature in the thermal analysis model; The processing unit is used to perform thermal simulation analysis on the thermal analysis model to obtain temperature analysis results for one or more nodes in the at least one chip.

14. The apparatus as claimed in claim 13, characterized in that, The thermal simulation analysis of the thermal analysis model includes: The thermal analysis model is reduced in order to obtain the order reduction result; The reduced-order result is calculated to obtain the temperature analysis results of one or more nodes in the at least one chip.

15. The apparatus as claimed in claim 14, characterized in that, The process of reducing the order of the thermal analysis model includes: The thermal analysis model is reduced in order using the Krylov subspace method; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

16. The apparatus as claimed in claim 14 or 15, characterized in that, The process of reducing the order of the thermal analysis model includes: The thermal analysis model is subjected to data separation based on the first type of boundary conditions to obtain a second processing result; the second processing result includes the thermal capacity and thermal resistance information of each node, the power consumption information of the boundary nodes and heat sources, and the temperature information of the sensing point. The order of the second processing result is reduced.

17. The apparatus as claimed in claim 16, characterized in that, Data separation of the thermal analysis model based on the first type of boundary conditions includes: Thermal analysis data is extracted from the thermal analysis model; the thermal analysis data includes one or more of the following: heat dissipation capacity information of each node in the at least one chip, location information of each node, boundary node information, temperature sensing point information, and heat source power information; the boundary node is a node in the at least one chip for which boundary conditions are applied. The thermal analysis data is reorganized to obtain a first processing result; the first processing result includes one or more of the following: heat dissipation capacity information of boundary nodes, heat dissipation capacity information of non-boundary nodes, and power density information of heat sources. Data separation is performed on the first processing result based on the first type of boundary conditions.

18. The apparatus as claimed in claim 17, characterized in that, The step of separating the data from the first processing result based on the first type of boundary conditions includes: Obtain the first power consumption information describing the power consumption of each heat source; Determine the isothermal boundary information based on the first type of boundary conditions; The isothermal boundary information is fused with the first power consumption information to obtain the second power consumption information; The first processing result is separated based on the second power consumption information.

19. The apparatus as claimed in claim 18, characterized in that, When the first type of boundary condition is empty, all elements in the isothermal boundary information are 0.

20. The apparatus as claimed in any one of claims 18-19, characterized in that, The first power consumption information includes a first power consumption vector U, the isothermal boundary information includes an isothermal boundary vector T0, and the second power consumption information includes a second power consumption vector U. new ; The step of fusing the isothermal boundary information with the first power consumption information to obtain the second power consumption information includes: The isothermal boundary vector T0 is used as a pseudo power consumption term and appended to the first power consumption vector U to obtain the second power consumption vector U. new .

21. The method as described in claim 20, characterized in that, The data separation of the first processing result based on the second power consumption information satisfies both the chip steady-state thermal conductivity formula and the chip transient thermal conductivity formula; wherein, the chip steady-state thermal conductivity formula includes: The transient thermal conductivity formula for chips includes: Among them, K 11 T is a non-boundary submatrix describing the heat dissipation capability of each non-boundary node; T is a temperature matrix describing each node of the at least one chip in steady state; P density This is a power density matrix describing the power density of each heat source; K 10 The boundary submatrix describes the heat dissipation capability of each boundary node; [P density -K 10 B and B are power consumption boundary matrices describing the thermal impact of boundary nodes and heat sources on the at least one chip; heat dissipation capability includes thermal capacity capability and thermal resistance capability; and U new It is a power vector matrix with pseudo-power consumption terms; E is the mass matrix describing the transient thermal capacity of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; A is the stiffness matrix describing the thermal resistance of each node, obtained by separating the non-boundary sub-matrix and the boundary sub-matrix; the second processing result includes the mass matrix E, the stiffness matrix A, the power consumption boundary matrix B, and the temperature sensing selection matrix C; the temperature sensing selection matrix C describes one or more temperature sensing points selected for thermal simulation analysis.

22. The method as described in claim 21, characterized in that, The Krylov subspace method uses the reduction parameter Q as the reduction matrix; the reduction of the second processing result by the Krylov subspace method satisfies the following formula: E r =Q T EQ; A r =Q T AQ; B r =Q T B; Among them, E r Let A be the mass matrix after the order reduction. r B is the reduced stiffness matrix. r This is the power consumption boundary matrix after order reduction. The reduced-order temperature-sensing selection matrix C r The transpose of the matrix; r represents the dimension of the reduced matrix.

23. The method as described in claim 22, characterized in that, The calculation of the order reduction result to obtain the temperature analysis results of one or more nodes in the at least one chip includes: Based on the reduced mass matrix E r Stiffness matrix A r Power consumption boundary matrix B r The transpose of the temperature-sensing selection matrix Perform calculations to determine the temperature set matrix Tr of one or more sensing points.

24. The method as described in claim 23, characterized in that, The temperature set matrix Tr satisfies the following formula: Where, x r This is the temperature matrix of the subspace after order reduction.

25. A thermal simulation analysis method for a thermal analysis model, characterized in that, The method includes: A thermal analysis model is obtained; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a third type of boundary conditions, which are used to control the heat transfer coefficient and fluid temperature between the preset boundary of the at least one chip and the surrounding fluid in the thermal analysis model. After reducing the order of the thermal analysis model using the Krylov subspace method, thermal simulation analysis is performed on the reduced order results to obtain the temperature analysis results of one or more nodes in the at least one chip; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

26. A thermal simulation analysis device for a thermal analysis model, characterized in that, include: An acquisition unit is used to acquire a thermal analysis model; the thermal analysis model includes boundary conditions and one or more of the following: geometric model information of at least one chip, heat source location information, and temperature sensing point location information; the boundary conditions include a third type of boundary conditions, which are used to control the heat transfer coefficient and fluid temperature between the preset boundary of the at least one chip and the surrounding fluid in the thermal analysis model. The processing unit is used to reduce the order of the thermal analysis model using the Krylov subspace method, and then perform thermal simulation analysis on the reduced order result to obtain the temperature analysis results of one or more nodes in the at least one chip; the reduction parameters used in the Krylov subspace method are determined after multiple block classical orthogonalization (BCGS) processes.

27. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed, implement the method as described in any one of claims 1-12 or 25.

28. A computer program, characterized in that, The computer program includes instructions that, when executed, implement the method as described in any one of claims 1-12 or 25.

Images