An inter-chip interconnect hierarchical accurate modeling simulation method for multi-node computing system

Abstract

The application is a kind of inter-chip interconnection hierarchical precise modeling simulation method for multi-node computing system, belonging to the field of computer architecture and integrated circuit design automation. The method firstly acquires inter-chip interconnection topology information, protocol-level inter-chip interconnection communication command stream and interconnection parameter configuration space, and determines the current interconnection parameter configuration from the interconnection parameter configuration space, then establishes the communication port cycle-level model and the switch structure and link transmission event-driven model according to the topology information and the current configuration respectively, connects each modeling object through the first-in-first-out queue, constructs a unified simulation framework, runs the simulation with the protocol-level inter-chip interconnection communication command stream as the simulation excitation, records the simulation results and calculates the performance indicators, finally iteratively selects a new configuration based on the interconnection parameter configuration and the corresponding performance indicators until the optimal parameter configuration is output. The application takes into account the simulation accuracy and efficiency, and improves the simulation scalability under large-scale multi-node system.

Description

Technical Field

[0001] This invention relates to the field of computer architecture and integrated circuit design automation technology, specifically to a hierarchical and accurate modeling and simulation method for inter-chip interconnects in multi-node computing systems, which is used to perform hierarchical modeling, performance evaluation and parameter selection of communication ports, switching structures, link transmission and related scheduling and resource allocation behaviors in inter-chip interconnects. Background Technology

[0002] As target workloads continue to grow, computing systems are gradually evolving from single-chip architectures to multi-chip collaborative computing architectures. In multi-node computing systems, multiple computing chips exchange data through inter-chip interconnects. The bandwidth, latency, scheduling strategies, buffer resources, and topology of these inter-chip interconnects directly affect the overall system performance.

[0003] In the design of multi-node computing systems, simulation methods are typically used to evaluate the performance of inter-chip interconnect architectures. However, existing simulation methods generally suffer from the following problems:

[0004] First, some simulation methods use overly simplified analysis models or packet-level abstractions, making it difficult to characterize the key timing behaviors in communication ports, link layers, and protocol layers. This results in simulation results that fail to accurately reflect the actual operating characteristics of the underlying inter-chip interconnects.

[0005] Secondly, some simulation methods adopt a global periodic accurate modeling approach, which can improve local timing accuracy, but will bring high simulation overhead in multi-node, large-scale concurrent communication scenarios, making it difficult to balance simulation accuracy and system scale.

[0006] Third, the design of inter-chip interconnect architecture often requires consideration of multiple factors such as data fragmentation method, scheduling strategy, buffer resources, number of virtual channels, port configuration and switching structure parameters. If there is a lack of simulation foundation that balances accuracy and efficiency, it will be difficult to support subsequent architecture parameter evaluation and optimization.

[0007] Therefore, there is an urgent need for a hierarchical, precise modeling and simulation method that employs differentiated modeling precision for communication ports, switching structures, link transmission, and related scheduling and resource allocation behaviors in inter-chip interconnects, while also balancing simulation accuracy and scalability. Summary of the Invention

[0008] The purpose of this invention is to provide a hierarchical and accurate modeling and simulation method for inter-chip interconnects in multi-node computing systems, addressing the problems of insufficient simulation accuracy, excessive overhead of global periodic accurate modeling, and difficulty in supporting subsequent architecture parameter evaluation in existing technologies. Its core lies in: employing differentiated simulation advancement mechanisms based on the timing sensitivity and scale characteristics of different components of the inter-chip interconnect; performing periodic-level accurate modeling of protocol processing, buffering, and pipeline behavior within communication ports; performing event-driven modeling of the switching structure and link transmission process; and connecting each modeling object through a first-in-first-out queue to form a unified simulation framework driven by protocol-level inter-chip interconnect communication command flow. Based on this, the simulation framework is repeatedly invoked for performance evaluation of the candidate value space for interconnect parameter configurations, and the optimal parameter configuration is selected based on the evaluation results.

[0009] The technical solution of the present invention is as follows:

[0010] A hierarchical and accurate modeling and simulation method for inter-chip interconnection in a multi-node computing system, wherein the multi-node computing system includes multiple computing nodes, communication ports, switching structures, and link transmission modules; the method includes the following steps:

[0011] Step 1, Input Configuration: Obtain the inter-chip interconnection topology information, protocol-level inter-chip interconnection communication command stream, and interconnection parameter configuration of the target computing system to be simulated. The inter-chip interconnection topology information includes the number and identifiers of computing nodes, switching structure identifiers, inter-chip communication port mapping relationships, and interconnection connection relationships. The protocol-level inter-chip interconnection communication command stream includes multiple transactions to be transmitted, each transaction including at least the source node identifier, destination node identifier, transaction type, transaction length, and corresponding timing information, used to characterize the communication transaction sequence to be simulated. The interconnection parameter configuration includes one or more of the following: data fragmentation parameters, scheduling parameters, buffer parameters, virtual channel parameters, and link parameters. Select a set of configurations from the interconnection parameter configuration space as the model configuration for the current round of simulation.

[0012] Step 2, Periodic Modeling of Communication Ports: Based on the inter-chip communication port mapping relationship and the current interconnection parameter configuration, establish a transmit path modeling instance and a receive path modeling instance for each inter-chip communication port. The transmit path modeling instance includes a protocol packetization module and a transmit buffer module, and the receive path modeling instance includes a receive buffer module, a protocol unpacking module, and a completion processing module. The data packet partitioning method for the transaction to be transmitted is determined according to the data fragmentation parameters. The transmit buffer module and receive buffer module are configured according to the buffer parameters and virtual channel parameters. The scheduling behavior of each module is configured according to the scheduling parameters, and corresponding processing delays are set for each module. Each module advances its state at the clock cycle granularity, performing periodic-level precise modeling of the processing delay, queuing, backpressure, and pipeline behavior within the module.

[0013] Step 3, Event-Driven Modeling of Switching Structure and Link Transmission: Event-driven modeling is performed on the switching structure and link transmission in the inter-chip interconnect. The switching structure modeling object receives data packets submitted by multiple sending path modeling instances and forwards them to the corresponding link transmission modeling object or receiving path modeling instance based on the destination node identifier, routing result, output port availability status, and arbitration result. The link transmission modeling object determines the data packet transmission completion time based on link bandwidth, link propagation delay, and data packet length. The switching structure modeling object and the link transmission modeling object update their state only when a preset event occurs.

[0014] Step 4, Simulation Framework Construction: The transmitting path modeling instance, switching structure modeling object, link transmission modeling object, and receiving path modeling instance are decoupled and connected using a first-in-first-out (FIFO) queue, forming a producer-consumer simulation pipeline. The transmitting path modeling instance and receiving path modeling instance corresponding to each inter-chip communication port are mapped to independent transmitting and receiving path tasks, respectively. The switching structure modeling object and link transmission modeling object are mapped to transmission tasks shared by multiple communication port tasks. The transmitting path task writes the generated data packet into the corresponding FIFO queue. The transmission task reads the data packet, completes arbitration, forwarding, and link transmission, and then writes it into the FIFO queue corresponding to the destination communication port. The receiving path task reads and processes the data packet, forming an end-to-end data transmission simulation process.

[0015] Step 5, Run the simulation and record the results: The simulation framework is constructed using the protocol-level inter-chip interconnection communication command stream as the simulation stimulus input, and the simulation is run using the current interconnection parameter configuration. For each transaction to be transmitted in the communication command stream, the sending path task reads the corresponding transaction according to the generation time of each transaction to be transmitted, and divides the transaction to be transmitted into one or more data packets according to the transaction length and data fragmentation parameters. Then, it sequentially executes protocol packing, sending buffer, switching and link transmission, receiving buffer, protocol unpacking, and completion processing. The simulation result recording module records the generation time and completion time of each transaction to be transmitted, the time when each data packet enters and leaves each modeling module, and the occupancy status of each buffer module. When all transactions to be transmitted are completed, or when the preset simulation termination condition is met, the current round of simulation ends.

[0016] Step 6, Performance Indicator Statistics and Evaluation: The performance indicator statistics module calculates the performance indicators corresponding to the current interconnect parameter configuration based on the time records and resource status records output by the simulation result recording module, and generates simulation evaluation results accordingly. The performance indicators include one or more of throughput, average latency, tail latency, buffer resource utilization, and multi-communication flow fairness. The simulation evaluation results include one or more of the individual performance indicators and a comprehensive evaluation value obtained from a combination of multiple performance indicators, and establishes a correspondence between the current interconnect parameter configuration and the simulation evaluation results.

[0017] Step 7, Parameter Screening and Optimization: The parameter screening and evaluation module iteratively determines the interconnect parameter configurations to be evaluated based on the interconnect parameter configuration space and the obtained simulation evaluation results. First, the interconnect parameter configuration space is screened according to the preset hardware feasibility constraints, eliminating parameter combinations that do not meet the constraints. Then, at least one initial interconnect parameter configuration is selected from the remaining parameter combinations, and steps 2 to 6 are executed respectively to obtain the corresponding simulation evaluation results. A surrogate model is constructed based on the evaluated interconnect parameter configurations and their simulation evaluation results, and the next set of interconnect parameter configurations to be evaluated is determined from the configurations that have not yet been evaluated through the acquisition function. Steps 2 to 6 are executed again for it, and the surrogate model is updated using the newly obtained simulation evaluation results. The above parameter selection, simulation evaluation, and surrogate model update process is repeated until the preset number of iterations, simulation budget, or convergence condition is reached, and the interconnect parameter configuration with the optimal comprehensive evaluation value is output from the evaluated interconnect parameter configurations.

[0018] Furthermore, in step 2, each module advances its state at the granularity of a clock cycle. Specifically, in each clock cycle, each processing module first determines whether the current processing is complete: if the current processing is complete and there is available space in the downstream FIFO queue, the processing result is written to the corresponding FIFO queue and the next transaction processing begins; if the downstream FIFO queue is full, the current processing state is maintained and backpressure information is propagated upstream; if the current processing is not yet complete, the subsequent clock cycles are occupied.

[0019] Furthermore, the preset events in step 3 include one or more of the following: data packet arrival, output port resource release, credit resource update, arbitration condition satisfaction, and transmission completion.

[0020] Furthermore, in step 6, the performance indicators include one or more of throughput, average latency, tail latency, buffer resource usage, and multi-communication flow fairness; the simulation evaluation results include one or more of the various performance indicators and the comprehensive evaluation value obtained by combining multiple performance indicators.

[0021] Furthermore, the parameter configuration space filtering process in step 7 is implemented using a constraint pruning method, an adaptive search method, or a combination of both.

[0022] Furthermore, when the target computing system is a fully connected inter-chip interconnect topology, the computing nodes are directly connected through point-to-point links, excluding the switching structure; the data packets output by the sending path task directly enter the input queue corresponding to the link transmission module, and the link transmission module, as a shared transmission task, completes event-driven modeling based on the link bandwidth and transmission delay; the receiving side communication port performs receive buffering, protocol unpacking, and processing.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. Periodic precise modeling is used for time-sensitive communication ports, while event-driven modeling is used for large-scale switching structures and link transmissions. Differentiated modeling balances simulation accuracy and simulation efficiency.

[0025] 2. By decoupling the modules through a first-in-first-out queue, a producer-consumer simulation pipeline is constructed, reducing global synchronization overhead and improving the simulation scalability of large-scale multi-node systems;

[0026] 3. Based on the data fragmentation parameters, the protocol-level communication transactions are converted into data packets, and the protocol packing, buffering, arbitration, forwarding, link transmission and protocol unpacking processes are simulated layer by layer to establish the mapping relationship between upper-layer communication transactions and lower-layer interconnection behavior;

[0027] 4. It uniformly records the time information and resource usage information of transactions and data packets in different modeling modules, and can output performance indicators such as throughput, average latency, tail latency, buffer usage, and fairness;

[0028] 5. Feed back the interconnection parameter configuration and corresponding simulation evaluation results to the parameter screening and evaluation module, so that the parameter screening process can iteratively call the simulation framework and update the configuration to be evaluated, reducing the number of simulations required to traverse all parameter combinations. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the overall process of the method of the present invention, which is used to illustrate the process of input configuration, periodic modeling of communication ports, event-driven modeling of switching structure and link transmission, simulation framework construction, simulation and result recording, performance index statistics and evaluation, and parameter screening and optimization.

[0030] Figure 2 This is a schematic diagram of the inter-chip interconnection hardware structure and its software task mapping in this invention, wherein... Figure 2 (a) shows the modeling objects of communication ports, switching structures, and link transmissions of different computing nodes in the hardware architecture. Figure 2(b) shows the functional mapping of the hardware module in the software, where each port includes parallel transmit path tasks and receive path tasks in the software, and the switching structure and link transmission are shared transmission tasks for the ports to which they are connected in the software.

[0031] Figure 3 This is a schematic diagram of the communication port periodic precise pipeline and queue decoupling relationship in the present invention, used to show the various processing modules inside the communication port and the process of forming a simulated pipeline through the connection of the first-in-first-out queue;

[0032] Figure 4 This is a schematic diagram of event-driven modeling of the switching structure and link transmission in this invention, used to illustrate how the switching structure and link transmission interact with multiple inter-chip communication port tasks and complete arbitration, queuing and transmission behavior modeling;

[0033] Figure 5 This is a schematic diagram of performance index statistics and candidate parameter evaluation in this invention, used to illustrate the process of statistically analyzing performance indexes based on simulation results and evaluating and screening candidate parameter combinations. Detailed Implementation

[0034] The present invention will be further described below with reference to specific embodiments. It should be understood that the following embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0035] This invention provides a hierarchical and accurate modeling and simulation method for inter-chip interconnects in multi-node computing systems. The overall process is as follows: Figure 1 As shown, the simulation first acquires the inter-chip interconnection topology information, protocol-level inter-chip interconnection communication command stream, and interconnection parameter configuration space, and determines the current interconnection parameter configuration from the interconnection parameter configuration space. Then, based on the topology information and the current configuration, a communication port periodic model, a switching structure, and a link transmission event-driven model are established respectively, and each modeling object is connected through a first-in-first-out queue to construct a unified simulation framework. Then, the simulation is run with the protocol-level inter-chip interconnection communication command stream as the simulation stimulus, the simulation results are recorded, and the performance indicators are calculated. Finally, based on the interconnection parameter configuration and the corresponding performance indicators, new configurations are iteratively selected until the optimal parameter configuration is output.

[0036] Example 1: A hierarchical and accurate modeling and simulation method for a 32-node switched inter-chip interconnect system.

[0037] In this embodiment, the target computing system is a switched inter-chip interconnect system, comprising 32 computing nodes, each configured with one inter-chip communication port. All 32 inter-chip communication ports are connected to a single switching structure, forming a 32-port switched inter-chip interconnect system. The link layer and transport layer of the target system adopt an Ethernet-based inter-chip interconnect protocol. Communication requests generated by upper-layer computing nodes are represented in AXI transaction format, and after protocol adaptation and encapsulation in the transmission path, they are converted into data packets suitable for transmission over the inter-chip interconnect. The modeling of each module is described using Python, but other languages ​​can also be used.

[0038] The inter-chip interconnection topology information includes: node identifiers of 32 computing nodes, inter-chip communication port identifiers corresponding to each node, switching structure identifiers, and the connection relationships between node communication ports and switching structures. The input communication traffic used for simulation is a protocol-level inter-chip interconnection communication command stream; this embodiment uses the AXI protocol.

[0039] Step 1, enter the configuration.

[0040] First, obtain the inter-chip interconnection topology information, protocol-level inter-chip interconnection communication command stream, and interconnection parameter configuration of the target computing system to be simulated. The inter-chip interconnection topology information is as follows: Figure 2 As shown in (a), the number of computing nodes N is 32. The inter-chip communication port mapping relationship is that each computing node is configured with one inter-chip communication port. The interconnection relationship is that the 32 inter-chip communication ports are interconnected through a switching structure. The protocol-level inter-chip interconnection communication command stream includes multiple transactions to be transmitted. Each transaction includes at least the source node identifier, destination node identifier, transaction type, transaction length, and corresponding timing information. The interconnection parameter configuration includes one or more of the following: data fragmentation parameters, scheduling parameters, buffer parameters, virtual channel parameters, and link parameters. Among them, the topology information is used to determine the number and connection relationship of each modeling instance. The communication command stream serves as the simulation stimulus when running the simulation. The interconnection parameter configuration is used to configure the data fragmentation method, scheduling behavior, buffer resources, number of virtual channels, and link transmission characteristics of each modeling module.

[0041] Step 2, Periodic modeling of communication ports.

[0042] Based on the inter-chip communication port mapping relationship and the current interconnection parameter configuration, a transmit path modeling instance and a receive path modeling instance are established for each inter-chip communication port. The transmit path modeling instance includes a protocol packetization module and a transmit buffer module, and the receive path modeling instance includes a receive buffer module, a protocol unpacking module, and a completion processing module. The data packet partitioning method for the transaction to be transmitted is determined according to the data fragmentation parameters. The transmit buffer module and receive buffer module are configured according to the buffer parameters and virtual channel parameters. The scheduling behavior of each module is configured according to the scheduling parameters, and corresponding processing delays are set for each module. Each module advances its state at the clock cycle granularity, and periodic-level precise modeling of the processing delay, queuing, backpressure, and pipeline behavior within the module is performed.

[0043] In this example, a transmit path modeling instance and a receive path modeling instance are established for each inter-chip communication port based on the topology information. The transmit path modeling instance includes a SoC boundary scheduling module, an AXI transaction adaptation module, a MAC frame encapsulation module, and a transmit buffer module, wherein the AXI transaction adaptation module and the MAC frame encapsulation module together constitute the protocol packing module. The receive path modeling instance includes a receive buffer module, a MAC frame parsing module, an AXI transaction recovery module, and a completion processing module, wherein the MAC frame parsing module and the AXI transaction recovery module together constitute the protocol unpacking module. Each processing module adopts periodic-level precise modeling and maintains its own processing status, functional configuration parameters, and processing latency parameters: the functional configuration parameters are used to configure the current interconnect parameters, including data fragmentation method, buffer capacity, number of virtual channels, and scheduling strategy, etc.; the processing latency parameter represents the number of clock cycles required for the module to complete one processing operation.

[0044] In each clock cycle, each processing module first determines whether the current processing is complete: if the current processing is complete and there is available space in the downstream FIFO queue, the processing result is written to the corresponding FIFO queue and the next transaction processing begins; if the downstream FIFO queue is full, the current processing state is maintained and backpressure information is propagated upstream; if the current processing is not yet complete, it continues to occupy subsequent clock cycles. This allows for precise periodic modeling of the protocol processing, buffer management, and pipeline behavior within the communication port.

[0045] Step 3: Event-driven modeling of the switching structure and link transmission.

[0046] Event-driven modeling is used for the switching structure and link transmission in inter-chip interconnects. The switching structure modeling object receives data packets submitted by multiple sending path modeling instances and forwards them to the corresponding link transmission modeling object or receiving path modeling instance based on the destination node identifier, routing result, output port availability status, and arbitration result. The link transmission modeling object determines the data packet transmission completion time based on link bandwidth, link propagation delay, and data packet length. Both the switching structure modeling object and the link transmission modeling object update their states only when preset events occur. These preset events include one or more of the following: data packet arrival, output port resource release, credit resource update, arbitration condition fulfillment, and transmission completion.

[0047] Based on the topology connection relationship, a switching structure and a link transmission modeling object are established. In this embodiment, the two are mapped together as a shared transmission modeling object. The shared transmission modeling object maintains: (1) an input first-in-first-out queue and an output first-in-first-out queue; (2) a virtual output queue, that is, the incoming data packets are classified and queued according to the destination output port to avoid head-of-line blocking; (3) the output port status; (4) the credit resource status; and (5) the pending event queue, which is used to store pending events in an orderly manner according to the time of event occurrence. During simulation, the status of the most recent event is taken each time.

[0048] After the data packet encapsulation is completed in the transmission path modeling instance, the data packet is written into the corresponding input FIFO queue. The shared transmission modeling object performs arbitration, switching, and link transmission on the data packets in the input queue based on the destination node identifier, routing result, output port resource status, and arbitration result carried by the data packet. This embodiment uses a round-robin arbitration strategy; priority arbitration or weighted round-robin arbitration can also be used in other implementations. The link transmission completion time corresponding to the data packet is calculated based on the data packet length, link bandwidth, and propagation delay. The switching structure and link transmission do not use periodic updates; instead, their internal states are updated when events such as data packet arrival, output port resource release, credit resource update, arbitration condition satisfaction, or link transmission completion occur. After the data packet completes link transmission, it is written into the corresponding output FIFO queue. By using an event-driven approach, only the changed data structures are updated, without traversing all switching ports and link states every clock cycle, thereby reducing the simulation overhead after system scaling.

[0049] Step 4: Simulation framework construction.

[0050] The transmit path modeling instance, switch structure modeling object, link transmission modeling object, and receive path modeling instance are decoupled using a first-in-first-out (FIFO) queue, forming a producer-consumer simulation pipeline. The transmit path modeling instance and receive path modeling instance corresponding to each inter-chip communication port are mapped to independent transmit path tasks and receive path tasks, respectively. The switch structure modeling object and link transmission modeling object are mapped to transmission tasks shared by multiple communication port tasks, such as... Figure 2 As shown in (b), the sending path task writes the generated data packet into the corresponding first-in-first-out queue, the transmission task reads the data packet and writes it into the first-in-first-out queue corresponding to the destination communication port after completing arbitration, forwarding and link transmission, and the receiving path task reads and processes the data packet, forming an end-to-end data transmission simulation process.

[0051] like Figure 3 As shown, the communication port internally includes a protocol packetization module, a transmit buffer module, a receive buffer module, a protocol depacketization module, and a completion processing module. Each processing module progresses at the clock cycle granularity and is decoupled through a first-in-first-out queue, forming a producer-consumer type internal simulation pipeline for the communication port; as shown... Figure 4 As shown, multiple sending path tasks submit data packets to the switching structure and link transmission module via their respective input FIFO queues (i.e., the first FIFO queue). This module completes queuing, arbitration, forwarding, and link transmission under the triggering of events such as data packet arrival, arbitration condition fulfillment, transmission completion, and resource release, and distributes the data to each receiving path task via the output FIFO queue (i.e., the second FIFO queue). Accordingly, the sending path modeling instance, the shared transmission modeling object, and the receiving path modeling instance are decoupled and connected through FIFO queues, and each modeling instance is mapped to a corresponding software task, constructing a producer-consumer unified simulation framework. The output of each sending path modeling instance is connected to the shared transmission modeling object through the first FIFO queue, and the output of the shared transmission modeling object is connected to the receiving path modeling instance corresponding to the destination communication port through the second FIFO queue, forming the following data transmission relationship: Sending path modeling instance → First FIFO queue → Shared transmission modeling object → Second FIFO queue → Receiving path modeling instance.

[0052] For each inter-chip communication port, a transmit path task and a receive path task are established. Therefore, the 32 inter-chip communication ports form a total of 32 transmit path tasks and 32 receive path tasks. Simultaneously, the switching structure and link transmission modeling object are mapped to a single transmission task shared by multiple communication port-side tasks. This task processes data packets submitted by multiple transmit path tasks, performs queuing, arbitration, forwarding, and link transmission, and then writes the data packets into the second first-in-first-out queue corresponding to the destination port. Therefore, the 32-port switched inter-chip interconnection system in this embodiment is mapped to a total of 64 communication port-side tasks and 1 shared transmission task.

[0053] In the unified simulation framework, the sending and receiving path tasks advance the internal state of the communication ports according to clock cycles, while the shared transmission task updates the switching structure and link transmission state via event triggering. Each task exchanges data through a first-in, first-out (FIFO) queue, forming an end-to-end data transmission simulation process. When the upstream task completes its current processing and the downstream FIFO queue has available space, the upstream task writes its processing result to the downstream FIFO queue; when the downstream FIFO queue has no available space, the upstream task maintains its current state and generates backpressure. This decoupling method reduces the strong synchronization dependency between periodic modeling tasks and event-driven modeling tasks, improving the scalability of large-scale simulations.

[0054] Step 5: Run the simulation and record the results.

[0055] A unified simulation framework is constructed using the protocol-level inter-chip interconnection communication command stream as the simulation stimulus input, and the simulation is run with the current interconnection parameter configuration. For each transaction to be transmitted in the communication command stream, the sending path task determines the corresponding sending path modeling instance based on the source node identifier of the transaction, determines the time when the transaction enters the simulation framework based on the transaction generation time, and divides the transaction into one or more data packets according to the transaction length and data fragmentation parameters. Each data packet first undergoes AXI transaction adaptation, MAC frame encapsulation, and sending buffer processing in the sending path, and then enters the shared transmission task through the first first-in-first-out queue; after completing input queuing, arbitration, switching, and link transmission, the shared transmission task writes the data packet into the second first-in-first-out queue corresponding to the destination communication port; the receiving path task reads the data packet from the second first-in-first-out queue and sequentially performs receive buffering, MAC frame parsing, AXI transaction recovery, and completion processing. When all data packets belonging to the same transaction to be transmitted have completed the receiving processing, the transaction is marked as completed.

[0056] The simulation results recording module records the generation and completion times of each transaction to be transmitted, the entry and exit times of each data packet into and out of each modeling module, and the occupancy status of buffer resources such as the sending buffer, receiving buffer, and input, output, and virtual output queues within the switching structure during the simulation process. The current simulation cycle ends when all transactions to be transmitted are completed, or when the preset maximum simulation time, preset maximum number of events, or other simulation termination conditions are reached.

[0057] Step 6: Performance index statistics and evaluation.

[0058] The performance index statistics module calculates the performance index corresponding to the current interconnect parameter configuration based on the time record and resource status record output by the simulation result recording module in step 5. The performance index includes: (1) system throughput, which represents the total amount of data transmitted per unit simulation time; (2) average latency, which represents the average latency of each transaction to be transmitted; (3) tail latency, which represents the preset high percentile value of the latency of each transaction to be transmitted; (4) buffer resource occupancy, which represents the average occupancy, peak occupancy, or resource configuration overhead of the sending buffer, receiving buffer, and related queues of the switching structure; and (5) multi-communication flow fairness index, which represents the transmission performance difference between different communication flows.

[0059] In this embodiment, the completion delay of each transaction to be transmitted is determined based on the difference between the transaction completion time and the generation time. The system throughput is determined based on the total amount of data transmitted and the simulation completion time. The tail delay can be characterized by the 99th percentile value of the completion delay of all transactions. When the ratio of the standard deviation to the mean of the completion delay of different communication flows is used as the evaluation metric, this metric is used to characterize the degree of delay dispersion between flows. Buffer resource occupancy may include the average and peak occupancy of each buffer queue during operation. The product of the number of virtual channels and the configuration capacity of each virtual channel can be used to characterize the buffer resource configuration overhead.

[0060] The performance index statistics module generates simulation evaluation results corresponding to the current interconnect parameter configuration based on the aforementioned performance indicators. These results may include individual performance indicators or a comprehensive evaluation value composed of one or more performance indicators. The current interconnect parameter configuration is associated and stored with its corresponding performance indicators and comprehensive evaluation value, establishing a correspondence between the interconnect parameter configuration and the simulation evaluation results, providing input for parameter selection and optimization in step 7.

[0061] Step 7: Parameter screening and optimization.

[0062] like Figure 5As shown, the parameter screening and evaluation module evaluates and screens candidate inter-chip interconnection architecture parameter combinations based on the simulation evaluation results output by the performance index statistics module, and iteratively determines the optimal performance configuration of the target inter-chip interconnection architecture. First, the interconnection parameter configuration space is constrained and pruned according to preset hardware feasibility constraints, eliminating parameter combinations that do not meet the constraints. These constraints may include constraints between data fragmentation parameters and protocol encapsulation parameters, buffer capacity constraints, virtual channel quantity constraints, credit resource constraints, and the hardware implementability range of link parameters.

[0063] Subsequently, Latin hypercube sampling is used to select at least one initial interconnect parameter configuration from the pruned feasible parameter space. For each configuration, the transmit path modeling instance, receive path modeling instance, switching structure modeling object, and link transmission modeling object are reconfigured, and steps 2 to 6 are executed respectively to obtain the corresponding simulation evaluation results. Based on the evaluated interconnect parameter configurations and their simulation evaluation results, a Gaussian process surrogate model is trained, and the expected improvement acquisition function is used to determine the next set of interconnect parameter configurations to be evaluated from the unevaluated parameter combinations. Steps 2 to 6 are executed again for this configuration to obtain new simulation evaluation results and update the Gaussian process surrogate model. The above parameter selection, simulation evaluation, and surrogate model update process is repeated until the preset number of iterations, simulation budget, or convergence condition is reached. Finally, the configuration with the best comprehensive evaluation value is selected from the evaluated interconnect parameter configurations as the preferred parameter configuration output for the target 32-port switched inter-chip interconnect system.

[0064] Example 2: Simulation process of inter-chip interconnection using a fully connected topology.

[0065] In another embodiment, the target computing system adopts a fully connected inter-chip interconnect topology, with each computing node directly connected via point-to-point links. This embodiment does not establish the switching structure modeling object in step 3, but only establishes a link transmission modeling object based on the point-to-point connection relationships between the computing nodes. Data packets output by the sending path task directly enter the input queue corresponding to the link transmission module. The link transmission module, as a shared transmission task, completes event-driven modeling based on link bandwidth and transmission latency. The receiving port performs receive buffering, protocol unpacking, and completion processing. Through the above-described hierarchical modeling method, this invention is also applicable to the simulation evaluation of fully connected inter-chip interconnect architectures.

[0066] Modified Implementation: Those skilled in the art should understand that, without departing from the spirit and scope of this invention, the module division, task mapping method, parameter selection, and performance index statistics method in the above embodiments can be appropriately modified or replaced. For example, the number of computing nodes in the target computing system may not be 32, but may be set to other numbers according to the simulation scale requirements; each computing node may be configured with one or more inter-chip communication ports; shared transmission tasks may correspond to switching structures, shared links, or other interconnected resource modules. Therefore, the scope of protection of this invention should be determined by the scope defined in the claims.

Claims

1. A hierarchical and accurate modeling and simulation method for inter-chip interconnects in multi-node computing systems, characterized in that, The multi-node computing system includes multiple computing nodes, communication ports, a switching structure, and a link transmission module; the method includes the following steps: Step 1, Input Configuration: Obtain the inter-chip interconnection topology information, protocol-level inter-chip interconnection communication command stream, and interconnection parameter configuration of the target computing system to be simulated; the inter-chip interconnection topology information includes the number and identifiers of computing nodes, switching structure identifiers, inter-chip communication port mapping relationships, and interconnection connection relationships; the protocol-level inter-chip interconnection communication command stream includes multiple transactions to be transmitted, each transaction including at least the source node identifier, destination node identifier, transaction type, transaction length, and corresponding timing information, used to characterize the communication transaction sequence to be simulated; The interconnection parameter configuration includes one or more of the following: data sharding parameters, scheduling parameters, buffering parameters, virtual channel parameters, and link parameters; Select a set of configurations from the interconnect parameter configuration space as the model configuration for the current round of simulation; Step 2, Periodic Modeling of Communication Ports: Based on the inter-chip communication port mapping relationship and the current interconnection parameter configuration, establish a transmission path modeling instance and a reception path modeling instance for each inter-chip communication port; The sending path modeling instance includes a protocol packetization module and a sending buffer module, and the receiving path modeling instance includes a receiving buffer module, a protocol unpacking module, and a completion processing module. The data packet segmentation method for the transaction to be transmitted is determined based on data fragmentation parameters. The sending buffer module and receiving buffer module are configured based on buffer parameters and virtual channel parameters. The scheduling behavior of each module is configured based on scheduling parameters, and corresponding processing delays are set for each module. Each module advances its state at the clock cycle level, performing periodic-level precise modeling of processing delays, queuing, backpressure, and pipeline behavior within the module. Step 3, Event-driven modeling of switching structure and link transmission: Perform event-driven modeling of the switching structure and link transmission in the inter-chip interconnect; The switching structure modeling object receives data packets submitted by multiple sending path modeling instances and forwards the data packets to the corresponding link transmission modeling object or receiving path modeling instance based on the destination node identifier, routing result, output port availability status, and arbitration result. The link transmission modeling object determines the completion time of data packet transmission based on link bandwidth, link propagation delay, and data packet length; The switching structure modeling object and the link transmission modeling object only update their state when a preset event occurs; Step 4, Simulation Framework Construction: The transmitting path modeling instance, switching structure modeling object, link transmission modeling object, and receiving path modeling instance are decoupled and connected using a first-in-first-out (FIFO) queue, forming a producer-consumer simulation pipeline. The transmitting path modeling instance and receiving path modeling instance corresponding to each inter-chip communication port are mapped to independent transmitting path tasks and receiving path tasks, respectively. The switching structure modeling object and link transmission modeling object are mapped to transmission tasks shared by multiple communication port tasks. The transmitting path task writes the generated data packet into the corresponding FIFO queue. The transmission task reads the data packet and completes arbitration, forwarding, and link transmission before writing it into the FIFO queue corresponding to the destination communication port. The receiving path task reads and processes the data packet, forming an end-to-end data transmission simulation process. Step 5, Run the simulation and record the results: Use the protocol-level inter-chip interconnection communication command stream as the simulation stimulus input to construct the simulation framework, and run the simulation with the current interconnection parameter configuration; For each transaction to be transmitted in the communication command stream, the sending path task reads the corresponding transaction according to the time of generation of each transaction to be transmitted, and divides the transaction to be transmitted into one or more data packets according to the transaction length and data fragmentation parameters, and then executes protocol packing, sending buffer, switching and link transmission, receiving buffer, protocol unpacking and completion processing in sequence. The simulation result recording module records the generation and completion times of each transaction to be transmitted, the times when each data packet enters and leaves each modeling module, and the occupancy status of each buffer module. The current round of simulation ends when all pending transactions are completed or the preset simulation termination condition is met. Step 6, Performance Indicator Statistics and Evaluation: The performance indicator statistics module calculates the performance indicators corresponding to the current interconnect parameter configuration based on the time records and resource status records output by the simulation result recording module, and generates simulation evaluation results accordingly; and establishes the correspondence between the current interconnect parameter configuration and the simulation evaluation results. Step 7, Parameter Screening and Optimization: The parameter screening and evaluation module iteratively determines the interconnect parameter configurations to be evaluated based on the interconnect parameter configuration space and the obtained simulation evaluation results; firstly, it screens the interconnect parameter configuration space according to the preset hardware feasibility constraints, and eliminates parameter combinations that do not meet the constraints. Subsequently, at least one initial interconnect parameter configuration is selected from the remaining parameter combinations, and steps 2 to 6 are executed respectively to obtain the corresponding simulation evaluation results. A surrogate model is constructed based on the evaluated interconnect parameter configurations and their simulation evaluation results, and the next set of interconnect parameter configurations to be evaluated is determined from the configurations that have not yet been evaluated through the acquisition function. Steps 2 to 6 are executed again for it, and the surrogate model is updated using the newly obtained simulation evaluation results. The above parameter selection, simulation evaluation and surrogate model update process is repeated until the preset number of iterations, simulation budget or convergence condition is reached, and the interconnect parameter configuration with the best comprehensive evaluation value is output from the evaluated interconnect parameter configurations.

2. The method as described in claim 1, characterized in that, In step 2, each module advances its state at the granularity of a clock cycle. Specifically, in each clock cycle, each processing module first determines whether the current processing is complete. If the current processing is complete and there is available space in the downstream first-in-first-out queue, the processing result is written to the corresponding first-in-first-out queue and the next transaction processing begins. If the downstream first-in-first-out queue is full, the current processing state is maintained and backpressure information is propagated upstream; if the current processing has not yet been completed, the subsequent clock cycles will continue to be occupied.

3. The method as described in claim 1, characterized in that, The preset events in step 3 include one or more of the following: data packet arrival, output port resource release, credit resource update, arbitration condition satisfaction, and transmission completion.

4. The method as described in claim 1, characterized in that, In step 6, the performance indicators include one or more of throughput, average latency, tail latency, buffer resource usage, and fairness among multiple communication flows; the simulation evaluation results include one or more of the various performance indicators and the comprehensive evaluation value obtained by combining multiple performance indicators.

5. The method as described in claim 1, characterized in that, The parameter configuration space filtering process in step 7 is implemented using constraint pruning, adaptive search, or a combination of both.

6. The method as described in claim 1, characterized in that, When the target computing system is a fully connected inter-chip interconnect topology, each computing node is directly connected to the other through point-to-point links, excluding the switching structure; the data packets output by the sending path task directly enter the input queue corresponding to the link transmission module, and the link transmission module, as a shared transmission task, completes event-driven modeling based on the link bandwidth and transmission delay; the receiving side communication port performs receive buffering, protocol unpacking and processing.

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