Microstructure-oriented hardware design space fast exploration method and system

Abstract

The application discloses a microstructure-oriented hardware design space rapid exploration method and system, characterized by extracting application features of hot code regions and structured coding of hardware parameters to construct unified multi-modal joint input; using a hardware and software correlation exploration agent network with multi-head self-attention and cross-modal attention fusion to perform multi-task prediction; constructing a collection function weighted aggregated by comprehensive performance score, estimated uncertainty, spatial novelty and bottleneck-parameter matching score, and actively selecting configuration for bottom-level simulation according to the collection function, and iteratively updating the collection function weight and fine-tuning the agent network using real labels until the optimal configuration is output; the advantage is that structured coding and cross-modal attention fusion realize hardware and software deep interaction modeling, and in the iteration, uncertainty perception, novelty exploration and bottleneck-oriented active sampling are fused, which significantly improves the performance prediction accuracy and search convergence efficiency of unseen programs and configurations under limited simulation budget.

Description

Technical Field

[0001] This invention relates to the field of computer architecture performance evaluation and hardware design space exploration technology, and in particular to a method and system for rapid exploration of hardware design space oriented towards microarchitecture. Background Technology

[0002] In the design flow of modern high-performance processors and system-on-a-chip (SoC), microarchitectural parameters such as cache hierarchy, TLB (Transition Buffer) capacity and associativity, out-of-order execution window size, load / store queue depth, issue width, branch predictor strategy, pipeline stage number, and on-chip interconnect topology constitute an extremely large design space. These parameters are highly coupled and their final performance strongly depends on the behavior of the target program being run. Therefore, chip design teams often cannot rely on physical verification before tape-out and must use cycle-level or instruction-level architecture simulators such as gem5 to repeatedly perform simulations on multiple test programs and multiple microarchitectural configuration combinations to obtain key evaluation indicators such as IPC (Instructions Per Cycle), runtime, and various microarchitectural bottleneck events (such as cache miss rate, branch misprediction penalty, etc.).

[0003] While the aforementioned evaluation methods based on periodic precise simulation have significant advantages in accuracy, their simulation speed is typically several orders of magnitude slower than that of real hardware. Program segments that take only seconds to complete on real hardware often take hours to run in a periodic simulation environment. When the size of the test program set grows in tandem with the number of microarchitecture configuration combinations to be explored, the time and computational resources consumed in fully traversing the entire design space will expand exponentially, severely restricting the efficiency of early architecture exploration. To alleviate this bottleneck, existing work attempts to introduce machine learning-based surrogate models or sampling strategies to accelerate evaluation. However, most of these solutions simply concatenate static or runtime features of the program with hardware parameters, lacking joint modeling and constraints on factors such as the inherent semantic relationships between hardware parameters (e.g., the synergistic effect between cache capacity and line size), the dynamic weights of program hotspot behaviors, the consistency of performance ranking among different configurations, and the confidence of evaluation results. This results in a significant decrease in the extrapolation prediction ability of the model when faced with unseen programs or unseen microarchitecture configurations, making it difficult to reliably guide the architecture search direction within a broad design space. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for rapid exploration of hardware design space for microstructures, which can jointly model the structured intrinsic relationship between program hotspot behavior and hardware parameters, and utilize an iterative active sampling mechanism that integrates uncertainty perception and ranking consistency to efficiently and reliably locate the optimal microstructure configuration under a limited simulation budget.

[0005] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a method for rapid exploration of hardware design space oriented towards microstructures, comprising the following steps: Step 1: Obtain multiple hotspot code regions in the application to be evaluated, and perform feature processing on each hotspot code region to obtain the corresponding application-side feature representation. Step 2: Obtain multiple candidate hardware configurations in the hardware design space to be explored. The candidate hardware configurations include multiple hardware parameters. Each hardware parameter is structured and encoded according to its type. The encoding results of all hardware parameters are then concatenated to obtain the hardware-side feature representation corresponding to each candidate hardware configuration. Step 3: For each software and hardware combination consisting of each hot code region and each candidate hardware configuration, map the application-side feature representation and hardware-side feature representation corresponding to the software and hardware combination to a unified dimension to obtain a unified multimodal joint input containing the software and hardware interaction context. Step 4: Input the unified multimodal joint input into the pre-trained hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layer. The multi-task prediction label of the candidate hardware configuration is calculated through the multi-task output head. Step 5: Calculate the comprehensive performance score corresponding to each hardware and software combination based on the multi-task prediction label, and perform weighted aggregation of the comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score to construct the acquisition function. Select some configurations from the candidate hardware configurations based on the acquisition function to perform low-level simulation and obtain the real multi-task label. Step 6: Update the weights of the acquisition function using real multi-task labels, and fine-tune the pre-trained hardware-software association exploration agent network. Step 7: Repeat steps 4 to 6 until the preset termination condition is met. From the set of hardware configurations that have completed the underlying simulation, the actual comprehensive performance scores of each candidate hardware configuration in each hot code region are weighted and summed according to the execution weight of each hot code region to obtain the actual application-level comprehensive performance score of each candidate hardware configuration that has completed the simulation. Select the candidate hardware configuration with the largest actual application-level comprehensive performance score as the final recommended hardware configuration and output it to complete the exploration of the hardware design space.

[0006] Compared with existing technologies, the advantages of this invention are as follows: By performing feature processing on hotspot code regions and structure-encoding hardware parameters according to their types, this invention focuses on key behavioral segments during program execution while preserving the collaborative relationships between various hardware parameters, providing a rich input foundation with inherent correlations for subsequent modeling; by mapping application-side and hardware-side features to a unified dimension to form a multimodal joint input, and utilizing the multi-head self-attention mechanism and cross-modal attention and gating fusion mechanism in the software-hardware correlation exploration agent network to encode and model the unified input, this network can dynamically mine the deep interaction weights between different hotspot code patterns and different hardware parameters, while multiple task output heads predict multiple performance-related labels in parallel, enabling the model to take into account various aspects within the same framework. The method incorporates absolute performance estimation and bottleneck direction indication, which helps maintain consistency in performance ranking among configurations. By constructing a data acquisition function that integrates comprehensive performance scores, estimation uncertainty, spatial novelty, and bottleneck-parameter matching scores, the method proactively selects the most informative configuration for low-level simulation. Uncertainty metrics guide the exploration of regions with high prediction variance, novelty encourages coverage of unvisited configuration subspaces, and the bottleneck-parameter matching score correlates predicted bottlenecks with adjustable parameter directions, ensuring highly targeted simulation sampling for each iteration. Furthermore, by updating the data acquisition function weights using real labels obtained from simulations and fine-tuning the proxy network, prediction bias is gradually corrected in the iterative loop, ultimately outputting the configuration with the highest aggregate score when the termination condition is met. This process significantly reduces the reliance on periodic simulations while enhancing prediction extrapolation capabilities and search convergence, providing an efficient and reliable automated decision-making approach for hardware design space exploration. Experimental validation on the test set further supports these conclusions. The predicted IPC and Top-Down bottleneck metrics for unseen programs by the hardware-software co-exploration agent network in the proposed method were compared with the actual values ​​from gem5 simulation. The results show that for the dominant Backend Bound bottleneck, the relative prediction errors for the three test hotspot samples are approximately 2.2%, 1.4%, and 0.4%, respectively. Simultaneously, the predicted IPC values ​​reasonably reflect the performance differences between different hotspots for both the high-IPC Gromacs (predicted 1.84 vs. actual 1.89) and the low-IPC OpenFoam (predicted 0.32 vs. actual 0.31). These experimental data demonstrate that the proposed method possesses high-fidelity prediction capabilities for key performance indicators, providing a reliable input basis for subsequent iterative exploration and optimal configuration selection.

[0007] Furthermore, in step 2, the types of hardware parameters include capacity parameters, counting parameters, and strategy parameters; Structured coding specifically includes: For capacity-type parameters, the interval normalized encoding after log2 transformation is used; For count-type parameters, interval normalization encoding is used; For policy parameters, embedding encoding is employed. Based on the different physical attributes of the three types of hardware parameters—capacity, counting, and policy—log2 transform normalization, interval normalization, and embedding encoding are used respectively. Capacity parameters (such as cache capacity) typically exhibit exponential size differences; the log2 transform maps them to a linear scale to conform to perceptual laws. Counting parameters are directly normalized to maintain proportional relationships. Policy parameters (such as branch predictor type) express the semantic similarity between discrete options in a low-dimensional space through embedding encoding. This differentiated and structured encoding approach allows all types of parameters to participate in modeling in numerical forms best suited to their characteristics, thereby enhancing the agent network's understanding of hardware configuration semantics and its generalization performance.

[0008] Furthermore, in step 3, the specific operation for obtaining the unified multimodal joint input containing the software and hardware interaction context is as follows: Apply a first linear mapping to the application-side feature representation and a second linear mapping to the hardware-side feature representation, so that the two are in the same vector space; The mapped application-side feature representations are constructed into an application-side token sequence, the mapped hardware-side feature representations are constructed into a hardware-side token sequence, and a global aggregation token and a sequence end token are added to the sequence to form a basic token sequence. Modal embedding, parameter set embedding, and positional embedding are superimposed on the basic token sequence to obtain a unified multimodal joint input.

[0009] Furthermore, in step 4, each layer in the multi-layer coding layer sequentially performs the following operations on the input sequence: multi-head self-attention operation, cross-modal attention and gating fusion operation, residual connection and layer normalization operation, and feedforward network operation. The output of the feedforward network is then processed by residual connection and layer normalization and used as the output of the current layer. The cross-modal attention and gating fusion operation includes: generating a key matrix and a value matrix based on hardware-side tokens, generating a query matrix based on the basic token sequence, and calculating the cross-modal cross-attention output; concatenating the average representation of application-side tokens and the average representation of hardware-side tokens and then calculating the fusion weight through a Sigmoid gating network; and using the fusion weight to perform weighted fusion of the cross-modal cross-attention output and the multi-head self-attention output. The specific operation of calculating the multi-task prediction label of the candidate hardware configuration through the multi-task output head includes: extracting the hidden representation corresponding to the global aggregate token from the output of the last coding layer, inputting the hidden representation into the multilayer perceptron for mapping, and obtaining the multi-task prediction label; The multi-task prediction labels include IPC estimates and Top-Down microstructure bottleneck metrics. Each encoding layer captures long-range dependencies within the same modality through multi-head self-attention operations. Then, cross-modal attention and gating fusion operations achieve targeted attention of hardware-side tokens to application-side global tokens. The gating network calculates Sigmoid fusion weights based on the average representation of tokens from both sides, dynamically adjusting the ratio of multi-head self-attention outputs to cross-modal cross-attention outputs. Residual connections and layer normalization ensure the stability of deep network training, and the feedforward network further enhances nonlinear expressive capabilities. Finally, hidden representations are extracted from the global aggregated tokens output from the last layer and mapped to IPC estimates and Top-Down microstructure bottleneck metrics by a multilayer perceptron. This multi-task output design enables a single network to simultaneously provide macroscopic throughput and fine-grained bottleneck decomposition, providing a unified and consistent prediction source for subsequent comprehensive scoring and bottleneck-aware acquisition functions.

[0010] Furthermore, in step 5, the comprehensive performance score is calculated by weighting the IPC estimate and the Top-Down microstructure bottleneck index in the multi-task prediction label; the estimation uncertainty is obtained by performing multiple forward inferences on the hardware-software association exploration agent network and calculating the variance of the comprehensive performance score; the spatial novelty is obtained by calculating the minimum feature distance between the current candidate hardware configuration and the set of hardware configurations that have completed simulation; the bottleneck-parameter matching score is obtained by evaluating the potential benefit of the hardware parameters of the current candidate hardware configuration in alleviating the predicted Top-Down bottleneck; and the acquisition function is constructed as a weighted sum of the normalized comprehensive performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score. The real multi-task labels include real IPC values ​​and real Top-Down microstructure bottleneck indicators. The acquisition function normalizes and weights the comprehensive performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score, so that each sampling can utilize the high-scoring configuration of the current prediction (utilization), while also taking into account regions with large prediction variance (exploration) and sparse configuration space (novelty), and specifically guides parameter adjustment for bottlenecks (matching), thereby maximizing the information gain and optimization progress efficiency of each low-level sampling within a limited simulation budget.

[0011] Furthermore, before the first execution of step 5, the process includes: selecting an initial seed configuration from candidate hardware configurations for low-level simulation; storing the simulated real multi-task labels into the feedback data pool; and storing the initial seed configuration into the simulated configuration set to initialize the feedback data pool and the simulated configuration set. Adding low-level simulation of the initial seed configuration before the first execution of step 5, and storing its real multi-task labels and the configuration itself into the feedback data pool and the simulated configuration set respectively, provides initial supervision signals and reference benchmarks for subsequent iterations. This avoids the cold start problem of the agent network lacking effective gradients during the initial fine-tuning without any real data, ensuring that weight updates and network calibration can be performed based on actual simulation results from the first iteration.

[0012] Furthermore, in step 6, the weights of the acquisition function are updated, including: based on the average relative error and effective discovery rate of the simulation results, the weights of the comprehensive performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score in the acquisition function are adaptively adjusted respectively. Step 6 involves fine-tuning the pre-trained hardware-software correlation exploration agent network. This includes freezing the parameters of the first L-2 coding layers and updating only the parameters of the last two coding layers, the gated fusion layer, and the multi-task output head. The fine-tuning uses a learning rate lower than the initial training rate, and calculates the fine-tuning loss using real multi-task labels and pre-reserved reference data. This partial fine-tuning strategy allows for rapid adaptation to newly acquired simulation data while preventing the destruction of existing good representations due to drastic parameter updates, thus balancing adaptation speed and model stability.

[0013] Furthermore, in step 7, the preset termination conditions include: the optimal real application-level comprehensive performance score converges, the preset maximum number of iterations is reached, or the total number of configurations for the underlying simulation reaches the preset simulation budget. The convergence of the optimal real-world application-level comprehensive performance score is determined by calculating the relative change between the known optimal real-world comprehensive performance score in the current round and the known optimal real-world comprehensive performance score in the previous round. Convergence is considered achieved when the relative change is less than a preset threshold. This multi-condition termination mechanism ensures that the exploration process does not miss better configurations due to premature termination, and also prevents computational waste caused by continuing ineffective iterations after convergence. Simultaneously, the simulation budget upper limit provides a hard constraint on actual engineering resource limitations, enabling a controllable balance between accuracy, time, and resources throughout the entire exploration process.

[0014] Furthermore, the pre-trained hardware-software association exploration agent network is obtained through the following pre-training steps: Step A1: Obtain the pre-trained sample set, which contains hot code regions of multiple known applications, multiple known hardware configurations, and corresponding real multi-task labels obtained through the underlying simulator. Step A2: Perform feature processing on each hotspot code region to obtain application-side feature representation; Step A3: For each known hardware configuration, perform structured encoding on the hardware parameters according to the type of the hardware parameters, and concatenate the encoding results of all hardware parameters to obtain the hardware-side feature representation. Step A4: For each software and hardware combination consisting of each hot code region and each known hardware configuration, map the application-side feature representation and hardware-side feature representation corresponding to the software and hardware combination to a unified dimension to obtain a unified multimodal joint input. Step A5: Input the unified multimodal joint input into the hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layer. The multi-task prediction label is calculated through the multi-task output head. Step A6: Calculate the joint loss based on the multi-task predicted labels and the real multi-task labels, and backpropagate to update the parameters of the hardware-software association exploration agent network until the pre-training termination condition is met, thus obtaining the pre-trained hardware-software association exploration agent network.

[0015] A rapid hardware design space exploration system for microarchitecture includes: The application feature extraction module is used to obtain multiple hotspot code regions in the application to be evaluated, and to perform feature processing on each hotspot code region to obtain the corresponding application-side feature representation. The hardware encoding module is used to obtain multiple candidate hardware configurations in the hardware design space to be explored. The candidate hardware configurations include multiple hardware parameters. Each hardware parameter is structured and encoded according to its type. The encoding results of all hardware parameters are then concatenated to obtain the hardware-side feature representation corresponding to each candidate hardware configuration. The joint token construction module is used to map the application-side feature representation and hardware-side feature representation corresponding to each software and hardware combination consisting of each hot code region and each candidate hardware configuration to a unified dimension, so as to obtain a unified multimodal joint input containing the software and hardware interaction context. The multi-task output module is used to input the unified multimodal joint input into the pre-trained hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layers. The multi-task output head is used to calculate the multi-task prediction label of the candidate hardware configuration. The simulation feedback module is used to calculate the comprehensive performance score corresponding to each hardware and software combination based on the multi-task prediction label, and to perform weighted aggregation of the comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score to construct the acquisition function. Based on the acquisition function, a portion of the configurations are selected from the candidate hardware configurations for low-level simulation to obtain the real multi-task labels. The model calibration module is used to update the weights of the acquisition function using real multi-task labels and to fine-tune the pre-trained hardware-software correlation exploration agent network. The configuration output module repeatedly executes the multi-task output module to the model calibration module until a preset termination condition is met. From the set of hardware configurations that have completed low-level simulations, the actual comprehensive performance scores of each candidate hardware configuration in each hotspot code region are weighted and summed according to the execution weight of each hotspot code region to obtain the actual application-level comprehensive performance score for each candidate hardware configuration that has completed simulations. The candidate hardware configuration with the highest actual application-level comprehensive performance score is selected as the final recommended hardware configuration and output. This modular architecture clearly divides different functional units, facilitating independent development and maintenance while ensuring the automation and reproducibility of the entire exploration process. The modules collaborate through standard data interfaces, jointly achieving efficient and reliable rapid exploration of the design space. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall process of the present invention; Figure 2 This is a schematic diagram of the system architecture of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0018] like Figure 1 As shown, a method and system for rapid exploration of hardware design space for microstructures includes two parts: a pre-training stage and an online exploration stage. The pre-training stage is used to pre-train a software-hardware association exploration agent network, while the online exploration stage is used to rapidly explore based on the pre-trained software-hardware association exploration agent network for specific target applications and target hardware design spaces, and output the optimal hardware configuration.

[0019] The pre-training phase is used to obtain the pre-trained hardware-software correlation exploration agent network, and specifically includes the following steps: Step A1: Obtain a pre-trained sample set, which includes hot code regions of multiple known applications, multiple known hardware configurations, and corresponding real multi-task labels obtained through the underlying simulator. Specifically, a pre-training sample set is constructed by combining publicly available benchmark test program sets (such as SPEC CPU2006, SPEC CPU2017 and custom microkernel programs) with hardware design space for simulation. For each program, multiple configurations are uniformly sampled from the hardware design space H using Latin hypercube sampling, and run on the gem5 cycle-accurate simulator to record IPC values ​​and Top-Down microstructure bottleneck data as real multi-task labels.

[0020] Step A2: Perform feature processing on each hotspot code region to obtain application-side feature representation; The specific steps to obtain multiple hot code regions in a known application are as follows: use low-level performance monitoring tools (such as Perf sampling) to sample the known application, and locate the frequently executed hot code regions (e.g., hot code regions with a large number of instructions or a high percentage of execution cycles) based on the number of instructions or the percentage of execution cycles. The specific operation for characterizing each hot code region is as follows: extract short source code with application features that can characterize the key microstructure behavior from the hot code region, perform static code feature extraction and runtime analysis feature extraction on the short source code with application features, and obtain application-side feature representations including at least one of the following: instruction hybrid features (such as ALU / FP / BRANCH / LOAD / STORE / VECTOR), memory access behavior features (such as memory access intensity, step size regularity, load / store ratio), control flow features (such as loop nesting depth, branch density, basic block distance), data dependency features (such as critical path length of dependency graph, average dependency distance), and data locality features (such as reuse distance distribution, cache hit related features). For example: For a known application A, let the application-side feature representation corresponding to its m-th hotspot code region be denoted as... , ,in, This represents the index of the m-th hotspot code region in a known application A. This indicates the proportion of scalar computation instructions in the total number of instructions executed by the Arithmetic Logic Unit (ALU). This indicates the proportion of floating-point instructions in the total number of instructions executed. This indicates the proportion of control flow branch instructions in the total number of instructions executed. This indicates the proportion of memory load instructions in the total number of instructions executed. This indicates the proportion of memory storage (Store) instructions in the total number of instructions executed. This indicates the proportion of vectorized / SIMD (Vector) instructions in the total number of instructions executed. This represents a subset of mixed instruction features formed by concatenating the frequencies / proportions of the aforementioned instruction types. Indicates the ratio of memory access to read / write operations. This represents the average memory access step size. A subset of memory access behavior features, concatenated by the memory access intensity and memory access stride parameter. This indicates the average nesting depth of the loops in the code. This represents the average base block distance between branch instructions. This represents a subset of control flow features concatenated by parameters such as loop depth and branch distance. Indicates dimension.

[0021] Step A3 involves performing structured encoding on the hardware parameters of each known hardware configuration to obtain hardware-side feature representations. Specifically: Obtain N known hardware configurations from the pre-training sample set, and denote the j-th known hardware configuration as... , Each known hardware configuration includes K hardware parameters. Let the k-th hardware parameter in the j-th known hardware configuration be denoted as... , Each hardware parameter is structured and encoded according to its type, and the encoded results of all hardware parameters are concatenated to obtain the hardware-side feature representation corresponding to each known hardware configuration. The types of hardware parameters include capacity parameters, count parameters, and policy parameters. The known hardware configuration includes at least two types of capacity parameters, count parameters, and policy parameters.

[0022] Structured coding specifically includes: For capacity-type parameters, such as L1 cache capacity, L2 cache capacity, or TLB capacity, the interval normalized encoding after log2 transformation is used, for example: ,in, Represents the j-th known hardware configuration The encoded value of the k-th hardware parameter; Indicates known hardware configuration The actual value of the kth hardware parameter; and These represent the minimum and maximum possible values ​​of the k-th hardware parameter in the design space, respectively; This indicates a very small positive number that prevents the denominator from being zero; For counting parameters, such as reorder buffer size, load queue size, store queue size, number of load pipelines, number of store pipelines, emission width, pipeline depth, etc., interval normalized encoding is used, for example: ; For policy-related parameters, such as cache replacement policies and branch prediction policies, embedding encoding is used, for example... ,in, Represents the embedding encoding function for policy parameters; The encoded results of the K hardware parameters are concatenated to form the hardware-side feature representation corresponding to the j-th known hardware configuration. , ,in, This represents the total number of hardware parameters in the j-th known hardware configuration. This indicates the dimension of the hardware-side feature representation.

[0023] Step A4: For each software and hardware combination consisting of each hot code region and each known hardware configuration, map the application-side feature representation and hardware-side feature representation corresponding to the software and hardware combination to a unified dimension to obtain a unified multimodal joint input containing the software and hardware interaction context. The specific operation for obtaining the unified multimodal joint input, which includes the software and hardware interaction context, is as follows: Apply a first linear mapping to the application-side feature representation and a second linear mapping to the hardware-side feature representation, so that the two are in the same vector space; ,in, This represents the application-side feature representation after mapping. This represents the application-side feature representation of the m-th hotspot code region. and These represent the application-side linear mapping weight matrix and bias term, respectively. ,in, This represents the mapped hardware-side feature representation. This represents the hardware-side feature vector of the j-th known hardware configuration. and These represent the hardware-side linear mapping weight matrix and bias term, respectively; The mapped application-side feature representations are constructed into application-side token sequences. The application-side token sequences are constructed according to feature groups such as instruction mixing, memory access behavior, control flow, data dependency, and locality. The mapped hardware-side feature representations are constructed into hardware-side token sequences. The hardware-side token sequences are constructed according to parameter groups such as cache, TLB, queue, pipeline, issue width, and policy parameters. This avoids compressing all application features or all hardware parameters into a single token without distinguishing semantics. A global aggregation token and a sequence end token are added to the sequence to form a basic token sequence. ,in, This represents the basic token sequence corresponding to the m-th hotspot code region and the j-th known hardware configuration. Represents the globally aggregated token. This indicates the application-side Token constructor. This indicates the hardware-side Token constructor. Indicates the end of the sequence (Token); By overlaying modal embedding, parameter set embedding, and positional embedding onto the basic token sequence, a unified multimodal joint input is obtained. ,in, This represents the unified multimodal joint input, i.e., the total embedding representation of the input hardware-software related exploration agent network at layer 0. This indicates modal embedding, used to distinguish between application-side token sequences and hardware-side token sequences; This indicates parameter group embedding, used to distinguish different application feature groups or hardware parameter groups; This indicates a positional embedding, used to represent feature order or parameter group category.

[0024] Step A5: Input the unified multimodal joint input into the hardware-software association exploration agent network. The hardware-software association exploration agent network includes an L-layer encoding layer. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the encoding layer. The multi-task prediction label containing IPC estimates and Top-Down microstructure bottleneck indicators is calculated through the multi-task output head. Each layer in the multi-layer coding layer performs the following operations on the input token sequence in sequence: multi-head self-attention operation, cross-modal attention and gating fusion operation, residual connection and layer normalization operation, and feedforward network operation. The output of the feedforward network is then processed by residual connection and layer normalization as the output of the current layer. The cross-modal attention and gating fusion operation includes: generating a key matrix and a value matrix based on hardware-side tokens, generating a query matrix based on the basic token sequence, and calculating the cross-modal cross-attention output; concatenating the average representation of application-side tokens and the average representation of hardware-side tokens and then calculating the fusion weight through a Sigmoid gating network; and using the fusion weight to perform weighted fusion of the cross-modal cross-attention output and the multi-head self-attention output. For the l-th layer, Its input is the output of the previous layer. Perform the following operations on each layer: First, the global context representation is obtained by calculating the global association between the application-side token, the hardware-side token, and the parameter group token through multi-head self-attention: Obtain the query matrix of the i-th attention head in the l-th layer. Key matrix Sum matrix , ,in, This represents the unified multimodal joint input of the l-th layer input. , and These represent the query projection matrix, key projection matrix, and value projection matrix of the i-th attention head in the l-th layer, respectively. Indicates the index of the hot code region. Indicates a known hardware configuration index. Indicates network layer index, Indicates the attention head index; Obtain the output of the i-th attention head in the l-th layer. , ,in, This represents the dimension of the key vector in a single attention head. This represents the normalized exponential function; Indicates matrix transpose; Obtain the global context representation, i.e., the multi-head self-attention output of layer l. , ,in, This means concatenating the outputs of multiple attention heads along their feature dimensions. Indicates the number of attention heads. , This represents the output projection matrix of the multi-head attention layer l; Secondly, to avoid relying solely on general self-attention, this invention introduces a cross-modal cross-attention and gating fusion mechanism for software-hardware interaction based on the global context. This mechanism is used to explicitly capture the sensitivity of a certain type of program hotspot to a specific set of hardware parameters. Obtain the average representation of the application-side token sequence at layer l. and the average representation of the layer l hardware-side token sequence , ,in, Indicates the number of application-side tokens. Indicates the number of tokens on the hardware side. and These represent the application-side token output vector and the hardware-side token output vector of the t-th layer, respectively. Obtain the cross-modal attention output of layer l , ,in, This represents a query matrix generated from the l-th layer basic token sequence, with the same number of rows as the multi-head self-attention output. This represents the key matrix generated from the token sequence on the l-th hardware side. This represents the value matrix generated from the token sequence on the l-th hardware side. This represents the dimension of the key vector in a single attention head; Obtain the gating fusion weight vector of layer l , ,in, This represents the Sigmoid activation function. This represents the weight matrix of the l-th layer gated network. Let represent the bias vector of the l-th layer gated network. This represents a vector concatenation operation; Obtain the attention output after gating and fusion at layer l. , ,in, This represents element-wise multiplication; the gated fusion weight vector is broadcast along the token dimension, so that the cross-modal cross-attention output and the multi-head self-attention output have the same shape. Next, residual connections, feedforward networks, and normalization are performed: Obtain the first residual connection of layer l and the normalized intermediate hidden layer state. , ,in, Indicates the layer normalization function; Let the operation of the feedforward network on the input x be denoted as , ,in, and Let these represent the first and second weight matrices of the l-th layer feedforward network, respectively. and Let represent the first bias vector and the second bias vector of the l-th layer feedforward network, respectively. Let the Gaussian error linear unit activation function operation be denoted as... , ,in, Indicates input variables, Represents the error function; Let the level normalization operation be denoted as , ,in, The learnable scaling parameter in layer normalization represents the representation. This represents the mean of the input x calculated along the feature dimension. This represents the variance calculated along the feature dimension of the input x. This indicates the smallest positive number whose denominator is zero. Learnable translation parameters in layer normalization; Finally, obtain the output sequence of the l-th layer. , .

[0025] The specific operations for calculating multi-task prediction labels through the multi-task output head include: extracting the hidden representation corresponding to the global aggregate token from the output of the last encoding layer, inputting the hidden representation into the multilayer perceptron for mapping, and obtaining the multi-task prediction label.

[0026] The multi-task output header uses a multilayer perceptron (MLP) to map the hidden representation corresponding to the global aggregated token, obtaining the multi-task predicted label of the m-th hotspot code region under the j-th known hardware configuration. , ,in, Indicates a multi-tasking output header. Represents the output sequence of the Lth layer The hidden representation of the global aggregated token sequence in the middle. , This indicates retrieving the 0th token from the output sequence of layer L; This indicates the hidden dimension of the model; The multi-task prediction labels include IPC estimates and Top-Down microstructure bottleneck indices.

[0027] Step A6: Calculate the joint loss based on the multi-task predicted labels and the real multi-task labels, and backpropagate to update the parameters of the software-hardware association exploration agent network until the pre-training termination condition is met, thus obtaining the pre-trained software-hardware association exploration agent network. The model pre-training employs a joint loss mechanism combining IPC numerical regression, Top-Down bottleneck index loss, configuration ranking loss, and parameter sensitivity soft constraints. The pre-training not only fits the IPC components of the m-th hotspot under the j-th hardware configuration but also learns the Top-Down microstructure bottleneck index and constrains the configuration ranking relationship of the same hotspot under different hardware configurations. For capacity-type and count-type parameters with explicit physical partial order relationships, parameter sensitivity soft constraints are further introduced; for policy-type parameters, categorical parameters, and parameters whose performance gains have entered the saturation range, monotonic direction constraints are not forcibly imposed.

[0028] ,in, Indicates the total training loss; This represents the multi-task labeled regression loss; Indicates the configuration sorting loss; This represents the soft constraint loss due to parameter sensitivity. , and These represent the weights of the corresponding loss terms; This indicates that the parameters of the agent model are being explored.

[0029] ,in, Represents the training batch sample set; Indicates the number of samples in the training batch; This represents the IPC and Top-Down multi-task prediction labels output by the model; This indicates a true multitasking tag.

[0030] IPC and various Top-Down tab components enter and Before inference, the data is normalized to a comparable scale using the statistics of the training set; after inference output, inverse normalization is performed to avoid the gradient being dominated by a single task due to differences in scale.

[0031] ,in, This represents the set of configuration pairs used for sorting constraints. This indicates the known configuration under the m-th hotspot code region. and The resulting training configuration pairs; and These represent the overall performance scores predicted by the model; Indicates the actual sorting direction, when The actual rating is higher than The value is 1 if the condition is met, otherwise it is -1. This indicates the sorting interval threshold.

[0032] ,in, This represents the set of configuration pairs used for parameter sensitivity constraints; and This indicates a known configuration that differs only in one capacity-type or count-type hardware parameter; This indicates the sensitivity direction determined by the physical partial order of the hardware parameter and the direction of its expected performance influence. and These represent the overall performance scores predicted by the model.

[0033] The pre-trained optimizer uses AdamW (β1=0.9, β2=0.999, weight decay wd=0.01).

[0034] Learning rate scheduling is a linear warm-up to peak during the first 5% of training steps. The cosine decays to Batch size is 256~1024, and training lasts 100~300 epochs. During training, Gaussian noise with a mean of 0 and a standard deviation of 0.01 is added to numerical features to enhance generalization ability, and an early stopping strategy is set: training is terminated when the MAPE on the validation set does not improve for 20 consecutive epochs, and the model parameters are restored to the lowest MAPE on the validation set.

[0035] The software-hardware association exploration agent network is pre-trained offline using the joint loss function described above. Training is terminated when the mean absolute percentage error (MAPE) on the validation set no longer decreases for several consecutive rounds, and the current network parameters are saved as the pre-trained software-hardware association exploration agent network.

[0036] After pre-training is completed, a subset of samples is extracted from the pre-training sample set according to a preset ratio (e.g., 5%~10%) to serve as the historical playback data subset. (i.e., the pre-reserved reference data) is retained. This subset of historical replay data is used as an experience replay constraint for fine-tuning the pre-trained hardware-software association exploration agent network in the subsequent online exploration phase. It is used together with newly added simulation samples to calculate the fine-tuning loss, thereby reducing the risk of catastrophic forgetting.

[0037] When rapid exploration of the hardware design space is required for a specific target application, the parameters of the pre-trained hardware-software correlation exploration agent network are used as initial parameters, and the following online iterative exploration steps are executed: Step 1: Obtain multiple hotspot code regions in the application to be evaluated, and perform feature processing on each hotspot code region to obtain the corresponding application-side feature representation. The specific steps to obtain multiple hot code regions in the application to be evaluated are as follows: use underlying performance monitoring tools (such as Perf sampling) to sample the application to be evaluated, and locate the frequently executed hot code regions (e.g., hot code regions with a large number of instructions or a high percentage of execution cycles) based on the number of instructions or the percentage of execution cycles. The specific operation for characterizing each hot code region is as follows: extract short source code with application features that can characterize the key microstructure behavior from the hot code region, perform static code feature extraction and runtime analysis feature extraction on the short source code with application features, and obtain application-side feature representations including at least one of the following: instruction hybrid features (such as ALU / FP / BRANCH / LOAD / STORE / VECTOR), memory access behavior features (such as memory access intensity, step size regularity, load / store ratio), control flow features (such as loop nesting depth, branch density, basic block distance), data dependency features (such as critical path length of dependency graph, average dependency distance), and data locality features (such as reuse distance distribution, cache hit related features). The specific implementation of this step is the same as step A2 in the pre-training stage, except that at this time, the target application to be evaluated is processed instead of the known applications in the pre-training sample set.

[0038] Step 2: Obtain N candidate hardware configurations in the hardware design space to be explored, and denote the j-th candidate hardware configuration as... j Each candidate hardware configuration includes K hardware parameters. Let the k-th hardware parameter in the j-th candidate hardware configuration be denoted as... , Each hardware parameter is structured and encoded according to its type, and the encoded results of all hardware parameters are concatenated to obtain the hardware-side feature representation corresponding to each candidate hardware configuration. The types of hardware parameters include capacity parameters, count parameters, and strategy parameters; the candidate hardware configuration includes at least two of the following types: capacity parameters, count parameters, and strategy parameters. Structured coding specifically includes: For capacity-type parameters, such as L1 cache capacity, L2 cache capacity, or TLB capacity, the interval normalized encoding after log2 transformation is used, for example: ,in, This represents the j-th candidate hardware configuration. The encoded value of the k-th hardware parameter; Indicates candidate hardware configuration The actual value of the kth hardware parameter; and These represent the minimum and maximum possible values ​​of the k-th hardware parameter in the design space, respectively; This indicates a very small positive number that prevents the denominator from being zero; For counting parameters, such as reorder buffer size, load queue size, store queue size, number of load pipelines, number of store pipelines, emission width, pipeline depth, etc., interval normalized encoding is used, for example: ; For policy-related parameters, such as cache replacement policies and branch prediction policies, embedding encoding is used, for example... ,in, Represents the embedding encoding function for policy parameters; The encoded results of the K hardware parameters are concatenated to form the hardware-side feature representation corresponding to the j-th candidate hardware configuration. , ,in, This represents the total number of hardware parameters in the j-th candidate hardware configuration. This indicates the dimension of the hardware-side feature representation.

[0039] Step 3: For each software and hardware combination consisting of each hot code region and each candidate hardware configuration, map the application-side feature representation and hardware-side feature representation corresponding to the software and hardware combination to a unified dimension to obtain a unified multimodal joint input containing the software and hardware interaction context. The specific operation for obtaining the unified multimodal joint input, which includes the software and hardware interaction context, is as follows: Apply a first linear mapping to the application-side feature representation and a second linear mapping to the hardware-side feature representation, so that the two are in the same vector space; ,in, This represents the application-side feature representation after mapping. This represents the application-side feature representation of the m-th hotspot code region. and These represent the application-side linear mapping weight matrix and bias term, respectively. ,in, This represents the mapped hardware-side feature representation. This represents the hardware-side feature vector of the j-th candidate hardware configuration. and These represent the hardware-side linear mapping weight matrix and bias term, respectively; The mapped application-side feature representations are constructed into application-side token sequences. The application-side token sequences are constructed according to feature groups such as instruction mixing, memory access behavior, control flow, data dependency, and locality. The mapped hardware-side feature representations are constructed into hardware-side token sequences. The hardware-side token sequences are constructed according to parameter groups such as cache, TLB, queue, pipeline, issue width, and policy parameters. This avoids compressing all application features or all hardware parameters into a single token without distinguishing semantics. A global aggregation token and a sequence end token are added to the sequence to form a basic token sequence. ,in, This represents the basic token sequence corresponding to the m-th hotspot code region and the j-th candidate hardware configuration. Represents the globally aggregated token. This indicates the application-side Token constructor. This indicates the hardware-side Token constructor. Indicates the end of the sequence (Token); By overlaying modal embedding, parameter set embedding, and positional embedding onto the basic token sequence, a unified multimodal joint input is obtained. ,in, This represents the unified multimodal joint input, i.e., the total embedding representation of the input hardware-software related exploration agent network at layer 0. This indicates modal embedding, used to distinguish between application-side token sequences and hardware-side token sequences; This indicates parameter group embedding, used to distinguish different application feature groups or hardware parameter groups; This indicates a positional embedding, used to represent feature order or parameter group category.

[0040] Step 4: Input the unified multimodal joint input into the pre-trained hardware-software association exploration agent network. Encode and model the unified multimodal joint input through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the encoding layer. Calculate the multi-task prediction label of the candidate hardware configuration, which includes IPC estimates and top-down microstructure bottleneck indicators, through the multi-task output head. Each layer in the multi-layer coding layer performs the following operations on the input token sequence in sequence: multi-head self-attention operation, cross-modal attention and gating fusion operation, residual connection and layer normalization operation, and feedforward network operation. The output of the feedforward network is then processed by residual connection and layer normalization as the output of the current layer. The cross-modal attention and gating fusion operation includes: generating a key matrix and a value matrix based on hardware-side tokens, generating a query matrix based on the basic token sequence, and calculating the cross-modal cross-attention output; concatenating the average representation of application-side tokens and the average representation of hardware-side tokens and then calculating the fusion weight through a Sigmoid gating network; and using the fusion weight to perform weighted fusion of the cross-modal cross-attention output and the multi-head self-attention output. For the l-th layer, Its input is the output of the previous layer. Perform the following operations on each layer: First, the global context representation is obtained by calculating the global association between the application-side token, the hardware-side token, and the parameter group token through multi-head self-attention: Obtain the query matrix of the i-th attention head in the l-th layer. Key matrix Sum matrix , ,in, This represents the unified multimodal joint input of the l-th layer input. , and These represent the query projection matrix, key projection matrix, and value projection matrix of the i-th attention head in the l-th layer, respectively. Indicates the index of the hot code region. Indicates the candidate hardware configuration index. Indicates network layer index, Indicates the attention head index; Obtain the output of the i-th attention head in the l-th layer. , ,in, This represents the dimension of the key vector in a single attention head. This represents the normalized exponential function; Indicates matrix transpose; Obtain the global context representation, i.e., the multi-head self-attention output of layer l. , ,in, This means concatenating the outputs of multiple attention heads along their feature dimensions. Indicates the number of attention heads. , This represents the output projection matrix of the multi-head attention layer l; Secondly, to avoid relying solely on general self-attention, this invention introduces a cross-modal cross-attention and gating fusion mechanism for software-hardware interaction based on the global context. This mechanism is used to explicitly capture the sensitivity of a certain type of program hotspot to a specific set of hardware parameters. Obtain the average representation of the application-side token sequence at layer l. and the average representation of the layer l hardware-side token sequence , ,in, Indicates the number of application-side tokens. Indicates the number of tokens on the hardware side. and These represent the application-side token output vector and the hardware-side token output vector of the t-th layer, respectively. Obtain the cross-modal attention output of layer l , ,in, This represents a query matrix generated from the l-th layer basic token sequence, with the same number of rows as the multi-head self-attention output. This represents the key matrix generated from the token sequence on the l-th hardware side. This represents the value matrix generated from the token sequence on the l-th hardware side. This represents the dimension of the key vector in a single attention head; Obtain the gating fusion weight vector of layer l , ,in, This represents the Sigmoid activation function. This represents the weight matrix of the l-th layer gated network. Let represent the bias vector of the l-th layer gated network. This represents a vector concatenation operation; Obtain the attention output after gating and fusion at layer l. , ,in, This represents element-wise multiplication; the gated fusion weight vector is broadcast along the token dimension, so that the cross-modal cross-attention output and the multi-head self-attention output have the same shape. Next, residual connections, feedforward networks, and normalization are performed: Obtain the first residual connection of layer l and the normalized intermediate hidden layer state. , ,in, Indicates the layer normalization function; Let the operation of the feedforward network on the input x be denoted as , ,in, and Let these represent the first and second weight matrices of the l-th layer feedforward network, respectively. and Let represent the first bias vector and the second bias vector of the l-th layer feedforward network, respectively. Let the Gaussian error linear unit activation function operation be denoted as... , ,in, Indicates input variables, Represents the error function; Let the level normalization operation be denoted as , ,in, The learnable scaling parameter in layer normalization represents the representation. This represents the mean of the input x calculated along the feature dimension. This represents the variance calculated along the feature dimension of the input x. This indicates the smallest positive number whose denominator is zero. Learnable translation parameters in layer normalization; Finally, obtain the output sequence of the l-th layer. , ; The specific operation of calculating the multi-task prediction label of the candidate hardware configuration through the multi-task output head includes: extracting the hidden representation corresponding to the global aggregate token from the output of the last coding layer, inputting the hidden representation into the multilayer perceptron for mapping, and obtaining the multi-task prediction label; The multi-task output header uses a multilayer perceptron (MLP) to map the hidden representation corresponding to the global aggregate token, obtaining the multi-task prediction label of the m-th hotspot code region under the j-th candidate hardware configuration. , ,in, Indicates a multi-tasking output header. Represents the output sequence of layer L. The hidden representation of the global aggregated token sequence in the middle. , This indicates retrieving the 0th token from the output sequence of layer L; This indicates the hidden dimension of the model; Before executing step 5 for the first time, select an initial seed configuration from the candidate hardware configurations for low-level simulation, store the real multi-task label in the feedback data pool, and store the seed configuration in the simulated configuration set, ensuring that neither is empty.

[0041] Let the initial seed hardware configuration set be denoted as , ,in, Represents the set of candidate hardware configurations. Indicates the initial number of seed hardware configurations. Indicates the number of elements in the set; Let the set of hardware configurations that have completed low-level simulation at the end of round 0 be denoted as . , ; The feedback data pool at the end of round 0 is denoted as ,in, This represents the application-side feature representation of the m-th hotspot code region. This represents the j-th candidate hardware configuration. This represents the real multi-task label obtained from the underlying simulation. This indicates the total number of hotspot code regions in application A to be evaluated.

[0042] Initialize the optimal real-world application-level score using the seed simulation results: .in, Apply weights to normalize hot spots.

[0043] Step 5: Calculate the comprehensive performance score corresponding to each hardware and software combination based on the multi-task prediction labels, and weight and aggregate the comprehensive performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score to construct a data acquisition function. Based on the data acquisition function, select some configurations from the candidate hardware configurations for low-level simulation to obtain the true multi-task labels containing the true IPC value and the true Top-Down microstructure bottleneck index. Calculate the true hotspot-level comprehensive performance score corresponding to each hotspot code region based on the true multi-task labels, and aggregate them according to the execution weight of the hotspot code region to obtain the true application-level comprehensive performance score of each candidate hardware configuration. Update the currently known best true application-level comprehensive performance score. The overall performance score is calculated by weighting the IPC estimate and the Top-Down microstructure bottleneck index in the multi-task prediction label. Let the overall performance score of the m-th hot code region under the j-th candidate hardware configuration be denoted as . , ,in, R represents the component weights estimated by IPC. This represents the normalized scoring function for the IPC estimate. This represents the estimated IPC value in the multi-task prediction label. T represents the weight of the Top-Down microstructure bottleneck index component. This represents the normalized scoring function obtained by transforming the Top-Down microstructure bottleneck index. This indicates the Top-Down microstructure bottleneck metric in the multi-task prediction label. , This represents the set of Top-Down bottleneck indicators; Indicates the bottleneck type index; This indicates that the m-th hotspot code region is in the candidate hardware configuration. Predicted values ​​for the bottleneck indicators of category b; This represents the penalty weight corresponding to the bottleneck indicator of type b. Each Top-Down metric is converted from a percentage to a [0,1] ratio before entering the scoring function. A set of bottleneck penalties at the same level that are mutually exclusive is selected, excluding Retiring classes and not including both parent and child items simultaneously, to avoid duplicate counting at different levels; each penalty weight satisfies the following conditions: ; The extreme value normalization process is performed on the overall performance score to obtain the normalized overall performance score. , ,in, and These represent the minimum and maximum overall performance scores in the current candidate configuration set, respectively. This indicates a very small positive number that prevents the denominator from being zero; The uncertainty is estimated by performing multiple forward inferences on the software and hardware correlation exploration agent network and calculating the variance of the overall performance score; Let the estimated uncertainty be denoted as , ,in, This indicates the number of perturbation forward inference, model ensemble inference, or history error calibration inference. This represents the overall performance score obtained from the t-th forward inference. express The average of the comprehensive performance scores; The estimation uncertainty is normalized by extreme value processing to obtain ; Spatial novelty is obtained by calculating the minimum feature distance between the current candidate hardware configuration and the set of hardware configurations that have been simulated. Candidate hardware configurations in round u Spatial novelty relative to the already simulated configuration set is denoted as , ,in, This represents the set of hardware configurations that have completed the underlying simulation at the end of round u-1. This indicates that the hardware configuration for the underlying simulation has been completed. Denotes the hardware-side feature mapping function, d A distance metric function representing the distance between hardware configurations; The spatial novelty was normalized to obtain ; The bottleneck-parameter matching score is obtained by evaluating the potential benefit of the hardware parameters of the current candidate hardware configuration in alleviating the predicted Top-Down bottleneck. The bottleneck-parameter matching score is denoted as... , Among them, G This represents a bottleneck-parameter matching function, used to evaluate whether candidate configurations can improve the current bottleneck based on the mapping relationship between top-down bottleneck types and hardware parameter sets; when When the backend is highly constrained, improve the matching score for changes in parameters related to cache, queue, load / store pipeline, and memory hierarchy; when the frontend is highly constrained, improve the matching score for changes in parameters related to ICache, fetch width, and branch prediction. The bottleneck-parameter matching score is normalized to obtain ; The comprehensive performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score are weighted and summed to construct the m-th hotspot code region in the u-th round on the candidate hardware configuration. The following acquisition function is used to obtain the joint acquisition score. , ,in, , , and These represent the weights of the overall performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score, respectively. To ensure that the same candidate hardware configuration forms a unique ranking across multiple hot code regions, application-level aggregation is performed based on normalized hot execution weights: .in, .

[0044] When step 5 is executed for the first time, the weights of the acquisition function satisfy the non-negativity and normalization constraints, and the preferred weights are... The number of forward inference steps used for variance estimation satisfies .

[0045] Let the set of candidate hardware configurations for low-level simulation in the u-th round be denoted as . That is, select up to a maximum number of applications based on their application-level collection scores, from highest to lowest. There are 10 candidate hardware configurations that have not yet completed the underlying simulation; if the number of remaining candidate configurations is less than 100... If so, select all remaining configurations.

[0046] The m-th hotspot code region is in the candidate hardware configuration The actual overall performance score is recorded as follows: ,in, This represents the actual IPC components obtained from the underlying simulation. This represents the true Top-Down bottleneck vector obtained from the underlying simulation.

[0047] The real-world application-level comprehensive performance score of the j-th candidate hardware configuration is: The predicted value before simulation is denoted as follows: .

[0048] make This represents the number of candidate hardware configurations in the actual simulation of the u-th round, and the average relative error of the u-th round is... ,in, For the r-th selected configuration index, To prevent extremely small positive numbers with a denominator of zero.

[0049] The effective detection rate in the u-th round of underlying simulation samples is The indicator function takes the value 1 when the condition is true and 0 otherwise. This is the best known real-world application-level score from the previous round. This is the preset minimum boost threshold.

[0050] At the end of round u, the known best real-world application-level overall performance score was updated to... .

[0051] Step 6: Update the weights of the acquisition function based on the average relative error and effective discovery rate calculated in Step 5; fine-tune the pre-trained hardware-software association exploration agent network using real multi-task labels in the feedback data pool and pre-reserved historical replay data. The weights of the acquisition function are updated by adaptively adjusting the weights of the comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score in the acquisition function based on the average relative error and effective discovery rate of the simulation results. After completing the underlying simulation and adding the new simulation samples to the feedback data pool, the u-th round of feedback data pool is obtained. The specific operation process is as follows: The weight of the overall performance score for round u+1 before normalization is denoted as... , ,in, Indicates the lower bound of the weight. This indicates the step size for weight updates in the data collection function; Let the uncertainty weight of the (u+1)th round estimate before normalization be denoted as... , ; Let the spatial novelty weight of the (u+1)th round before normalization be denoted as . , ; Let the unnormalized bottleneck-parameter matching score weight of round u+1 be denoted as , ; Let the weight normalization factor of the (u+1)th round acquisition function be denoted as , ; Obtain the normalized weights of the comprehensive performance score for the (u+1)th round. Estimating uncertainty weights Spatial novelty weight Bottleneck-parameter matching score weights , , ; Let the set of hardware configurations that have completed low-level simulation at the end of round u be denoted as . , ,in, Represents the union of sets; The feedback data pool after the end of round u is denoted as , ,in, This represents the set of hardware configurations corresponding to the newly added simulation samples in the u-th round. Feedback Data Pool The sample format in the middle is To mitigate the risk of overfitting due to a small number of newly added samples, the hardware-software correlation exploration agent network is fine-tuned. This includes: freezing the parameters of the first L-2 coding layers in the multi-layer coding system, and only updating the parameters of the last two coding layers, the gated fusion layer, and the multi-task output head; the fine-tuning uses a learning rate lower than that used in the initial training phase, and the fine-tuning loss is calculated using real multi-task labels and pre-reserved reference data. The specific steps are as follows: The set of parameters frozen during the online fine-tuning phase is denoted as... , ,in, This indicates the total number of coding layers in the exploratory proxy model; Let the set of parameters to be updated during the online fine-tuning phase be denoted as . , ,in, Indicates the parameters of the gating fusion module. Indicates multi-tasking output header parameters; Obtain the fine-tuning loss in the uth round , ,in, This indicates pre-reserved reference data. Indicates the weight of historical playback loss; Obtain the parameters to be updated after the u-th round of fine-tuning. , ,in, This represents the parameters to be updated before the u-th round of fine-tuning. This indicates fine-tuning the learning rate; this formula represents a gradient update, which is repeated in preset batches and 16~32 epochs during actual training.

[0052] When acquiring underlying simulation data to trigger online fine-tuning, due to the small sample size and the need to prevent catastrophic forgetting, the system adopts low learning rate, local parameter updates, and experience replay constraints: all parameters of the first L-2 coding layers are frozen, and only the parameters of the last two coding layers, the gated fusion layer, and the multi-task output head are updated; the optimizer keeps AdamW unchanged, disables learning rate warm-up and cosine decay, and adopts a constant learning rate. Batch size reduced to 32-128, training for 16-32 epochs; Gaussian noise superposition of input features turned off to achieve stable fitting and fast convergence of high-value configurations.

[0053] Step 7: Repeat steps 4 to 6 until a preset termination condition is met. From the set of hardware configurations that have completed low-level simulation, the actual comprehensive performance scores of each candidate hardware configuration in each hotspot code region are weighted and summed according to the execution weight of each hotspot code region to obtain the actual application-level comprehensive performance score of each candidate hardware configuration that has completed simulation. The candidate hardware configuration with the largest actual application-level comprehensive performance score is selected as the final recommended hardware configuration and output, thus completing the exploration of the hardware design space. The preset termination conditions include: convergence of the optimal actual application-level comprehensive performance score and reaching the preset maximum number of iterations. Or the total number of configurations for the underlying simulation reaches the preset simulation budget; The convergence of the optimal real application-level comprehensive performance score is determined as follows: calculate the relative change between the known optimal real comprehensive performance score in the current round and the known optimal real comprehensive performance score in the previous round. When the relative change of the optimal real application-level comprehensive performance score is less than the convergence threshold for all C_conv rounds, it is considered converged. The best real-world application-level overall performance score at the end of round u is .when The optimal real-world application-level comprehensive performance score is determined to converge at a given time. To prevent extremely small positive numbers with a denominator of zero, This is the preset convergence threshold.

[0054] The condition for the total number of configurations for the underlying simulation to reach the preset simulation budget is: Where v is the index of the online exploration iteration round, and u is the current iteration round. This represents the number of candidate hardware configurations in the actual simulation of round v. This represents the budget for the total number of configurations allowed to perform low-level simulations.

[0055] The specific steps to obtain the final recommended hardware configuration are as follows: For application A to be evaluated, first analyze each hot code region m and each candidate hardware configuration. Calculate the overall performance score at the hotspot level. ; Then, based on the execution weight of the hot code regions, application-level aggregation is performed to obtain the j-th candidate hardware configuration for application A. Application-level overall performance score , ,in This represents the normalized weight of the m-th hotspot code region. , This represents the weight source quantity of the m-th hot code region. The number of instructions, the number of cycles, or the sampling percentage of the hot code region can be used. This represents the total number of hotspot code regions in application A to be evaluated. This indicates the index for summing hotspot code regions. This represents the overall performance score of the m-th hotspot code region under the j-th candidate hardware configuration. From the set of hardware configurations that have completed low-level simulation, the candidate hardware configuration with the highest comprehensive performance score at the real application level is selected as the final recommendation. , ,in, Represents the set of candidate hardware configurations. This represents the j-th candidate hardware configuration. This represents the set of hardware configurations for application A to be evaluated, based on the completed low-level simulation. The following is an application-level overall performance score. This indicates the selection of the candidate hardware configuration that yields the highest overall application-level performance score.

[0056] like Figure 2 As shown, a rapid exploration system for hardware design space oriented towards microstructures includes: The application feature extraction module is used to obtain multiple hotspot code regions in the application to be evaluated, and to perform feature processing on each hotspot code region to obtain the corresponding application-side feature representation. The hardware encoding module is used to obtain multiple candidate hardware configurations in the hardware design space to be explored. The candidate hardware configurations include multiple hardware parameters. Each hardware parameter is structured and encoded according to its type. The encoding results of all hardware parameters are then concatenated to obtain the hardware-side feature representation corresponding to each candidate hardware configuration. The joint token sequence construction module is used to map the application-side feature representation and hardware-side feature representation corresponding to each software and hardware combination consisting of each hot code region and each candidate hardware configuration to a unified dimension, so as to obtain a unified multimodal joint input containing the software and hardware interaction context. The multi-task output module is used to input the unified multimodal joint input into the pre-trained hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layers. The multi-task output head is used to calculate the multi-task prediction label of the candidate hardware configuration. The simulation feedback module is used to calculate the comprehensive performance score corresponding to each hardware and software combination based on the multi-task prediction label, and to perform weighted aggregation of the comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score to construct the acquisition function. Based on the acquisition function, a portion of the configurations are selected from the candidate hardware configurations for low-level simulation to obtain the real multi-task labels. The model calibration module is used to update the weights of the acquisition function using real multi-task labels and to fine-tune the pre-trained hardware-software correlation exploration agent network. The configuration output module is used to repeatedly execute the multi-task output module to the model calibration module until the preset termination condition is met. From the set of hardware configurations that have completed the low-level simulation, the real comprehensive performance scores of each candidate hardware configuration in each hot code region are weighted and summed according to the execution weight of each hot code region to obtain the real application-level comprehensive performance score of each candidate hardware configuration that has completed the simulation. The candidate hardware configuration with the largest real application-level comprehensive performance score is selected as the final recommended hardware configuration and output.

[0057] To verify the effectiveness of the proposed method, a pre-training sample set was constructed using a combination of publicly available benchmark program sets and hardware design space simulation. On the application side, SPEC CPU2006, SPEC CPU2017, and a custom microkernel program were selected. Application-side feature representations were extracted using LLVM compiler front-end analysis and performance sampling tools. The hardware side defined a design space including L1D cache capacity, L1I cache capacity, L2 cache capacity, TLB entries, reordering buffer size, load queue size, store queue size, issue width, pipeline depth, cache replacement strategy, and branch predictor type. Latin hypercube sampling was used for each procedure. Approximately 200 configurations were uniformly sampled, and the dataset was run on the gem5 periodic precision simulator, recording IPC values ​​and Top-Down microstructure bottleneck data as ground truth labels to obtain the final pre-trained sample set. ,in The labels are multi-task vectors, containing IPC and Top-Down bottleneck metrics. The total number of samples is approximately 10,000. The pre-training sample set is divided into training, validation, and test sets (8:1:1 ratio) according to the program dimension. There is no program overlap between the three subsets to ensure that the evaluation focuses on the model's cross-program generalization ability to unseen programs.

[0058] The experimental environment adopts an ARMv8-A (AArch64) architecture with dual 128 cores and a main frequency of 2.6 GHz; L1d is 64 KB per core (4-way associative), L1i is 64 KB per core (4-way associative), L2 is 512 KB per core (16-way associative), and L3 is shared between chips for a total of 128 MiB; the issue width is 4, the reorder buffer (ROB) depth is 128, the pipeline depth is 11 stages, and a multi-stage dynamic branch predictor is used; the system is a 4-node NUMA structure.

[0059] On the test set, the estimated IPC values ​​and predicted Top-Down bottleneck indicators of the software and hardware association exploration agent network in the proposed method of this invention are compared with the actual values ​​obtained from gem5 simulation. Typical results are shown in Table 1 (the two columns of OpenFoam in Table 1 correspond to different hot spots of the same program; except for IPC, the values ​​of other bottleneck indicators are all percentages).

[0060] Table 1

[0061] As shown in Table 1, the hardware-software correlation exploration proxy network in the proposed method can accurately reproduce the dominant conclusion of Top-Down bottleneck decomposition. For the Backend Bound, which accounts for the highest proportion of the first-level bottleneck, the predicted values ​​of the three test hotspot samples are 53.85%, 89.36%, and 91.95%, respectively, corresponding to actual values ​​of 52.66%, 88.07%, and 92.29%, with relative errors of approximately 2.2%, 1.4%, and 0.4%, respectively. This indicates that the proxy network has high estimation accuracy for large-scale performance bottlenecks. For indicators such as Frontend Bound and Bad Spec, which have relatively small values ​​(usually below 1%), their absolute errors remain at a low level. However, due to the small ontology values, the relative errors are easily amplified. Therefore, it is advisable to combine the absolute errors for comprehensive evaluation, which does not affect the proxy network's ability to identify the dominant bottleneck.

[0062] Regarding the macro-level throughput metric IPC, the hardware-software correlation exploration agent network proposed in this invention can also effectively track performance differences between different workloads. For Gromacs with high IPC (predicted 1.84 vs. actual 1.89) and OpenFoam with low IPC (predicted 0.32 vs. actual 0.31), the agent network can reasonably reflect the differences in hardware resource requirements of different hotspots, providing a reliable performance estimation basis for subsequent hardware configuration selection.

[0063] In summary, the method proposed in this invention has good fidelity in multi-task prediction of IPC and Top-Down bottleneck metrics, especially in providing low-error estimates for bottleneck categories that dominate performance, thus providing reliable input for subsequent bottleneck-aware acquisition functions and exploration processes.

Claims

1. A method for rapid exploration of hardware design space for microstructures, characterized in that... Includes the following steps: Step 1: Obtain multiple hotspot code regions in the application to be evaluated, and perform feature processing on each hotspot code region to obtain the corresponding application-side feature representation. Step 2: Obtain multiple candidate hardware configurations in the hardware design space to be explored. The candidate hardware configurations include multiple hardware parameters. Each hardware parameter is structured and encoded according to its type. The encoding results of all hardware parameters are then concatenated to obtain the hardware-side feature representation corresponding to each candidate hardware configuration. Step 3: For each software and hardware combination consisting of each hot code region and each candidate hardware configuration, map the application-side feature representation and hardware-side feature representation corresponding to the software and hardware combination to a unified dimension to obtain a unified multimodal joint input containing the software and hardware interaction context. Step 4: Input the unified multimodal joint input into the pre-trained hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layer. The multi-task prediction label of the candidate hardware configuration is calculated through the multi-task output head. Step 5: Calculate the comprehensive performance score corresponding to each hardware and software combination based on the multi-task prediction label, and perform weighted aggregation of the comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score to construct the acquisition function. Select some configurations from the candidate hardware configurations based on the acquisition function to perform low-level simulation and obtain the real multi-task label. Step 6: Update the weights of the acquisition function using real multi-task labels, and fine-tune the pre-trained hardware-software association exploration agent network. Step 7: Repeat steps 4 to 6 until the preset termination condition is met. From the set of hardware configurations that have completed the underlying simulation, the actual comprehensive performance scores of each candidate hardware configuration in each hot code region are weighted and summed according to the execution weight of each hot code region to obtain the actual application-level comprehensive performance score of each candidate hardware configuration that has completed the simulation. Select the candidate hardware configuration with the largest actual application-level comprehensive performance score as the final recommended hardware configuration and output it to complete the exploration of the hardware design space.

2. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... In step 2, the types of hardware parameters include capacity parameters, counting parameters, and strategy parameters; Structured coding specifically includes: For capacity-type parameters, the interval normalized encoding after log2 transformation is used; For count-type parameters, interval normalization encoding is used; For strategy parameters, embedded encoding is used.

3. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... In step 3, the specific operation to obtain the unified multimodal joint input containing the software and hardware interaction context is as follows: Apply a first linear mapping to the application-side feature representation and a second linear mapping to the hardware-side feature representation, so that the two are in the same vector space; The mapped application-side feature representations are constructed into an application-side token sequence, the mapped hardware-side feature representations are constructed into a hardware-side token sequence, and a global aggregation token and a sequence end token are added to the sequence to form a basic token sequence. Modal embedding, parameter set embedding, and positional embedding are superimposed on the basic token sequence to obtain a unified multimodal joint input.

4. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... In step 4, each layer in the multi-layer coding layer performs the following operations on the input sequence in sequence: multi-head self-attention operation, cross-modal attention and gating fusion operation, residual connection and layer normalization operation, and feedforward network operation. The output of the feedforward network is then processed by residual connection and layer normalization and used as the output of the current layer. The cross-modal attention and gating fusion operation includes: generating a key matrix and a value matrix based on the hardware-side token sequence, generating a query matrix based on the basic token sequence, and calculating the cross-modal cross-attention output; concatenating the average representation of the application-side token sequence and the average representation of the hardware-side token and then calculating the fusion weight through a Sigmoid gating network; and using the fusion weight to perform weighted fusion of the cross-modal cross-attention output and the multi-head self-attention output. The specific operation of calculating the multi-task prediction label of the candidate hardware configuration through the multi-task output head includes: extracting the hidden representation corresponding to the global aggregate token from the output of the last coding layer, inputting the hidden representation into the multilayer perceptron for mapping, and obtaining the multi-task prediction label; The multi-task prediction labels include IPC estimates and Top-Down microstructure bottleneck indices.

5. The method for rapid exploration of hardware design space for microstructures according to claim 4, characterized in that... In step 5, the comprehensive performance score is calculated by weighting the IPC estimate from the multi-task prediction label and the Top-Down microstructure bottleneck index; The estimated uncertainty is obtained by performing multiple forward inferences on the hardware-software association exploration agent network and calculating the variance of the comprehensive performance score; the spatial novelty is obtained by calculating the minimum feature distance between the current candidate hardware configuration and the set of hardware configurations that have completed simulation. The bottleneck-parameter matching score is obtained by evaluating the potential benefit of the hardware parameters of the current candidate hardware configuration in alleviating the predicted Top-Down bottleneck; the acquisition function is constructed as a weighted sum of the normalized comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score. The real multitasking labels include real IPC values ​​and real Top-Down microstructure bottleneck metrics.

6. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... Before the first execution of step 5, the process also includes: selecting an initial seed configuration from candidate hardware configurations for low-level simulation, storing the simulated real multi-task labels into the feedback data pool, and storing the initial seed configuration into the simulated configuration set to initialize the feedback data pool and the simulated configuration set.

7. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... Step 6 updates the weights of the acquisition function, including: adaptively adjusting the weights of the comprehensive performance score, estimation uncertainty, spatial novelty, and bottleneck-parameter matching score in the acquisition function based on the average relative error and effective discovery rate of the simulation results in this round. Step 6 involves fine-tuning the pre-trained hardware-software association exploration agent network, including: freezing the parameters of the first L-2 coding layers in the multi-layer coding layers, and updating only the parameters of the last two coding layers, the gated fusion layer, and the multi-task output head; fine-tuning uses a learning rate lower than that in the initial training phase, and calculates the fine-tuning loss using real multi-task labels and pre-reserved reference data.

8. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... In step 7, the preset termination conditions include: the optimal real application-level comprehensive performance score converges, the preset maximum number of iterations is reached, or the total number of configurations for the underlying simulation reaches the preset simulation budget. The convergence of the optimal real-application-level comprehensive performance score is determined by calculating the relative change between the known optimal real-application comprehensive performance score in the current round and the known optimal real-application comprehensive performance score in the previous round. When the relative change is less than a preset threshold, it is considered converged.

9. The method for rapid exploration of hardware design space for microstructures according to claim 1, characterized in that... The pre-trained hardware-software association exploration agent network is obtained through the following pre-training steps: Step A1: Obtain the pre-trained sample set, which contains hot code regions of multiple known applications, multiple known hardware configurations, and corresponding real multi-task labels obtained through the underlying simulator. Step A2: Perform feature processing on each hotspot code region to obtain application-side feature representation; Step A3: For each known hardware configuration, perform structured encoding on the hardware parameters according to the type of the hardware parameters, and concatenate the encoding results of all hardware parameters to obtain the hardware-side feature representation. Step A4: For each software and hardware combination consisting of each hot code region and each known hardware configuration, map the application-side feature representation and hardware-side feature representation corresponding to the software and hardware combination to a unified dimension to obtain a unified multimodal joint input. Step A5: Input the unified multimodal joint input into the hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layer. The multi-task prediction label is calculated through the multi-task output head. Step A6: Calculate the joint loss based on the multi-task predicted labels and the real multi-task labels, and backpropagate to update the parameters of the hardware-software association exploration agent network until the pre-training termination condition is met, thus obtaining the pre-trained hardware-software association exploration agent network.

10. A rapid exploration system for hardware design space oriented towards microstructures, characterized in that... include: The application feature extraction module is used to obtain multiple hotspot code regions in the application to be evaluated, and to perform feature processing on each hotspot code region to obtain the corresponding application-side feature representation. The hardware encoding module is used to obtain multiple candidate hardware configurations in the hardware design space to be explored. The candidate hardware configurations include multiple hardware parameters. Each hardware parameter is structured and encoded according to its type. The encoding results of all hardware parameters are then concatenated to obtain the hardware-side feature representation corresponding to each candidate hardware configuration. The joint token sequence construction module is used to map the application-side feature representation and hardware-side feature representation corresponding to each software and hardware combination consisting of each hot code region and each candidate hardware configuration to a unified dimension, so as to obtain a unified multimodal joint input containing the software and hardware interaction context. The multi-task output module is used to input the unified multimodal joint input into the pre-trained hardware-software association exploration agent network. The hardware-software association exploration agent network includes multiple coding layers. The unified multimodal joint input is encoded and modeled through the multi-head self-attention mechanism and the cross-modal attention and gating fusion mechanism of the coding layers. The multi-task output head is used to calculate the multi-task prediction label of the candidate hardware configuration. The simulation feedback module is used to calculate the comprehensive performance score corresponding to each hardware and software combination based on the multi-task prediction label, and to perform weighted aggregation of the comprehensive performance score, estimation uncertainty, spatial novelty and bottleneck-parameter matching score to construct the acquisition function. Based on the acquisition function, a portion of the configurations are selected from the candidate hardware configurations for low-level simulation to obtain the real multi-task labels. The model calibration module is used to update the weights of the acquisition function using real multi-task labels and to fine-tune the pre-trained hardware-software correlation exploration agent network. The configuration output module is used to repeatedly execute the multi-task output module to the model calibration module until the preset termination condition is met. From the set of hardware configurations that have completed the low-level simulation, the real comprehensive performance scores of each candidate hardware configuration in each hot code region are weighted and summed according to the execution weight of each hot code region to obtain the real application-level comprehensive performance score of each candidate hardware configuration that has completed the simulation. The candidate hardware configuration with the largest real application-level comprehensive performance score is selected as the final recommended hardware configuration and output.

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