Semiconductor process yield prediction method, device, apparatus and medium

Abstract

The application relates to a semiconductor process yield prediction method, device, equipment and medium, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: acquiring a wafer manufacturing recipe comprising preset key process parameters of a plurality of chips at different positions on a wafer; acquiring measurement information of a wafer after the wafer is manufactured according to the wafer manufacturing recipe; acquiring input data-output data sets comprising chip numbers and chip position information of the chips at different positions according to the measurement information of the chips at different positions; automatically tuning hyperparameters of a gradient boosting decision tree based on Bayesian optimization according to the input data-output data sets to obtain a target prediction model with a test result meeting a standard; applying a constraint condition, screening in a virtual process parameter space based on the target prediction model, and acquiring key process parameters and a yield of an optimal recipe used for guiding a mass production batch. At least the yield and performance of an advanced process can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus, equipment and medium for predicting semiconductor process yield. Background Technology

[0002] In semiconductor manufacturing, as the design size of semiconductor devices continues to shrink, the market is placing higher demands on the yield and performance of advanced processes.

[0003] Semiconductor device yield is strongly positively correlated with manufacturing equipment: the precision, stability, cleanliness and process control capabilities of the equipment directly determine the defect density, and thus dominate the yield; under advanced processes, equipment performance has even become the primary bottleneck for yield ramp-up.

[0004] Semiconductor device manufacturing equipment is a precision instrument, susceptible to environmental, systematic, and measurement errors, making it difficult to effectively predict and discover the key process parameters and yield of current semiconductor device manufacturing equipment. Improving the yield of advanced processes has become one of the important research directions for researchers in this field. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor process yield prediction method, apparatus, equipment, and medium to address the aforementioned technical problems. This method should be able to effectively predict and discover the key process parameters and yield of the optimal formulation of current semiconductor device manufacturing equipment, thereby further improving the yield and performance of advanced processes.

[0006] In a first aspect, this application provides a method for predicting semiconductor process yield, including:

[0007] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0008] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0009] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0010] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0011] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0012] In some embodiments, obtaining a wafer fabrication recipe includes:

[0013] Starting with the critical dimension of the center gate of the wafer and ending with the critical dimension of the edge of the wafer, the radial gradient algorithm is used to determine the critical dimensions of multiple chips between the center and the edge.

[0014] Using the ion implantation dose at the first and second endpoints of the wafer's X-axis diameter as the starting and ending points, respectively, a linear gradient algorithm is employed to determine the ion implantation dose of multiple chips between the first and second endpoints.

[0015] Using the bottom and top annealing temperatures of the wafer's Y-axis diameter as the starting and ending points, respectively, a linear gradient algorithm is employed to determine the annealing temperatures of multiple chips between the bottom and top points.

[0016] In some embodiments, the gate critical size is 18nm-22nm.

[0017] In some embodiments, the ion implantation dose is .

[0018] In some embodiments, the annealing temperature is 900-1100 degrees Celsius.

[0019] In some embodiments, with the center of the wafer as the origin of the coordinate system, the chip numbering on the wafer along the X-axis away from the origin is used to characterize the chip's horizontal coordinate, and the chip numbering on the wafer along the Y-axis away from the origin is used to characterize the chip's vertical coordinate.

[0020] In some embodiments, before training the initial model to obtain the target prediction model, the method further includes:

[0021] Data cleaning algorithms are used to remove outliers from the input-output data set.

[0022] In some embodiments, the target prediction model includes an electrical parameter regression model and a good product classification model;

[0023] By using a regularized empirical risk minimization model, we search for an electrical parameter regression model in the function set that minimizes the mean squared deviation between the electrical parameter values ​​predicted by the electrical parameter regression model and the corresponding true target values.

[0024] Find a good product classification model in the function space that minimizes the average log loss based on the input-output data set plus the regularization term.

[0025] In some embodiments, the semiconductor process yield prediction method further includes the step of obtaining a virtual process parameter space:

[0026] A virtual recipe in the virtual process parameter space is generated using Latin hypercube sampling. The virtual recipe includes target key process parameters, predicted electrical parameters, and predicted yield, which contain chip number and chip location information.

[0027] Secondly, this application also provides a semiconductor process yield prediction device, including an input information acquisition module, a measurement information acquisition module, a position information acquisition module, a prediction model training module, and a prediction module. The input information acquisition module is used to acquire a wafer manufacturing recipe that includes at least preset key process parameters for chips at multiple different locations on the wafer; the key process parameters include ion implantation dose, gate critical dimension, and annealing temperature. The measurement information acquisition module is used to acquire measurement information of the wafer after fabrication according to the wafer manufacturing recipe, including the actual key process parameters, electrical parameters, and yield status of chips at multiple different locations on the wafer. The position information acquisition module is used to acquire measurement information of chips at different locations... The system acquires input-output data sets containing chip number and chip location information for chips at different locations. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters, and yield status. The prediction model training module is used to automatically fine-tune the hyperparameters of the gradient boosting decision tree based on Bayesian optimization using the input-output data set to obtain a target prediction model that meets the test results. The prediction module is used to apply constraints and, based on the target prediction model, filter in the virtual process parameter space to obtain the key process parameters and yield of the optimal formula for guiding mass production batches. The constraints include a predicted yield greater than or equal to a yield threshold, and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0028] In some embodiments, the input information acquisition module is configured to: use a radial gradient algorithm to determine the critical dimensions of multiple chips between the center and the edge, starting from the center gate critical dimension of the wafer and ending at the edge critical dimension of the wafer;

[0029] Using the ion implantation dose at the first and second endpoints of the wafer's X-axis diameter as the starting and ending points, respectively, a linear gradient algorithm is used to determine the ion implantation dose of multiple chips between the first and second endpoints. Using the annealing temperatures at the bottom and top points of the wafer's Y-axis diameter as the starting and ending points, respectively, a linear gradient algorithm is used to determine the annealing temperatures of multiple chips between the bottom and top points.

[0030] In some embodiments, the semiconductor process yield prediction apparatus further includes a virtual recipe generation module; the virtual recipe generation module is configured to generate a virtual recipe in a virtual process parameter space using Latin hypercube sampling, the virtual recipe including target key process parameters containing chip number and chip location information, predicted electrical parameters and predicted yield.

[0031] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0032] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0033] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0034] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0035] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0036] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0037] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0038] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0039] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0040] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0041] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0042] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0043] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0044] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0045] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0046] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0047] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0048] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0049] The aforementioned semiconductor process yield prediction methods, apparatus, computer equipment, computer-readable storage media, and computer program products include at least the following unexpected technical effects:

[0050] After obtaining a wafer manufacturing recipe with preset key process parameters for chips at multiple different locations on the wafer, including ion implantation dose, gate critical dimension, and annealing temperature, the wafer measurement information after tape-out according to the wafer manufacturing recipe is then obtained. This measurement information includes the actual key process parameters, electrical parameters, and yield status of chips at multiple different locations on the wafer. Then, based on the wafer manufacturing recipe and measurement information, an input-output data set containing chip number and chip location information for chips at different locations is obtained. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters, and yield status, to achieve the goal of determining the chip's location information based on its chip number. This method establishes a one-to-one relationship between preset key process parameters and measurement information. Based on the input-output data set, it automatically tunes the hyperparameters of the gradient boosting decision tree using Bayesian optimization to obtain a target prediction model that meets test results. Then, it applies constraints to filter key process parameters and yields in a virtual process parameter space based on the target prediction model, obtaining the optimal formulation for mass production batches. These constraints include a predicted yield greater than or equal to a yield threshold, and minimal absolute deviation of electrical parameters from the corresponding threshold. This effectively predicts and discovers the optimal formulation key process parameters and yields for current semiconductor device manufacturing equipment, further improving the yield and performance of advanced processes. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a flowchart illustrating a semiconductor process yield prediction method in one embodiment of this application;

[0053] Figure 2 This is a structural block diagram of a semiconductor process yield prediction device in one embodiment of this application;

[0054] Figure 3 This is an internal structural diagram of a computer device according to an embodiment of this application;

[0055] Figure labels and descriptions:

[0056] 11. Input information acquisition module; 12. Measurement information acquisition module; 13. Location information acquisition module; 14. Prediction model training module; 15. Prediction module. Detailed Implementation

[0057] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0059] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0060] Furthermore, the terms “first”, “second”, etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0061] Given the limitations of equipment precision and the unavoidable nature of various errors, how to tap into technological potential and continuously improve yield is not only a daily task for process integration engineers, but also one of the key factors determining whether chip manufacturing can move from "being able to do it" to "being able to do it well and make money".

[0062] Based on this, this application aims to provide a semiconductor process yield prediction method, apparatus, equipment and medium, which can at least effectively predict and discover the key process parameters and yield of the optimal formulation of current semiconductor device manufacturing equipment, and further improve the yield and performance of advanced processes.

[0063] The semiconductor process yield prediction methods provided in this application can be applied to various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Head-mounted devices can include virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc.

[0064] Please refer to Figure 1 In some embodiments, a semiconductor process yield prediction method is provided, including:

[0065] Step S210: Obtain a wafer manufacturing recipe that includes at least a number of chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0066] For example, in order to reduce the difficulty of data acquisition and improve the accuracy of the acquired data, after determining the types of key process parameters that need to be optimized, such as the key dimensions of the silicon gate, the interlayer overlay accuracy of metal layers, the gate oxide thickness, the ion implantation dose, the gate key dimensions and the annealing temperature, it is necessary to determine the spatial distribution of each type of key process parameter on the wafer surface.

[0067] For example, the specific implementation principle of the embodiments of this application is illustrated by taking the joint optimization of the threshold voltage and yield of FinFET devices as an example. Fluctuations in the threshold voltage (Vt) of FinFET devices can lead to unstable yield. In order to find the optimal combination of process parameters to stabilize the threshold voltage Vt within the range of 0.35V±5% while achieving a yield ≥99.5%, the key process parameters that need to be predicted and optimized include ion implantation dose, gate critical dimension, and annealing temperature.

[0068] For example, with the center of the wafer as the origin, the chip number along the X-axis away from the origin is used to characterize the chip's abscissa u, and the chip number along the Y-axis away from the origin is used to characterize the chip's ordinate v. The angle between the line connecting the chip's center point and the origin and the X-axis is θ. Specific parameter setting schemes can be adopted as follows: 1) Ion implantation dose: Using the ion implantation dose at the first and second endpoints of the wafer's X-axis diameter as the starting and ending points, a linear gradient algorithm is used to determine the ion implantation dose of multiple chips between the first and second endpoints; 2) Gate critical dimension: Using the center gate critical dimension of the wafer as the starting point and the edge critical dimension of the wafer as the ending point, a radial gradient algorithm is used to determine the critical dimensions of multiple chips between the center and the edge; 3) Annealing temperature: Using the bottom and top annealing temperatures of the wafer's Y-axis diameter as the starting and ending points, a linear gradient algorithm is used to determine the annealing temperatures of multiple chips between the bottom and top points.

[0069] For example, for gate critical dimensions (target range 18nm-22nm), if the center gate critical dimension of the wafer is 18nm and the edge gate critical dimension is 22nm, then the multiple chips between the aforementioned center and edge... The critical dimension CD can be calculated using the radial gradient, as follows:

[0070] Formula (1).

[0071] For example, the ion implantation dose at the first endpoint of the diameter on the X-axis of the wafer is used. Second-terminal ion implantation dose Using X-axis linear gradient algorithm as the starting and ending points, the ion implantation dose (Dose) of multiple chips between the first and second endpoints is determined:

[0072] Formula (2).

[0073] For example, using the bottom endpoint annealing temperature of 900 degrees Celsius and the top endpoint annealing temperature of 1100 degrees Celsius on the Y-axis of the wafer as the starting and ending points respectively, the following Y-axis linear gradient algorithm is used to determine the annealing temperature Temp of multiple chips between the bottom endpoint and the top endpoint:

[0074] Formula (3).

[0075] Based on the above formulas (1)-(3), the parameterized wafer manufacturing formulas shown in Table 1 below can be obtained.

[0076] Step S220: Obtain the measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0077] For example, according to the wafer manufacturing formula, the actual critical process parameters, electrical parameters and yield status of each chip on the wafer are measured. The actual critical process parameters include ion implantation dose, gate critical dimension and annealing temperature.

[0078] Step S230: Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0079] Table 1

[0080]

[0081] Table 2

[0082]

[0083] For example, with the center of the wafer as the origin, the chip numbers on the wafer along the X-axis away from the origin are used to characterize the chip's horizontal coordinate, and the chip numbers along the Y-axis away from the origin are used to characterize the chip's vertical coordinate. Based on the chip's location information including its chip number, a one-to-one relationship is established between preset key process parameters and measurement information, resulting in the input-output data set shown in Table 2 above. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters, and product yield status.

[0084] Step S240: Based on the input data-output data set, automatically tune the hyperparameters of the gradient boosting decision tree using Bayesian optimization to obtain the target prediction model that meets the test results.

[0085] For example, after obtaining the input data-output data set as shown in Table 2 above, the following four-dimensional data matrix can be obtained. Where i represents the number of codes or the code index of the chip, and the chip's process data and electrical data are arranged according to the chip coordinates. Precise correspondence. With the center of the wafer as the origin, the chip number along the X-axis away from the origin is used to characterize the chip's horizontal coordinate u, and the chip number along the Y-axis away from the origin is used to characterize the chip's vertical coordinate v. or The i-th chip on the wafer is located at coordinates The target critical dimension value measured at the location. or The i-th chip on the wafer is located at coordinates Location, target ion implantation dose value. or The i-th chip on the wafer is located at coordinates The target temperature value for a key heat treatment process (such as rapid thermal annealing) at a given location. The i-th chip on the wafer is located at coordinates Good product status value measured at the location; The i-th chip on the wafer is located at coordinates Electrical parameter values ​​(e.g., threshold voltage) measured at the location.

[0086] For example, before training the initial model to obtain the target prediction model, the following is also included:

[0087] Data cleaning algorithms are used to remove outliers from the input-output data set.

[0088] For example, a golden dataset D can be created based on the data matrix after removing outliers. For instance, if the golden dataset D contains 720 data points, these 720 data points can be randomly divided into a training set Ntrain, a validation set Nval, and a test set Ntest. Ntrain = 504, Nval = 144, and Ntest = 72.

[0089] Step S250: Apply constraints and filter in the virtual process parameter space based on the target prediction model to obtain the key process parameters and yield of the optimal formula for guiding mass production batches; the constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimal.

[0090] For example, the target prediction models include electrical parameter regression models and good product classification models.

[0091] For example, a regularized empirical risk minimization model is used to find an electrical parameter regression model in the function set that minimizes the mean squared deviation between the electrical parameter values ​​predicted by the electrical parameter regression model and the corresponding true target values.

[0092] ;

[0093] Loss function: Mean squared error L is the squared loss for a single sample, representing the model's predicted value. Compared with the true value The square of the error between them.

[0094] ;

[0095] In the above formula, It is the final learned target electrical parameter regression model.

[0096] The following are empirical risk items (data fitting items):

[0097] ;

[0098] This is the mean squared error (MSE) loss. It measures the average squared deviation between the model's predicted values ​​and the true target values. Minimizing this term allows the model to fit the target value as accurately as possible. In the set of functions Find the function that minimizes the following expression. Regularization term: This is used to penalize the complexity of the function and prevent overfitting. The threshold voltage representing the i-th sample , For key process parameters, including ion implantation dose, gate critical dimension, and annealing temperature, represents the input feature vector of the i-th sample. Let be the predicted value for i samples. The regularization coefficient (hyperparameter) controls the regularization term. The weights are determined. A mapping relationship is learned using 504 sample points for rapid prediction and process optimization.

[0099] For example, this is achieved by finding a good product classification model in the function space that minimizes the average log loss based on the input-output data set plus a regularization term. For instance, the regularization empirical risk can be defined as follows:

[0100] Minimize the framework:

[0101] ;

[0102] In the above formula, This represents a good product classification model. Used to indicate in a set of functions Find the function that minimizes the following expression. . Used to represent the true yield of the i-th sample (usually 0 indicates that the yield is not up to standard, or 1 indicates that the yield is up to standard). The input feature vector used to represent the i-th sample. Used to represent the predicted value output by the good product classification model. This represents the logarithmic loss function. This is the regularization coefficient, used to control the strength of the regularization term. The regularization term represents the complexity of the penalty function.

[0103] The loss function includes binary cross-entropy:

[0104] ;

[0105] In the above formula, , True label (e.g., 1 represents the yield rate meets the standard, 0 represents the yield rate does not meet the standard). This represents the probability predicted by the model, indicating the likelihood that a sample meets the yield standard. Using a binary classification cross-entropy loss function, it is possible to predict whether a chip is qualified based on process parameters.

[0106] In some embodiments, electrical parameter regression model The training results of the good product classification model are shown in Table 3 below:

[0107] Table 3

[0108]

[0109] In Table 3 above, It is a very powerful machine learning algorithm, especially adept at handling massive, high-dimensional data to predict specific targets (such as yield). In learning algorithms, The maximum depth of each decision tree is Controlling the complexity of the tree is crucial. A shallower tree results in a simpler model, preventing overfitting; a deeper tree allows the model to capture more complex patterns, but it is also more prone to overfitting. Learning rate It controls the contribution of each new tree to the final model. A smaller learning rate (e.g.) More trees are needed for convergence, but this can improve generalization ability and reduce the risk of overfitting. yes The root mean square error of the regression model in predicting the threshold voltage, this error ensures The regression model has predictive accuracy with practical engineering value, sufficient to support subsequent process optimization (such as finding models that meet certain requirements). And yield (The recipe).

[0110] In Table 3 above, the performance of the good product classification model (XGBoost, max_depth=4, lr=0.08, accuracy=96.2%) has practical value in the semiconductor good product classification task.

[0111] In some embodiments, the semiconductor process yield prediction method further includes the step of obtaining a virtual process parameter space:

[0112] A virtual recipe in the virtual process parameter space is generated using Latin hypercube sampling. The virtual recipe includes target key process parameters, predicted electrical parameters, and predicted yield, which contain chip number and chip location information.

[0113] By using the Latin hypercube sampling method, a mapping bridge can be built between wafer manufacturing recipes and electrical parameters and yield, forming a complete dataset. This dataset can then be used to train a machine learning model that learns the complex mapping relationship between "process parameters" and "electrical / yield" parameters, thereby improving model accuracy.

[0114] In some embodiments, using a pre-trained model and model High-throughput filtering is performed in a virtual process parameter space. The virtual process parameter space is defined as follows: Latin hypercube sampling is used to generate A virtual recipe is shown in Table 4 below.

[0115] In some embodiments, constraints are applied to screen for the optimal formulation.

[0116] Multi-objective optimization problem definition: ; Used to represent decision variables, representing a set of process parameters, it belongs to the feasible region. . Used to characterize based on process parameters Predicted threshold voltage The goal is to The predicted value should be as close as possible to 0.35V.

[0117] The yield constraint in the constraints is: ; Indicates based on process parameters Predicted yield rate. Its output value is between 0 and 1. A yield rate of at least 99.5% is required. It can be used for high-value chips (such as CPUs, memory, and automotive-grade chips).

[0118] Process parameter boundary constraints:

[0119] ;

[0120] Table 4

[0121]

[0122] Within the feasible space generated by process parameters such as CD, Dose, and Temp In, find a set of parameters , so that:

[0123] 1) Electrical target: The threshold voltage Vt of the device falls exactly around 0.35V (minimize deviation);

[0124] 2) Yield target: The predicted yield under this parameter combination is no less than 99.5%;

[0125] 3) Physical feasibility: All parameters are within the range allowed by the equipment.

[0126] The top 5 high-yield formulations selected based on the aforementioned constraints are shown in Table 5 below.

[0127] Table 5

[0128]

[0129] Final selection: Considering both Vt accuracy and yield, formula 2 was chosen as the optimal solution. The predicted threshold voltage Vt = 0.3498V (deviation from the target 0.35V by only 0.0002V), and the predicted yield = 99.6%. The optimal formula... Feedback is sent to the Manufacturing Execution System to guide mass production batches.

[0130] The aforementioned semiconductor process yield prediction method includes at least the following unexpected technical effects:

[0131] After obtaining a wafer manufacturing recipe with preset key process parameters for chips at multiple different locations on the wafer, including ion implantation dose, gate critical dimension, and annealing temperature, the wafer measurement information after tape-out according to the wafer manufacturing recipe is then obtained. This measurement information includes the actual key process parameters, electrical parameters, and yield status of chips at multiple different locations on the wafer. Then, based on the wafer manufacturing recipe and measurement information, an input-output data set containing chip number and chip location information for chips at different locations is obtained. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters, and yield status, to achieve the goal of determining the chip's location information based on its chip number. This method establishes a one-to-one relationship between preset key process parameters and measurement information. Based on the input-output data set, it automatically tunes the hyperparameters of the gradient boosting decision tree using Bayesian optimization to obtain a target prediction model that meets test results. Then, it applies constraints to filter key process parameters and yields in a virtual process parameter space based on the target prediction model, obtaining the optimal formulation for mass production batches. These constraints include a predicted yield greater than or equal to a yield threshold, and minimal absolute deviation of electrical parameters from the corresponding threshold. This effectively predicts and discovers the optimal formulation key process parameters and yields for current semiconductor device manufacturing equipment, further improving the yield and performance of advanced processes.

[0132] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0133] Based on the same inventive concept, this application also provides a semiconductor process yield prediction apparatus for implementing the semiconductor process yield prediction method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the semiconductor process yield prediction apparatus provided below can be found in the limitations of the semiconductor process yield prediction method described above, and will not be repeated here.

[0134] Please refer to Figure 2 In some embodiments, this application also provides a semiconductor process yield prediction device, including an input information acquisition module 11, a measurement information acquisition module 12, a position information acquisition module 13, a prediction model training module 14, and a prediction module 15. The input information acquisition module 11 is used to acquire a wafer manufacturing recipe that includes at least preset key process parameters for chips at multiple different locations on the wafer; the key process parameters include ion implantation dose, gate critical dimension, and annealing temperature. The measurement information acquisition module 12 is used to acquire measurement information of the wafer after fabrication according to the wafer manufacturing recipe, the measurement information including the actual key process parameters, electrical parameters, and yield status of chips at multiple different locations on the wafer. The position information acquisition module 13 is used to acquire the prediction model training module 14 and the prediction module 15 based on the chip at different locations. The measurement information is used to obtain input-output data sets containing chip number and chip location information for chips at different locations. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters, and product status. The prediction model training module 14 is used to automatically fine-tune the hyperparameters of the gradient boosting decision tree based on Bayesian optimization according to the input-output data set to obtain the target prediction model that meets the test results. The prediction module 15 is used to apply constraints and filter in the virtual process parameter space based on the target prediction model to obtain the key process parameters and yield of the optimal formula for guiding mass production batches. The constraints include that the predicted yield is greater than or equal to the yield threshold, and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0135] Please continue to refer to this. Figure 2 In some embodiments, the input information acquisition module 11 is configured to: use a radial gradient algorithm to determine the critical dimensions of multiple chips between the center and the edge, starting from the critical dimension of the center gate of the wafer and ending from the critical dimension of the edge of the wafer; use a linear gradient algorithm to determine the ion implantation dose of multiple chips between the first and second endpoints, starting from and ending from the ion implantation dose at the first and second endpoints of the diameter on the X-axis of the wafer; and use a linear gradient algorithm to determine the annealing temperature of multiple chips between the bottom and top endpoints, starting from and ending from the bottom and top annealing temperatures of the diameter on the Y-axis of the wafer.

[0136] In some embodiments, the semiconductor process yield prediction apparatus further includes a virtual recipe generation module (not shown); the virtual recipe generation module is configured to generate a virtual recipe in a virtual process parameter space using Latin hypercube sampling, the virtual recipe including target key process parameters containing chip number and chip location information, predicted electrical parameters and predicted yield.

[0137] In some embodiments, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0138] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0139] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0140] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0141] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0142] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0143] In some embodiments, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the following steps:

[0144] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0145] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0146] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0147] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0148] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0149] In some embodiments, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0150] Obtain a wafer manufacturing recipe that includes at least several chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature.

[0151] Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer.

[0152] Based on the measurement information of chips at different locations, obtain the input data-output data set of chips at different locations, including chip number and chip location information. The input data includes preset key process parameters, and the output data includes actual key process parameters, electrical parameters and good product status.

[0153] Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results.

[0154] By applying constraints, the key process parameters and yield of the optimal formulation for mass production batches are obtained by screening in the virtual process parameter space based on the target prediction model. The constraints include that the predicted yield is greater than or equal to the yield threshold and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

[0155] Each module in the aforementioned semiconductor process yield prediction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0156] In an exemplary embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a semiconductor process yield prediction method. The display unit of the computer device is used to form a visually visible image and may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0157] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0158] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic resistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0160] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A method for predicting semiconductor process yield, characterized in that, include: Obtain a wafer manufacturing recipe that includes at least a number of chips at different locations on the wafer, with preset key process parameters including ion implantation dose, gate critical dimension, and annealing temperature. Obtain measurement information of the wafer after it has been fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and yield status of chips at multiple different locations on the wafer. Based on the measurement information of the chips at different locations, an input data-output data set containing chip number and chip location information of the chips at different locations is obtained. The input data includes the preset key process parameters, and the output data includes the actual key process parameters, electrical parameters, and good product status. Based on the input-output data set, the hyperparameters of the gradient boosting decision tree are automatically tuned using Bayesian optimization to obtain the target prediction model that meets the test results. By applying constraints, the target prediction model is used to filter key process parameters and yields in the virtual process parameter space to guide the optimal formulation for mass production batches. The constraints include a predicted yield greater than or equal to a yield threshold, and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

2. The semiconductor process yield prediction method according to claim 1, characterized in that, Obtaining the wafer manufacturing formula includes: Starting from the critical dimension of the center gate of the wafer and ending at the critical dimension of the edge of the wafer, the critical dimensions of multiple chips between the center and the edge are determined using a radial gradient algorithm. Using the ion implantation dose at the first and second endpoints of the wafer's X-axis diameter as the starting and ending points, respectively, a linear gradient algorithm is employed to determine the ion implantation dose of multiple chips between the first and second endpoints. Using the bottom end point annealing temperature and the top end point annealing temperature on the Y-axis diameter of the wafer as the starting and ending points respectively, a linear gradient algorithm is used to determine the annealing temperatures of multiple chips between the bottom end point and the top end point.

3. The semiconductor process yield prediction method according to claim 1, characterized in that, Includes at least one of the following features: The critical gate dimension is 18nm-22nm; The ion implantation dose is 1.0 × 10⁻⁶. 15 ions / cm 2 -3.0×10 15 ions / cm 2 ; The annealing temperature is 900-1100 degrees Celsius.

4. The semiconductor process yield prediction method according to any one of claims 1-3, characterized in that, Before training the initial model to obtain the target prediction model, the following steps are also included: Data cleaning algorithms are used to remove outliers from the input-output data set.

5. The semiconductor process yield prediction method according to any one of claims 1-3, characterized in that, The target prediction model includes an electrical parameter regression model and a good product classification model; Using a regularized empirical risk minimization model, an electrical parameter regression model is found in the function set such that the mean squared deviation between the electrical parameter values ​​predicted based on the electrical parameter regression model and the corresponding true target values ​​is minimized. Find a good product classification model in the function space that minimizes the average log loss plus the regularization term based on the input-output data set.

6. The semiconductor process yield prediction method according to any one of claims 1-3, characterized in that, It also includes the following steps for obtaining the virtual process parameter space: A virtual recipe in a virtual process parameter space is generated using Latin hypercube sampling. The virtual recipe includes target key process parameters, predicted electrical parameters, and predicted yield, which contain chip number and chip location information.

7. A semiconductor process yield prediction device, characterized in that, The device includes: The input information acquisition module is used to acquire a wafer manufacturing recipe that includes at least preset key process parameters of chips at multiple different locations on the wafer; the key process parameters include ion implantation dose, gate critical dimension, and annealing temperature; The measurement information acquisition module is used to acquire the measurement information of the wafer after it is fabricated according to the wafer manufacturing formula. The measurement information includes the actual key process parameters, electrical parameters and good status of chips at multiple different locations on the wafer. The location information acquisition module is used to acquire an input data-output data set containing chip number and chip location information of the chips at different locations based on the measurement information of the chips at different locations. The input data includes the preset key process parameters, and the output data includes the actual key process parameters, electrical parameters and good product status. The prediction model training module is used to automatically tune the hyperparameters of the gradient boosting decision tree based on Bayesian optimization according to the input data-output data set, so as to obtain the target prediction model that meets the test results. The prediction module is used to apply constraints and, based on the target prediction model, filter in the virtual process parameter space to obtain key process parameters and yields for the optimal formulation used to guide mass production batches; the constraints include a predicted yield greater than or equal to a yield threshold, and the absolute deviation of the electrical parameters from the corresponding threshold is minimized.

8. The semiconductor process yield prediction device according to claim 7, characterized in that: The input information acquisition module is configured as follows: Starting from the critical dimension of the center gate of the wafer and ending at the critical dimension of the edge of the wafer, the critical dimensions of multiple chips between the center and the edge are determined using a radial gradient algorithm. Using the ion implantation dose at the first and second endpoints of the wafer's X-axis diameter as the starting and ending points, respectively, a linear gradient algorithm is employed to determine the ion implantation dose of multiple chips between the first and second endpoints. Using the bottom and top annealing temperatures along the Y-axis diameter of the wafer as the starting and ending points, respectively, a linear gradient algorithm is employed to determine the annealing temperatures of multiple chips between the bottom and top points; and / or The semiconductor process yield prediction device also includes a virtual recipe generation module; The virtual recipe generation module is configured as follows: A virtual recipe in a virtual process parameter space is generated using Latin hypercube sampling. The virtual recipe includes target key process parameters, predicted electrical parameters, and predicted yield, which contain chip number and chip location information.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the semiconductor process yield prediction method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the semiconductor process yield prediction method according to any one of claims 1 to 6.

Images