Method for verifying a design of an integrated circuit

Abstract

Embodiments of the present disclosure provide a method for verifying a design of an integrated circuit (IC). The method includes identifying a common path portion that overlaps a global path and an individual or AC path, wherein the global path represents a timing path for the IC and the individual or AC path represents a timing path for an individual module in the IC; in response to determining that a timing design of the global path is to be changed, determining a correlation between the change of the timing design and the common path portion; and in response to determining that the change of the timing design is correlated to the common path portion, generating an indication representing whether the change of the timing design can be performed with respect to the individual or AC path based on timing conditions of the individual module obtained in advance. Through embodiments of the present disclosure, the time for making a design change in an IC design process can be reduced, thereby improving efficiency and reducing cost.

Description

Technical Field

[0001] This disclosure relates to integrated circuit design, and more specifically, to methods for verifying integrated circuit designs, as well as computer program products and computer-readable storage media. Background Technology

[0002] With the advancement of technology, semiconductor integrated circuits (ICs) are becoming increasingly larger, making their design more complex. Design problems may arise in the later stages of IC design or after tape-out, such as timing discrepancies that do not meet various timing requirements. To eliminate these problems, techniques such as engineering change orders (ECOs) can be used to make partial modifications without redesigning, improving the efficiency and reducing the cost of IC design.

[0003] The disclosed technologies are listed below.

[0004] [Patent Document 1] JP2012-174226A

[0005] For example, Patent Document 1 discloses technology related to design changes of integrated circuits. Summary of the Invention

[0006] During the design modification process of an IC, hypothesis testing is required to verify whether the modified IC design meets timing requirements. However, current hypothesis testing is time-consuming, especially for individual paths or alternating current (AC) paths, which can take more than 8 hours. This results in time-consuming and inefficient IC design and modification processes, impacting the overall design schedule. Other issues and novel features will become apparent from the description in this specification and accompanying figures.

[0007] According to a first aspect of this disclosure, a method for verifying the design of an integrated circuit (IC) is provided, the method comprising: identifying a common path portion that overlaps with a global path and an individual or AC path, wherein the global path represents a timing path for the IC, and the individual or AC path represents a timing path for an individual module in the IC; in response to determining that the timing design of the global path is to be changed, determining the association between the timing design change and the common path portion; and in response to determining that the timing design change is associated with the common path portion, generating an indication of whether the timing design change can be performed relative to the individual or AC path based on previously obtained timing conditions of the individual module.

[0008] According to a second aspect of this disclosure, a computer program product is provided, wherein the computer program product includes computer-executable instructions, and when the computer-executable instructions are executed by a processor, implement the method according to the first aspect.

[0009] According to a third aspect of this disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, implements the method according to the first aspect.

[0010] The summary section is provided to present the chosen concepts in a simplified form, which will be further described in the detailed description below. The summary section is not intended to identify key or principal features of this disclosure, nor is it intended to limit the scope of this disclosure. Attached Figure Description

[0011] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0012] Figure 1 This illustrates a schematic process for making changes to the design of an IC.

[0013] Figure 2 A schematic diagram of a system for performing a timing design method for an IC according to an embodiment of the present disclosure is shown.

[0014] Figure 3A An illustrative process for modifying the design of an IC according to an embodiment of this disclosure is shown.

[0015] Figure 3B An exemplary design layout of an IC with timing design modifications according to embodiments of the present disclosure is shown.

[0016] Figure 4 A schematic flowchart of a method for verifying an IC design according to an embodiment of the present disclosure is shown.

[0017] Figure 5 A schematic flowchart of a method for hypothesis testing of timing design changes according to an embodiment of the present disclosure is shown.

[0018] Figure 6 A schematic diagram of an example circuit of an IC according to an embodiment of the present disclosure is shown.

[0019] Figure 7 A schematic diagram of an example circuit of an IC with timing design modifications according to embodiments of the present disclosure is shown. Detailed Implementation

[0020] In the following description, embodiments will be referenced to the accompanying drawings. Since the drawings are simplified, the technical scope of the embodiments should not be narrowly interpreted based on the description in the drawings. Furthermore, the same elements are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0021] In the following embodiments, for convenience, the descriptions are divided into multiple sections or embodiments where necessary. However, unless otherwise stated, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed description, supplementary description, etc., of the other. Furthermore, in the following embodiments, when referring to the number of elements, etc. (including number of pieces, numerical values, quantities, ranges, etc.), the number is not limited to a specific number unless otherwise stated or clearly limited to that specific number in principle, and the number may be equal to or greater than that specific number, or may be equal to or less than that specific number.

[0022] Furthermore, in the following embodiments, components (including operating steps, etc.) are not necessarily necessary unless otherwise stated or deemed obviously necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise stated or deemed obviously different in principle, it includes those that are substantially similar or approximate in shape, etc. This also applies to the aforementioned numbers, etc. (including number of pieces, numerical values, quantities, ranges, etc.).

[0023] <Inventor's Preliminary Research>

[0024] The manufacturing of semiconductor integrated circuits or semiconductor chips typically involves multiple stages, such as design, manufacturing, packaging, and testing. The design stage can be accomplished using electronic design automation (EDA) software. During the design process, the timing of the designed circuit needs to be analyzed and verified to determine whether the paths of the digital circuits in the semiconductor integrated circuit can achieve timing convergence, thereby ensuring that the integrated circuit meets timing requirements. For example, static timing analysis (STA) can be performed using analysis software, which statically verifies whether the delays of all signal paths in the circuit meet timing requirements, thus ensuring that the chip operates reliably at a specified clock frequency. If paths in the designed circuit fail to achieve timing convergence or other design problems are found, techniques such as ECO can be used to modify the circuit design, thereby adjusting and improving the design.

[0025] Figure 1 This illustrates a schematic process for making changes to the design of a semiconductor integrated circuit. For example... Figure 1As shown, in the first stage S1', timing analysis (e.g., STA) is performed on the semiconductor integrated circuit design results, and a timing report is obtained to determine whether the designed semiconductor integrated circuit can achieve timing convergence. In the second stage S2', the designer uses the analysis results of STA to make changes to the circuit design, such as generating an ECO command. In the third stage S3', the designer needs to perform hypothesis testing on the circuit design results after inserting the ECO command to preliminarily determine whether the changes meet timing requirements. The hypothesis testing in the third stage S3' can be performed using software such as PrimeTime and involves multiple timing verification checklist items, including hypothesis testing S31' for the global path in user mode and hypothesis testing S32' in scan mode.

[0026] In chip design, a global path typically refers to a normal path within an IC or chip, primarily located between registers within the IC or chip. Furthermore, the approval process may include hypothesis verification S33' for AC path timing and hypothesis verification S34' for individual path timing. An AC path typically represents a path between a module and an external interface, and can also be considered an interface path. Individual paths typically represent special paths, including additional paths requiring timing measurements and timing path checks, and may not be part of the global path. When comparing differences between paths, the timing values ​​of each path need to be obtained and processed (e.g., addition and subtraction). Additional special timing path checks include, for example, clock skew gaps and maximum / minimum path delays. Moreover, the above three stages of design changes may need to be iterated until the timing fully meets the requirements.

[0027] The inventors' initial research revealed that hypothesis verification of the AC path timing (S33') and / or hypothesis verification of individual path timing (S34') is time-consuming on tools such as PrimeTime. The total time required for hypothesis verification of individual paths and / or the AC path can exceed 8 hours, making the third-stage hypothesis verification a bottleneck in the tapeout schedule and increasing design costs and risks. Therefore, shortening the time required for the third stage (S3') would improve the efficiency of semiconductor integrated circuit design changes and reduce costs.

[0028] The embodiments of this disclosure provide an improved timing design and verification method for integrated circuits, which can effectively shorten the time for design changes of semiconductor integrated circuits, and in particular shorten the time for hypothesis verification of design changes.

[0029] <First Embodiment>

[0030] Figure 2 A schematic diagram of a system 20 for performing a timing design method for a semiconductor integrated circuit according to embodiments of the present disclosure is shown. Figure 2 As shown, system 20 may include a computer terminal 21, a server 22, and a network 23. Computer terminal 21 is communicatively connected to server 22 via network 23. Server 22 may include a storage device 221 for storing programs to be executed. Computer terminal 21 can download the program to be executed from storage device 221 of server 22 via network 23 and store it in the memory of computer terminal 21. Alternatively, the program to be executed may be stored on other storage media and installed onto computer terminal 21 from other storage media.

[0031] Figure 3A This illustrates an illustrative process for making changes to the design of a semiconductor integrated circuit according to embodiments of this disclosure, and Figure 3B An exemplary design layout of an IC with timing design modifications according to embodiments of the present disclosure is shown. Figure 3A As shown, in the first stage S1, EDA tools (such as PrimeTime) can be used to perform STA on the semiconductor integrated circuit design results and obtain timing reports. These timing reports can include timing reports for global paths, timing reports for AC paths, and timing reports for individual paths. In the second stage S2, the analysis results of STA can be used to modify the circuit design, for example, generating ECO commands for global paths in user mode or scan mode. In the third stage S3, hypothesis testing can be performed on the circuit design results after inserting ECO commands to preliminarily determine whether the changes meet timing requirements. If hypothesis testing confirms that the modified design meets timing requirements, subsequent steps are continued, such as performing static timing analysis and placement and routing, or modifying and testing other ECO commands until all ECO commands meet timing requirements. If hypothesis testing finds timing violations, the ECO commands can be modified, such as changing the location of the ECO, until the timing violation is eliminated. As an example, such as... Figure 3B As shown, the revised layout may include changes indicated by markings 301, 302 and 303, such as local changes like increasing the size of standard cells, inserting buffers or removing buffers.

[0032] The third stage, S3, can include hypothesis verification S31 for global paths in user mode and hypothesis verification S32 for global paths in scan mode, and can be implemented using tools such as PrimeTime. User mode is the mode in which the IC normally performs its design functions, and all timing paths must meet timing requirements, such as setup and hold times. Scan mode is the test mode of the integrated circuit and has timing paths different from user mode.

[0033] Furthermore, Phase 3 S3 also includes hypothesis testing S33 for verifying ECO commands for AC and individual paths. Whether an ECO command making design changes to a global path meets timing requirements can be verified using hypothesis testing S31 and S32. However, because global paths and individual or AC paths share common paths, ECO commands making design changes to global paths may affect the timing of individual or AC paths. Therefore, hypothesis testing of the timing of individual or AC paths is necessary. Unlike... Figure 1 As shown in S3', hypothesis verification S33 can perform hypothesis verification on the AC path and individual paths based on existing timing information (such as timing path information in the timing report obtained in the first stage S1) without running tools such as PrimeTime. For example, the timing report obtained in the first stage S1 includes information related to each path, such as the modules, devices, device interfaces, fan-out numbers, capacitors, signal transition times, and accumulated path delays traversed by each path. Without running tools such as PrimeTime, based on existing timing information and delay changes caused by design changes, it can be determined whether design changes will cause timing non-convergence and timing violations in the AC path and individual paths.

[0034] Figure 4 A schematic flowchart of a method 4000 for verifying an IC design according to an embodiment of the present disclosure is shown. Method 4000 may correspond to hypothesis verification S33 in FIG3, and... Figure 2 The method 4000 is implemented in system 20 and executed by computer terminal 21. However, it is understood that the method 4000 can also be implemented in other scenarios and executed by processors or processing devices in other scenarios, and this disclosure does not limit this. For the purposes of discussion, reference will be made to... Figure 2 Method 4000 is described in conjunction with Figure 3.

[0035] At box 4001, computer terminal 21 identifies a common path portion in the IC design where global paths and individual or AC paths overlap, where a global path represents a timing path for the IC, and an individual or AC path represents a timing path for an individual module within the IC. A common path portion may exist between an individual or AC path and a global path, which is part of both a global path and an individual or AC path.

[0036] At block 4002, in response to determining that the timing design of a global path needs to be changed, computer terminal 21 determines the correlation between the timing design change and the common path portion. As an example, an ECO command is generated after the first stage S1 and the second stage S2 shown in Figure 3. The ECO command requires design changes to the global path in the integrated circuit design to eliminate design problems, such as timing violations in the global path. These design changes may be local design changes such as increasing the size of standard cells, inserting or removing buffers, and will increase or decrease path delays. Such design changes to the global path alter the timing of the global path, and if such changes are located on a common path portion shared by the global path and individual or AC paths, they may also cause timing changes to the individual or AC paths. Therefore, by determining the correlation between the timing design change of the global path and the common path portion, it can be determined whether such design changes will affect the timing of individual or AC paths in addition to affecting the timing of the global path. In some embodiments, method 4000 may further include performing a static timing analysis (STA) on the IC design and determining, based on the static timing analysis, that the timing design of the global path needs to be changed. As an example, after the initial design of the IC is completed, and before block 4001 or 4002, a static timing analysis can be performed using tools such as PrimeTime to determine whether the global paths in the IC design can converge in timing. In the event of a timing violation, an ECO command can be issued to make local changes to the IC design so that the IC design can meet timing requirements.

[0037] At box 4003, in response to determining that a timing design change is associated with a common path portion, computer terminal 21 generates an indication, based on the timing conditions of the individual modules obtained in advance, indicating whether the timing design change can be executed relative to the individual or AC path. Specifically, timing path information may already exist during the IC design process, such as path delays caused by devices in the path. Therefore, timing path information can be obtained in advance and formed into a database or used to build a model. Furthermore, timing design changes typically include inserting devices, deleting devices, or changing device dimensions, and the resulting delay changes are also easily obtained in advance, for example, based on design experience from previous products or the parameters and settings of the devices themselves. Thus, this information obtained in advance can serve as the timing conditions of the individual modules, and based on this, the timing impact of the timing design change on the individual or AC path can be estimated, thereby determining whether the timing requirements of the individual or AC path are met.

[0038] Compared to Figure 1 The hypothesis verification method used in Method 4000 does not require running tools such as PrimeTime when performing hypothesis verification on individuals or AC paths. Instead, it can use pre-obtained timing conditions to quickly verify the hypotheses of individuals or AC paths, thereby significantly shortening the time required for timing design changes, thus improving the efficiency of IC design and reducing design costs.

[0039] In some embodiments of this disclosure, method 4000 may further include generating a timing report based on static timing analysis, wherein the timing conditions of individual modules include information obtained in advance from the timing report. As an example, prior to block 4001 or 4002, a timing report may be generated after performing static timing analysis on the IC design. This timing report records all IC timing path information, including various path information related to the timing of individual or AC paths, such as modules, devices, device interfaces, fan-out numbers, capacitances, signal transition times, accumulated path delays, etc., within the AC path. The IC timing path information in the timing report forms a database or is used to build a model. The database or model can be searched using scripts such as Perl / Python to obtain the path information required for hypothesis testing of individual or AC paths as the timing conditions required in block 4003.

[0040] In some embodiments of this disclosure, computer terminal 21 can determine the correlation between timing design changes and common path portions based on timing reports. Specifically, timing reports may include path information for global paths, individual paths of each module, and AC paths. By comparing and analyzing the location points involved in the design change with this path information, it can be determined whether the location points involved in the design change are located on the common path portion. For example, timing reports may include separate AC reports, and if the location points involved in the timing design change of the global path are located in the paths in the AC report, it can be determined that the timing design change is related to the common path portion; if the location points are not located in the paths in the AC report, it can be determined that the timing design change is unrelated to the common path portion.

[0041] In some embodiments of this disclosure, the timing conditions of individual modules also include delay variation information obtained in advance from timing design changes to the developed integrated circuit. As an example, timing design changes typically include inserting devices, deleting devices, or changing device dimensions, and such changes may have occurred during the design process of the developed product. For products using the same manufacturing process, the delay value changes caused by inserting, deleting, or changing device dimensions are usually the same or similar. Therefore, the delay variation caused by the current design change can be determined based on the delay variation information related to the design changes of the developed product. For example, by collecting the same or similar ECO commands from the released product, the delay variation value caused by the current ECO command can be obtained. In this way, after obtaining the path information in the timing report, the delay variation value caused by the change is further obtained, thereby allowing for accurate estimation of the timing status of individual or AC paths based on this information, and thus determining whether the design change will cause timing violations in individual or AC paths.

[0042] In some embodiments of this disclosure, method 4000 further includes modifying the timing design for the global path, performing hypothesis testing on the global path in user mode and scan mode, and generating an indication of whether the timing design modification is executable relative to the global path based on the hypothesis testing of the global path in user mode and scan mode. As an example, a tool such as Primetime can be run to verify the global path of the IC design, and to verify it separately in user mode and scan mode, thereby determining whether a timing violation occurs in the global path after an ECO. If a timing violation still exists, the ECO can be reformulated, and the verification method repeated until the timing requirements are met.

[0043] In some embodiments of this disclosure, the IC includes multiple individual modules. Therefore, method 4000 can be executed for each individual module of the IC to ensure that the individual paths and AC paths of each individual module meet timing requirements after timing design changes to the global paths, thereby completing the overall timing verification of the IC. In one embodiment, timing design verification of the IC can be performed iteratively. For example, the timing design changes and verifications in the first stage S1 to the third stage S3 of Figure 3 can be repeated two or more times until all paths of the IC are free of timing violations.

[0044] <Second Embodiment>

[0045] Figure 5 A schematic flowchart of a method 5000 for hypothesis testing of timing design changes according to embodiments of the present disclosure is shown. Method 5000 can... Figure 4 Implemented at box 4003.

[0046] At box 5001, based on the timing conditions of the individual module obtained in advance, computer terminal 21 calculates the slack value for the individual or AC path of the individual module. As an example, timing path information for the individual or AC path of the individual module is obtained from a timing report. Furthermore, changes in latency caused by design changes can be obtained or determined in advance, such as the increase in latency due to inserting a device or the decrease in latency due to removing a device. The slack value for the individual or AC path of the individual module is calculated based on this information. The slack value, also known as timing margin, is a key parameter for measuring whether timing requirements are met; it represents the difference between the actual arrival time of a signal and the theoretically required time. The slack value can include setup time slack and hold time slack. Setup time slack ensures that data is sufficiently stable before being latched by the register's clock, while hold time slack ensures that data remains stable after being latched by the register's clock. Setup time slack and hold time slack can be calculated using the following equation:

[0047] Setup_Slack=Data_required_time-Data_arrival_time (1)

[0048] Hold_Slack= Data_arrival_time- Data_required_time (2)

[0049] Setup_Slack and Hold_Slack represent the setup time slack and hold time slack, respectively. Data_required_time represents the required arrival time, and Data_arrival_time represents the actual arrival time.

[0050] At box 5002, computer terminal 21 determines whether the calculated relaxation value is greater than or equal to zero. As an example, the sign of the setup time relaxation value and the hold time relaxation value can be determined, or they can be compared with zero, to determine whether there is sufficient setup time and hold time when the data is transferred to the data end of the register.

[0051] At box 5003, if the relaxation value for an individual or AC path is positive or zero, computer terminal 21 generates a first indication that the timing design change can be executed relative to the individual or AC path. Specifically, if both the setup and hold time relaxation values ​​are positive or zero, it indicates that there is sufficient time margin or just enough time to meet the timing requirements. If, after hypothesis verification S31 and S32, it is determined that the global path after the timing design change also meets the timing requirements, subsequent steps can be performed. For example, in subsequent steps, the modified IC design can be submitted to the backend for placement and routing, and data can be retrieved from the backend to continue executing STA to determine if there are timing violations requiring further ECO. If further ECO is required, the next round of changes and verification can be performed (i.e., repeating stages S1 to S3 again) until all timing violations are eliminated.

[0052] In block 5004, if the relaxation value for an individual or AC path is negative, computer terminal 21 generates a second instruction that the timing design change cannot be executed relative to the individual or AC path. Specifically, if either the setup time relaxation value or the hold time relaxation value is negative, it indicates insufficient time, and therefore a timing violation exists in the individual or AC path after the timing design change. In one embodiment, computer terminal 21 cancels the timing design change based on the second instruction. As an example, after a timing violation is detected, an ECO can be canceled, and the location of the ECO can be changed to generate a new ECO for re-verification until the timing requirements are met.

[0053] Figure 6 A schematic diagram of an example circuit of an IC according to an embodiment of the present disclosure is shown. (As shown) Figure 6As shown, the example circuitry for the IC includes registers 8011, 8012, 8013, and 8014, input / output (IO) elements 8021 and 8022, and interfaces 8031 ​​and 8032. The AC path is represented by dashed lines and includes the internal clock, register 8011, IO elements 8021 and 8022 / interfaces 8031 ​​and 8032, register 8012, and the wiring between these devices, as well as other components. The global path is represented by solid lines and includes the internal clock, registers 8013 and 8014, and the wiring between these devices, as well as other components. The common path is represented by bold solid lines and is the path shared by both the AC path and the global path.

[0054] Figure 7 The circuit diagram of the IC after the timing design change is shown. Figure 7 IC design in China Figure 6 The IC design in the example inserts three buffers, 8041, 8042, and 8043, and these three buffers are added to the common path section. As an example, the ECO command used to modify the timing design of the IC and add the three buffers 8041, 8042, and 8043 can be as follows:

[0055] insert_buffer cspf / sysss / syspf / cpg / cgpre / cgsrc_mdrv / cg_en4 / g_nand2 / ATM7BUFCLX20-new_net_namesSTA01_CLK_USER_N45-new_cell_names STA01_CKL_USER_I45insert_buffer cspf / sysss / syspf / cpg / cgpre / cgsrc_mdrv / cg_en4 / g_nand2 / ATM7BUFCLX20-new_net_namesSTA01_CLK_USER_N46-new_cell_names STA01_CKL_USER_I46insert_buffer cspf / sysss / syspf / cpg / cgpre / cgsrc_mdrv / cg_en4 / g_nand2 / ATM7BUFCLX20-new_net_namesSTA01_CLK_USER_N47-new_cell_names STA01_CKL_USER_I47

[0056] In the exemplary ECO command shown above, the three inserted buffers 8041, 8042, and 8043 are all devices TM7BUFCLX20, and the insertion point is located at "cspf / sysss / syspf / cpg / cgpre / cgsrc_mdrv / cg_en4 / g_nand2 / A". This location can be found in the AC report by searching and querying timing reports generated by timing analysis (e.g., STA) or databases or models formed from these timing reports. Therefore, the timing report can be used to determine that the insertion location of the three buffers 8041, 8042, and 8043 is located in the common path portion of the global path and the AC path.

[0057] Furthermore, by querying the latency values ​​of the TM7BUFCLX20 device in existing products, the latency values ​​of the three buffers 8041, 8042, and 8043 at a specific process corner can be obtained. For example, the device latency value at a specific process corner for setup time is 0.23ns, and the device latency value at a specific process corner for hold time is 0.2ns. Additionally, by searching and querying the timing report, the required arrival time (Data_required_time) for setup time is found to be 49.644115ns, and the actual arrival time (Data_arrival_time) for setup time is 48.913113ns. Similarly, by searching and querying the timing report, the actual arrival time (Data_arrival_time) for hold time is found to be 31.521149ns, and the required arrival time (Data_required_time) for hold time is 15.357479ns. Because the three buffers 8041, 8042, and 8043 are located on the clock path from the internal clock to the clock end of register 8012, but not on the data path from the internal clock to register 8012, this increases the delay required for arrival time.

[0058] The setup time relaxation value Setup_Slack for the AC path at a specific process angle can be calculated and determined according to equation (1). The calculation process of Setup_Slack is as follows:

[0059] Setup_Slack=(49.644115+0.23*3)-48.913113=1.421002(3)

[0060] The hold time relaxation value Hold_Slack for the AC path at a specific process angle can be calculated and determined according to equation (2). The calculation process of Hold_Slack is as follows:

[0061] Hold_Slack=31.521149-(15.357479+0.2*3)=15.56367(4)

[0062] Therefore, it can be seen that both the setup time relaxation value Setup_Slack and the hold time relaxation value Hold_Slack are greater than zero, thus satisfying the timing requirements of the AC path.

[0063] Furthermore, different process voltage temperature (PVT) combinations and mode combinations may exist under different process corners. Therefore, timing reports for all process corners can be obtained, and timing hypothesis testing can be performed on all signed-off items (i.e., user mode, scan mode, AC path timing, and individual path timing) under all process corners. In one example, a Perl / Python script can be run using Linux / script tools to quickly complete the timing report search for all process corners and the hypothesis testing of AC path timing and individual path timing in a very short time.

[0064] In embodiments of this disclosure, timing conditions of individual modules obtained in advance are used to verify the timing of individual or AC paths after timing design changes in the global path, without the need to run timing verification tools such as PrimeTime. In some cases, the method of embodiments of this disclosure can reduce the hypothesis verification time of ECO from more than 8 hours to less than 1 hour, thereby improving the efficiency of chip design and ECO and reducing design costs.

[0065] The aforementioned program includes a set of commands (or software code) that, when read by a computer, cause the computer to perform one or more functions described in the embodiments. The program may be stored in a non-transitory computer-readable medium or tangible storage medium. By way of example, and not limitation, computer-readable media or tangible storage media include random access memory (RAM), read-only memory (ROM), flash memory, solid-state drives (SSDs) or other storage technologies, CD-ROMs, and DVDs. Disks or other optical disc storage devices, magnetic tape cassettes, magnetic tapes, and disk storage devices or other magnetic storage devices. The program may be transmitted on a temporary computer-readable medium or communication medium. By way of example and not limitation, a temporary computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

[0066] From the teachings given in the foregoing description and related drawings, many modifications and other embodiments of the present disclosure will become apparent to those skilled in the art. Therefore, it is to be understood that embodiments of the present disclosure are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of this disclosure. Furthermore, although the foregoing description and related drawings have described exemplary embodiments in the context of certain example combinations of components and / or functions, it should be appreciated that different combinations of components and / or functions may be provided by alternative embodiments without departing from the scope of this disclosure. In this regard, for example, other combinations of components and / or functions that differ from those explicitly described above are also contemplated within the scope of this disclosure. Although specific terms are used herein, they are used in a general and descriptive sense only and are not intended to be limiting.

Claims

1. A method for verifying the design of an integrated circuit (IC), comprising: Identify the common path portion where a global path overlaps with an individual or AC path, wherein the global path represents a timing path for the IC, and the individual or AC path represents a timing path for an individual module within the IC; In response to determining that the timing design of the global path needs to be changed, the correlation between the change in the timing design and the common path portion is determined; as well as In response to determining that the timing design change is associated with the common path portion, an indication is generated based on the timing conditions of the individual modules obtained in advance, indicating whether the timing design change can be executed relative to the individual or the AC path.

2. The method according to claim 1, comprising: Perform static timing analysis on the design of the IC. The timing design of the global path to be changed is determined based on the static timing analysis.

3. The method according to claim 2, comprising: A time series report is generated based on the static time series analysis. The timing conditions of the individual modules include information obtained in advance from the timing report.

4. The method according to claim 3, wherein the timing conditions of the individual module further include delay change information obtained in advance from timing design changes of the developed IC.

5. The method of claim 3, wherein determining the association between the timing design change and the common path portion comprises: The correlation between the changes to the timing design and the common path portion is determined based on the timing report.

6. The method of claim 3 or 4, wherein generating an indication of whether a change to the timing design can be executed relative to the individual or AC path based on the timing conditions of the individual modules obtained in advance comprises: Based on the previously obtained timing conditions, calculate the relaxation value for the individual or AC path; as well as If the relaxation value for the individual or AC path is positive or zero, a first indication is generated that the changes to the timing design can be executed relative to the individual or AC path.

7. The method of claim 6, wherein generating an indication based on the timing conditions of the previously obtained individual modules, representing whether a change in the timing design can be executed relative to the individual or the AC path, further comprises: If the relaxation value for the individual or AC path is negative, a second indication is generated that the change in the timing design cannot be executed relative to the individual or AC path, and The change to the timing design is cancelled based on the second instruction.

8. The method according to claim 1, comprising: In response to the changes in the timing design, the global path is hypothesized and verified in both user mode and scanning mode; as well as Based on the hypothesis verification of the global path in the user mode and the scanning mode, an indication is generated indicating whether the changes to the timing design can be executed relative to the global path.

9. The method according to claim 1, wherein the IC comprises a plurality of individual modules.

10. The method of claim 1, wherein the timing design change includes an engineering change command.

11. A computer program product comprising computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the method according to any one of claims 1-10.

12. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium and, when the computer program is executed by a processor, implements the method according to any one of claims 1-10.

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