Analysis method and device of combinational logic circuit, computer device and storage medium

Abstract

The application discloses a kind of analysis method, device, computer equipment and storage medium of combination logic circuit, method includes: obtaining the and-or logic array of combination logic circuit, and determine target parameter;In the case where target parameter does not satisfy condition, the output signal of input dependence quantity satisfying second preset condition is analyzed, and first input-output mapping relationship is obtained;The output signal of input dependence quantity not satisfying second preset condition is handled, and second input-output mapping relationship is obtained;Formal verification is carried out to input-output mapping relationship, and analysis result is obtained.The method provided in the application can separate the output signal with simple logic association first, and then iteratively process the remaining complex output signal, solving the problem that traditional combinational logic analysis mode is difficult to ensure analysis integrity while considering result readability when facing multiple-input, multiple-output complex circuit, improving the readability and analysis efficiency of analysis result.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and specifically to a method, apparatus, computer device, and storage medium for analyzing combinational logic circuits. Background Technology

[0002] In the field of integrated circuit design and verification, functional analysis of combinational logic circuits is a fundamental step in understanding circuit behavior, verifying design correctness, and iterating architecture. As chip design scales continue to increase, combinational logic circuits exhibit characteristics such as multiple inputs, multiple outputs, multi-level nesting, and logic coupling, making accurate and complete functional analysis increasingly difficult.

[0003] Currently, the analysis of combinational logic circuit functions commonly employs traditional methods such as manual logic decomposition, truth table enumeration, and partial logic simulation. Manual logic decomposition heavily relies on engineer experience, is labor-intensive, time-consuming, and costly, and is prone to omissions of logical relationships or misjudgments of rules due to human error. Truth table enumeration becomes difficult to implement practically when the number of input signals is large, as the input combinations grow exponentially, making it unsuitable for large-scale complex circuits. Partial logic simulation can only cover limited input scenarios and cannot fully reflect the complete logical mapping relationships of the circuit. These traditional methods have low levels of automation and struggle to comprehensively cover logical mapping relationships and accurately reconstruct the circuit's logical function when dealing with complex combinational logic circuits with multiple inputs, multiple outputs, multi-level nesting, and logical coupling. This results in difficulty in guaranteeing the accuracy and completeness of core function reconstruction, leading to poor overall versatility and practicality. Summary of the Invention

[0004] This application provides a method, apparatus, computer device, and storage medium for analyzing combinational logic circuits, aiming to provide a process flow for analyzing complex combinational logic circuits of any size, so as to at least partially solve the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for analyzing combinational logic circuits, including: Obtain an AND-OR logic array of a combinational logic circuit and determine target parameters of the AND-OR logic array, the target parameters including at least one of the number of output signals and the number of input signals with different input values; If the target parameter does not meet the first preset condition, the output signals in the AND-OR logic array that meet the second preset condition are analyzed according to the number of input dependencies of the output signal to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. The output signal whose number of input dependencies in the AND-OR logic array does not meet the second preset condition is processed to obtain the second input-output mapping relationship; Formal verification is performed on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

[0006] In one embodiment of this application, the target parameter includes the number of output signals and the number of input signals with different input values; When the target parameter does not meet the first preset condition, the output signal in the AND-OR logic array that meets the second preset condition is analyzed based on the number of input dependencies of the output signal to obtain the first input-output mapping relationship, including: If neither the number of output signals nor the number of input signals with different input values ​​satisfies the first preset condition, the output signals in the AND-OR logic array that satisfy the second preset condition are analyzed based on the number of input dependencies of the output signals to obtain the first input-output mapping relationship. The method further includes: If at least one of the number of output signals and the number of input signals with different input values ​​satisfies a first preset condition, the mapping relationship in the AND-OR logic array is grouped according to the signal whose number satisfies the first preset condition, and the grouped mapping relationship is analyzed to obtain a third input-output mapping relationship.

[0007] In one embodiment of this application, the method further includes: If both the number of output signals and the number of input signals with different input values ​​meet the first preset condition, the processing priority of the signals is determined based on the number of output signals and the number of input signals with different input values. The processing priority of the signal is used to determine whether to group the mapping relationships in the AND-OR logic array according to different values ​​of the input signal, or to group the mapping relationships in the AND-OR logic array according to different values ​​of the output signal.

[0008] In one embodiment of this application, processing the output signal whose input dependency quantity in the AND-OR logic array does not satisfy the second preset condition to obtain the second input-output mapping relationship includes: The output signals that do not meet the second preset condition are combined into an updated AND-OR logic array, and the target parameters of the updated AND-OR logic array are obtained, so as to process the second input-output mapping relationship according to the updated target parameters.

[0009] In one embodiment of this application, obtaining the AND-OR logic array of the combinational logic circuit includes: Receive user-specified input space, the input space including a portion of the valid input value combinations of the combinational logic circuit; Extract the subarray corresponding to the input space from the original AND-OR logic array of the combinational logic circuit, and use the subarray as the AND-OR logic array.

[0010] In one embodiment of this application, the method further includes: If the target parameter does not meet the first preset condition and there is no output signal in the AND-OR logic array that meets the second preset condition in terms of the number of input dependencies, each output signal in the AND-OR logic array is analyzed independently to obtain the input-output mapping relationship of the combinational logic circuit.

[0011] In one embodiment of this application, the first preset condition includes the number of signals being less than a preset number threshold, and the second preset condition includes the number of input dependencies of the output signal being less than a preset dependency threshold. Wherein, the preset quantity threshold and / or the preset dependency threshold are determined by at least one of the following: Determined based on the maximum allowed number of unfoldings; Determined based on the total number of rows in the AND-OR logic array; Determined based on available computing resources; Determined based on user configuration information.

[0012] Secondly, this application provides an analysis apparatus for combinational logic circuits, comprising: An acquisition module is used to acquire an AND-OR logic array of a combinational logic circuit and determine target parameters of the AND-OR logic array, wherein the target parameters include at least one of the number of output signals and the number of input signals with different input values; The analysis module is used to analyze the output signals in the AND-OR logic array that satisfy the second preset condition based on the number of input dependencies of the output signals when the target parameters do not meet the first preset condition, and to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. The processing module is used to process the output signal in the AND-OR logic array whose number of input dependencies does not meet the second preset condition, and obtain the second input-output mapping relationship; The verification module is used to perform formal verification on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

[0013] Thirdly, this application provides a computer device, the computer device comprising: One or more processors; Memory; and One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the processor to implement the analysis method for combinational logic circuits as described in any of the preceding claims.

[0014] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, the computer program being loaded by a processor to perform the analysis method for combinational logic circuits as described in any of the preceding claims.

[0015] The combinational logic circuit analysis method provided in this application determines the target parameters of the AND-OR logic array. When the target parameters do not meet a first preset condition, the method analyzes the output signals whose input dependencies meet a second preset condition to obtain a first input-output mapping relationship based on the number of input dependencies of the output signals. Then, it processes the output signals that do not meet the second preset condition to obtain a second input-output mapping relationship. Finally, it performs formal verification on the obtained input-output mapping relationship. This method can first separate the output signals with simple logical associations for separate analysis, and then iteratively process the remaining complex output signals. This solves the problem that traditional combinational logic analysis methods are difficult to maintain both the integrity of the analysis and the readability of the results when dealing with complex circuits with multiple inputs and multiple outputs, thus improving the readability and efficiency of the analysis results. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating the steps of an analysis method for combinational logic circuits provided in this application embodiment; Figure 2 A schematic diagram illustrating the execution flow of an analysis method for combinational logic circuits provided in an embodiment of this application; Figure 3a A flowchart illustrating an analysis strategy based on input expansion provided in an embodiment of this application; Figure 3b A flowchart illustrating an output-based analysis strategy provided in this application embodiment; Figure 3c A flowchart illustrating an analysis strategy based on output grouping provided in this application embodiment; Figure 3dA flowchart illustrating a dependency-based optimization analysis strategy provided in an embodiment of this application; Figure 3e A flowchart illustrating a standalone analysis strategy provided in an embodiment of this application; Figure 4 A schematic diagram of the structure of an analysis device for combinational logic circuits provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0020] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0021] To clearly understand the automated analysis method, apparatus, device, and storage medium for combinational logic circuits provided in this application, the relevant application scenarios of the automated analysis method for combinational logic circuits provided in this application will be described below. Specifically, the automated analysis method for combinational logic circuits provided in this application is typically used to analyze the function of combinational logic circuits, and is particularly suitable for complex combinational logic circuits with multiple inputs, multiple outputs, multiple levels of nesting, and logical coupling. Complex combinational logic circuits, due to their large number of input / output signals, deep logic levels, and complex coupling relationships between signals, suffer from drawbacks such as difficulty in fully sorting out the logical mapping relationships manually, difficulty in completing functional reconstruction within a limited time, and difficulty in ensuring the completeness and readability of the analysis results.

[0022] In related technologies, methods such as manual logic analysis, truth table enumeration, and partial logic simulation are commonly used to analyze combinational logic circuits. Manual logic analysis relies on engineer experience, is labor-intensive, time-consuming, and costly, and is prone to omissions of logical relationships or misjudgments of rules due to human factors. Truth table enumeration becomes difficult to implement in practice when the number of input signals is large, as the number of input combinations grows exponentially. Partial logic simulation can only cover limited input scenarios and cannot fully reflect the complete logical mapping relationship of the circuit. These technologies are mainly used to gain partial functional understanding of simple or small-scale combinational logic circuits, but their automation level is low. When faced with complex combinational logic circuits, they still cannot fully cover the logical mapping relationship and accurately restore the circuit's logical function, resulting in difficulty in guaranteeing the accuracy and completeness of core function restoration, and poor overall versatility and practicality.

[0023] To address the aforementioned technical problems, this application provides an automated analysis method for combinational logic circuits, specifically a method and apparatus capable of automatically selecting analysis strategies, ensuring readability while restoring input-output mapping relationships, and guaranteeing the correctness of the restored logic through formal verification. This application converts combinational logic circuits into AND-OR logic arrays and determines the target parameters of the AND-OR logic arrays. If the target parameters do not meet a first preset condition, based on the number of input dependencies of the output signals, it first analyzes output signals whose input dependencies meet a second preset condition, then iteratively processes output signals that do not meet the second preset condition, and finally performs formal verification on the obtained input-output mapping relationships. This achieves automated analysis of complex combinational logic circuits of any scale, improving the completeness and readability of the analysis results. Specific details will be provided below with reference to embodiments. Specifically, to facilitate understanding of the above content, specific embodiments will be described below.

[0024] For details, please refer to Figure 1 , Figure 1This application provides a flowchart illustrating the steps of an analysis method for combinational logic circuits, specifically including steps S110 to S140: S110, obtain the AND-OR logic array of the combinational logic circuit, and determine the target parameters of the AND-OR logic array.

[0025] In one embodiment of this application, an AND-OR logic array is a form of combinational logic circuit, functionally equivalent to the original combinational logic circuit. An AND-OR logic array typically includes multiple input signals, multiple output signals, and multiple rows of input-to-output value mappings. Each row represents a combination of input values ​​and its corresponding output value, where each bit in the input value combination can be 0, 1, or an indeterminate state. For example, in a specific example, the AND-OR logic array includes four input signals a[1], a[0], b, and c, and two output signals d and e. Each row in the table represents a mapping relationship between an input value and an output value. Here, 0 indicates a signal value of 0, 1 indicates a signal value of 1, and ? indicates that the current signal value has no effect on the mapping relationship. This application does not limit the specific source and form of the AND-OR logic array, as long as it can characterize the input-output mapping relationship of the combinational logic circuit. For easier understanding of the above, please refer to Table 1, which is an example diagram of an AND-OR logic array provided in an embodiment of this application, as follows: Table 1:

[0026] In one embodiment, a logic synthesis tool can be used to convert combinational logic circuits into AND-OR logic arrays. The logic synthesis tool is used to convert combinational logic circuits into AND-OR logic arrays and optionally performs logical simplification on the AND-OR logic arrays. This application does not limit the specific type of logic synthesis tool, as long as it can convert combinational logic circuits into functionally equivalent AND-OR logic arrays. Through the conversion using a logic synthesis tool, subsequent analysis processes can be performed uniformly on the AND-OR logic array without depending on the specific structure of the original circuit, facilitating automated processing. In one specific embodiment, the logic synthesis tool can be a tool such as Yosys that can convert combinational logic circuits into AND-OR logic arrays, but this application does not limit this.

[0027] In one implementation, the target parameter includes at least one of the number of output signals and the number of input signals with different input values. The number of output signals refers to the number of output ports in the AND-OR logic array, i.e., the total number of output signals. The number of input signals with different input values ​​refers to the number of input signals whose values ​​actually change across all rows of the AND-OR logic array. For example, if an input signal takes the value of 0 or 1 in all rows, it is considered a constant input, does not affect the output logic, and is not counted in the number of input signals with different input values. Counting the number of input signals with different input values ​​can eliminate redundant inputs that are fixed and do not affect the logic, or inputs that do not change within a specified input space, thus more accurately reflecting the number of active variables in the circuit.

[0028] In one implementation, the target parameter may include only the number of output signals, only the number of input signals with different input values, or both. The specific content of the target parameter can be determined according to actual analysis needs. This application does not limit the specific composition of the target parameter.

[0029] In one implementation, for complex and large-scale combinational logic circuits, the circuit can first be divided into multiple sub-circuits. Each sub-circuit is converted into a corresponding AND-OR logic array and analyzed according to the method described in any of the above embodiments of this application to obtain the input-output mapping relationship corresponding to each sub-circuit. Then, the input-output mapping relationships of each sub-circuit are combined to obtain the input-output mapping relationship of the entire combinational logic circuit. The circuit division can be performed according to functional blocks, fan-in cones, or other conventional circuit division methods. This application does not limit the specific division method. Through circuit division, a complex circuit that is difficult to analyze directly can be decomposed into multiple smaller, relatively independent sub-circuits, and the analysis strategy of this application can be applied to each sub-circuit, thereby reducing the analysis complexity of a single array and improving the overall analysis efficiency. For each sub-circuit obtained by division, the method of obtaining the AND-OR logic array, the method of determining the target parameters, the method of judging the first and second preset conditions, and the method of formal verification can all be performed with reference to the method described in any of the above embodiments of this application. The analysis results of each sub-circuit can be formally verified separately, or the entire mapping relationship can be formally verified after combining them to obtain the input-output mapping relationship of the entire combinational logic circuit. This application does not limit this approach.

[0030] In one embodiment, the solution provided in this application can also support analysis within a user-specified input space. Specifically, obtaining the AND / OR logic array of the combinational logic circuit includes: The system receives a user-specified input space, which includes a subset of valid input value combinations for the combinational logic circuit. It then extracts a subarray corresponding to the input space from the original AND-OR logic array of the combinational logic circuit and uses this subarray as the AND-OR logic array. If the user does not specify an input space, the original AND-OR logic array of the combinational logic circuit is directly used as the AND-OR logic array.

[0031] The input space refers to the partially valid combinations of input values ​​that the user is interested in. In practical applications, not all combinations of input signals for certain combinational logic circuits are meaningful. For example, in an instruction decoding circuit, the input signal contains the instruction code, and each instruction corresponds to only the valid values ​​within its code space. The user can specify an input space according to actual needs, so that subsequent analysis is performed only within that input space.

[0032] In one embodiment, the subarray corresponding to the input space is extracted from the original AND-OR logic array of the combinational logic circuit. Only rows where the input value combinations fall within the input space are retained, and the array formed by these rows is used as the subarray. Since the original AND-OR logic array has been transformed by a logic synthesis tool and optionally simplified, the extracted subarray can be directly used as the AND-OR logic array for subsequent analysis without further simplification. In another embodiment, the extracted subarray can be simplified again according to actual needs; this application does not limit this. This application does not limit the specific implementation method of extracting subarrays from the original AND-OR logic array, as long as the analysis scope is limited to the user-specified input space.

[0033] Subsequent steps, including determining the target parameters of the AND-OR logic array, judging the first preset condition, analyzing the output signals that satisfy the second preset condition based on the number of input dependencies of the output signals, and processing the output signals that do not satisfy the second preset condition, are all performed on the subarray. Correspondingly, formal verification is also performed within the input space. In subsequent iterative processing, the analysis and formal verification of the updated AND-OR logic array can remain within the same input space. This application does not impose limitations here; specific details will be described in subsequent related embodiments.

[0034] By specifying an input space, users can focus on functional analysis within a specific input range, obtaining the input-output mapping relationship corresponding to that input space, which facilitates understanding of specific functions. For example, for instruction decoding combinational logic circuits, users can specify the input space as the encoding space of a certain instruction, thereby obtaining the decoding logic mapping relationship of that instruction, without having to analyze the mixed mapping relationship of all instructions in the entire input space. This application does not limit the specific method of specifying the input space, nor does it limit the specific range of the input space.

[0035] S120, if the target parameter does not meet the first preset condition, the output signal in the AND-OR logic array that meets the second preset condition is analyzed according to the number of input dependencies of the output signal to obtain the first input-output mapping relationship.

[0036] In one embodiment of this application, a first preset condition is used to determine whether the AND / OR logic array is suitable for direct expansion analysis. In one implementation, the first preset condition includes: the number of input signals with different input values ​​and / or the number of output signals is less than a preset number threshold. When the target parameter meets the first preset condition, it indicates that the number of input or output signals is small, and analysis can be performed directly using an input-by-input expansion or output-by-output expansion method to obtain a highly readable input-output mapping relationship. When the target parameter does not meet the first preset condition, it indicates that the number of both input and output signals is large, making direct expansion impossible, and analysis needs to be performed using a grouped iterative method.

[0037] In one implementation, the first preset condition includes: the number of input signals with different input values ​​is less than a first threshold, and / or the number of output signals is less than a second threshold. The first threshold and the second threshold may be the same or different. The preset quantity threshold can be determined according to actual needs, and the specific determination method will be described in detail in subsequent embodiments.

[0038] If the target parameters do not meet the first preset condition, the output signals whose input dependencies in the AND-OR logic array meet the second preset condition are analyzed based on the number of input dependencies of the output signals. Here, the number of input dependencies represents the number of input signals that the output signal logically depends on. For an output signal, its input dependency number refers to the number of input signals that actually affect its value in the logic function of that output signal. For example, if changing an input signal in the truth table of an output signal does not affect the value of the output signal, then that input signal is not dependent on the output signal. The smaller the number of input dependencies, the simpler the logic of the output signal and the easier it is to analyze independently.

[0039] In one implementation, the second preset condition includes: the number of input dependencies of the output signal is less than a preset dependency threshold. The preset dependency threshold can be determined according to actual needs. Output signals that meet the second preset condition have a small number of input dependencies and are output signals with simple logical associations. By analyzing these output signals, they can be separated from the original AND / OR logic array, reducing the correlation between the remaining output signals and the input signals.

[0040] The output signals that satisfy the second preset condition are analyzed to obtain the first input-output mapping relationship. In one embodiment, a subarray corresponding to each output signal that satisfies the second preset condition can be extracted from the original AND-OR logic array. The extracted subarrays are simplified using a logic synthesis tool, and then the simplified subarrays are analyzed to obtain the input-output mapping relationship of the output signal. Since the number of input dependencies of these output signals is small and their logic is simple, the analysis results are highly readable.

[0041] In one implementation, if there is no output signal in the AND-OR logic array whose input dependency quantity meets the second preset condition, it indicates that the logic of all output signals is relatively complex and cannot be grouped through dependency optimization. In this case, an analysis strategy that expands each output bit individually can be used to analyze the AND-OR logic array. This strategy directly extracts and analyzes the AND-OR logic array for each output signal individually, ensuring that analysis can be completed for AND-OR logic arrays of any size and complexity. It is the final fallback strategy; that is, in one embodiment of this application, the method further includes: If the target parameter does not meet the first preset condition and there is no output signal in the AND-OR logic array that meets the second preset condition in terms of the number of input dependencies, each output signal in the AND-OR logic array is analyzed independently to obtain the input-output mapping relationship of the combinational logic circuit.

[0042] In one implementation, when the target parameter includes the number of output signals and the number of input signals with different input values, if neither of them satisfies the first preset condition, the above-mentioned step of analyzing based on the number of input dependencies is performed. That is, in one embodiment of this application, the target parameter includes the number of output signals and the number of input signals with different input values. When the target parameter does not meet the first preset condition, the output signal in the AND-OR logic array that meets the second preset condition is analyzed based on the number of input dependencies of the output signal to obtain the first input-output mapping relationship, including: If neither the number of output signals nor the number of input signals with different input values ​​satisfies the first preset condition, the output signals in the AND-OR logic array that satisfy the second preset condition are analyzed based on the number of input dependencies of the output signals to obtain the first input-output mapping relationship.

[0043] Based on the foregoing, if at least one of the two conditions satisfies a first preset condition, the mapping relationships in the AND-OR logic array are grouped according to the signals corresponding to the number of signals satisfying the first preset condition. The grouped mapping relationships are then analyzed to obtain a third input-output mapping relationship. In other words, the method further includes: If at least one of the number of output signals and the number of input signals with different input values ​​satisfies a first preset condition, the mapping relationship in the AND-OR logic array is grouped according to the signal whose number satisfies the first preset condition, and the grouped mapping relationship is analyzed to obtain a third input-output mapping relationship.

[0044] Specifically, if the number of input signals with different input values ​​meets the first preset condition, the mapping relationship in the AND-OR logic array is grouped according to the different values ​​of the input signals; if the number of output signals meets the first preset condition, the mapping relationship in the AND-OR logic array is grouped according to the different values ​​of the output signals.

[0045] In one implementation, when both the number of output signals and the number of input signals with different input values ​​meet a first preset condition, the processing priority of the signals is determined based on the number of output signals and the number of input signals with different input values. That is, the method further includes: If both the number of output signals and the number of input signals with different input values ​​meet the first preset condition, the processing priority of the signals is determined based on the number of output signals and the number of input signals with different input values. The processing priority of the signal is used to determine whether to group the mapping relationships in the AND-OR logic array according to different values ​​of the input signal, or to group the mapping relationships in the AND-OR logic array according to different values ​​of the output signal.

[0046] For example, if the number of input signals with different input values ​​is less than the number of output signals, then the signals are grouped according to their different values; if the number of output signals is less than the number of input signals with different input values, then the signals are grouped according to their different values; if the two are equal, then the signals are grouped according to a preset priority, such as grouping according to their different values.

[0047] S130, the output signal whose input dependency quantity in the AND-OR logic array does not meet the second preset condition is processed to obtain the second input-output mapping relationship.

[0048] In one embodiment of this application, output signals whose input dependency count does not meet the second preset condition, i.e., output signals with complex logical associations, require further processing. In one implementation, these output signals that do not meet the second preset condition can be grouped into an updated AND-OR logic array, and the target parameters of the updated AND-OR logic array can be obtained, so as to process the second input-output mapping relationship according to the updated target parameters.

[0049] In other words, in one embodiment of this application, processing the output signal whose input dependency quantity in the AND-OR logic array does not satisfy the second preset condition to obtain the second input-output mapping relationship includes: The output signals that do not meet the second preset condition are combined into an updated AND-OR logic array, and the target parameters of the updated AND-OR logic array are obtained, so as to process the second input-output mapping relationship according to the updated target parameters.

[0050] Specifically, the output signals that do not meet the second preset condition are used as the updated set of output signals, while keeping the input signals unchanged, to generate an updated AND-OR logic array. Since the updated AND-OR logic array has eliminated those logically simple output signals, its number of output signals is reduced, and the correlation between output and input may also decrease. Then, for the updated AND-OR logic array, the steps of determining the target parameters in S110 and analyzing the number of input dependencies in S120 when the target parameters do not meet the first preset condition are re-executed. That is, the updated AND-OR logic array is used as the current AND-OR logic array, and the aforementioned strategy selection process is returned to execution. Through this iterative method, the simple parts of complex output signals can be gradually separated until all output signals have been analyzed and the second input-output mapping relationship is obtained.

[0051] In one implementation, the process of generating the updated AND-OR logic array and re-executing the steps of determining the target parameters and subsequent analysis can be repeated until all output signals in the updated AND-OR logic array have been analyzed to obtain the second input-output mapping relationship. This application does not limit the specific replacement strategy and iteration termination conditions; those skilled in the art can determine them according to actual needs.

[0052] S140, perform formal verification on the obtained input-output mapping relationship to obtain the analysis results of the combinational logic circuit.

[0053] In one implementation, the formal verification of the obtained input-output mapping relationship can be achieved by: taking the combinational logic circuit or the original AND-OR logic array corresponding to the combinational logic circuit as a reference model, taking the restored input-output mapping relationship as the model to be verified, and using a formal verification tool to perform an equivalence check on the reference model and the model to be verified, so as to verify whether the model to be verified and the reference model are functionally equivalent.

[0054] In one implementation, the formal verification can be performed within the entire input space or within a user-specified input space. When the user specifies an input space, the formal verification is performed only within that input space; when the user does not specify an input space, the formal verification is performed within the entire input space. This application does not limit the specific tools and algorithms used for formal verification, as long as they can verify whether the restored input-output mapping relationship is equivalent to the original combinational logic circuit.

[0055] In one implementation, if the formal verification result is equivalent, the analysis result of the combinational logic circuit is output; if the formal verification result is not equivalent, a verification failure message is output, or the aforementioned analysis steps are re-executed. This application does not limit this.

[0056] The combinational logic circuit analysis method provided in this application determines the target parameters of the AND-OR logic array. When the target parameters do not meet a first preset condition, the method analyzes the output signals whose input dependencies meet a second preset condition to obtain a first input-output mapping relationship based on the number of input dependencies of the output signals. Then, it processes the output signals that do not meet the second preset condition to obtain a second input-output mapping relationship. Finally, it performs formal verification on the obtained input-output mapping relationship. This method can first separate the output signals with simple logical associations for separate analysis, and then iteratively process the remaining complex output signals. This solves the problem that traditional combinational logic analysis methods are difficult to maintain both the integrity of the analysis and the readability of the results when dealing with complex circuits with multiple inputs and multiple outputs, thus improving the readability and efficiency of the analysis results.

[0057] To clearly understand the analysis method for combinational logic circuits provided in the embodiments of this application, the following will describe it in conjunction with a specific process. Please refer to... Figure 2 , Figure 2 The following is a detailed flowchart illustrating the execution process of an analysis method for combinational logic circuits provided in an embodiment of this application.

[0058] First, determine whether the user has specified an input space. If the user has specified an input space, extract the valid AND-OR logic array within the specified input space as the AND-OR logic array for subsequent analysis; if the user has not specified an input space, use the original AND-OR logic array directly.

[0059] Next, the number of input signals with distinct input values ​​in the AND / OR logic array is calculated. It is then determined whether this number is less than a specified threshold. If the number is less than the specified threshold, an analysis strategy based on input expansion is adopted. If the number is not less than the specified threshold, the number of output signals is further determined. If the number of output signals is less than the specified threshold, an analysis strategy based on output expansion is adopted. If the number of output signals is not less than the specified threshold, it is then determined whether the user has specified output groups. If the user has specified output groups, an analysis strategy based on output group expansion is adopted. If the user has not specified output groups, it is then determined whether the user has specified the number of input dependencies. If the user has specified the number of input dependencies, an analysis strategy based on output dependency optimization is adopted. If the user has not specified the number of input dependencies, an analysis strategy based on individual expansion of each output bit is adopted.

[0060] After the analysis is complete, it is determined again whether the user has specified an input space. If the user has specified an input space, formal verification is performed within the specified input space; if the user has not specified an input space, formal verification is performed across the entire input space.

[0061] From the perspective of ensuring readability, among the five analysis strategies mentioned above, the analysis strategy based on input expansion is equal to the analysis strategy based on output expansion; the analysis strategies based on input expansion and output expansion are superior to the analysis strategy based on output grouping expansion; the analysis strategy based on output grouping expansion is superior to the analysis strategy based on output dependency optimization; and the analysis strategy based on output dependency optimization is superior to the analysis strategy based on expanding each bit of the output individually. The overall analysis strategy is selected according to the degree to which it ensures readability and feasibility.

[0062] Please see Figures 3a-3e These are schematic diagrams illustrating the execution flow of different analysis strategies in the above analysis process, which will be explained separately below.

[0063] Please see Figure 3a , Figure 3a A flowchart illustrating an analysis strategy based on input expansion provided in this application embodiment is described in detail below.

[0064] First, calculate the required number of expansions, which is equal to 2 raised to the power of the number of input signals with different input values. Then, initialize the number of expansions to 0.

[0065] Next, the expansion loop begins. During each expansion, the value of each bit of the current expansion iteration is sequentially filled into the positions of the input signals with different input values, while the positions of the remaining input signals are filled with the original values ​​from the AND-OR logic array.

[0066] Next, it is determined whether the user has specified an input space. If the user has not specified an input space, the subsequent calculations are performed directly; if the user has specified an input space, it is further determined whether the filled input signal value is within the user-specified input space. If it is within the specified input space, the subsequent calculations are performed; if it is not within the specified input space, the current expansion is ignored, and the process proceeds directly to the step of incrementing the expansion count by one.

[0067] Valid input values ​​are passed to an AND-OR logic array for calculation, the output value is obtained, and the mapping relationship between the input value and the output value is saved.

[0068] Then, increment the number of unfolds by one and check if the required number of unfolds has been reached. If not, return to continue executing the unfolding loop; if the required number of unfolds has been reached, end the loop.

[0069] After the loop ends, all the input and output value mappings obtained from the expansion are categorized according to the output value. The AND-OR logic arrays of all input values ​​with the same output value are logically simplified to obtain the set of all input values ​​mapped to each output value, which is the final input-output mapping table.

[0070] In the final input-output mapping table, each mapping represents a mapping from an input value to an output value in the entire combinational logic circuit. If an input value is contained within the input space of a mapping, the output value can be obtained directly through that mapping without having to look at the entire mapping table, resulting in the best readability.

[0071] Please see Figure 3b , Figure 3b A flowchart illustrating an output-based analysis strategy provided in this application embodiment is described in detail below.

[0072] First, calculate the required number of expansions, which is equal to 2 raised to the power of (number of output signals). Then, initialize the number of expansions to 0.

[0073] Next, the unwinding loop begins. During each unwinding iteration, a combinational logic circuit is constructed. This circuit determines whether the output of the input combinational logic circuit equals the output value corresponding to the current unwinding iteration; therefore, the output signal of this combinational logic circuit is only one bit. A logic synthesis tool is used to convert this combinational logic circuit into an AND-OR logic array and then performs logic simplification. In the AND-OR logic array, all input values ​​with an output value of 1 represent the set of input values ​​mapped to the current output value.

[0074] Next, it is determined whether the user has specified an input space. If the user has specified an input space, valid input values ​​falling within the specified input space are extracted from the above input value set and used as the input value set mapped to the current output value; if the user has not specified an input space, the above input value set is directly retained. The mapping relationship between the current output value and the corresponding input value set is saved.

[0075] Then, increment the number of unfolds by one and check if the required number of unfolds has been reached. If not, return to continue executing the unfolding loop; if the required number of unfolds has been reached, end the loop.

[0076] The resulting input-output mapping table is consistent with the analysis strategy of expanding by input, and its readability is also the same. In the final input-output mapping table, each mapping relationship represents the set of all input values ​​corresponding to an output value of the entire combinational logic circuit.

[0077] Please see Figure 3c , Figure 3c A flowchart illustrating an analysis strategy based on output grouping provided in this application embodiment is described in detail below.

[0078] First, the number of output groups is initialized to 0. Then, a grouping loop is entered. The AND / OR logic array corresponding to the current group's output signal is extracted from the AND / OR logic array, and the extracted AND / OR logic array is simplified using a logic synthesis tool. Then, the simplified AND / OR logic array is used as input to the automated analysis method provided in this application, without specifying an output group, to obtain and save the input-output mapping table of the group's output signals.

[0079] Then, the number of output groups is incremented by one, and it is checked whether the number of output groups is equal to the specified number of output groups. If it is not equal, the process returns to continue to extract and analyze the next group of output signals; if it is equal, the loop ends, and the final input-output mapping table grouped by output is obtained.

[0080] In the final input-output mapping table, each mapping represents only the mapping from the input value to the output value for a specific set of outputs. In other words, to query the complete output value mapped to a given input value, multiple rows in the mapping table need to be searched. Its readability is slightly lower than analysis strategies that expand by input and by output, but it still ensures the readability of the mapping relationships for each set of output signals specified by the user.

[0081] Please see Figure 3d , Figure 3d A flowchart illustrating a dependency-based optimization analysis strategy provided in this application embodiment is described in detail below.

[0082] First, initialize the output signal count to 0. Then, enter the output signal traversal loop. Extract the current output signal's AND / OR logic array from the AND / OR logic array and simplify the extracted array. Next, calculate the number of input signals with different input values ​​in the simplified AND / OR logic array.

[0083] Determine if the number is less than or equal to the specified number of input dependencies. If the number is less than or equal to the specified number of input dependencies, use an input-expansion analysis strategy to obtain and save the input-output mapping table of the output signal. If the number is greater than the specified number of input dependencies, mark the output signal as pending analysis.

[0084] Then, the output signal count is incremented by one, and it is checked whether the output signal count equals the number of output signals. If they do not equal, the process returns to continue executing the capture and analysis of the next output signal; if they equal, the traversal loop ends.

[0085] After the traversal loop ends, the AND-OR logic arrays of all output signals to be analyzed are extracted from the AND-OR logic array, and the extracted AND-OR logic arrays are simplified logically. Then, the simplified AND-OR logic arrays are used as inputs, and the analysis method provided in this application is executed again without specifying the number of input dependencies, to obtain and save the input-output mapping table of the output signals to be analyzed.

[0086] The resulting input-output mapping table consists of two parts: one part shows the input-output mapping relationships of the output signals after output dependency optimization, and the other part shows the input-output mapping relationships of the output signals without output dependency optimization. The former has a simple logical mapping relationship but can only display the mapping relationship of a single output signal; the latter retains the input-output mapping relationships of all remaining output signals that have not undergone output dependency optimization. In other words, to query the complete output value mapped to a specific input value, both parts of the mapping table need to be consulted. Its readability is somewhat reduced compared to the analysis strategy that expands by output grouping.

[0087] Please see Figure 3e , Figure 3e A flowchart illustrating a standalone analysis strategy provided in this application embodiment is described in detail below.

[0088] First, initialize the output signal count to 0. Then, enter the output signal traversal loop. Extract the AND-OR logic array of the current output signal from the AND-OR logic array, and use a logic synthesis tool to perform logic simplification on the extracted AND-OR logic array to obtain and save the input-output mapping table of the output signal.

[0089] Then, the output signal count is incremented by one, and it is determined whether the output signal count equals the number of output signals. If they do not equal, the process returns to continue extracting and analyzing the next output signal; if they equal, the traversal loop ends, and the final input-output mapping table for each output signal is obtained.

[0090] In the final input-output mapping table, each mapping relationship contains only the input-output mapping relationship for a single output signal. To query the complete output value of a certain input value, multiple mapping relationships in the mapping table need to be queried. This approach has the lowest readability and is the most conservative analysis strategy in this application, but it can guarantee the completion of the analysis of complex combinational logic circuits.

[0091] The combinational logic circuit analysis method provided in this application determines the target parameters of the AND-OR logic array. When the target parameters do not meet a first preset condition, the method analyzes the output signals whose input dependencies meet a second preset condition to obtain a first input-output mapping relationship based on the number of input dependencies of the output signals. Then, it processes the output signals that do not meet the second preset condition to obtain a second input-output mapping relationship. Finally, it performs formal verification on the obtained input-output mapping relationship. This method can first separate the output signals with simple logical associations for separate analysis, and then iteratively process the remaining complex output signals. This solves the problem that traditional combinational logic analysis methods are difficult to maintain both the integrity of the analysis and the readability of the results when dealing with complex circuits with multiple inputs and multiple outputs, thus improving the readability and efficiency of the analysis results.

[0092] Based on the aforementioned analysis method for combinational logic circuits, this application also provides an analysis apparatus for combinational logic circuits. Please refer to... Figure 4 , Figure 4 A schematic diagram of the structure of an analysis device for combinational logic circuits provided in this application embodiment, specifically including: The acquisition module 410 is used to acquire the AND-OR logic array of the combinational logic circuit and determine the target parameters of the AND-OR logic array, wherein the target parameters include at least one of the number of output signals and the number of input signals with different input values; Analysis module 420 is used to analyze the output signals in the AND-OR logic array that satisfy the second preset condition based on the number of input dependencies of the output signals when the target parameters do not satisfy the first preset condition, and to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. Processing module 430 is used to process the output signal in the AND-OR logic array whose number of input dependencies does not meet the second preset condition, and obtain the second input-output mapping relationship; The verification module 440 is used to perform formal verification on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

[0093] In one embodiment of this application, the analysis module 420 is further configured to, when the number of output signals and the number of input signals with different input values ​​do not meet the first preset condition, analyze the output signals in the AND-OR logic array that meet the second preset condition based on the number of input dependencies of the output signals, and obtain the first input-output mapping relationship; If at least one of the number of output signals and the number of input signals with different input values ​​satisfies a first preset condition, the mapping relationship in the AND-OR logic array is grouped according to the signal whose number satisfies the first preset condition, and the grouped mapping relationship is analyzed to obtain a third input-output mapping relationship.

[0094] In one embodiment of this application, the analysis module 420 is further configured to determine the processing priority of the signal based on the number of the output signal and the number of the input signals with different input values ​​when both the number of the output signal and the number of the input signals with different input values ​​meet the first preset condition; The processing priority of the signal is used to determine whether to group the mapping relationships in the AND-OR logic array according to different values ​​of the input signal, or to group the mapping relationships in the AND-OR logic array according to different values ​​of the output signal.

[0095] In one embodiment of this application, the processing module 430 is further configured to form an updated AND-OR logic array from the output signals that do not meet the second preset condition, and obtain the target parameters of the updated AND-OR logic array, so as to process and obtain the second input-output mapping relationship according to the updated target parameters.

[0096] In one embodiment of this application, the acquisition module 410 is further configured to receive a user-specified input space, the input space including a portion of the valid input value combinations of the combinational logic circuit; Extract the subarray corresponding to the input space from the original AND-OR logic array of the combinational logic circuit, and use the subarray as the AND-OR logic array.

[0097] In one embodiment of this application, the verification module 440 is further configured to independently analyze each output signal in the AND-OR logic array to obtain the input-output mapping relationship of the combinational logic circuit when the target parameter does not meet the first preset condition and there is no output signal in the AND-OR logic array that meets the second preset condition for the number of input dependencies.

[0098] The combinational logic circuit analysis device provided in this application determines the target parameters of the AND-OR logic array. When the target parameters do not meet a first preset condition, it analyzes the output signals whose input dependency number meets a second preset condition to obtain a first input-output mapping relationship based on the number of input dependencies of the output signals. Then, it processes the output signals that do not meet the second preset condition to obtain a second input-output mapping relationship. Finally, it performs formal verification on the obtained input-output mapping relationship. This device can first separate the output signals with simple logical associations for separate analysis, and then iteratively process the remaining complex output signals. This solves the problem that traditional combinational logic analysis methods are difficult to maintain both the integrity of the analysis and the readability of the results when dealing with complex circuits with multiple inputs and multiple outputs, thus improving the readability and efficiency of the analysis results.

[0099] In some embodiments of this application, the analysis method for combinational logic circuits can be implemented as a computer program, which can be implemented in, for example... Figure 5 It runs on the computer device shown. The computer device's memory can store the various functional modules of the analysis device that make up the combinational logic circuit, for example, Figure 4 The diagram shows an acquisition module 410, an analysis module 420, a processing module 430, and a verification module 440. The computer program comprised of these modules causes the processor to execute the steps in the analysis methods for combinational logic circuits of the various embodiments of this application described in this specification.

[0100] For example, Figure 5 The computer device shown can be used as follows Figure 4The acquisition module 410 in the analysis device for combinational logic circuits shown executes step S110. The computer device can execute step S120 via the analysis module 420. The computer device can execute step S130 via the processing module 430. The computer device can execute step S140 via the verification module 440. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor of the computer device provides computational and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communication with external computer devices via a network connection. When the computer program is executed by the processor, it implements a method for analyzing combinational logic circuits.

[0101] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0102] In some embodiments of this application, a computer device is provided, including one or more processors; memory; and one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the processor to perform the following steps: Obtain an AND-OR logic array of a combinational logic circuit and determine target parameters of the AND-OR logic array, the target parameters including at least one of the number of output signals and the number of input signals with different input values; If the target parameter does not meet the first preset condition, the output signals in the AND-OR logic array that meet the second preset condition are analyzed according to the number of input dependencies of the output signal to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. The output signal whose number of input dependencies in the AND-OR logic array does not meet the second preset condition is processed to obtain the second input-output mapping relationship; Formal verification is performed on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

[0103] In some embodiments of this application, a computer-readable storage medium is provided, storing a computer program that is loaded by a processor, causing the processor to perform the following steps: Obtain an AND-OR logic array of a combinational logic circuit and determine target parameters of the AND-OR logic array, the target parameters including at least one of the number of output signals and the number of input signals with different input values; If the target parameter does not meet the first preset condition, the output signals in the AND-OR logic array that meet the second preset condition are analyzed according to the number of input dependencies of the output signal to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. The output signal whose number of input dependencies in the AND-OR logic array does not meet the second preset condition is processed to obtain the second input-output mapping relationship; Formal verification is performed on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

[0104] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The analysis method, apparatus, computer device, and storage medium for combinational logic circuits provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for analyzing combinational logic circuits, characterized in that, include: Obtain an AND-OR logic array of a combinational logic circuit and determine target parameters of the AND-OR logic array, the target parameters including at least one of the number of output signals and the number of input signals with different input values; If the target parameter does not meet the first preset condition, the output signals in the AND-OR logic array that meet the second preset condition are analyzed according to the number of input dependencies of the output signal to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. The output signal whose number of input dependencies in the AND-OR logic array does not meet the second preset condition is processed to obtain the second input-output mapping relationship; Formal verification is performed on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

2. The method according to claim 1, characterized in that, The target parameters include the number of output signals and the number of input signals with different input values; When the target parameter does not meet the first preset condition, the output signal in the AND-OR logic array that meets the second preset condition is analyzed based on the number of input dependencies of the output signal to obtain the first input-output mapping relationship, including: If neither the number of output signals nor the number of input signals with different input values ​​satisfies the first preset condition, the output signals in the AND-OR logic array that satisfy the second preset condition are analyzed based on the number of input dependencies of the output signals to obtain the first input-output mapping relationship. The method further includes: If at least one of the number of output signals and the number of input signals with different input values ​​satisfies a first preset condition, the mapping relationship in the AND-OR logic array is grouped according to the signal whose number satisfies the first preset condition, and the grouped mapping relationship is analyzed to obtain a third input-output mapping relationship.

3. The method according to claim 2, characterized in that, The method further includes: If both the number of output signals and the number of input signals with different input values ​​meet the first preset condition, the processing priority of the signals is determined based on the number of output signals and the number of input signals with different input values. The processing priority of the signal is used to determine whether to group the mapping relationships in the AND-OR logic array according to different values ​​of the input signal, or to group the mapping relationships in the AND-OR logic array according to different values ​​of the output signal.

4. The method according to claim 1, characterized in that, The step of processing the output signal whose input dependency quantity in the AND-OR logic array does not meet the second preset condition to obtain the second input-output mapping relationship includes: The output signals that do not meet the second preset condition are combined into an updated AND-OR logic array, and the target parameters of the updated AND-OR logic array are obtained, so as to process the second input-output mapping relationship according to the updated target parameters.

5. The method according to claim 1, characterized in that, The acquisition of the AND / OR logic array of the combinational logic circuit includes: Receive user-specified input space, the input space including a portion of the valid input value combinations of the combinational logic circuit; Extract the subarray corresponding to the input space from the original AND-OR logic array of the combinational logic circuit, and use the subarray as the AND-OR logic array.

6. The method according to claim 1, characterized in that, The method further includes: If the target parameter does not meet the first preset condition and there is no output signal in the AND-OR logic array that meets the second preset condition in terms of the number of input dependencies, each output signal in the AND-OR logic array is analyzed independently to obtain the input-output mapping relationship of the combinational logic circuit.

7. The method according to any one of claims 1 to 6, characterized in that, The first preset condition includes that the number of signals is less than a preset number threshold, and the second preset condition includes that the number of input dependencies of the output signal is less than a preset dependency threshold. Wherein, the preset quantity threshold and / or the preset dependency threshold are determined by at least one of the following: Determined based on the maximum allowed number of unfoldings; Determined based on the total number of rows in the AND-OR logic array; Determined based on available computing resources; Determined based on user configuration information.

8. An analysis device for combinational logic circuits, characterized in that, include: An acquisition module is used to acquire an AND-OR logic array of a combinational logic circuit and determine target parameters of the AND-OR logic array, wherein the target parameters include at least one of the number of output signals and the number of input signals with different input values; The analysis module is used to analyze the output signals in the AND-OR logic array that satisfy the second preset condition based on the number of input dependencies of the output signals when the target parameters do not meet the first preset condition, and to obtain the first input-output mapping relationship; the number of input dependencies represents the number of input signals that the output signal actually depends on logically. The processing module is used to process the output signal in the AND-OR logic array whose number of input dependencies does not meet the second preset condition, and obtain the second input-output mapping relationship; The verification module is used to perform formal verification on the obtained input-output mapping relationship to obtain the analysis result of the combinational logic circuit. The input-output mapping relationship includes the first input-output mapping relationship and the second input-output mapping relationship.

9. A computer device, characterized in that, The computer device includes: One or more processors; Memory; and One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the processor to implement the analysis method of combinational logic circuits as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which is loaded by a processor to execute the analysis method for combinational logic circuits as described in any one of claims 1 to 7.

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