Simulation method for logic system design and related device
Patent Information
- Application Number
- CN202611076282.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-20
- Publication Date
- 2026-10-30
AI Technical Summary
然而，在大型芯片完整系统的仿真验证场景下，目前的仿真方法存在仿真速度慢，仿真效率低的问题
[0010]本公开提供的一种逻辑系统设计的仿真方法及相关设备，通过将寄存器传输级模块和与其功能一致的行为级模型封装为封装模型，替代原始的寄存器传输级模块，从而利用封装模型中的行为级模型提高仿真器的仿真速度和仿真效率；通过封装模块中的时序对齐单元对齐寄存器传输级模块和行为级模型两者输出信号的时序，为行为级模型的输出信号补充时序信息。由此，本公开可以通过为通过高阶形式等价性验证的寄存器传输级模块自动封装包括其对应的行为级模型的封装模块，替代原始寄存器传输级模块，提高仿真器的仿真速度和仿真效率。
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Figure CN123013801A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer software technology, and more particularly to a simulation method and related equipment for logic system design. Background Technology
[0002] In the field of integrated circuit verification, simulation can refer to compiling a logic system design and then running it using simulation tools to test various functions of the design. The design can be, for example, an application-specific integrated circuit (ASIC) or a system-on-a-chip (SOC) design. Therefore, the design being tested or verified in simulation can also be called a design under test (DUT).
[0003] Logic system designs can be described using Register Transfer Level (RTL) languages and simulated using simulation tools. However, in simulation and verification scenarios of large-scale complete chip systems, current simulation methods suffer from slow simulation speed and low simulation efficiency. Summary of the Invention
[0004] This disclosure proposes a simulation method and related equipment for logic system design, which can solve or partially solve the above-mentioned problems to a certain extent.
[0005] In a first aspect, this disclosure provides a simulation method for logic system design, comprising:
[0006] The system receives the verification results of the higher-order formal equivalence verification of the register transfer level module; the higher-order formal equivalence verification verifies the functional consistency between the register transfer level module and the behavioral level model based on conditional expressions and assertion expressions. In response to the register transfer stage module passing the higher-order equivalence verification, an encapsulation module and a mapping relationship between the register transfer stage module and the encapsulation module are generated based on the register transfer stage module; the encapsulation module is configured to encapsulate the register transfer stage module and the behavioral level model, wherein the first output signal of the behavioral level model is time-aligned with the second output signal of the register transfer stage module; For instances generated based on the register transfer level module, the register transfer level module called by the instance is mapped to the encapsulation module based on the mapping relationship.
[0007] A second aspect of this disclosure provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method as described in the first aspect.
[0008] A third aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect.
[0009] In a fourth aspect, this disclosure provides a computer program product including computer program instructions that, when executed on a computer, cause the computer to perform the method as described in the first aspect.
[0010] This disclosure provides a simulation method and related equipment for logic system design. By encapsulating a register-transfer level (RTL) module and a functionally identical behavioral-level model into a packaged model, the original RTL module is replaced. This improves the simulation speed and efficiency of the simulator by utilizing the behavioral-level model within the packaged model. Furthermore, timing alignment units within the packaged module align the timing of the output signals of both the RTL module and the behavioral-level model, supplementing the output signals of the behavioral-level model with timing information. Therefore, this disclosure can automatically encapsulate a RTL module that has passed higher-order equivalence verification into a packaged model including its corresponding behavioral-level model, replacing the original RTL module and improving the simulation speed and efficiency of the simulator. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in one or more embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only one or more embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 A schematic diagram of the structure of an exemplary electronic device according to an embodiment of the present disclosure is shown.
[0013] Figure 2A A schematic diagram of an exemplary simulation system according to an embodiment of the present disclosure is shown.
[0014] Figure 2B A schematic diagram of an exemplary compiler according to an embodiment of this disclosure is shown.
[0015] Figure 3 A schematic diagram of an exemplary packaging module provided in an embodiment of this disclosure is shown.
[0016] Figure 4 A flowchart illustrating an exemplary logic system design simulation method provided in this disclosure is shown. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0018] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.
[0019] As mentioned above, with the continuous increase in the scale and design complexity of integrated circuits, the simulation and verification scenarios in the chip development stage have become extremely complex, especially for logic system designs described in register-transfer level languages, which pose a great challenge to their simulation speed and efficiency.
[0020] In chip design, the goal of writing RTL code is to achieve a better PPA (Power, Performance, and Area), that is, to minimize area and power consumption while improving performance. However, this code design aimed at optimizing hardware specifications significantly increases the overhead of the simulator's signal calculation, event scheduling, and branch judgment, thereby reducing simulation speed and efficiency.
[0021] This disclosure provides a simulation method and related equipment for logic system design. By encapsulating a register-transfer level (RTL) module and a functionally identical behavioral-level model into a packaged model, the original RTL module is replaced. This improves the simulation speed and efficiency of the simulator by utilizing the behavioral-level model within the packaged model. Furthermore, timing alignment units within the packaged module align the timing of the output signals of both the RTL module and the behavioral-level model, supplementing the output signals of the behavioral-level model with timing information. Therefore, this disclosure can automatically encapsulate a RTL module that has passed higher-order equivalence verification into a packaged model including its corresponding behavioral-level model, replacing the original RTL module and improving the simulation speed and efficiency of the simulator.
[0022] Figure 1 A schematic diagram of an electronic device 100 according to an embodiment of the present disclosure is shown. The electronic device 100 may be an electronic device running a simulation system. For example... Figure 1 As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected within the electronic device via the bus 110.
[0023] Processor 102 may be a central processing unit (CPU), image processor, neural network processor (NPU), microcontroller (MCU), programmable logic device, digital signal processor (DSP), application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated as a single logic component. Figure 1 As shown, processor 102 may include multiple processors 102a, 102b and 102c.
[0024] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulation test design can be a computer program stored in memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing a simulation method for the logic system design of this disclosure) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.
[0025] Network interface 106 can be configured to provide communication with other external devices to electronic device 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.
[0026] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.
[0027] Bus 110 can be configured to transfer information between various components of electronic device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.
[0028] It should be noted that although the above electronic device architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, the electronic device architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above electronic device architecture may only include the components necessary for implementing the embodiments of this disclosure, and does not necessarily include all the components shown in the figures.
[0029] Figure 2A A schematic diagram of an exemplary simulation tool 200 according to an embodiment of the present disclosure is shown. The simulation tool 200 may be a computer program running on an electronic device 100.
[0030] In the field of chip design, simulation tools are typically used to simulate a design. One example of such a tool is GalaxSim, a simulation tool produced by Chipsys Technology Co., Ltd. Figure 2AThe exemplary simulation tool 200 shown may include a compiler 210 and a simulator 220. The compiler 210 may receive source code 204 (e.g., a hardware description language such as VHDL, Verilog, SystemVerilog, etc.) and compile it into executable code 206 (e.g., machine code, assembly code, software code, etc.). It is understood that the description of the logic system design may be in a register-transfer level language. The simulator 220 may perform simulation based on the executable code 206 and output the simulation result 208. For example, the simulation tool 200 may transmit the simulation result 208 via... Figure 1 The peripheral interface 108 outputs to an output device (e.g., displayed on a monitor).
[0031] Figure 2B This is a schematic diagram of an exemplary compiler 210 according to an embodiment of this disclosure. Figure 2B As shown, compiler 210 may include front-end 212, middle-end 214 and back-end 216.
[0032] Frontend212 can be used to analyze the lexical, syntactic, and semantic aspects of source code based on the specific source language.
[0033] After lexical, syntactic, and semantic analysis of the source code, the intermediate stage 214 can convert the source code into an intermediate representation (or intermediate code) and optimize this intermediate representation. Intermediate language (intermediate code) is a syntax-oriented code that is an equivalent internal representation of the source code, easily translated into the target program's source code. Its understandability and ease of generating executable code fall between that of the source code and the executable code. Commonly used intermediate codes include Reverse Polish Notation, quadruples, triples, and tree representations. For example, the intermediate stage 214 can remove useless code, inaccessible code, and unused variables. Optimization can include machine-dependent and machine-independent optimizations. Machine-dependent optimizations, for example, can be optimizations of the testbench (TB) and can utilize some of the testbench's features to aid in optimization. Machine-independent optimizations, for example, can be optimizations of the Design Under Test (DUT). The optimized intermediate representation can then be passed to the backend 126 for further processing.
[0034] Backend 216 can be based on the target processor (e.g., Figure 1 The processor (102) architecture is used to further optimize the intermediate representation and generate executable code. Typically, the executable code is machine code.
[0035] Understandably, the structure of a compiler is not limited to... Figure 2B Examples. For instance, frontend 212 and middleend 214 can be collectively referred to as the compiler's frontend.
[0036] The compiler 210 can generate executable code based on the computer code to be compiled. The computer code to be compiled can also be called source code, such as a written logic system design. Typically, the source language used to write the source code is a high-level programming language. High-level programming languages can be the aforementioned software programming languages or hardware programming languages. The executable code can be, for example, assembly code, machine code, etc. Typically, the compiler 210 can store... Figure 1 The logic system design is stored in memory 104 and executed by processor 102 to compile it into executable code. Compiler 210 can translate the description of the logic system design from a high-level language description (e.g., HDL language) into a lower-level description (e.g., RTL language or binary code), thereby enabling the underlying hardware to run the logic system design.
[0037] As mentioned above, related technologies suffer from slow simulation speed and low simulation efficiency. To at least address these issues, this disclosure proposes a simulation method for logic system design.
[0038] Figure 4 A flowchart illustrating a simulation method 400 for an exemplary logic system design according to an embodiment of this disclosure is shown. Method 400 can be derived from... Figure 1 The illustrated electronic device 100 is implemented, more specifically, by a compiler / emulation system (e.g., running on the electronic device 100) Figure 2A The simulation tool 200 in the middle is used for implementation. Method 400 can also be implemented by... Figure 3 The acceleration tool 310 shown is implemented.
[0039] Method 400 may include the following steps.
[0040] In step 402, the verification result of the higher-order form equivalence verification of the register transfer stage module is received.
[0041] In this step, the verification results of the higher-order form equivalence verification of the register transfer level module (RTL module) in the logic system design can be obtained.
[0042] High-level equivalence checking (HEC), also known as high-level form equivalence verification, is a technique that uses mathematical proof methods, such as symbolic simulation and model testing, to verify whether two designs are consistent under given constraints.
[0043] In this step, higher-order formal equivalence can be used to verify whether the register transfer level module and the behavioral level model have functional consistency under given constraints.
[0044] The behavioral-level model in this step can be an abstract model at a higher level than the register-transfer level (e.g., algorithm-level or transaction-level), and its simulation speed is faster than that of the register-transfer level module. Optionally, the behavioral-level model can be described using languages such as C++, SystemC, and SystemVerilog.
[0045] In some cases, formal verification tools can be used to perform high-order formal equivalence verification. The aforementioned formal verification tool can be the GalaxFV formal verification tool produced by Xinhuazhang Technology Co., Ltd. The formal verification tool can be a computer program running on the electronic device 100.
[0046] Based on the register-transfer level module to be verified, the behavioral model, and assertion statements for higher-order formal equivalence verification, formal verification tools can perform functional consistency verification on the register-transfer level module and the behavioral model. The input to the verification tool can include the register-transfer level module, the behavioral model, and assertion statements. Assertion statements can include assertion expressions (Assert), conditional expressions (Assume), etc. Assert is used to indicate that a given assertion statement must be satisfied under any condition. Assume is used to represent various constraints for formal verification.
[0047] After processing by formal verification tools, the register-transfer level module and the behavioral level model ultimately output verification results. Verification results can be either assertion success or assertion failure. In some embodiments, the verification result may also be "no conclusion can be drawn."
[0048] If the verification result indicates that the assertion is successful, the register-transfer level module and the behavioral level model satisfy the assertion expression under the constraints of the predetermined conditional expression, meaning that the register-transfer level module and the behavioral level model have functional consistency.
[0049] This step determines whether the register transfer level module has a corresponding functionally consistent behavioral level model, thus providing support for the subsequent generation of a behavioral level model with the same functionality as the register transfer level model, as well as the generation of a wrapper module that includes the register transfer level model and the corresponding behavioral level model.
[0050] In step 404, in response to the register transfer level module passing the higher-order form equivalence verification, a wrapper module and a mapping relationship between the register transfer level module and the wrapper module are generated based on the register transfer level module.
[0051] Provided that the register transfer level module passes the higher-order equivalence verification, its corresponding encapsulation module can be generated based on the register transfer level module, and a mapping relationship between the register transfer level module and the encapsulation module can be generated.
[0052] In this step, the encapsulation module can be a top-level module used to encapsulate the register transfer level module and the behavioral level model. The first output signal of the behavioral level model is time-aligned with the second output signal of the register transfer level module to solve the problem of lack of timing information in the behavioral level model to a certain extent.
[0053] The mapping relationship between register transfer level modules and encapsulation modules can be used to replace register transfer level modules and encapsulation modules.
[0054] Optionally, by Figure 2A The simulation tool shown is 200, or... Figure 3 The acceleration tool 310 shown uses the higher-order equivalence verification of the register transfer level module as the triggering starting point, and generates the mapping relationship between the encapsulation module-level register transfer level module and the encapsulation module based on the register transfer level module.
[0055] This step generates a wrapper module corresponding to the register transfer level module. This wrapper module is the top-level module that encapsulates the register transfer level module and the behavioral level model. Depending on the conditions, you can choose to use the register transfer level module or the behavioral level model, which has the same function but a faster simulation speed, thereby improving the simulation speed and efficiency to a certain extent.
[0056] In step 406, for instances generated based on register transfer level modules, the register transfer level modules called by the instances are mapped to encapsulation modules based on the mapping relationship.
[0057] In this step, for instances generated based on the above register transfer level module in the logic system design, that is, instances that need to call the above register transfer level module, the register transfer level module called is mapped to the above encapsulation module to replace the original register transfer level module.
[0058] Optionally, the mapping relationship between register-transfer level modules and wrapper modules can be indicated through SystemVerilog configuration declarations (config_declarations). These declarations specify that the register-transfer level modules called by instances of register-transfer level modules in the design are mapped to their corresponding wrapper modules. Through configuration declarations, the binding relationship of module instances can be replaced without changing the instantiation location or modifying the source code, thus achieving the mapping between register-transfer level modules and wrapper modules.
[0059] Alternatively, the register transfer level module files can be replaced with packaged module files by modifying the simulation file list to achieve the mapping between register transfer level modules and packaged modules.
[0060] Alternatively, it can also be in Figure 2AThe simulation tool 200 is shown to define a dynamic overload module at the PLI / VPI interface level to achieve the mapping between the register transfer level module and the encapsulation module.
[0061] This step enables the mapping between the encapsulation module and the register transfer level module, thereby facilitating the simulation of logic system designs based on the encapsulation module.
[0062] The simulation method for logic system design provided in this disclosure can automatically generate a wrapper module that encapsulates the register-transfer level module and its corresponding behavioral level model based on the high-order formal equivalence verification results of the register-transfer level module, thereby replacing the original register-transfer level module. This wrapper model can conditionally switch between the register-transfer level module and the behavioral level model, ensuring that the timing of their output signals remains consistent, thus mitigating the functional impact of the behavioral level model on the simulation to a certain extent. Therefore, the simulation method for logic system design provided in this disclosure can improve simulation speed and efficiency while ensuring functional safety of the design to a certain extent.
[0063] Alternatively, the method 400 of this disclosure can be derived from... Figure 3 The acceleration tool 310 shown is implemented as follows. The input to the acceleration tool 310 may include the verification result of the higher-order formal equivalence verification of the register-transfer level module and the configuration file of the register-transfer level module. If the verification result is successful, the acceleration tool 310 automatically processes the register-transfer level module and finally outputs the encapsulation module and the mapping relationship between the register-transfer level module and the encapsulation module, thereby achieving automatic generation of the encapsulation module and avoiding the tedious process of manual encapsulation to a certain extent. For example, for register-transfer level modules corresponding to multiple configurations and matching multiple behavioral models, the encapsulation difficulty can be reduced using the method 400 of this disclosure.
[0064] Understandable. Figure 3 The acceleration tool 310 shown can also execute the method 400 of this disclosure on multiple register transfer stage modules simultaneously, further improving encapsulation efficiency.
[0065] Optionally, the input to the aforementioned acceleration tool 310 may also include a configuration file of the register transfer stage module.
[0066] Optionally, the verification results may include conditional expressions, assertion expressions, and the number of clock cycles corresponding to the register transfer stage module. The configuration file may include port information of all ports of the register transfer stage module (e.g., control signal port information, output ports that need to be taken over).
[0067] In some embodiments, step S404, which generates a package module based on a register transfer level module, may further include the following steps.
[0068] Step S502: Based on the assertion expression and / or the configuration file of the register transfer level module, extract the output ports that the register transfer level module needs to take over.
[0069] In this step, the output port that needs to be taken over can refer to the port among the multiple ports of the register transfer level module that needs to be taken over by the behavioral level model. The operation logic of the output signal of this port can be implemented by the behavioral level model.
[0070] In the embodiments of this disclosure, the prerequisite for generating the encapsulation module is that the register transfer stage module passes the higher-order equivalence verification, which requires that the conditional expression and the assertion expression be satisfied. That is, for a register transfer stage module that passes the higher-order equivalence verification, it has a corresponding assertion expression, for example, the output signal of a certain output port of the register transfer stage module is equal to the expected value after a certain clock cycle.
[0071] Therefore, the output ports that need to be taken over can be determined based on the above assertion expressions, thereby improving the automation of generating encapsulation modules.
[0072] Alternatively, the output ports that need to be taken over can be determined based on this configuration file, so as to facilitate unified management of multiple register transfer level modules.
[0073] Alternatively, the output ports to be managed can be determined based on assertion expressions and configuration files to achieve standardized control over register-transfer level modules. For example, if a register-transfer level module passes the above verification, but due to its high importance and the desire to avoid having its functionality replaced by a behavioral model, this register-transfer level module is listed in the register-transfer level module configuration file. Therefore, a behavioral model will not be generated based on this register-transfer level module, and consequently, no wrapper module will be created for it.
[0074] Step S504: Using the register transfer level module as a reference model, generate the behavioral level model.
[0075] In this step, the register transfer level module with a successful verification result is used as a reference model to generate its corresponding behavioral level model, so as to provide a basis for the subsequent generation of the encapsulation module.
[0076] It is understandable that this behavioral-level model is completely consistent with the functionality of the register transfer-level module.
[0077] In this step, the output port names of the behavioral-level model correspond one-to-one with the output port names that the register transfer-level module needs to take over, so as to avoid adding extra signal transfer logic and thus simplify the model encapsulation steps.
[0078] Step S506: Instantiate the register transfer level module and the behavior level model.
[0079] In this step, the register transfer level module and the behavior level model are instantiated.
[0080] The control signal port of the register transfer stage module can be connected to an inverted control signal.
[0081] Optionally, the control signal port information of the register transfer stage module can be determined based on the configuration file of the register transfer stage module.
[0082] The aforementioned control signals are used to control the register transfer level module to enter the enabled or disabled state, thereby selecting either the register transfer level module or the behavioral level model in the encapsulation module as needed, and realizing the autonomous switching between the register transfer level module and the behavioral level model.
[0083] Step S508: Encapsulate the instantiated register transfer level module and behavioral level model to generate the encapsulated module.
[0084] In some embodiments, it can be by Figure 3 The acceleration tool 310 shown takes a conditional expression as input, and outputs a control signal based on the instance obtained by instantiating the register transfer stage module and the above conditional expression. This control signal is used to instantiate the register transfer stage module 320 in the encapsulation module. The control signal port of the register transfer stage module 320 is connected to the inverted control signal.
[0085] In some embodiments, step S504, which uses the register transfer level module as a reference model to generate a behavioral level model, may further include the following steps.
[0086] Step S5042: Based on the assertion expression, retrieve the logically equivalent function within the modeling language domain of the register transfer level module.
[0087] Step S5044: In response to the existence of a function, the function is invoked through the direct programming interface of the modeling language domain to generate a behavioral-level model.
[0088] In some cases, projects that perform higher-order equivalence verification have functions that are consistent with the register-transfer level modules, and these functions can be called through the Direct Programming Interface (DPI) to implement the behavioral model.
[0089] In other cases, a pre-defined hardware description language can also be used.
[0090] In some embodiments, the encapsulation module generated based on the register transfer level module is consistent with the port declaration of the register transfer level module to avoid additional signal switching and remapping during instantiation, thereby reducing the encapsulation difficulty and the mapping difficulty between the register transfer level module and the behavioral level model.
[0091] In some embodiments, the method 400 of this disclosure may further include the following steps.
[0092] Step S602: Generate control signals based on conditional expressions.
[0093] The control signal is active when all conditional expressions are true. The control signal is in an invalid state when any conditional expression is not true.
[0094] Based on the above control signals, the register transfer level module and the behavior level model can be switched autonomously, thereby realizing the autonomous selection of the output signal of the encapsulation module.
[0095] In some embodiments, such as Figure 3 The encapsulation module 310 shown may further include a multiplexer unit 350, the selection control port of which is connected to a control signal. The multiplexer unit 350 is used to select either the first output signal of the output behavior level model 330 or the second output signal of the register transfer level module 320.
[0096] In some embodiments, the method 400 of this disclosure further includes the following steps.
[0097] In step S702, in response to the control signal being in an active state, the register transfer stage module enters the off state, and the multiplexing unit outputs the first output signal; In step S704, in response to the control signal being in an invalid state, the register transfer stage module enters the enabled state, and the multiplexing unit outputs the second output signal.
[0098] Since the register transfer level module and the behavioral level model in this encapsulation module have passed the high-order form equivalence verification, when all conditional expressions are true, the behavioral level model in this encapsulation module has the same function as the register transfer level module, and the function of the register transfer level module can be implemented by the behavioral level model.
[0099] Conversely, when any conditional expression is false, the behavioral-level model within this encapsulation module is not functionally equivalent to the register-transfer-level module, and the operation still needs to be performed by the register-transfer-level module.
[0100] Therefore, in some embodiments of this disclosure, the control signal is connected to the selection control port of the multiplexing unit, and the inverted control signal is connected to the control signal port of the register transfer stage module.
[0101] When all conditional expressions are true, the control signal is in an active state, the register transfer stage module enters the off state based on the inverted control signal, and the multiplexing unit outputs the first output signal of the behavioral stage model based on the control signal.
[0102] If any conditional expression is not true, the control signal is in an invalid state, the register transfer stage module enters the enabled state based on the inverted control signal, and the multiplexing unit outputs the second output signal of the register transfer stage module based on the control signal.
[0103] Optionally, the control signal can be a dynamic enable signal.
[0104] Alternatively, control signals can be generated using a finite state machine (FSM) to maintain superior performance when dealing with more complex conditional expressions. Alternatively, the conditional expressions can be embedded in SystemVerilog assertions, and control signals can be generated through the assertion monitoring mechanism.
[0105] The above embodiments can further mitigate functional risks that may arise during the simulation process to a certain extent.
[0106] In some embodiments, the method 400 of this disclosure may further include the following steps.
[0107] Step S802: Based on the verification results, extract the number of clock cycles corresponding to the register transfer stage module.
[0108] Step S804: The first output signal of the behavioral-level model is output after a delay of a number of clock cycles to align the timing of the first output signal and the second output signal.
[0109] As mentioned above, behavioral-level models lack timing information. By delaying the first output signal of the behavioral-level model by a number of clock cycles, the timing alignment of the first and second output signals can be guaranteed to a certain extent without complex rewriting.
[0110] The aforementioned clock cycle count can be extracted from the verification results of the register transfer stage module.
[0111] Optionally, such as Figure 3 The encapsulation module shown may also include a timing alignment unit 340 for delaying the first output signal of the delay behavior level model to ensure that the first output signal is aligned with the second output signal of the register transfer level module.
[0112] Optionally, the timing alignment unit 340 can be implemented by a multi-stage flip-flop (forming a shift register) or by a combination of a counter and a register.
[0113] Optionally, for a large number of delay cycles (e.g., a multi-cycle delay of 100 cycles), a RAM circular cache can be used to implement the timing alignment unit 340 to save register resources.
[0114] Alternatively, for behavioral models that can output transaction delay information, the delay information of the transaction can be directly used to implement the delay.
[0115] By delaying the first output signal of the behavioral level model 330, it is possible to further ensure that the behavioral level model 330 and the register transfer level module 320 are completely equivalent, while ensuring that the behavioral level model 330 and the register transfer level module 320 are functionally equivalent.
[0116] This disclosure also provides an electronic device. The electronic device may be... Figure 1 The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 400.
[0117] This disclosure also provides a non-transitory computer-readable storage medium. This non-transitory computer-readable storage medium stores a set of instructions for a computer, which, when executed, cause the electronic device to perform method 400.
[0118] The computer program stored in the storage medium of the above embodiments is used to cause the one or more processors to execute the method 400 as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0119] Based on the same inventive concept, corresponding to the method 400 of any of the above embodiments, this disclosure also provides a computer program product, which includes one or more computer programs. In some embodiments, the one or more computer programs are executable by one or more processors to cause the one or more processors to perform the method 400. Corresponding to the execution entity for each step in each embodiment of method 400, the processor executing the corresponding step may belong to the corresponding execution entity.
[0120] The computer program product of the above embodiments is used to cause the processor to execute the method 400 as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0121] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0122] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.
[0123] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.
[0124] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A simulation method for logic system design, comprising: The verification results of the higher-order form equivalence verification of the receive register transfer stage module; The higher-order equivalence verification is based on conditional expressions and assertion expressions to verify the functional consistency between the register transfer level module and the behavioral level model. In response to the register transfer stage module passing the higher-order equivalence verification, an encapsulation module and a mapping relationship between the register transfer stage module and the encapsulation module are generated based on the register transfer stage module. The encapsulation module is configured to encapsulate the register transfer stage module and the behavioral stage model, wherein the first output signal of the behavioral stage model is time-aligned with the second output signal of the register transfer stage module; For instances generated based on the register transfer level module, the register transfer level module called by the instance is mapped to the encapsulation module based on the mapping relationship.
2. The method according to claim 1, wherein, The encapsulation module is generated based on the register transfer level module, including: Based on the assertion expression and / or the configuration file of the register transfer level module, extract the output ports that the register transfer level module needs to take over; Using the register transfer level module as a reference model, the behavior level model is generated; the output port name of the behavior level model corresponds to the output port name that the register transfer level module needs to take over. Instantiate the register transfer stage module and the behavior stage model; connect the control signal port of the register transfer stage module to an inverted control signal; The instantiated register transfer level module and the behavioral level model are encapsulated to generate the encapsulated module.
3. The method according to claim 2, wherein, Using the register transfer level module as a reference model, the behavioral level model is generated, including: Based on the assertion expression, retrieve the logically equivalent function within the modeling language domain of the register transfer level module; In response to the existence of the function, the function is invoked through the direct programming interface of the modeling language domain to generate the behavioral-level model.
4. The method according to claim 2, wherein, The port declaration of the encapsulation module is consistent with that of the register transfer level module.
5. The method according to claim 2, wherein, Also includes: Control signals are generated based on the conditional expression; The control signal is active when all of the conditional expressions are true. The control signal is invalid if any of the stated conditional expressions are not true.
6. The method according to claim 5, wherein, The encapsulation module also includes a multiplexing unit; The selection control port of the multiplexing unit is connected to the control signal; The method further includes: In response to the control signal being active, the register transfer stage module enters a closed state, and the multiplexing unit outputs the first output signal; In response to the control signal being in an invalid state, the register transfer stage module enters an enabled state, and the multiplexing unit outputs the second output signal.
7. The method according to claim 1, wherein, Also includes: Based on the verification results, the number of clock cycles corresponding to the register transfer stage module is extracted; The first output signal of the behavioral-level model is output after being delayed by the number of clock cycles to align the timing of the first output signal and the second output signal.
8. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method as described in any one of claims 1-7.
9. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method according to any one of claims 1-7.
10. A computer program product comprising computer program instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-7.