A method for standardizing and simplifying massive time series paths

Abstract

The application discloses a method for standardizing and simplifying mass timing paths, comprising the following steps: obtaining timing path data to be compared; under a multi-process angle and a multi-working mode environment, switching to a script where a current path is located, and ensuring that subsequent path standardization and data comparison are performed under the same timing view; performing standardization and simplification processing on the path to generate a lib_func_path with comparability; main change operations include lib_cell replacement, foot_print replacement and logic merging; and data calculation and saving are performed, and the generated lib_func_path and key data of each node are output in a unified format at different stages of an EDA whole process. The application generates the lib_func_path with unique comparability, thereby realizing accurate comparison of paths across processes and stages.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit EDA, specifically involving a cross-process path comparison method for EDA timing path analysis, which can be widely applied to chip physical design (Place & Route), timing optimization, ECO verification and back-end acceptance process. Background Technology

[0002] In QoR (Timing Optimization) testing and analysis, the primary focus is on the Timing Path. Because different stages in the EDA (Electronic Design Automation) workflow (Synthesis, Placement, Clock Tree Staging, Route, Opt, etc.) continuously optimize the Timing Path, the number of nodes, node names, and hierarchical structure along the path change. For example, inserting buffers, inverters, or resizing standard cells adds nodes or changes instance names, resulting in the same physical path appearing as "different" paths at different stages.

[0003] In existing technologies, it is difficult to efficiently identify the "same path" across stages, which makes it impossible to reliably compare key indicators such as timing, area, power, resistance, and capacitance. This severely restricts the efficiency of automated analysis and optimization convergence speed of AE / QA teams. Summary of the Invention

[0004] The purpose of this invention is to provide a method for standardizing and simplifying massive time-series paths to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a method for standardizing and simplifying massive time-series paths, comprising the following steps: Step 1: Obtain the time series path data to be compared; Step 2: In a multi-process angle and multi-working mode environment, switch to the script where the current path is located to ensure that subsequent path standardization and data comparison are performed under the same timing view; Step 3: Standardize and simplify the path to generate a comparable lib_func_path; the main changes include: lib_cell replacement, foot_print replacement, and logical merging; Step 4: Data calculation and storage. At different stages of the EDA process, the generated lib_func_path and key data of each node are output in a unified format.

[0006] In one implementation, the timing path data is obtained through relevant commands of EDA tools or the internal interface of EDA software.

[0007] In one implementation, under the multi-process corner and multi-working mode environment, the timing data of the same timing path differs significantly under different process corners and different working modes. It is necessary to switch to the script to which the path currently belongs in order to obtain accurate and consistent timing information.

[0008] In one implementation, the lib_cell replacement includes: since the nodes traversed by the path may be instances instantiated from the same lib_cell, replacing the instance name of each node in the path with its corresponding standard unit library name lib_cell name to eliminate instantiation differences.

[0009] In one implementation, the foot_print replacement includes: the foot_print is defined in the EDA standard cell library and provided by the manufacturer or library vendor; each lib_cell has a foot_print name, and different lib_cells have the same foot_print; the lib_cell name is further replaced with the footprint name defined in the standard cell library.

[0010] In one implementation, the logical merging includes: First, perform type checking. If the instance type of a node in the path is a buffer, then it is directly omitted. If a node in a timing path has an even number of consecutive inverters, then all of them are omitted; if it has an odd number of inverters, then one is retained.

[0011] It should be noted that sometimes the tool will use clock inverters and clock buffers. Clock inverters and clock buffers should be treated in the same way.

[0012] In one implementation, the data to be saved includes: Net delay, resistance, and capacitance of the logic nets connected to each node in the path; The instance's cell delay; Other key metrics related to timing, area, and power consumption; There are no restrictions on the save format; JSON, CSV, or database table formats are all acceptable and convenient for subsequent AE / QA analysis.

[0013] In one implementation, if the start and end points of the timing path are resized during the optimization process, their names will not change and may be "Port". Therefore, the above-mentioned lib_cell replacement, footprint replacement and logical merging operations are not required, and their original names are retained.

[0014] The present invention provides a method for standardizing and simplifying massive time-series paths, which has the following beneficial effects: It enables accurate identification and comparison of cross-process time-series paths, effectively solving the problem of path structure differences caused by netlist modifications such as Opt, resyn, swapping, and buffer / inverter insertion, so that the same physical path at different stages can be directly compared after standardization. Significantly improves QoR analysis efficiency; AE / QA teams can quickly locate the changing trends of Timing, Area, Power, Resistance, and Capacitance of the same path at different stages based on lib_func_path, greatly shortening the problem location and optimization iteration cycle. It is compatible with existing EDA processes, requires no modification to the tool kernel, relies only on standard EDA commands and library information, and is easy to integrate into existing mainstream tool processes such as Innovus, ICC2, and PrimeTime, with low implementation costs; With good scalability, this method is applicable not only to data paths but also to clock paths, and supports path normalization comparison in complex library scenarios such as multiple VTs and multiple drive strengths. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the method for standardizing and simplifying massive time-series paths.

[0016] Figures 2(a) to 2(e) are schematic diagrams of the operation process of the same path generated by two time-series paths with different numbers of nodes and names. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for standardizing and simplifying massive time-series paths proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0018] This invention provides a method for standardizing and simplifying massive time-series paths, employing a technical solution of "path standardization and simplification + key data extraction," with the overall process as follows: Figure 1 As shown, it includes the following steps: Step 1: We need to obtain the time series path data to be compared. This can be obtained through relevant commands of EDA tools, such as get_paths, report_timing, etc. (tcl), or internal interfaces of EDA software. There are no restrictions here; the key is to obtain the input data. Step 2: In the MCMM (Multi-Corner Multi-Mode) environment, switch to the script containing the current path. In the MCMM environment, because the timing data such as delays and transition times for the same timing path differ significantly across different process corners and operating modes, it is essential to switch to the script currently containing that path to obtain accurate and consistent timing information. This ensures that subsequent path standardization and data comparison are performed under the same timing view. Step 3: Standardize and simplify the path to generate a comparable lib_func_path; the main changes include: (1) lib_cell replacement: Since the nodes passed through the path may be instances instantiated from the same lib_cell, the instance name of each node in the path is replaced with its corresponding standard unit library name to eliminate the instantiation difference; (2) Footprint replacement: The footprint is defined in the EDA Standard Cell Library and provided by manufacturers (TSMC, Samsung, Intel, etc.) or library vendors. Each lib_cell has a footprint name, and different lib_cells may have the same footprint. The lib_cell name is further replaced with the footprint name defined in the Standard Cell Library. Since different lib_cells may share the same footprint, this step can further normalize the equivalent cells; (3) Logical merging: First, perform type checking. If the instance type of a node in the path is Buffer, it can be omitted.

[0019] If a time-series path has an even number of consecutive Inverters, all of them can be omitted; if it has an odd number of Inverters, one should be retained.

[0020] It should be noted that the tool may sometimes use a Clock Inverter and a Clock Buffer. The Clock Inverter and Inverter are treated the same way, and the Clock Buffer and Buffer are treated the same way.

[0021] Note: The start and end points of the timing path will not change their names even if they are resized during the optimization process, and may be ports. Therefore, there is no need to perform the above lib_cell replacement, footprint replacement and logical merging operations, and their original names are retained.

[0022] Through the above three steps, timing paths of different lengths and node names will be simplified into lib_func_path with completely identical structures, thus achieving direct comparability. For example... Figure 1 As shown, the two original paths are completely identical standardized paths after lib_cell replacement, footprint replacement, and logical merging.

[0023] As shown in Figure 2(a), the two paths PATH1 and PATH2 both start and end from reg_0 to reg_1. The paths pass through instances with different names, such as U1, U2, U3, U4 and BUF1, BUF2, BUF3. This example is used to illustrate the point. The first step, as shown in Figure 2(b), involves replacing the library cell. By searching the netlist or other relevant input files, the library cell name corresponding to this instance can be found. The instance name is then replaced with the library cell name. The library cell is a specific logical unit defined in the Standard Cell Library. The library cell name corresponding to U1 is found to be AO131D28WP3, and the library cell name corresponding to U4 is AO1211. The rest are similar, resulting in new PATH1 and PATH2.

[0024] The second step, as shown in Figure 2(c), involves replacing the physical footprints. The specific names are defined in the physical library .lef (Library Exchange Format) or .gds (layout data) files. The physical footprints corresponding to the library unit AO131D28WP3 are found to be AOI / ZN, AO122D48WP4 and AO121102BWP, AO122D, and AO1211 are also AOI / ZN; the physical footprint corresponding to BUFFD is BUFF. This results in the new PATH1 and PATH2 shown in the figure above.

[0025] The third step, as shown in Figure 2(d), is to perform logical merging. According to the method described above in this invention, it is found that PATH1 has one BUFF, which is removed; PATH2 has two consecutive BUFFs, which are also removed.

[0026] The final path is shown in Figure 2(e). It is then discovered that they are actually one path. However, during the entire process, other buffers or inverters were inserted due to timing modifications. At this point, the timing changes of the same timing path at different stages can be compared.

[0027] Figures 2(a) to 2(e) fully illustrate the process of generating the same path after two timing paths with different numbers of nodes and names are replaced by lib_cell, replaced by foot_print, and logically merged. Then, the timing, area, power, resistance, capacity, etc. of these two paths can be compared at different stages.

[0028] (4) Data calculation and storage This invention focuses on the standardized structure of the path and the key data that needs to be saved, without limiting specific numerical calculation methods. The data to be saved includes, but is not limited to: Net delay, resistance, and capacitance of the logic nets connected to each node in the path; The instance's cell delay; Other key metrics related to timing, area, and power consumption.

[0029] There are no restrictions on the saving format; any format that is convenient for subsequent AE / QA analysis, such as JSON, CSV, or database tables, can be used.

[0030] Throughout the entire EDA workflow (e.g., Synthesis, Placement, Clock Tree Strategy (CTS), Route, and Post-Opt optimization), the generated lib_func_path and key data for each node (including but not limited to net delay, resistance, capacity, cell delay, timing, area, and power) are uniformly output in CSV format. Subsequent analysis allows direct comparison / loading of CSV files output from different EDA stages, leveraging the uniqueness of lib_func_path to achieve accurate comparison and trend analysis of the same physical path across workflows and stages.

[0031] Compared with existing technologies, this invention proposes for the first time a three-level path standardization framework of "lib_cell → footprint → logical merging", which fundamentally solves the problem of "incomparability" of timing paths in the entire EDA process, and has significant engineering practical value and innovation.

[0032] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for standardizing and simplifying massive time-series paths, characterized in that, Includes the following steps: Step 1: Obtain the time series path data to be compared; Step 2: In a multi-process angle and multi-working mode environment, switch to the script where the current path is located to ensure that subsequent path standardization and data comparison are performed under the same timing view; Step 3: Standardize and simplify the path to generate a comparable lib_func_path; The main changes include: lib_cell replacement, foot_print replacement, and logical merging; Step 4: Data calculation and storage. At different stages of the EDA process, the generated lib_func_path and key data of each node are output in a unified format.

2. The method for standardizing and simplifying massive time-series paths as described in claim 1, characterized in that, The timing path data is obtained through relevant commands of EDA tools or internal interfaces of EDA software.

3. The method for standardizing and simplifying massive time-series paths as described in claim 1, characterized in that, In the multi-process-angle and multi-working-mode environment, the timing data of the same timing path varies significantly in different process-angles and working modes. It is necessary to switch to the script to which the path currently belongs in order to obtain accurate and consistent timing information.

4. The method for standardizing and simplifying massive time-series paths as described in claim 1, characterized in that, The lib_cell replacement includes: since the nodes traversed by the path may be instances instantiated from the same lib_cell, the instance name of each node in the path is replaced with its corresponding standard unit library name lib_cell name to eliminate instantiation differences.

5. The method for standardizing and simplifying massive time-series paths as described in claim 1, characterized in that, The foot_print replacement includes: the foot_print is defined in the EDA standard cell library and provided by the factory or library vendor. Each lib_cell will have a foot_print name, and different lib_cells may have the same foot_print; the lib_cell name is further replaced with the footprint name defined in the standard cell library.

6. The method for standardizing and simplifying massive time-series paths as described in claim 1, characterized in that, The logical merging includes: First, perform type checking. If the instance type of a node in the path is a buffer, then it is directly omitted. If a node in a timing path has an even number of consecutive inverters, then all of them are omitted; if there is an odd number of inverters, then one is retained. It should be noted that sometimes the tool will use clock inverters and clock buffers. Clock inverters and clock buffers should be treated in the same way.

7. The method for standardizing and simplifying massive time-series paths as described in claim 1, characterized in that, The data that needs to be saved includes: Net delay, resistance, and capacitance of the logic nets connected to each node in the path; The instance's cell delay; Other key metrics related to timing, area, and power consumption; There are no restrictions on the save format; JSON, CSV, or database table formats are all acceptable and convenient for subsequent AE / QA analysis.

8. The method for standardizing and simplifying massive time-series paths as described in claim 6, characterized in that, If the start and end points of the timing path are resized during the optimization process, their names will not change and may be "Port". Therefore, there is no need to perform the above-mentioned lib_cell replacement, footprint replacement and logical merging operations, and their original names will be retained.

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