Timing detection method and apparatus, computer device, readable storage medium, and program product

Abstract

The application relates to a timing detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining at least one timing path through which a to-be-detected clock signal is transmitted in a to-be-detected chip; for voltage fluctuation on each timing path, quantifying the influence of the voltage fluctuation on clock propagation delay of the to-be-detected clock signal as a target delay factor; and performing timing detection on at least one timing path based on the target delay factor. The method can improve the accuracy of timing detection.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a timing detection method, apparatus, computer device, computer-readable storage medium, and computer program product. Background Technology

[0002] As chip size and integration continue to increase, clock network structures in digital systems become increasingly complex, and data interaction between various logic modules within the chip places higher demands on timing accuracy. To ensure that data is correctly triggered at the expected clock edge, timing verification of the chip is necessary.

[0003] Currently, timing verification of chips includes two methods. One is to use a +10% voltage during setup checks and a -10% voltage during hold checks to cover the timing effects that voltage fluctuations may cause. The other is to add empirical timing margins to multi-voltage domain interface circuits to roughly cover the effects of voltage fluctuations across voltage domains.

[0004] However, the two methods mentioned above either introduce significant timing pessimism or rely too heavily on empirical margins, failing to reflect real power supply conditions. This results in discrepancies between the timing verification results and the actual operating state of the chip, leading to insufficient accuracy. Summary of the Invention

[0005] Therefore, it is necessary to provide a timing detection method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve the accuracy of timing detection in response to the above-mentioned technical problems.

[0006] Firstly, this application provides a timing detection method, including:

[0007] Determine at least one timing path that the clock signal under test traverses during its transmission in the chip under test;

[0008] For voltage fluctuations on each of the timing paths, the impact of the voltage fluctuations on the clock propagation delay of the clock signal under test is quantified into a target delay factor;

[0009] Based on the target delay factor, timing detection is performed on at least one of the timing paths.

[0010] In one embodiment, the voltage fluctuation includes static voltage drop and ripple; quantifying the impact of the voltage fluctuation on the clock propagation delay of the clock signal under test into a target delay factor includes:

[0011] The effect of the static voltage drop on the clock propagation delay of the clock signal under test is quantified as a first delay factor, and the effect of the ripple on the clock propagation delay of the clock signal under test is quantified as a second delay factor.

[0012] The first delay factor and the second delay factor are added together to determine the target delay factor.

[0013] In one embodiment, quantifying the effect of the static voltage drop on the clock propagation delay as a first delay factor includes:

[0014] Based on the static voltage drop corresponding to each common clock path in the chip under test of the clock signal under test, the representative value of the static voltage drop is calculated.

[0015] Using the static voltage drop representative value, the target device in the clock tree corresponding to the clock signal under test is simulated to obtain the first delay factor.

[0016] In one embodiment, the process for determining the static voltage drop corresponding to each of the common clock paths includes:

[0017] The common clock path is determined based on the clock tree structure of the clock signal to be tested;

[0018] By combining the power network information, a static voltage drop analysis is performed on the power network where each of the common clock paths is located, and the static voltage drop corresponding to each of the common clock paths is obtained.

[0019] In one embodiment, the starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger; quantifying the impact of the ripple on the clock propagation delay of the clock signal under test as a second delay factor includes:

[0020] When the data transmission trigger and the data capture trigger on the same timing path are in the same voltage domain, the first ripple voltage difference corresponding to the clock signal under test is calculated based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain.

[0021] Using the first ripple voltage difference, the target device in the clock tree corresponding to the clock signal under test is simulated to obtain the second delay factor.

[0022] In one embodiment, calculating the first ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain includes:

[0023] A ripple voltage model is constructed based on the ripple amplitude and the frequency.

[0024] Based on the ripple voltage model, the ripple voltage values ​​corresponding to adjacent clock edges in the clock signal under test are calculated.

[0025] The first ripple voltage difference is determined based on the ripple voltage values ​​corresponding to adjacent clock edges.

[0026] In one embodiment, the starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger; quantifying the impact of the ripple on the clock propagation delay of the clock signal under test as a second delay factor includes:

[0027] When the data transmission trigger and the data capture trigger on the same timing path are not in the same voltage domain, the target amplitude is determined based on the ripple amplitude corresponding to each voltage domain, and the second ripple voltage difference is calculated based on the target amplitude.

[0028] Using the second ripple voltage difference, the target device in the clock tree corresponding to the clock signal under test is simulated to obtain the second delay factor.

[0029] In one embodiment, performing timing detection on the timing path based on the target delay factor includes:

[0030] The timing path delay is adjusted by the target delay factor to obtain the target clock delay; the timing path delay is determined based on the common clock path delay and the internal clock tree delay.

[0031] Timing detection is performed on the timing path using the target clock delay.

[0032] Secondly, this application also provides a timing detection device, the device comprising:

[0033] The determination module is used to determine at least one timing path that the clock signal under test traverses during transmission in the chip under test;

[0034] The quantization module is used to quantify the impact of voltage fluctuations on the clock propagation delay of the clock signal under test into a target delay factor for each of the timing paths.

[0035] The detection module is used to perform timing detection on at least one of the timing paths based on the target delay factor.

[0036] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0037] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0038] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0039] The aforementioned timing detection method, apparatus, computer equipment, computer-readable storage medium, and computer program product first determine at least one timing path traversed by the clock signal under test during transmission in the chip under test. Then, for voltage fluctuations along each timing path, the impact of these fluctuations on clock propagation delay is quantified into a target delay factor. Finally, timing detection is performed in conjunction with the target delay factor. Since the target delay factor characterizes the impact of voltage fluctuations on clock propagation delay under actual power supply conditions, quantifying the impact of voltage fluctuations on clock propagation delay into a unified target delay factor and directly incorporating this target delay factor into the timing detection process effectively reflects the impact of voltage fluctuations on clock propagation delay under actual power supply conditions, thus improving the accuracy of the timing detection results. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the chip power supply system in one embodiment;

[0042] Figure 2 This is a schematic diagram of a timing signature methodology in one embodiment;

[0043] Figure 3 This is a flowchart illustrating the timing detection process in one embodiment;

[0044] Figure 4 This is a schematic diagram of the timing path of a sequential circuit in one embodiment;

[0045] Figure 5 This is a schematic diagram illustrating the impact of ripple on timing in one embodiment;

[0046] Figure 6 This is a schematic diagram of the timing path of the sequential circuit in another embodiment;

[0047] Figure 7This is a schematic diagram illustrating the effect of ripple on timing in another embodiment;

[0048] Figure 8 This is a structural block diagram of a timing detection device in one embodiment;

[0049] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] For example, in combination Figure 1 , Figure 1 This is a schematic diagram of a chip power supply system in one embodiment. In the diagram, 1 represents VRM (Voltage Regulator Module), 2 represents PCB (Printed Circuit Board), 3 represents Die (chip die), and 4 represents packaging substrate.

[0052] The power supply to the chip goes from the system to the chip device, through the VRM PCB package to the internal power network of the chip, and finally to the device. In this process, due to parasitic inductance, resistance and capacitance, the resistance will generate a voltage drop (DC). The parasitic inductance and capacitance of the PCB and package cause the voltage to be superimposed with a sinusoidal AC ripple. The superposition effect of these two factors leads to the deviation of the power supply, which can be called voltage variation.

[0053] In traditional timing auditing, power supply fluctuations such as voltage drop and ripple are typically covered using a technology library-based voltage angle approach. This means that a technology library with approximately -10% voltage is used during setup checks, and approximately +10% voltage is used during hold checks to cover the impact of power supply fluctuations on timing. For example, such as... Figure 2As shown, under the same voltage domain (Single Voltage, SV), lower voltage angles correspond to slower circuit speeds, while higher voltage angles correspond to faster circuit speeds, constraining setup and hold timings respectively. In multi-voltage domain scenarios, existing methods typically combine ±10% voltage angles to cover different voltage domains based on the aforementioned SV approval method, or introduce additional timing margins based on experience to cope with power fluctuations between different voltage domains. However, both of these approaches rely mainly on fixed assumptions or empirical parameters when covering power fluctuations, making it difficult to match the actual power supply state of the chip. This often introduces additional timing margins, leading to inaccurate approval results.

[0054] Therefore, this application proposes a timing detection method that can accurately characterize real voltage fluctuations. For example... Figure 3 As shown, a timing detection method is provided, which includes the following steps:

[0055] Step 302: Determine at least one timing path that the clock signal under test passes through during transmission in the chip under test.

[0056] Among them, the chip under test refers to the integrated circuit chip that needs to be subjected to timing analysis and timing verification. There are multiple clock signals in the chip under test. Different clock signals have different clock frequencies, clock networks and power supply characteristics. Therefore, when performing timing testing, it is necessary to first determine the clock signal under test, which is the clock signal selected as the test object in the current timing analysis process.

[0057] After determining the clock signal under test (TD), at least one timing path is determined along which the TD clock signal travels during transmission within the chip under test (DUT). The TD clock signal triggers corresponding flip-flops in the DUT. Different clock signals typically correspond to different flip-flop sets. Therefore, after determining the TD clock signal, the set of flip-flops driven by that TD clock signal can be determined, and at least one set of timing endpoint pairs can be determined based on this set of flip-flops. Each timing endpoint pair includes a data transmit flip-flop and a data capture flip-flop, where the data transmit flip-flop is the start point of the corresponding timing path, and the data capture flip-flop is the end point of the corresponding timing path. Accordingly, each set of timing endpoint pairs defines a timing path that requires timing detection.

[0058] Step 304: For voltage fluctuations on each timing path, quantify the impact of voltage fluctuations on the clock propagation delay of the clock signal under test into a target delay factor.

[0059] The target delay factor is a quantitative parameter used to characterize the degree of impact of voltage fluctuations on the propagation delay of the clock signal under test on the timing path between timing endpoint pairs.

[0060] In the chip under test, the clock and logic units along the timing path are all supplied with operating voltage by the power supply network. Due to voltage fluctuations such as static voltage drop and ripple in the power supply network, the actual supply voltage in the corresponding region of different timing paths usually differs from the nominal supply voltage, resulting in changes in the propagation delay of the clock unit. Therefore, before performing timing testing on each timing path, it is necessary to obtain the voltage fluctuation information corresponding to each timing path.

[0061] In order to effectively introduce the impact of voltage fluctuations on timing during timing detection, this embodiment performs equivalent processing on voltage fluctuations, converting the impact of voltage fluctuations on clock propagation delay into a target delay factor.

[0062] Optionally, the voltage parameters corresponding to the voltage fluctuation can be obtained, and the clock propagation path corresponding to the target clock signal can be simulated based on the voltage parameters to determine the clock propagation delay under voltage fluctuation conditions; then, the target delay factor can be determined based on the clock propagation delay under voltage fluctuation conditions and the clock propagation delay under nominal power supply conditions.

[0063] Step 306: Perform timing detection on at least one timing path based on the target delay factor.

[0064] Optionally, after obtaining the target delay factor, the timing path delay can be adjusted based on the target delay factor to obtain the target clock delay. Here, the timing path delay refers to the delay on the timing path.

[0065] The target clock delay refers to the propagation delay of the clock signal under test after correction on the timing path, taking into account the impact of voltage fluctuations. It is used to correct the timing position of the clock signal under test in subsequent timing detection.

[0066] Once the target clock delay is determined, timing checks can be performed on the clock path based on the target clock delay during timing checks.

[0067] Optionally, during Static Timing Analysis (STA), the target clock delay is introduced into the timing analysis model as clock uncertainty or equivalent clock delay offset to correct the timing position of the clock signal under test at the transmission or acquisition time. This allows the impact of voltage fluctuations on clock path propagation delay to be incorporated into the timing detection results when performing setup and hold checks.

[0068] It should be noted that the use of STA for timing detection in this embodiment is merely an example. In other embodiments, timing detection can also be performed on the timing path by utilizing the target clock delay through any other means.

[0069] In the above embodiment, firstly, at least one timing path is determined along which the clock signal under test travels during transmission in the chip under test. Then, for voltage fluctuations along each timing path, the impact of these fluctuations on clock propagation delay is quantified into a target delay factor. Finally, timing detection is performed using the target delay factor. Since the target delay factor characterizes the impact of voltage fluctuations on clock propagation delay under actual power supply conditions, quantifying the impact of voltage fluctuations on clock propagation delay into a unified target delay factor and directly incorporating this target delay factor into the timing detection process effectively reflects the impact of voltage fluctuations on clock propagation delay under actual power supply conditions, thus improving the accuracy of the timing detection results.

[0070] Furthermore, voltage fluctuations include static voltage drop and ripple. In order to characterize the effects of different types of voltage fluctuations on clock propagation delay separately, in one embodiment, the effect of static voltage drop on the clock propagation delay of the clock signal under test is quantified as a first delay factor, and the effect of ripple on the clock propagation delay of the clock signal under test is quantified as a second delay factor; the first delay factor and the second delay factor are added together to determine the target delay factor.

[0071] Optionally, voltage fluctuations include static voltage drop (IR) and ripple (RIP). The target delay factor can be obtained by quantifying the static voltage drop and ripple respectively based on their characteristics.

[0072] Optionally, the propagation delay of the clock signal under test on the timing path can be calculated separately under IR and RIP conditions, and the first delay factor and the second delay factor can be calculated based on the propagation delay of the clock signal under test on the timing path under the nominal power supply condition.

[0073] Here, IR refers to the voltage drop caused by resistance in the power network during the transmission of power from the power supply bump (solder bump) to the internal devices of the chip; while RIP refers to the voltage fluctuation that varies with time superimposed on the supply DC voltage. Since these two types of voltage fluctuations have different mechanisms, in order to accurately characterize these two different types of voltage fluctuations, this embodiment quantifies the impact of IR on clock propagation delay as a first delay factor, and the impact of RIP on clock propagation delay as a second delay factor.

[0074] Optionally, the first delay factor and the second delay factor can be added together to obtain the target delay factor.

[0075] In the above embodiments, the effects of IR and RIP on clock propagation delay are quantified respectively, which can characterize the impact of different types of voltage fluctuations on clock propagation delay, thereby obtaining a more accurate target delay factor.

[0076] When IR occurs on the clock path, it causes propagation delay differences between different clock branches, resulting in clock skew and timing deviations. Figure 4 As shown, in a timing path, due to the differences in physical location and connected power network between the clock path of the transmit data trigger and the clock path of the receive data trigger, the voltage conditions they experience are not the same, which causes the launch clock and capture clock in CTS (Clock Tree Synthesis) to deviate in propagation delay.

[0077] To reduce clock skew caused by voltage differences, a voltage-dependent delay reduction factor is typically introduced during the CTS (Cyclic Time Series) stage. However, during Static Timing Analysis (STA), the Common Path Pessimism Removal (CRPR) mechanism treats delay differences on the common clock path as a pessimistic term and eliminates them, thus removing the voltage reduction applied to the common path in the CTS.

[0078] Therefore, it is necessary to model the clock delay effect caused by static voltage drop separately and calculate the corresponding IRderating, which is the first delay factor.

[0079] Furthermore, in one embodiment, the impact of static voltage drop on clock propagation delay is quantified into a first delay factor, including: calculating a representative value of static voltage drop based on the static voltage drop corresponding to each common clock path of the clock signal under test in the chip under test; and using the representative value of static voltage drop, simulating the target device in the clock tree corresponding to the clock signal under test to obtain the first delay factor.

[0080] The first delay factor represents the proportional relationship between voltage change and device propagation delay change.

[0081] The clock signal under test (DUT) drives multiple flip-flops in the chip under test (CUT), resulting in multiple timing endpoint pairs and corresponding to multiple common clock paths. Because different timing endpoint pairs branch at different points in the clock signal under test (CTS), their corresponding common clock paths differ in physical location and the power network they are connected to, thus each common clock path corresponds to a different input counter (IR). Therefore, it is necessary to analyze each IR to obtain a representative IR value that characterizes the DUT. Then, simulation is performed based on the representative IR value to obtain the first delay factor.

[0082] Optionally, the static voltage drop corresponding to each common clock path can be statistically analyzed. For example, the mean of the static voltage drop can be calculated, and the mean can be used as the IR representative value to characterize the average static voltage drop level of the common clock path corresponding to the clock signal under test. Alternatively, the dispersion of the static voltage drop distribution can be statistically analyzed. For example, the standard deviation (Sigma) of the static voltage drop can be calculated, and the voltage drop characteristic value corresponding to the standard deviation can be used as the IR representative value. In other embodiments, the mean and standard deviation can be considered simultaneously. For example, the IR representative value can be obtained by combining the mean with a preset multiple of the standard deviation. For instance, the mean plus three times the standard deviation (Mean + 3Sigma) can be used as the IR representative value to cover the static voltage drop situation corresponding to most common clock paths.

[0083] It should be noted that the above method for calculating the IR representative value is merely an example. In other embodiments, any calculation method can be used to calculate the IR representative value.

[0084] Optionally, a first supply voltage condition is determined based on the representative IR value, and the corresponding propagation delay is obtained through simulation under the first supply voltage condition; at the same time, a reference propagation delay is obtained under the nominal supply condition; and the first delay factor caused by IR is determined according to the proportional relationship between the propagation delay and the reference propagation delay.

[0085] In timing analysis, delay variations on the common clock path have a critical impact because they synchronously affect the clock arrival times of multiple registers driven by the same clock signal. The common clock path typically consists of a large number of clock cells with identical or similar structural and electrical characteristics. Therefore, in this embodiment, representative clock cells can be selected for simulation at a representative IR value.

[0086] In this embodiment, representative clock cells from the clock tree synthesis are used as target devices for simulation. As mentioned above, the common clock path typically consists of a large number of clock cells with similar or identical structures and electrical characteristics. To avoid the computational overhead of large-scale simulation, this embodiment filters the clock cells on the common clock path, selecting only representative clock cells as target clock cells for simulation, in order to quickly obtain the impact of IR on the propagation delay of the common clock path.

[0087] In the above embodiments, statistical analysis is performed on the IR on each common clock path corresponding to the clock signal under test to obtain the IR representative value. Then, simulation is performed based on the IR representative value to obtain the first delay factor. The clock propagation delay changes caused by power network differences on different common clock paths can be uniformly quantified, so that the first delay factor can characterize the IR influence of the clock signal under test on each common clock path.

[0088] In one embodiment, the process of determining the static voltage drop corresponding to the common clock path includes: determining the common clock path based on the clock tree structure of the clock signal under test; and performing static voltage drop analysis on the power network where each common clock path is located, in conjunction with power network information, to obtain the static voltage drop corresponding to each common clock path.

[0089] In the clock tree structure, different timing endpoints may correspond to different common clock paths. Therefore, the common clock path corresponding to each timing endpoint is first determined based on the clock tree structure corresponding to the clock signal under test. Since the common clock paths are distributed in different physical locations and connected to different power network regions, the static voltage drop impact on each common clock path usually differs. Therefore, after determining the common clock path, a static voltage drop analysis is performed on the power network where each common clock path is located, combined with the corresponding power network information, to determine the static voltage drop corresponding to each common clock path. This provides a basis for subsequent quantification of the impact of static voltage drop on clock propagation delay.

[0090] In the above embodiments, by determining the common clock path based on the clock tree structure and performing static voltage drop analysis in conjunction with the corresponding power network, the static voltage drop corresponding to each common clock path can be accurately obtained, providing accurate voltage parameters for subsequent determination of the first delay factor and improving the quantitative accuracy of the impact of static voltage drop on clock propagation delay.

[0091] Furthermore, voltage fluctuations also include RIPs, such as Figure 5 As shown, the actual supply voltage of the chip is not an ideal constant DC voltage, but rather an AC voltage component with a certain amplitude and frequency superimposed on the nominal DC supply voltage (DC), thus forming a RIP. Figure 5 The horizontal straight line represents the nominal DC voltage, and the sine wave superimposed on it represents the power supply ripple.

[0092] exist Figure 5 In the diagram, voltage1 and voltage2 represent the instantaneous supply voltage values ​​corresponding to the arrival of the clock signal under test at two adjacent clock edges (Edge1 and Edge2), respectively. Due to the presence of ripple, the supply voltages corresponding to Edge1 and Edge2 are at different phase positions of the ripple waveform, resulting in a voltage difference between voltage1 and voltage2.

[0093] The propagation delay of the clock signal within the chip is closely related to the supply voltage. When the supply voltage is high, the propagation speed is faster, and the clock edge arrives earlier; when the supply voltage is low, the propagation speed is slower, and the clock edge arrives relatively later. Therefore, due to the difference between voltage1 and voltage2, Edge1 and Edge2 will have different degrees of time offset relative to the clock edge under ideal ripple-free conditions. This time offset constitutes the clock jitter introduced by power supply ripple.

[0094] exist Figure 5 In this setup, the clock edge corresponding to the launch trigger for transmitting data is at a lower supply voltage position, causing the launch clock edge to be relatively slower; while the clock edge corresponding to the capture trigger for receiving data is at a higher supply voltage position, causing the capture clock edge to be relatively faster. This situation shortens the available time window for data to travel from launch to capture, thus introducing ripple jitter that is not covered by the traditional voltage angle during setup checks, posing a potential risk of insufficient setup timing margin.

[0095] Therefore, in this embodiment, the impact of power supply voltage fluctuations caused by ripple on clock propagation delay is quantified to obtain Rip_Derating, which is the second delay factor.

[0096] Furthermore, since power supply ripple is a dynamic voltage fluctuation that varies with time, the amplitude and phase relationship of the ripple in different voltage domains are uncertain. For example, combining... Figure 6 When the Launch and Capture flip-flops of a timing path are located in different voltage domains, the power supply ripple effects on adjacent clock edges are different, resulting in uncertainty in timing deviations caused by ripple. Therefore, voltage domain must be introduced as a constraint when quantizing ripple.

[0097] Furthermore, in one embodiment, the starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger; quantifying the impact of ripple on the clock propagation delay of the clock signal under test into a second delay factor includes: when the data transmission trigger and the data capture trigger on the same timing path are in the same voltage domain, calculating the first ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain; using the first ripple voltage difference, simulating the target device in the clock tree corresponding to the clock signal under test to obtain the second delay factor.

[0098] In this embodiment, the voltage variation range of the clock signal under test under power supply ripple is determined by combining the voltage domain of the timing endpoints, and simulation is performed based on the voltage variation range to obtain the second delay factor. The ripple voltage difference is used to characterize the impact of power supply ripple on the difference in supply voltage at different clock times. For example, as... Figure 5 As shown, the ripple voltage difference can be represented by the difference between voltage1 and voltage2.

[0099] Therefore, by combining the timing endpoints with the voltage domain to calculate the ripple voltage difference, the effect of power supply ripple on clock propagation delay can be calculated more accurately.

[0100] In one embodiment, the above-mentioned calculation of the ripple voltage difference corresponding to the clock signal under test based on the voltage domain corresponding to the timing endpoint includes: when the data transmit trigger and the data capture trigger on the same timing path are in the same voltage domain, calculating the first ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain; using the first ripple voltage difference, simulating the target device in the clock tree corresponding to the clock signal under test to obtain the second delay factor.

[0101] Optionally, when the data transmit trigger and the data capture trigger on the same timing path are in the same voltage domain, since the transmit clock edge and the receive clock edge are affected by the same power supply ripple source, the voltage changes corresponding to them have a definite phase relationship. Therefore, the first ripple voltage difference corresponding to adjacent clock edges can be calculated based on the ripple amplitude and ripple frequency in the voltage domain.

[0102] The step of simulating the target device in the clock tree corresponding to the clock signal under test based on the first ripple voltage drop to obtain the second delay factor can be referenced from the step in the above embodiment where a representative value of static voltage drop is used to simulate the target device in the clock tree corresponding to the clock signal under test to obtain the first delay factor. The simulation objects and purposes are the same in both cases; the difference lies in that the simulation input used to obtain the first delay factor is the representative value of static voltage drop, while the simulation input used to obtain the second delay factor is the first ripple voltage drop.

[0103] Furthermore, in one embodiment, the above-mentioned calculation of the first ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain includes: constructing a ripple voltage model based on the ripple amplitude and frequency; solving for the ripple voltage value corresponding to adjacent clock edges in the clock signal under test based on the ripple voltage model; and determining the first ripple voltage difference based on the ripple voltage value corresponding to adjacent clock edges.

[0104] Optionally, based on the known power supply ripple amplitude and ripple frequency in the design, a sinusoidal ripple voltage model with the ripple frequency as the period and the ripple amplitude as the magnitude is constructed to describe the voltage relationship of the power supply ripple changing with time.

[0105] Since data transmission and sampling occur at two adjacent effective clock edges, when quantifying the impact of power supply ripple on timing, the ripple voltage value corresponding to adjacent clock edges is determined by the ripple voltage model, and the voltage difference is used as the first ripple voltage difference.

[0106] Furthermore, after obtaining the ripple voltage model, the time corresponding to the adjacent clock edges is used as input into the ripple voltage model to obtain the corresponding ripple voltage value, and the first ripple voltage difference is determined based on the difference between the ripple voltage values.

[0107] In the above embodiments, the first ripple voltage can be accurately solved by constructing a ripple voltage model.

[0108] In one embodiment, the starting point of the timing path is a data transmit trigger; the ending point of the timing path is a data capture trigger; quantifying the impact of ripple on clock propagation delay into a second delay factor includes: when the data transmit trigger and the data capture trigger on the same timing path are not in the same voltage domain, determining the target amplitude based on the ripple amplitude corresponding to each voltage domain, and calculating the second ripple voltage difference based on the target amplitude; using the second ripple voltage difference, simulating the target device in the clock tree corresponding to the clock signal under test to obtain the second delay factor.

[0109] Optionally, combined Figure 7 In the example scenario shown, the timing endpoints are located in voltage domains A and B, respectively, corresponding to two independent sets of ripples: the ripple for domain A and the ripple for domain B. The first clock edge (EDGE1) of the clock signal under test is located in voltage domain A, and the second clock edge (EDGE2) is located in voltage domain B. Because the phase relationship of the power supply ripples between different voltage domains is uncertain, the instantaneous ripple voltage difference corresponding to the two clock edges cannot be accurately determined. Therefore, it is necessary to determine the second ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude in the voltage domain.

[0110] The step of simulating the target device in the clock tree corresponding to the clock signal under test based on the second ripple voltage difference to obtain the second delay factor can be referenced from the step in the above embodiment where a representative value of static voltage drop is used to simulate the target device in the clock tree corresponding to the clock signal under test to obtain the first delay factor. The simulation objects and purposes are the same in both cases; the difference lies in that the simulation input used to obtain the first delay factor is the representative value of static voltage drop, while the simulation input used to obtain the second delay factor is the second ripple voltage difference.

[0111] The target amplitude is an amplitude parameter selected from the power supply ripple corresponding to each voltage domain according to preset conditions, used to characterize the range of ripple voltage variation. For example, the target amplitude can be the ripple peak value, ripple valley value, a part of the peak-to-peak value, the effective value, or an equivalent amplitude parameter derived from the ripple waveform, which is not limited here.

[0112] For example, the amplitudes used to define the upper and lower bounds of the ripple voltage can be selected from the power supply ripples of Domain A and Domain B, respectively, as target amplitudes, and the second ripple difference can be calculated based on the target amplitudes.

[0113] For example, the amplitudes used to define the upper and lower bounds of the ripple voltage can be selected from the power supply ripples of Domain A and Domain B, respectively, as target amplitudes, and the second ripple voltage difference can be calculated based on the target amplitudes. For instance, the peak value of the power supply ripple in Domain A can be selected as the first target amplitude, and the valley value of the power supply ripple in Domain B can be selected as the second target amplitude, with the voltage difference between the peak and valley values ​​used as the second ripple voltage difference; or, the valley value of the power supply ripple in Domain A can be selected as the first target amplitude, and the peak value of the power supply ripple in Domain B can be selected as the second target amplitude, with the corresponding voltage difference used as the second ripple voltage difference.

[0114] Using the above method, when the timing endpoints are in different voltage domains, the second ripple voltage can be determined by determining the target amplitude in different ripples.

[0115] In one embodiment, the above-mentioned adjustment of the total delay of the target common path based on the first delay factor and the second delay factor to determine the target clock delay includes: adjusting the timing path delay through the target delay factor to obtain the target clock delay; the timing path delay is determined based on the common clock path delay and the internal clock tree delay; and using the target clock delay to perform timing detection on the timing path.

[0116] Among them, the common clock path delay refers to the clock propagation delay on the common clock path before the clock signal under test propagates from the clock source to the corresponding clock bifurcation point of the timing endpoint; the internal clock tree delay refers to the clock tree delay of the clock signal under test propagating from the clock input port to the internal register within the hard core IP or encapsulated IP.

[0117] Optionally, the common clock path delay and the internal clock tree delay can be obtained using the STA tool.

[0118] Optionally, the common clock path delay can be added to the internal clock tree delay to characterize the delay on the timing path between timing endpoint pairs, i.e., the timing path delay.

[0119] Optionally, the first delay factor and the second delay factor can be added together to obtain the target delay factor. The target delay factor characterizes the impact of power supply fluctuations on the timing path between timing endpoint pairs.

[0120] Finally, the timing path delay is adjusted using the target delay factor to obtain the target clock delay.

[0121] Optionally, the target delay factor can be multiplied by the timing path delay to obtain the target clock delay.

[0122] In the above embodiments, the target clock delay can be accurately obtained by adjusting the timing path delay through the target delay factor.

[0123] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0124] Based on the same inventive concept, this application also provides a timing detection apparatus for implementing the timing detection method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more timing detection apparatus embodiments provided below can be found in the limitations of the timing detection method described above, and will not be repeated here.

[0125] In one exemplary embodiment, such as Figure 8 As shown, a timing detection device is provided, comprising: a determination module, a quantization module, and a detection module, wherein:

[0126] The determination module is used to determine at least one timing path that the clock signal under test traverses during transmission in the chip under test.

[0127] The quantization module is used to quantify the impact of voltage fluctuations on the clock propagation delay of the clock signal under test into a target delay factor for each timing path.

[0128] The detection module is used to perform timing detection on at least one timing path based on the target delay factor.

[0129] In one embodiment, the voltage fluctuation includes static voltage drop and ripple; the quantization module includes:

[0130] The voltage quantization submodule is used to quantize the effect of static voltage drop on clock propagation delay as a first delay factor, and to quantize the effect of ripple on clock propagation delay as a second delay factor.

[0131] The delay factor calculation submodule is used to add the first delay factor and the second delay factor to determine the target delay factor.

[0132] In one embodiment, the voltage quantization submodule includes:

[0133] The representative value calculation unit is used to calculate the representative value of the static voltage drop based on the static voltage drop corresponding to each common clock path in the chip under test of the clock signal under test.

[0134] The first simulation unit is used to simulate the target device in the clock tree corresponding to the clock signal under test using the static voltage drop representative value, and obtain the first delay factor.

[0135] In one embodiment, the representative value calculation unit includes:

[0136] The common path determination subunit is used to determine the common clock path based on the clock tree structure of the clock signal under test.

[0137] The static voltage drop determination subunit is used to perform static voltage drop analysis on the power networks where each common clock path is located, in conjunction with power network information, to obtain the static voltage drop corresponding to each common clock path.

[0138] In one embodiment, the starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger; the voltage quantization submodule mentioned above includes:

[0139] The first ripple voltage difference calculation unit is used to calculate the first ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain when the data transmission trigger and the data capture trigger on the same timing path are in the same voltage domain.

[0140] The first ripple simulation unit is used to simulate the target device in the clock tree corresponding to the clock signal under test using the first ripple voltage difference, and obtain the second delay factor.

[0141] In one embodiment, the first ripple calculation subunit includes:

[0142] The model constructs sub-units, which are used to construct the ripple voltage model based on the ripple amplitude and frequency.

[0143] The voltage value calculation unit is used to calculate the ripple voltage value corresponding to adjacent clock edges in the clock signal under test based on the ripple voltage model.

[0144] The first differential pressure calculation unit is used to determine the first ripple voltage difference based on the ripple voltage values ​​corresponding to adjacent clock edges.

[0145] In one embodiment, the starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger; the above-mentioned ripple voltage difference calculation unit further includes:

[0146] The second ripple calculation subunit is used to determine the target amplitude based on the ripple amplitude corresponding to each voltage domain when the data transmission trigger and the data capture trigger on the same timing path are not in the same voltage domain, and to calculate the second ripple voltage difference based on the target amplitude.

[0147] The first ripple simulation unit is used to simulate the target device in the clock tree corresponding to the clock signal under test using the second ripple voltage difference, and obtain the second delay factor.

[0148] In one embodiment, the detection module includes:

[0149] The delay calculation submodule is used to adjust the timing path delay by the target delay factor to obtain the target clock delay; the timing path delay is determined based on the common clock path delay and the internal clock tree delay.

[0150] The timing calculation submodule is used to perform timing detection on the timing path using the target clock delay.

[0151] Each module in the aforementioned timing detection device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0152] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When executed by the processor, the computer program implements a timing detection method.

[0153] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0154] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0155] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0156] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0157] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0158] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0159] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A timing detection method, characterized in that, The method includes: Determine at least one timing path that the clock signal under test traverses during its transmission in the chip under test; For voltage fluctuations on each of the timing paths, the impact of the voltage fluctuations on the clock propagation delay of the clock signal under test is quantified into a target delay factor; Based on the target delay factor, timing detection is performed on at least one of the timing paths.

2. The method according to claim 1, characterized in that, The voltage fluctuation includes static voltage drop and ripple; quantifying the impact of the voltage fluctuation on the clock propagation delay of the clock signal under test into a target delay factor includes: The effect of the static voltage drop on the clock propagation delay of the clock signal under test is quantified as a first delay factor, and the effect of the ripple on the clock propagation delay of the clock signal under test is quantified as a second delay factor. The first delay factor and the second delay factor are added together to determine the target delay factor.

3. The method according to claim 2, characterized in that, The step of quantifying the impact of the static voltage drop on the clock propagation delay into a first delay factor includes: Based on the static voltage drop corresponding to each common clock path in the chip under test of the clock signal under test, the representative value of the static voltage drop is calculated. Using the static voltage drop representative value, the target device in the clock tree corresponding to the clock signal under test is simulated to obtain the first delay factor.

4. The method according to claim 3, characterized in that, The process for determining the static voltage drop corresponding to each of the aforementioned common clock paths includes: The common clock path is determined based on the clock tree structure of the clock signal to be tested; By combining the power network information, a static voltage drop analysis is performed on the power network where each of the common clock paths is located, and the static voltage drop corresponding to each of the common clock paths is obtained.

5. The method according to claim 2, characterized in that, The starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger. The step of quantifying the impact of the ripple on the clock propagation delay of the clock signal under test as a second delay factor includes: When the data transmission trigger and the data capture trigger on the same timing path are in the same voltage domain, the first ripple voltage difference corresponding to the clock signal under test is calculated based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain. Using the first ripple voltage difference, the target device in the clock tree corresponding to the clock signal under test is simulated to obtain the second delay factor.

6. The method according to claim 5, characterized in that, The step of calculating the first ripple voltage difference corresponding to the clock signal under test based on the ripple amplitude and ripple frequency of the power supply ripple corresponding to the voltage domain includes: A ripple voltage model is constructed based on the ripple amplitude and the frequency. Based on the ripple voltage model, the ripple voltage values ​​corresponding to adjacent clock edges in the clock signal under test are calculated. The first ripple voltage difference is determined based on the ripple voltage values ​​corresponding to adjacent clock edges.

7. The method according to claim 2, characterized in that, The starting point of the timing path is a data transmission trigger; the ending point of the timing path is a data capture trigger. The step of quantifying the impact of the ripple on the clock propagation delay of the clock signal under test as a second delay factor includes: When the data transmission trigger and the data capture trigger on the same timing path are not in the same voltage domain, a target amplitude is determined based on the ripple amplitude corresponding to each voltage domain, and a second ripple voltage difference is calculated based on the target amplitude. Using the second ripple voltage difference, the target device in the clock tree corresponding to the clock signal under test is simulated to obtain the second delay factor.

8. The method according to claim 1, characterized in that, The step of performing timing detection on the timing path based on the target delay factor includes: The timing path delay is adjusted by the target delay factor to obtain the target clock delay; the timing path delay is determined based on the common clock path delay and the internal clock tree delay. Timing detection is performed on the timing path using the target clock delay.

9. A timing detection device, characterized in that, The device includes: The determination module is used to determine at least one timing path that the clock signal under test traverses during transmission in the chip under test; The quantization module is used to quantify the impact of voltage fluctuations on the clock propagation delay of the clock signal under test into a target delay factor for each of the timing paths. The detection module is used to perform timing detection on at least one of the timing paths based on the target delay factor.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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