Chip standard cell performance prediction method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a chip standard cell performance prediction method and device, electronic equipment and storage medium; the method comprises: obtaining layout data of a standard cell and netlist data of the standard cell; based on the layout data, extracting image features of a specific structure layer of the standard cell to generate corresponding layout tensors; based on the netlist data, constructing heterogeneous graph data for representing the topology structure of the standard cell; according to the layout tensors, extracting spatial geometric information of the standard cell to obtain a first feature sequence; encoding the heterogeneous graph data to obtain a second feature sequence; according to a predetermined mapping relationship, mapping the first feature sequence into a key vector and a value vector respectively, and mapping the second feature sequence into a query vector; according to the similarity between the query vector and the key vector, performing weighted processing on the value vector to obtain a fusion vector; and according to the fusion vector, predicting the performance of the standard cell to obtain a performance index of the standard cell.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus, electronic device, and storage medium for predicting the performance of a standard chip cell. Background Technology

[0002] The standard cell is the basic unit for designing a very large scale integration circuit (VLSI). Its performance, power consumption, and area directly determine the PPA (Performance, Power, Area) of the integrated circuit.

[0003] At advanced process nodes (such as 7nm and below), the process of process design co-optimization and system process co-optimization requires the evaluation of a large number of standard cell variants with different drive strengths and layout structures. In chip design, the process of evaluating the performance indicators such as latency and power consumption of standard cells is called characterization. Traditional standard cell characterization typically involves first extracting parasitic resistance and capacitance parameters from the standard cell layout using a field solver, and then using circuit simulators such as SPICE to calculate the latency and power consumption performance indicators of standard cells at different PVT (Process, Voltage, Temperature) nodes. However, with the explosive growth in the number of PVT nodes and the rapid increase in cell variants, this process often takes several days or even longer, becoming a bottleneck in chip design iteration. Therefore, how to quickly obtain the performance indicators of standard cells has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method, apparatus, electronic device, and storage medium for predicting the performance of a standard chip cell, in order to solve or at least alleviate the above-mentioned problems.

[0005] According to a first aspect of the present application, a method for performance prediction of a chip standard cell is provided, comprising: acquiring layout data of the standard cell and netlist data of the standard cell, wherein the netlist data is used to represent the connection relationship of various electronic devices in the standard cell; extracting image features of specific structural layers of the standard cell based on the layout data to generate corresponding layout tensors; constructing heterogeneous graph data to represent the topology of the standard cell based on the netlist data; extracting spatial geometric information of the standard cell based on the layout tensor to obtain a first feature sequence; encoding the heterogeneous graph data to obtain a second feature sequence; mapping the first feature sequence to a key vector and a value vector respectively according to a predetermined mapping relationship, and mapping the second feature sequence to a query vector; weighting the value vector according to the similarity between the query vector and the key vector to obtain a fusion vector; and predicting the performance of the standard cell based on the fusion vector to obtain the performance index of the standard cell.

[0006] In some optional embodiments, the topology represented by the heterogeneous graph data includes first-type nodes, second-type nodes, first-type edges, and second-type edges; the step of constructing heterogeneous graph data to represent the topology of the standard unit based on the netlist data includes: determining the electronic devices of the standard unit as first-type nodes according to the netlist data; determining the connection nodes between each of the electronic devices and determining the connection nodes as second-type nodes; determining the connection edges between each of the first-type nodes and each of the second-type nodes and determining the connection edges as first-type edges; and determining the second-type edges existing between the connection nodes, wherein the second-type edges are used to indicate that there is a coupling relationship between the multiple connection nodes connected by the second-type edge.

[0007] In some optional embodiments, determining the existence of a second type of edge between the connected nodes includes: establishing a second type of edge between multiple second type nodes connected to the same first type node.

[0008] In some optional embodiments, encoding the heterogeneous graph data to obtain a second feature sequence includes: processing the heterogeneous graph data using a graph Transformer encoder to obtain a second feature sequence.

[0009] In some optional embodiments, the parameters of the graph Transformer encoder include a graph mask and a structural bias term. The graph mask is used to limit the calculation range of the attention mechanism of the graph Transformer encoder to node pairs where there is a first type edge or a second type edge between the two included nodes. The structural bias term is used to represent the correspondence between the edge type and the weight adjustment parameter, serving as the basis for the graph Transformer encoder to determine the attention weights of the node pairs.

[0010] In some optional embodiments, the step of extracting the spatial geometric information of the standard unit based on the layout tensor to obtain the first feature sequence includes: dividing the layout tensor into multiple tile tensors; performing linear projection processing on the tile tensors to generate tile vectors corresponding to the tile tensors; obtaining an initial feature sequence including each tile vector based on each tile vector; and processing the initial feature sequence through a visual Transformer encoder to obtain the first feature sequence.

[0011] In some optional embodiments, obtaining an initial feature sequence including each of the tile vectors includes: obtaining predetermined category items and distillation items, and concatenating the category items, the distillation items and each of the tile vectors to obtain the initial feature sequence.

[0012] In some optional embodiments, the step of extracting image features of a specific structural layer of the standard cell based on the layout data and generating a corresponding layout tensor includes: expanding the pixels occupied by the vias of the specific structural layer based on the layout data to obtain preprocessed layout data; and extracting image features of the specific structural layer based on the preprocessed layout data to generate a corresponding layout tensor.

[0013] In some optional embodiments, the step of weighting the value vector based on the similarity between the query vector and the key vector to obtain a fusion vector includes: determining a corresponding similarity vector based on the similarity between the query vector and the key vector; determining a weight vector for weighting the value vector based on the similarity vector; and weighting the value vector based on the weight vector to obtain the fusion vector.

[0014] In some alternative embodiments, the specific structural layer of the standard cell includes a bottom metal layer, a top metal layer, and an intermediate metal layer between the bottom metal layer and the top metal layer.

[0015] According to a second aspect of the present application, a performance prediction apparatus for a chip standard cell is provided, comprising: an acquisition unit, configured to acquire layout data of the standard cell and netlist data of the standard cell, wherein the netlist data is used to represent the connection relationship of various electronic devices in the standard cell; a first preprocessing unit, configured to extract image features of a specific structural layer of the standard cell based on the layout data, and generate a corresponding layout tensor; a second preprocessing unit, configured to construct heterogeneous graph data representing the topology of the standard cell based on the netlist data; an encoding unit, configured to extract spatial geometric information of the standard cell according to the layout tensor, and obtain a first feature sequence; and encode the heterogeneous graph data to obtain a second feature sequence; a mapping unit, configured to map the first feature sequence to a key vector and a value vector respectively according to a predetermined mapping relationship, and map the second feature sequence to a query vector; a weighted fusion unit, configured to weight the value vector according to the similarity between the query vector and the key vector to obtain a fusion vector; and a prediction unit, configured to predict the performance of the standard cell based on the fusion vector to obtain the performance index of the standard cell.

[0016] According to a third aspect of the present application, an electronic device is provided, comprising: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory is used to store at least one executable instruction, wherein the executable instruction causes the processor to perform an operation corresponding to the method of any of the above embodiments.

[0017] According to a fourth aspect of the embodiments of this application, a computer storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the operations corresponding to the methods of any of the above embodiments.

[0018] In this embodiment, layout data and netlist data of standard cells can be obtained. Image features of specific structural layers of the standard cells are extracted based on the layout data to generate corresponding layout tensors. Heterogeneous graph data representing the topology of the standard cells is constructed based on the netlist data. Spatial geometric information of the standard cells is extracted from the layout tensors to obtain a first feature sequence. The heterogeneous graph data is encoded to obtain a second feature sequence. According to a predetermined mapping relationship, the first feature sequence is mapped to key vectors and value vectors, and the second feature sequence is mapped to a query vector. The value vectors are weighted based on the similarity between the query vector and the key vector to obtain a fusion vector. The performance of the standard cells is predicted based on the fusion vector to obtain the performance index of the standard cells. The method of this embodiment obtains the fusion vector and predicts the performance index based on it through the above steps. The entire process only requires one forward inference, without the need to use circuit simulators such as SPICE to calculate the performance index of standard cells under different PVT nodes as in traditional methods. This avoids the iterative solution caused by calculating the performance index of standard cells under different PVT nodes, greatly reducing the computation time required to evaluate standard cells and significantly improving the speed of obtaining the performance index of standard cells.

[0019] Furthermore, according to the predetermined mapping relationship, the first feature sequence is mapped to the key vector and the value vector respectively, and the second feature sequence is mapped to the query vector. The value vector is weighted according to the similarity between the query vector and the key vector to obtain the fusion vector. In this process, the second feature sequence is the source of the query vector, and the first feature sequence is the source of the key vector and the value vector. This makes the process of obtaining the fusion vector through weighted processing form an asymmetric cross-attention mechanism. Since the first feature sequence is obtained from the spatial geometric information of the standard cell extracted from the layout tensor, which is generated based on the layout data, and the second feature sequence is obtained by encoding the heterogeneous graph data, which is constructed based on the netlist data, the asymmetric cross-attention mechanism formed in this implementation can search and aggregate the layout regions corresponding to the electrical connection relationships in the image information represented by the layout data, such as metal interconnects and via regions, based on the electrical connection relationships represented by the netlist data. This achieves precise alignment between the circuit logic and the physical layout, ensuring that the information carried by the fusion vector has a consistent correspondence between the physical implementation and the circuit logic. This allows the fusion vector to accurately reflect the impact of the circuit structure of the standard cell on its performance, effectively improving the accuracy of subsequent performance index predictions based on the fusion vector. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0021] Figure 1 This is a flowchart of the steps of a performance prediction method provided in some optional embodiments of this application.

[0022] Figure 2 This is a schematic diagram showing the connection relationship of some electronic devices represented by netlist data in some optional embodiments of this application.

[0023] Figure 3 According to some optional embodiments of this application Figure 2 The diagram shows the topology structure constructed by the connection relationships shown.

[0024] Figure 4 These are some optional embodiments provided in this application. Figure 1 S140 includes a step diagram.

[0025] Figure 5 These are some optional embodiments provided in this application. Figure 1 S160 includes a step diagram.

[0026] Figure 6 This is a schematic diagram of the structure of a performance prediction device provided in some optional embodiments of this application.

[0027] Figure 7 This is a schematic diagram of the structure of an electronic device provided in some optional embodiments of this application. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0029] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “an,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0030] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0031] This application provides a method, apparatus, electronic device, and storage medium for predicting the performance of standard chip cells, to at least partially solve the aforementioned problems existing in the prior art. For example... Figure 1 As shown in the embodiments of this application, the performance prediction method for a standard chip cell includes: S110. Obtain the layout data and netlist data of the standard cell.

[0032] In the field of integrated circuit design, layout data refers to design documents that describe the geometric shape and hierarchical relationships of the circuit structure in an integrated circuit. The layout data of a standard cell can contain the two-dimensional geometry (position, size, shape) of each structural layer (such as active regions, metal layers, etc.), as well as the stacking and connection relationships between different structural layers. Netlist-only data refers to design data used to describe electronic devices (such as transistors, resistors, capacitors, etc.) and their interconnection topology. Accordingly, the netlist data of a standard cell is used to represent the connection relationships of various electronic devices within the standard cell.

[0033] Optionally, the layout data and netlist data of the standard cell can be data input or imported by the user in real time. In this embodiment, the layout data and netlist data can be obtained through the data port for user input or import of layout data and netlist data. The layout data and netlist data of the standard cell can be stored in a predetermined memory, cloud server, or cloud disk. In this embodiment, the layout data and netlist data of the standard cell can be obtained from a predetermined memory, cloud server, or cloud disk.

[0034] S120. Based on the layout data, extract the image features of specific structural layers of the standard unit and generate the corresponding layout tensor.

[0035] Image features of the structural layer can include image information of the geometry on the structural layer, such as the pixel arrangement of the geometry. In some optional embodiments, the layout data can be converted into image data through rasterization, and image features of a specific structural layer can be extracted from the image data. After the image features are extracted, they can be represented in the form of tensors to obtain the corresponding layout tensors.

[0036] In some alternative embodiments, a specific structural layer of the standard cell includes a bottom metal layer, a top metal layer, and an intermediate metal layer between the bottom metal layer and the top metal layer.

[0037] The metal layers of a standard cell can be categorized by location into a bottom metal layer, a top metal layer, and an intermediate metal layer between the bottom and top metal layers. The bottom metal layer is closest to the substrate, while the top metal layer is furthest from the substrate. When extracting image features from the bottom, top, and intermediate metal layers based on layout data, the data extracted from each metal layer can be located in the three data channels of the layout tensor, generating a layout tensor of dimension 3×H×W. Here, 3 represents the three data channels containing the data from the bottom, top, and intermediate metal layers. H and W represent the vertical and horizontal dimensions of the data extracted from each metal layer, respectively. This allows for the alignment of the image features of the bottom, top, and intermediate metal layers within the three data channels of the layout tensor, representing their hierarchical relationship.

[0038] The bottom metal layer is typically adjacent to the active region of the transistor and is responsible for the device port leads. Its linewidth and spacing directly affect local parasitic resistance and coupling capacitance. The middle metal layer is used for signal interconnection within the standard cell, and its routing and length determine signal transmission delay and crosstalk. The top metal layer is typically thicker and has lower resistance. It carries the power / ground lines of the standard cell and wiring that needs to cross long distances within the cell, significantly impacting power quality and electromagnetic coupling. In this embodiment, a specific structural layer is set, including the bottom metal layer, the top metal layer, and the middle metal layer between the bottom and top metal layers of the standard cell. This covers the main physical layers of the standard cell, allowing the layout tensor generated based on the specific structural layer to more comprehensively reflect the impact of the physical structure of the standard cell on its performance parameters, which is beneficial for ensuring the accuracy of subsequent performance parameter predictions.

[0039] In some optional embodiments, image features of specific structural layers of standard units are extracted based on layout data to generate corresponding layout tensors, including: Based on the layout data, the pixels occupied by vias in a specific structural layer are expanded to obtain preprocessed layout data. Based on the preprocessed layout data, image features of the specific structural layer are extracted to generate the corresponding layout tensor.

[0040] When extracting image features of specific structural layers of standard cells based on layout data, the layout data can be converted into image data of a fixed resolution through rasterization, and then the image features of specific structural layers can be extracted from the image data. For example, during the rasterization process, the image pixels corresponding to circuit units such as metal interconnects and vias of the standard cell can be set to 1, while the image pixels of other areas can be set to 0, thereby highlighting the geometry of the circuit units and facilitating the subsequent extraction of image features from the image data.

[0041] After obtaining image data through rasterization, the pixels occupied by vias in specific structural layers of the image data can be expanded. For example, the pixels occupied by the vias can be expanded by one or two pixels, or by other numbers of pixels, to obtain expanded image data. The expanded image data can be used as the preprocessed layout data mentioned above. Based on the expanded image data, image features of specific structural layers can be extracted to generate the corresponding layout tensor.

[0042] In standard cells, vias typically occupy only a small number of pixels in the image corresponding to the layout data, and their geometric information is easily ignored by subsequent processing. In this embodiment, by expanding the pixels occupied by the vias, the effective area occupied by the vias in the image features extracted from the layout tensor can be increased, thereby strengthening the positional and shape information of the vias carried by the layout tensor. This allows for a more complete capture of the geometric information of the via region when extracting spatial geometric information from the layout tensor, and thus enables the first feature sequence obtained subsequently to more accurately reflect the parasitic effect brought about by the vias.

[0043] S130. Based on netlist data, construct heterogeneous graph data to represent the topology of standard cells.

[0044] Based on the netlist data, the topological relationships between electronic devices are transformed into edges between nodes, resulting in heterogeneous graph data containing nodes and edges. The topological structure of standard cells is represented by the structure composed of nodes and edges.

[0045] In some optional embodiments, the topology represented by the heterogeneous graph data includes first-type nodes, second-type nodes, first-type edges, and second-type edges. Based on netlist data, heterogeneous graph data for representing the topology of standard cells is constructed, including: Based on the netlist data, the electronic components of the standard cell are identified as first-type nodes. The connection nodes between the various electronic components are determined and classified as second-type nodes. The connection edges between each first-type node and each second-type node are determined and classified as first-type edges. Furthermore, second-type edges existing between the connection nodes are identified, where second-type edges represent coupling relationships between multiple connection nodes connected by that second-type edge.

[0046] It should be noted that the power supply terminal of a standard cell can be considered a connection node. The power supply terminal of a standard cell can be identified as a second-type node to capture the connection relationship between the electronic components and the power supply of the standard cell. When two electronic components are connected and there are no other electronic components between them, a second-type node connecting the two electronic components can be identified. Similarly, when a first-type node and a second-type node are connected and there are no other nodes between them, a connection edge connecting the first-type node and the second-type node can be identified. The coupling relationship represented by the second-type edge can be understood as the parasitic interaction (e.g., parasitic capacitance, parasitic inductance, etc.) between the connection lines represented by different connection nodes due to spatial proximity or overlap. The second-type edge can be determined based on the adjacency relationship between the connection nodes.

[0047] Heterogeneous graph data can include node information for both types of nodes and edges. Based on this information, corresponding heterogeneous graph data can be generated. The node and edge information in the heterogeneous graph data can be represented as vectors; by encoding or extracting features from this information, corresponding vectors can be generated.

[0048] In some alternative embodiments, the electronics of the standard cell can be transistors. In this case, the node information of the first type of node may include the transistor type (NMOS / PMOS), polarity flag, and width-to-length ratio (W / L) information. The node information of the second type of node may include a flag indicating whether it is an input / output pin (IO pin), and first connection information indicating its connection object. The edge information of the first type of edge may include second connection information indicating its connection object. The edge information of the second type of edge may include third connection information indicating its connection object. It should be understood that the connection object of the second type of node is the first type of node, the connection object of the first type of edge includes both first and second type nodes, and the connection object of the second type of edge is the second type of node.

[0049] In some alternative embodiments, the electronic components of the standard cell can be any of the following: electronic components, resistors, and capacitors. In this case, the node information of the first type of node can include the physical specifications of the corresponding electronic components, such as the resistance value of a resistor and the capacitance value of a capacitor. This embodiment does not limit the way the electronic components in the standard cell are configured.

[0050] In this embodiment, based on netlist data, the electronic devices of the standard cell are identified as first-type nodes. Connection nodes between the various electronic devices are determined and designated as second-type nodes. Connection edges between each first-type node and each second-type node are determined and designated as first-type edges. Furthermore, second-type edges existing between connection nodes are identified, whereby second-type edges represent coupling relationships between multiple connection nodes connected by the second-type edge. This scheme, by introducing second-type edges, enables heterogeneous graph data to not only characterize the original circuit topology formed by the electronic devices in the standard cell through connection nodes (i.e., first-type edges), but also to explicitly characterize the parasitic coupling effects generated by the connection lines represented by different connection nodes. This allows subsequent encoding of the heterogeneous graph data to simultaneously encode the parasitic coupling relationships between the connection lines of the standard cell, incorporating more physical factors affecting performance into the second feature sequence. Therefore, the fusion vector generated based on this second feature sequence can more comprehensively reflect the actual impact of signal crosstalk, coupling capacitance, etc., between physical structures in the standard cell layout on performance indicators, which is beneficial for improving the prediction accuracy of performance indicators.

[0051] In some optional embodiments, determining the existence of a second type of edge between connected nodes includes: Establish second-type edges between multiple second-type nodes connected to the same first-type node. For example, such as... Figure 3 As shown, when multiple second-type nodes are directly connected to the same first-type node, a second-type edge can be established between two second-type nodes among the multiple second-type nodes.

[0052] The electronic devices represented by the first type of node typically have multiple connection terminals (such as the gate, source, and drain of a transistor). Each connection terminal can be connected to a connection node, namely the second type of node. There is often a tight spatial coupling relationship between second type nodes connected to the same first type of node. For example, when the first type of node is a transistor, a gate-source parasitic capacitance will be formed between the second type of node connected to the gate of the first type of node and the second type of node connected to the source of the first type of node.

[0053] For example, Figure 2The diagram illustrates the connection relationships of a portion of the electronic components indicated by the netlist data of a standard cell. These components include a first transistor D1, a second transistor D2, a third transistor D3, and a fourth transistor D4. The drains of the first transistor D1 and the second transistor D2 are connected to the positive power supply terminal VDD. The sources of the first transistor D1 and the second transistor D2 are connected to line Y and the source of the third transistor D3, respectively. The gate of the first transistor D1 is connected to line A, the gate of the second transistor D2 is connected to line B, the gate of the third transistor D3 is connected to line A, the drain of the third transistor D3 is connected to the source of the fourth transistor D4 via line N1, the gate of the fourth transistor D4 is connected to line B, and the drain of the fourth transistor D4 is connected to the negative power supply terminal VSS.

[0054] By using the above steps, it is possible to base on Figure 2 The connection relationships shown determine Figure 3 The heterogeneous graph data showing the topological relationships is shown. Specifically, Figure 3 The first type of nodes d1, d2, d3, and d4 represent respectively Figure 2 The transistors are: first transistor D1, second transistor D2, third transistor D3, and fourth transistor D4. Second-class nodes a, b, n1, vdd, and vss can represent the connection nodes between these transistors. Figure 3 The solid lines between the first-type nodes d1, d2, d3, d4 and the second-type nodes a, b, y, n1, vdd, vss are the first-type edges. Figure 3 The dashed line between the second-type nodes a, b, y, n1 and vss represents the second-type edge established between multiple second-type nodes connected to the same first-type node.

[0055] In this embodiment of the application, by establishing a second type of edge between multiple second type nodes connected to the same first type node, the heterogeneous graph data can characterize the coupling relationship between the connected nodes represented by the second type nodes in a concise and circuit-structure-compliant manner, without relying on spatial distance judgment in the layout geometry information, which can significantly reduce the difficulty of capturing the coupling relationship between connected nodes.

[0056] S140. Based on the layout tensor, extract the spatial geometric information of the standard cells to obtain the first feature sequence. Encode the heterogeneous graph data to obtain the second feature sequence.

[0057] The spatial geometry information of a standard cell can include the geometric and positional information of circuit structures (e.g., metal interconnects) within a specific structural layer. Based on the image features of a specific structural layer represented by a layout tensor, the spatial geometry information of the circuit structures within that layer can be obtained. Heterogeneous graph data can be understood as a dataset describing nodes and edges; encoding heterogeneous graph data into a second feature sequence facilitates machine processing.

[0058] like Figure 4 As shown, in some optional embodiments, spatial geometric information of standard cells is extracted based on the layout tensor to obtain a first feature sequence, including: S141. Divide the map tensor into multiple map tensors.

[0059] Optionally, the layout tensor can be divided into multiple block tensors of the same size according to a fixed tensor size.

[0060] S142. Perform linear projection on the tile tensor to generate the tile vector corresponding to the tile tensor.

[0061] Through linear projection, each tile tensor can be mapped to a one-dimensional tile vector of fixed dimensions.

[0062] S143. Based on each tile vector, obtain the initial feature sequence including each tile vector.

[0063] After obtaining the individual tile vectors, adding them into a sequence yields the initial feature sequence.

[0064] S144. The initial feature sequence is processed by a visual Transformer encoder to obtain the first feature sequence.

[0065] The Vision Transformer (ViT) encoder is an image feature extraction model based on a multi-head self-attention mechanism. It can be composed of multiple stacked encoding layers, each including a multi-head self-attention mechanism and a feedforward neural network. Its specific structure can be pre-defined according to actual design requirements and optimized through learning from patch vector samples during training. For example, a Vision Transformer encoder can be configured with 12 encoding layers, each with 8 attention heads. The specific training process of the Vision Transformer encoder can be found in related technologies and will not be elaborated here.

[0066] When processing the initial feature sequence, the visual Transformer encoder gradually aggregates information from the tile vectors through layer-by-layer computation across multiple encoding layers, capturing long-distance spatial dependencies between different tiles. After multiple layers of encoding, the first feature sequence is output, which encodes the spatial geometric information of each local region in the map tensor and its global interaction relationships, and can be used for subsequent cross-modal fusion with the second feature sequence.

[0067] In this embodiment, the layout tensor is divided into multiple tile tensors. Linear projection is performed on the tile tensors to generate tile vectors corresponding to the tile tensors. An initial feature sequence, including each tile vector, is obtained based on these vectors. The initial feature sequence is then processed by a visual Transformer encoder to obtain a first feature sequence. This scheme, based on the multi-head self-attention mechanism of the visual Transformer encoder, can model the relationships between different tiles globally, effectively capturing the spatial dependencies of distant tile regions in the standard unit layout. Compared to schemes relying solely on local convolution operations, the visual Transformer encoder has a larger receptive field and stronger global context aggregation capabilities, enabling more complete extraction of spatial geometric information such as width, spacing, and interlayer overlap of the physical structure in the standard unit layout. This results in a first feature sequence with richer global spatial representation capabilities, providing more accurate layout geometric features for subsequent fusion vectors.

[0068] In some optional embodiments, obtaining an initial feature sequence including each tile vector is performed based on each tile vector, including: obtaining predetermined category items and distillation items, and concatenating the category items, distillation items and each tile vector to obtain the initial feature sequence.

[0069] The class token, also known as the category token, is used to aggregate global map feature information during subsequent encoding. The distillation token, also known as the distillation token, is used to improve the model's generalization ability during training by employing knowledge distillation strategies. In this embodiment, two learnable vectors can be pre-defined as the class token and the distillation token, respectively. Concatenating the class token and the distillation token with each tile vector in sequence forms a longer sequence, which serves as the initial feature sequence. For example, if the number of tile vectors is N, the length of the concatenated initial feature sequence is N+2. In the initial feature sequence, the first vector can be the class token, the second vector can be the distillation token, and the subsequent tile vectors are arranged sequentially.

[0070] In some alternative embodiments, pre-defined distillation terms can be obtained through knowledge distillation training. For example, before training the visual Transformer encoder, a teacher model that performs better than the visual Transformer encoder can be pre-trained. When training the visual Transformer encoder, the distillation terms are trained by fitting the training results of the distillation terms to the prediction results of the teacher model.

[0071] When the initial feature sequence is input into the visual Transformer encoder, the visual Transformer encoder, under its self-attention mechanism, allows the category and distillation terms to interact with other patch vectors. This enables the category and distillation terms to learn global context information from the patch vectors, thereby updating the category and distillation terms. The final output includes the updated category and distillation terms as the first feature sequence. It can be represented as ,in Indicates category items, Indicates the distillation term. This represents the sequence of tile vectors from the first to the Pth tile vector, where P is equal to the number of tile vectors. In some alternative embodiments, the visual Transformer encoder can be a DeiT (Data-efficient Image Transformers) model.

[0072] In this embodiment, predetermined category terms and distillation terms can be obtained. These category terms and distillation terms are then concatenated with each tile vector to obtain an initial feature sequence. The category terms can serve as global feature aggregation nodes, interacting fully with each tile vector in the subsequent self-attention calculation of the visual Transformer encoder. This gradually aggregates the global spatial geometric information of the complete map, including all tiles, ensuring the encoded first feature sequence contains more complete global map features. Distillation terms are used for knowledge distillation during training. Specifically, a more complex and powerful visual Transformer model can be pre-trained as the teacher model, while the visual Transformer encoder in this application serves as the student model. Through distillation terms, the output of the corresponding teacher model can be fitted using a knowledge distillation strategy, improving the generalization ability and convergence efficiency of the visual Transformer encoder, mitigating the overfitting problem that may arise due to limited training data, and enhancing the stability of the graph Transformer encoder.

[0073] like Figure 4 As shown, in some optional embodiments, the heterogeneous graph data is encoded to obtain a second feature sequence, including: S145. The heterogeneous graph data is processed by the graph Transformer encoder to obtain the second feature sequence.

[0074] The Graph Transformer encoder is a graph neural network model based on a multi-head self-attention mechanism. Its structural parameters can be pre-set according to actual design requirements and optimized through learning from standard unit samples during training. For example, the Graph Transformer encoder can be configured to include four graph self-attention layers, each with eight attention heads, and node feature dimensions set to 256 dimensions. The specific training process of the Graph Transformer encoder can be found in related technologies and will not be elaborated here.

[0075] The graph Transformer encoder, based on a self-attention mechanism, is used in this embodiment to process heterogeneous graph data. It can simultaneously capture the local connectivity and global topological dependencies of each node in the heterogeneous graph data. Especially for the inter-network coupling relationships represented by the second type of edge, it can perform long-distance information aggregation across multiple nodes, thus avoiding the oversmoothing problem caused by the multi-layer stacking of traditional graph neural networks to expand the receptive field. Therefore, the second feature sequence encoded by the graph Transformer encoder can more fully integrate the information carried by different types of nodes and edges in the heterogeneous graph data. This allows the fusion vector generated based on the second feature sequence to more accurately reflect the impact of complex coupling effects within the standard unit on performance indicators, thereby providing a more reliable data foundation for subsequent performance indicator prediction and further improving prediction accuracy.

[0076] In some optional embodiments, the parameters of the Graph Transformer encoder include a graph mask and a structural bias term. The graph mask is used to limit the computational scope of the attention mechanism of the Graph Transformer encoder to node pairs where there is a first-type edge or a second-type edge between the two nodes. That is, the computational scope of the attention mechanism is limited to node pairs where there is a first-type edge or a second-type edge between the two nodes in the node pair. The structural bias term is used to represent the correspondence between edge types and weight adjustment parameters, serving as the basis for the Graph Transformer encoder to determine the attention weights of node pairs.

[0077] Node pairs can include node pairs consisting of two nodes of the first type, node pairs consisting of two nodes of the first type and one node of the second type, and node pairs consisting of two nodes of the second type. A graph mask is used to limit the computational scope of the attention mechanism of the graph Transformer encoder to node pairs with edges of the first or second type. In specific implementations, the graph mask can be a mask matrix or a mask vector composed of masks, and the masks in the mask matrix or mask vector can be determined based on the heterogeneous graph data. The number of graph masks corresponds to the number of node pairs; that is, one mask corresponds to one node pair, and each mask is used to limit whether its corresponding node pair is within the computational scope of the attention mechanism. For example, when there is an edge of the first or second type between the two nodes in a node pair, the corresponding mask can be set to 1, thereby indicating that the node pair is within the computational scope of the attention mechanism. When there is no edge of the first or second type between the two nodes in a node pair, the corresponding mask can be set to 0, thereby indicating that the node pair is not within the computational scope of the attention mechanism. Of course, the mask can use other suitable values ​​to represent its indicated content, and this embodiment does not limit this.

[0078] The structural bias term can be a mapping function or a mapping table, which maps each type of edge (e.g., type I edge, type II edge) to a weight adjustment parameter. For example, when a graph Transformer encoder calculates the attention weights between two nodes, it can calculate the original attention weights between the two nodes and determine the corresponding weight adjustment parameter based on the type of edge between them and the structural bias term. The weight adjustment parameter is then added to the original attention weights to obtain the adjusted attention weights.

[0079] In this embodiment, by setting a graph mask, the computational scope of the self-attention mechanism is limited to node pairs where there is a first-type edge or a second-type edge between the included two nodes. This avoids calculating attention weights between unrelated nodes, thereby reducing invalid computation and noise interference. The model can then focus on node pairs with actual connections or coupling relationships, improving encoding efficiency and the purity of feature representation. By setting a structural bias term, a correspondence is established between edge types and weight adjustment parameters. This allows the graph Transformer encoder to adaptively adjust attention scores based on edge types when determining attention weights for node pairs, thus distinguishing the importance of first-type edges representing connections and second-type edges representing coupling relationships. Consequently, the encoded second feature sequence can more precisely reflect the structural information carried by different types of edges in heterogeneous graph data, providing more accurate topological information for subsequent fusion vectors.

[0080] S150. According to the predetermined mapping relationship, the first feature sequence is mapped to a key vector and a value vector respectively, and the second feature sequence is mapped to a query vector.

[0081] Key vectors, value vectors, and query vectors are the fundamental vectors of the attention mechanism. A query vector can be understood as a vector used to initiate a retrieval and express the retrieval request. A key vector can be understood as an index label of the target information being retrieved, used for comparison with the query vector. A value vector can be understood as the information content of the target information being retrieved.

[0082] The mapping relationship can be represented in matrix form. The matrix corresponding to the predetermined mapping relationship may include a first matrix representing the mapping relationship between the first feature sequence and the key vector, a second matrix representing the mapping relationship between the first feature sequence and the value vector, and a third matrix representing the mapping relationship between the second feature sequence and the query vector. Based on the first, second, and third matrices, a linear transformation can be performed on the first and second feature sequences to obtain the key vector, value vector, and query vector. Specifically, multiplying the first feature sequence by the first matrix yields the key vector. Multiplying the first feature sequence by the second matrix yields the value vector. Multiplying the second feature sequence by the third matrix yields the query vector.

[0083] For example, key vector It can be represented as: value vector It can be represented as: Query vector It can be represented as: .in, Represents the first characteristic sequence. Indicates the second characteristic sequence. Describes the first matrix. Represents the second matrix, This represents the third matrix.

[0084] S160. Based on the similarity between the query vector and the key vector, the value vector is weighted to obtain the fused vector.

[0085] In this embodiment, the similarity between the query vector and the key vector is related to the weighting parameter used to weight the value vectors. In some alternative embodiments, the similarity can be considered to be positively correlated with the weighting parameter.

[0086] According to a predetermined mapping relationship, the first feature sequence is mapped to key vectors and value vectors respectively, and the second feature sequence is mapped to query vectors. The value vectors are weighted based on the similarity between the query vector and the key vector, forming an asymmetric cross-attention mechanism that uses the second feature sequence as the retrieval anchor and retrieves key and value vectors from the first feature sequence. It should be noted that the inventors of this application have discovered that if the first feature sequence is used as the source of query vectors, key vectors, and value vectors, and the second feature sequence is also used as the source of query vectors, key vectors, and value vectors, then when the value vectors are weighted based on the similarity between the query vector and the key vector, a symmetric cross-attention mechanism is formed. However, this symmetric mechanism often suffers from attention divergence and data fusion disorder due to the mixed sources of query vectors, key vectors, and value vectors, leading to a significant decrease in the accuracy of subsequent prediction performance indicators.

[0087] like Figure 5 As shown, in some optional embodiments, the value vector is weighted based on the similarity between the query vector and the key vector to obtain a fused vector, including: S161. Determine the corresponding similarity vector based on the similarity between the query vector and the key vector.

[0088] S162. Determine the weight vector for weighting the value vector based on the similarity vector.

[0089] S163. The value vector is weighted according to the weight vector to obtain the fusion vector.

[0090] For ease of understanding, the above steps will be explained based on Equation 1 below.

[0091]

[0092] In the formula, Q Represents the query vector. K Represents the key vector. V Represents a value vector. This represents the vector dimension of the query vector and the key vector.

[0093] It can be calculated and product Determine the similarity between the query vector and the key vector, and Divide by The above similarity scores can be scaled to obtain the corresponding similarity vector. Apply the following to each row of the similarity vector: Softmax Normalizing the function so that the sum of the weights in each row is 1 yields the corresponding weight vector. This weight vector is then compared with the value vector. V Multiplying them together yields a weighted fusion vector.

[0094] In this embodiment, a similarity vector can be determined based on the similarity between the query vector and the key vector. A weight vector is then determined based on the similarity vector to weight the value vector. The value vector is then weighted according to the weight vector to obtain a fusion vector. This scheme quantifies the matching degree between the query vector and the key vector by determining the similarity vector. Therefore, in determining the weight vector, value vectors corresponding to key vectors with a high degree of matching with the query vector are assigned larger weights, while value vectors corresponding to key vectors with a low degree of matching are assigned smaller weights, thus obtaining the corresponding weight vectors. Since the query vector originates from the electrical connection relationships represented by the netlist data, and the key and value vectors originate from the spatial geometric information represented by the layout data, the above weighting process essentially searches for and aggregates the corresponding physical structure information in the image corresponding to the layout data based on the electrical connection relationships. This enables precise alignment between circuit logic and physical layout, ensuring a consistent correspondence between the information carried by the fusion vector and the physical implementation, providing a reliable data foundation for subsequent performance indicator prediction.

[0095] S170. Predict the performance of the standard cell based on the fusion vector to obtain the performance index of the standard cell.

[0096] The performance metrics of a standard cell may include power consumption, latency, and other metrics. In some optional embodiments, the performance metrics of a standard cell may include some or all of the following metrics: rise delay, fall delay, rise transition time, fall transition time, rise power, and fall power.

[0097] In some optional embodiments, a prediction model for mapping fused vectors to performance metrics can be preset. During step S170, the fused vector can be input into the preset prediction model, and the performance of the standard cell can be predicted through the mapping processing of the prediction model. The prediction model may include one or more fully connected layers. During prediction, operators such as fully connected layers in the prediction model can be used to process the fused vector to obtain the performance metrics of the standard cell. The preset prediction model can be obtained through training. For example, multiple standard cell samples can be set, and the prediction model can be trained based on the fused vectors and actual performance metrics corresponding to the standard cell samples. The actual performance metrics of the standard cell samples can be obtained through actual measurement or through simulation techniques such as SPICE simulation; this embodiment does not impose any limitations on this.

[0098] In some optional embodiments, the prediction model can be combined with the graph Transformer encoder, visual Transformer encoder, predetermined mapping relationship, and model represented by Equation 1 in the above embodiments to form a test model. The test model is directly trained. The input samples used to train the test model can be layout tensors and heterogeneous graph data obtained from layout data and netlist data based on standard unit samples. The output samples used can be the actual performance indicators of standard unit samples. The training method can be fully supervised or semi-supervised, etc. For details, please refer to the relevant technology, which will not be repeated here.

[0099] Research has found that if the first feature sequence is used as the source of the query vector, key vector, and value vector, and the second feature sequence is also used as the source of the query vector, key vector, and value vector, then when the value vector is weighted using an attention mechanism based on the similarity between the query vector and the key vector, attention divergence and vector source confusion may occur because the query vector, key vector, and value vector have the same data source, leading to a decrease in the accuracy of the subsequent performance metrics.

[0100] In this embodiment, layout data and netlist data of standard cells can be obtained. Image features of specific structural layers of the standard cells are extracted based on the layout data to generate corresponding layout tensors. Heterogeneous graph data representing the topology of the standard cells is constructed based on the netlist data. Spatial geometric information of the standard cells is extracted from the layout tensors to obtain a first feature sequence. The heterogeneous graph data is encoded to obtain a second feature sequence. According to a predetermined mapping relationship, the first feature sequence is mapped to key vectors and value vectors, and the second feature sequence is mapped to a query vector. The value vectors are weighted based on the similarity between the query vector and the key vector to obtain a fusion vector. The performance of the standard cells is predicted based on the fusion vector to obtain the performance index of the standard cells. The method of this embodiment obtains the fusion vector and predicts the performance index based on it through the above steps. The entire process only requires one forward inference, without the need to use circuit simulators such as SPICE to calculate the performance index of standard cells under different PVT nodes as in traditional methods. This avoids the iterative solution caused by calculating the performance index of standard cells under different PVT nodes, greatly reducing the computation time required to evaluate standard cells and significantly improving the speed of obtaining the performance index of standard cells.

[0101] Furthermore, according to the predetermined mapping relationship, the first feature sequence is mapped to the key vector and the value vector respectively, and the second feature sequence is mapped to the query vector. The value vector is weighted according to the similarity between the query vector and the key vector to obtain the fusion vector. In this process, the second feature sequence is the source of the query vector, and the first feature sequence is the source of the key vector and the value vector. This makes the process of obtaining the fusion vector through weighted processing form an asymmetric cross-attention mechanism. Since the first feature sequence is obtained from the spatial geometric information of the standard cell extracted from the layout tensor, which is generated based on the layout data, and the second feature sequence is obtained by encoding the heterogeneous graph data, which is constructed based on the netlist data, the asymmetric cross-attention mechanism formed in this implementation can search and aggregate the layout regions corresponding to the electrical connection relationships in the image information represented by the layout data, such as metal interconnects and via regions, based on the electrical connection relationships represented by the netlist data. This achieves precise alignment between the circuit logic and the physical layout, ensuring that the information carried by the fusion vector has a consistent correspondence between the physical implementation and the circuit logic. This allows the fusion vector to accurately reflect the impact of the circuit structure of the standard cell on its performance and avoids the aforementioned problems of attention divergence and data fusion disorder. It can effectively improve the accuracy of subsequent performance index prediction based on the fusion vector.

[0102] like Figure 6 As shown in the illustration, this application also provides a performance prediction device 600 for a standard chip cell, comprising: The acquisition unit 610 is used to acquire the layout data and netlist data of the standard cell, wherein the netlist data is used to represent the connection relationship of each electronic device in the standard cell.

[0103] The first preprocessing unit 620 is used to extract image features of specific structural layers of standard units based on layout data and generate corresponding layout tensors.

[0104] The second preprocessing unit 630 is used to construct heterogeneous graph data to represent the topology of standard cells based on netlist data.

[0105] Encoding unit 640 is used to extract the spatial geometric information of standard cells based on the layout tensor to obtain the first feature sequence. It then encodes the heterogeneous graph data to obtain the second feature sequence.

[0106] The mapping unit 650 is used to map the first feature sequence into a key vector and a value vector respectively, and to map the second feature sequence into a query vector according to a predetermined mapping relationship.

[0107] The weighted fusion unit 660 is used to weight the value vector based on the similarity between the query vector and the key vector to obtain the fusion vector.

[0108] The prediction unit 670 is used to predict the performance of the standard unit based on the fusion vector and obtain the performance index of the standard unit.

[0109] It should be understood that the performance prediction device 600 provided in this application embodiment is based on the same inventive concept as the aforementioned performance prediction method embodiment and can achieve the same effect. For the specific implementation process, please refer to the description in the aforementioned performance prediction method embodiment, which will not be repeated here.

[0110] Figure 7 This is a schematic diagram of the structure of an electronic device 700 provided in an embodiment of the present invention. The specific embodiments of the present invention do not limit the specific implementation of the electronic device. Figure 7 As shown, the electronic device 700 may include: a processor 702, a communications interface 704, a memory 706, and a communications bus 708.

[0111] in: The processor 702, communication interface 704, and memory 706 communicate with each other via communication bus 708.

[0112] Communication interface 704 is used to communicate with other electronic devices or servers, such as the aforementioned source device.

[0113] The processor 702 is used to execute the computer software 710, specifically to perform the relevant steps in the embodiments of the above performance prediction method.

[0114] Specifically, computer software 710 may include program code, which includes executable instructions, which may be computer operation instructions.

[0115] The processor 702 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The electronic device 700 includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0116] Memory 706 is used to store computer software 710. Memory 706 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0117] The computer software 710 may include one or more executable instructions. Specifically, the computer software 710 may use multiple executable instructions to cause the processor 702 to perform the operation corresponding to the performance prediction method described in any of the foregoing embodiments.

[0118] The specific implementation of each step in computer software 710 can be found in the corresponding descriptions of the steps and units in the above method embodiments, which have corresponding beneficial effects, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0119] This invention also provides a computer storage medium storing a computer program that, when executed by a processor, implements the method described in any of the embodiments of the aforementioned performance prediction methods. The computer storage medium includes, but is not limited to, compact disc read-only memory (CD-ROM), random access memory (RAM), floppy disk, hard disk, or magneto-optical disk.

[0120] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0121] The methods described in the embodiments of this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0122] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0123] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A method for predicting the performance of a standard cell in a chip, comprising: Obtain the layout data of the standard cell and the netlist data of the standard cell, wherein the netlist data is used to represent the connection relationship of each electronic device in the standard cell; Based on the layout data, image features of specific structural layers of the standard unit are extracted to generate corresponding layout tensors; Based on the netlist data, heterogeneous graph data is constructed to represent the topology of the standard unit; Based on the layout tensor, the spatial geometric information of the standard unit is extracted to obtain a first feature sequence; the heterogeneous graph data is encoded to obtain a second feature sequence. According to a predetermined mapping relationship, the first feature sequence is mapped to a key vector and a value vector, respectively, and the second feature sequence is mapped to a query vector; Based on the similarity between the query vector and the key vector, the value vector is weighted to obtain the fusion vector; The performance of the standard unit is predicted based on the fusion vector to obtain the performance index of the standard unit.

2. The method according to claim 1, wherein, The topology represented by the heterogeneous graph data includes first-type nodes, second-type nodes, first-type edges, and second-type edges; the construction of heterogeneous graph data to represent the topology of the standard unit based on the netlist data includes: Based on the netlist data, the electronic devices of the standard unit are identified as first-type nodes; the connection nodes between the electronic devices are identified and the connection nodes are identified as second-type nodes; the connection edges between the first-type nodes and the second-type nodes are identified and the connection edges are identified as first-type edges; and the second-type edges between the connection nodes are identified, wherein the second-type edges are used to indicate that there is a coupling relationship between the multiple connection nodes connected by the second-type edges.

3. The method according to claim 2, wherein, The determination of the existence of a second type of edge between the connected nodes includes: Establish second-type edges between multiple second-type nodes that are connected to the same first-type node.

4. The method according to claim 3, wherein, The process of encoding the heterogeneous graph data to obtain the second feature sequence includes: The heterogeneous graph data is processed by a graph Transformer encoder to obtain a second feature sequence.

5. The method according to claim 4, wherein, The parameters of the graph Transformer encoder include graph mask and structural bias terms. The graph mask is used to limit the calculation range of the attention mechanism of the graph Transformer encoder to node pairs where there is a first type edge or a second type edge between the two nodes included; the structural bias term is used to represent the correspondence between the edge type and the weight adjustment parameter, as the basis for the graph Transformer encoder to determine the attention weight of the node pair.

6. The method according to any one of claims 1-5, wherein, The step of extracting the spatial geometric information of the standard cell based on the layout tensor to obtain the first feature sequence includes: The map tensor is divided into multiple tile tensors; Perform linear projection on the tile tensor to generate a tile vector corresponding to the tile tensor; Based on each of the said tile vectors, an initial feature sequence including each of the said tile vectors is obtained; The initial feature sequence is processed by a visual Transformer encoder to obtain the first feature sequence.

7. The method according to claim 6, wherein, The step of obtaining an initial feature sequence including each of the tile vectors includes: Obtain predetermined category items and distillation items, and concatenate the category items, the distillation items, and each of the tile vectors to obtain the initial feature sequence.

8. The method according to any one of claims 1-5, wherein, The step of extracting image features of specific structural layers of the standard unit based on the layout data and generating corresponding layout tensors includes: Based on the layout data, the pixels occupied by the vias of the specific structural layer are expanded to obtain preprocessed layout data; Based on the preprocessed layout data, image features of the specific structural layer are extracted to generate the corresponding layout tensor.

9. The method according to any one of claims 1-5, wherein, The step of weighting the value vector based on the similarity between the query vector and the key vector to obtain the fusion vector includes: Based on the similarity between the query vector and the key vector, determine the corresponding similarity vector; A weight vector is determined based on the similarity vector to weight the value vector; The value vector is weighted according to the weight vector to obtain the fusion vector.

10. The method according to any one of claims 1-5, wherein, The specific structural layer of the standard unit includes the bottom metal layer, the top metal layer, and the intermediate metal layer between the bottom metal layer and the top metal layer.

11. A performance prediction device for a standard chip cell, comprising: An acquisition unit is used to acquire the layout data of a standard cell and the netlist data of the standard cell, wherein the netlist data is used to represent the connection relationship of each electronic device in the standard cell; The first preprocessing unit is used to extract image features of specific structural layers of the standard unit based on the layout data, and generate corresponding layout tensors; The second preprocessing unit is used to construct heterogeneous graph data representing the topology of the standard unit based on the netlist data. The encoding unit is used to extract the spatial geometric information of the standard unit based on the layout tensor to obtain a first feature sequence; and to encode the heterogeneous graph data to obtain a second feature sequence. The mapping unit is used to map the first feature sequence into a key vector and a value vector respectively, and to map the second feature sequence into a query vector according to a predetermined mapping relationship; The weighted fusion unit is used to weight the value vector according to the similarity between the query vector and the key vector to obtain the fusion vector; The prediction unit is used to predict the performance of the standard unit based on the fusion vector, and obtain the performance index of the standard unit.

12. An electronic device, comprising: The processor, the communication interface, the memory, and the communication bus are provided, and the processor, the communication interface, and the memory communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform an operation corresponding to the method as described in any one of claims 1-10.

13. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any one of claims 1-10.

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