An equivalent modeling method and system for customizing SRAM array behavior of ASIC

Abstract

The application discloses an equivalent modeling method and system for ASIC customized SRAM array behavior. The method comprises the following steps: performing interface analysis on an ASIC customized SRAM macro, and constructing an FPGA behavior equivalent model; dividing an SRAM address space into a plurality of local subarrays, blockizing the SRAM array, reconstructing, and storing into the FPGA behavior equivalent model data; reconstructing a discrete bit level addition chain of the behavior equivalent model data into a vector addition expression, and mapping to a FPGA special carry chain; and performing timing compensation on a local data path or clock branch of the FPGA special carry chain through a FPGA delay chain. The application can reduce fanout and wiring congestion, reduce LUT usage, reduce path delay by more than 50%, and realize synthesis and timing convergence of ASIC SRAM on an FPGA platform without modifying original RTL and software code of the ASIC.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and in particular relates to an equivalent modeling method and system for the behavior of ASIC custom SRAM arrays. Background Technology

[0002] In the application-specific integrated circuit (ASIC) design flow, on-chip static random access memory (SRAM) typically only provides library files, place-and-route files, and black-box netlists, without providing complete register-transfer level source code. This type of memory macro is essentially an analog-assisted digital circuit and cannot be directly recognized and mapped by field-programmable gate array (FPGA) synthesis tools.

[0003] Therefore, the following problems usually arise:

[0004] First, the memory black box cannot be unfolded, leading to synthesis failure, data path loss, and system boot failure.

[0005] Second, the original read / write behavior of application-specific integrated circuit memory is inconsistent with the inherent behavior of field-programmable gate array block memory. For example, there are differences in read-while-write, asynchronous output window, write priority and timing relationship, which leads to abnormal software initialization, CPU crashes and state machine failures.

[0006] Third, there are a large number of address generation, page address offset, column address expansion and control logic around the application-specific integrated circuit (ASIC) memory. Its original implementation is usually based on the gate-level structure optimized by the ASIC process. In the field-programmable gate array (FPGA), it will form serious wiring congestion, high fan-out network and deep combination path, which will lead to a large number of setup time violations and hold time violations.

[0007] Existing technologies typically employ several methods for replacement: first, directly replacing the application-specific integrated circuit (ASIC) memory with a field-programmable gate array (FPGA) block memory; second, using a two-dimensional register array for behavioral modeling; and third, using a black-box bypass method to skip memory macros. However, all of these methods have significant drawbacks. Direct block memory replacement alters the timing and access behavior of the original ASIC memory, failing to guarantee software and system-level logic compatibility. Two-dimensional register arrays generate extremely high lookup table overhead, address fan-out, and routing delays in large-scale memory scenarios, making timing closure difficult. Black-box bypass, on the other hand, cannot perform real-world functional verification.

[0008] To address the shortcomings of existing technologies, there is a need for a method, system, and FPGA prototype verification platform for equivalent modeling of ASIC-customized SRAM array behavior in FPGA synthesis tools. Summary of the Invention

[0009] This invention discloses an equivalent modeling method for the behavior of ASIC custom SRAM arrays.

[0010] include:

[0011] Interface parsing of ASIC-customized SRAM macros and construction of FPGA behavioral equivalent models;

[0012] The SRAM address space is divided into multiple local subarrays, the SRAM array is segmented and reconstructed, and the FPGA behavioral equivalent model data is stored in it.

[0013] The discrete bit-level addition chain of the behavioral equivalent model data is reconstructed into a vector addition expression and mapped to the FPGA-specific carry chain;

[0014] Timing compensation is performed on the local data path or clock branch of the FPGA dedicated carry chain through the FPGA delay chain.

[0015] Furthermore, the timing compensation is applied to local data paths or local clock branches.

[0016] Preferably, the FPGA behavioral equivalent model includes the top-level port definition, address width, data width, and control timing relationship of the ASIC SRAM.

[0017] Furthermore, the identified objects of the discrete bit-level adder chain include bit-level adder chains composed of cascaded XOR gates, AND gates, OR gates and full adders.

[0018] Furthermore, the FPGA delay chain includes a multi-level buffer unit cascade structure, and each buffer unit output is provided with a selection port.

[0019] On the other hand, an equivalent modeling system for ASIC-customized SRAM behavior is provided, including:

[0020] The interface parsing module extracts the netlist information of the ASIC SRAM macros and outputs the equivalent model of FPGA behavior.

[0021] The array reconstruction module divides the SRAM address space into multiple local sub-arrays, outputs a block-based storage structure, and stores the FPGA behavioral equivalent model data.

[0022] The address logic vectorization module converts the discrete bit-level addition chain of the behavioral equivalent data into a vector addition expression, which is then mapped to the FPGA carry chain.

[0023] Furthermore, the array reconstruction module selects the storage area through the high-order address and uses the low-order address for local addressing.

[0024] Furthermore, the address logic vectorization module identifies XOR, AND, OR, and full adder chain structures, and outputs vector addition expressions.

[0025] Preferably, the timing compensation module includes an FPGA delay chain and a local clock branch buffer.

[0026] On the other hand, an FPGA prototyping platform is provided, including the aforementioned ASIC-customized SRAM behavior equivalent modeling system for FPGA synthesis tools.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. By parsing the interface of ASIC SRAM macros, an equivalent model of FPGA behavior is constructed, including its port definition, address width, data width, and control timing relationship. This enables FPGA synthesis tools to recognize ASIC SRAM macros that were originally unmappable, solving the synthesis failure problem. The upper-layer RTL, CPU software, and system bus can run directly without modification.

[0029] 2. Divide the SRAM address space into multiple local subarrays, select the bank by high-order address and local addressing by low-order address, transform global access into local access, reduce fan-out and routing congestion, and reduce LUT utilization.

[0030] 3. Identify discrete bit-level addition chains (including XOR, AND, OR and full adder cascade chains), reconstruct them into vector addition expressions and map them to FPGA-specific carry chains, reducing the number of logic levels in the critical path from more than twenty to single digits, and reducing path latency by more than 50%.

[0031] 4. Timing compensation is performed on local data paths or clock branches by using an FPGA delay chain containing multi-level buffer units and selection ports to restore the original timing window relationship and solve the problems of data arriving early and holding time violations.

[0032] 5. An FPGA prototyping platform containing the above modules enables the synthesis and timing closure of ASIC SRAM on an FPGA platform without modifying the original ASIC RTL and software code, making it particularly suitable for ASIC prototyping scenarios. Attached Figure Description

[0033] Figure 1 This is a flowchart illustrating an equivalent modeling method for the behavior of a custom SRAM array in an embodiment of this application.

[0034] Figure 2 This is a schematic diagram of the application hierarchy of a discrete bit-level addition chain provided in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the application hierarchy of an FPGA delay chain provided in an embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the structure of an equivalent modeling system for the behavior of a custom SRAM array in ASIC provided in one embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and technical effects of the embodiments of the present invention clearer, the technical solutions of the ink cartridge of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely preferred embodiments of the present invention, and not all embodiments. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the protection scope of the present invention.

[0038] Please see Figure 1 , Figure 1 This is a flowchart illustrating an equivalent modeling method for the behavior of a custom SRAM array in an ASIC according to an embodiment of this application, including the following steps S1 to S4.

[0039] S1: Perform interface parsing on the ASIC custom SRAM macro and construct an equivalent model of FPGA behavior;

[0040] For example, an ASIC chip may contain a custom SRAM with a depth of 4096 and a data width of 32 bits. Its interface includes address ports Addr[11:0], data input ports 401 (Din[31:0]), data output ports 404 (Dout[31:0]), write enable WEn, output enable OEn, chip select CSn, clock CLK, and byte enable ByteEn. This invention first performs interface parsing on the SRAM macro, extracting the aforementioned port information one by one, and constructing a behavioral equivalent model recognizable by the FPGA. This model maintains the same port names, bit widths, and timing relationships as the original ASIC SRAM at the top level, such as sampling on the rising edge of the clock, writing data when write enable is active, and reading data when output enable is active. In this way, the upper-level RTL module, CPU bus, and software code originally connected to the SRAM can be directly connected to the behavioral model in the FPGA and run without any modification.

[0041] S2: Divide the SRAM address space into multiple local subarrays, block the SRAM array and reconstruct it;

[0042] For the SRAM array with a depth of 4096, if a two-dimensional reg array reg[31:0] mem[0:4095] is directly implemented in the FPGA, a high fan-out global decoding network will be generated, with the address signal fan-out reaching as high as 4096 paths, leading to severe wiring congestion. This invention divides the address space into 8 local banks, each managing 512 address units. Specifically, the high 3 bits of the address (Addr[11:9]) are used to select the bank, and the low 9 bits (Addr[8:0]) are used for addressing within the bank. For example, when the address is 0x0A3F, the high 3 bits are 010, selecting bank 2, and the low 9 bits are 0x03F, searching for the 63rd unit within that bank. Through this block-based reconstruction, a large-scale global access is broken down into multiple small-scale local accesses, with each bank's decoding fan-out being only 512 paths, significantly reducing the signal load and effectively alleviating the wiring congestion problem.

[0043] S3: Identify discrete bit-level addition chains in the peripheral address logic of ASIC SRAM, reconstruct them into vector addition expressions, and map them to FPGA-specific carry chains;

[0044] SRAM peripherals typically contain logic for address incrementing and page address offsets. For example, an address accumulator might consist of multiple cascaded XOR gates, AND gates, OR gates, and full adders to achieve the function `addr_next = addr_current + offset`. In ASIC gate-level netlists, this logic is expanded into discrete bit-level gate circuits. FPGA synthesis tools cannot recognize that it is essentially an adder and can only synthesize it into a cascaded LUT structure, forming a combinational path of more than 20 levels. This invention automatically identifies the bit-level addition chain in these discrete gate-level structures and reconstructs it into a vector addition expression in the form `sum = addr_base + addr_offset`. After the FPGA synthesis tool recognizes this vector addition expression, it automatically infers and maps it to a high-speed dedicated carry chain inside the FPGA. Since the carry chain is a dedicated high-speed path in the FPGA, its latency is much lower than that of ordinary LUT cascading, thereby reducing the number of logic levels in the critical address path from more than 20 levels to single digits, and reducing path latency by more than 50%.

[0045] S4: Timing compensation for local data paths or clock branches is performed through the FPGA delay chain.

[0046] The read data output of ASIC custom SRAM typically has a certain delay, for example, the data is output stably after 2ns following the rising edge of the clock, while the output delay of FPGA internal memory may only be 0.5ns. This difference can cause subsequent logic to sample data that arrives too early in the FPGA, resulting in a hold-time violation. To solve this problem, this invention inserts an FPGA delay chain into the data output path. This delay chain consists of multiple cascaded buffer units, and each buffer unit has a selection port at its output, allowing the selection of the delay level as needed. For example, by configuring the selection port, the data output path delay can be increased by 1.5ns, matching the data arrival time with the original ASIC SRAM's 2ns output window. In addition, for paths with local clock skew mismatches, this invention also inserts buffer units on the local clock branches for fine-tuning. These timing compensations only apply to local paths and do not modify the global clock structure, thus not disrupting the original system-level timing relationships of the ASIC.

[0047] Please see Figure 2 , Figure 2 This is a schematic diagram of the application hierarchy of a discrete bit-level addition chain provided in an embodiment of this application.

[0048] The discrete bit-level adder chain 100 includes XOR gates, AND gates, OR gates, and a full adder cascaded 200.

[0049] Generally,

[0050] The XOR gate calculates the half-sum of each bit;

[0051] The AND gate generates the carry for each bit;

[0052] OR gate merge carry propagation condition;

[0053] A full adder cascaded with 200 bits will pass the carry from the lower bit to the higher bit.

[0054] These gate circuits are connected in series bit by bit to form a bit-level addition chain.

[0055] From the netlist, it looks like just a bunch of XOR, AND, OR gates and full adders cascaded together with each other.

[0056] Existing FPGA synthesis tools cannot recognize that this is a complete adder, and can only synthesize it into a LUT cascade structure, resulting in long paths and large delays.

[0057] The address logic vectorization module in this invention automatically scans the ASIC netlist, identifies this "XOR gate + AND gate + OR gate + full adder cascade" topology, and determines that it is essentially a discrete bit-level addition chain.

[0058] Subsequently, this set of discrete gate circuits is reconstructed into a vector addition expression (e.g., next_addr = current_addr + 4) and directly mapped to the FPGA's dedicated carry chain 300, thereby significantly reducing path delay.

[0059] Specifically,

[0060] The XOR gate is responsible for calculating the "half-sum" between each bit of the current address and the corresponding bit of the constant 4. For example, performing an XOR operation between the 0th bit of the address and the 0th bit of 4 yields the first bit of the sum.

[0061] The AND gate is used to calculate whether a carry is generated after adding each bit. For example, if the 0th bit of the address and the 0th bit of 4 are both 1, the AND gate outputs 1, indicating that a carry is generated.

[0062] The OR gate is responsible for combining multiple carry conditions. For example, a bit may receive a carry from multiple paths. The OR gate summarizes these conditions and decides whether to pass the carry to the higher bits.

[0063] The full adder cascade 200 connects the above XOR, AND, and OR gates bit by bit. The carry generated by the lower bit is passed to the higher bit, and the calculation of the higher bit depends on the carry result of the lower bit.

[0064] Next, the technical solution of the present invention will scan the ASIC netlist, identify the above-mentioned topology of "XOR gate + AND gate + OR gate + full adder cascade", and determine that this circuit is essentially an addition operation.

[0065] After identification, these scattered gate circuits are reconstructed into a concise vector addition expression.

[0066] For example:

[0067] next_addr = current_addr + 4

[0068] This vector addition expression is directly mapped to the dedicated carry chain 300 inside the FPGA.

[0069] Please see Figure 3 , Figure 3 This is a schematic diagram of the application hierarchy of an FPGA delay chain provided in an embodiment of this application.

[0070] The FPGA delay chain 400 consists of N buffer units (buffer unit 1 to buffer unit N) connected in series. Data signals enter from the left input terminal and pass through each buffer unit sequentially. The output of each buffer unit is connected to a selection port (selection port 1 to selection port N), and all selection ports are aggregated to the configuration selection module 403. The configuration selection module 403 receives an external configuration signal 402, selects the corresponding selection port based on the value of the configuration signal, and transmits the data signal on the selected port to the output terminal.

[0071] Specifically, the buffer serves two purposes: first, to amplify the input signal to drive the output, ensuring that the signal strength does not attenuate; and second, to artificially introduce a controllable small delay in the signal propagation path.

[0072] More specifically, each buffer unit provides a delay of 0.1 nanoseconds. Cascading 10 levels results in 1 nanosecond, 20 levels in 2 nanoseconds, 50 levels in 5 nanoseconds, and so on. The delay time is strictly proportional to the number of cascaded levels: the more levels, the greater the total delay.

[0073] Each time a signal passes through a buffer unit, its propagation is delayed by a fixed small time unit. The more stages it passes through, the longer the total delay becomes. The advantage of this cascaded structure is that the delay accumulation is linear and predictable, and the exact amount of delay contributed by each stage can be known.

[0074] Furthermore, each buffer unit output is equipped with a selection port.

[0075] Each buffer unit has a selection port at its output. Its function is to bring the output signal of that buffer unit to the common bus.

[0076] More specifically, each selection port is an input of a multiplexer. The outputs of all selection ports converge onto a common selection bus, which ultimately connects to a configuration selection module 403. The configuration selection module 403 is responsible for determining, based on external instructions, which selection port to enable and from which stage to output signals.

[0077] The more buffer stages a signal passes through in the delay chain, the longer the delay time. The selected port determines which stage the signal is output from, thus determining the total delay.

[0078] Furthermore, the port selection is controlled by external configuration signal 402.

[0079] This control system can operate in two modes: one is fixed during power-on initialization, suitable for scenarios with defined delay requirements; the other is dynamically adjusted during system operation, suitable for scenarios requiring real-time compensation based on operating conditions (such as voltage and temperature changes). This design offers two significant advantages:

[0080] First, the granularity is adjustable. Each buffer unit provides a small step delay, such as 0.1 nanoseconds, 0.15 nanoseconds, or 0.2 nanoseconds, the specific value of which can be preset according to actual process and timing requirements. By selecting different levels, any integer multiple of the delay from a single step size to the maximum total delay can be achieved. For example, with a step size of 0.1 nanoseconds, selecting level 3 yields 0.3 nanoseconds, selecting level 8 yields 0.8 nanoseconds, and selecting level 15 yields 1.5 nanoseconds. This granularity adjustment capability allows for very fine-grained delay compensation, meeting the various timing window requirements of different ASIC SRAMs.

[0081] Secondly, the range is adjustable. The total number of cascaded stages determines the maximum compensable delay range. If an ASIC SRAM has a very large output window and needs to compensate for a 5-nanosecond delay difference, but the existing delay chain only has 20 stages, each with a delay of 0.1 nanoseconds (maximum 2 nanoseconds), then simply increasing the number of cascaded buffer units, for example, expanding to 50 stages, will reduce the maximum delay to 5 nanoseconds. This expansion does not require changing the circuit structure; it only requires adding more cascaded stages in the design, which is very convenient. Therefore, this delay chain scheme has good scalability and can adapt to the needs of different projects.

[0082] Please see Figure 4 This application also provides an equivalent modeling system for the behavior of ASIC-customized SRAM arrays.

[0083] Figure 4 This is a schematic diagram of the structure of an equivalent modeling system for the behavior of a custom SRAM in an ASIC provided in one embodiment of this application.

[0084] The equivalent modeling system 500 for the behavior of the ASIC-customized SRAM includes: an interface parsing module 501, an array reconstruction module 502, an address logic vectorization module 503, and a timing compensation module 504.

[0085] The interface parsing module 501 automatically scans and extracts the hardware description language netlist or physical library file of the original ASIC SRAM macro, and extracts key information such as address port, data port, write enable, output enable, chip select, clock and byte enable.

[0086] In this embodiment, the module extracts the address ports Addr[11:0], data input ports Din[31:0], data output ports Dout[31:0], write enable WEn, output enable OEn, chip select CSn, clock CLK, and byte enable ByteEn for a 4096-bit, 32-bit ASIC SRAM. Based on the extracted information, the interface parsing module 501 generates an equivalent FPGA behavior model that includes the aforementioned top-level port definitions, a 12-bit address width, a 32-bit data width, and strictly controlled timing relationships.

[0087] This equivalent model serves as the processing benchmark for subsequent modules, ensuring seamless integration between the upper-layer RTL code and the system bus.

[0088] The array reconstruction module 502 is used to receive the behavioral equivalent model output by the interface parsing module 501 and to reconstruct the original global large-capacity storage array in blocks.

[0089] In this embodiment, the array reconstruction module 502 decouples the 4096 address spaces corresponding to the 12-bit address lines (Addr[11:0]). This module internally includes a high-order address decoding unit and multiple low-order local addressing units. Specifically, the array reconstruction module 502 generates a chip select control signal using the high-order address (Addr[11:9]) to select one of the eight local memory banks (Bank 0 to Bank 7).

[0090] Simultaneously, the low-order address (Addr[8:0]) is directly routed to each local memory cell for 9-bit local addressing. Through this segmented memory structure, the global 4096 high fan-out network is transformed into 512 local access paths, thereby outputting the segmented memory structure to the FPGA synthesis tool.

[0091] The address logic vectorization module 503 is used to scan the netlist of peripheral circuits surrounding the ASIC SRAM. This module integrates a gate-level topology recognition operator specifically designed to identify discrete bit-level addition chains 100 composed of XOR gates, AND gates, OR gates, and a full adder cascaded 200. After identifying this specific topology, the expression reconstruction unit within the module eliminates the discrete gate-level connections in the original netlist and reconstructs it into a vector addition expression at the high-level hardware description language level, such as $next_addr = current_addr + 4$.

[0092] Finally, the module outputs the vector addition expression to the FPGA synthesis tool, which directly maps it to the FPGA-specific high-speed carry chain 300 (such as the CARRY4 / CARRY8 cell of Xilinx FPGA or the CarryChain structure of Intel FPGA), thereby eliminating the deep combinational logic delay caused by conventional LUT cascading.

[0093] The timing compensation module 504 includes an FPGA delay chain 400 and a local clock branch buffer, which is specifically used to adjust the timing window of the local path. The FPGA delay chain 400 adopts a cascaded structure of multi-level buffer units (buffer unit 1 to buffer unit N) connected in series.

[0094] In this embodiment, taking a fixed line delay of 0.1ns per buffer unit as an example, the timing compensation module 504 determines, based on the calculation results of the static timing analysis (STA) report, that there is a 1.5ns output data delay difference between the FPGA internal memory and the original ASIC custom SRAM.

[0095] The timing compensation module 504 sends a corresponding external configuration signal 402 to the delay chain through the configuration selection module 403, selecting the selection port corresponding to the Nth level buffer unit. At this time, the data signal entering from the data input end passes through the Nth level buffer unit and is led out to the common selection bus through this selection port, thereby accurately introducing a 1.5ns timing compensation on the local data path, so that the data arrival time at the output end is perfectly matched with the original ASIC SRAM's 2ns read output window, eliminating hold time violations.

[0096] Meanwhile, for paths with abnormal clock skew, this module uses its internal local clock branch buffer to drive and fine-tune the local clock branches, ensuring the convergence of local timing relationships.

[0097] This system 500 can be deployed in an FPGA prototyping platform, which fully integrates the aforementioned ASIC custom SRAM behavioral equivalent modeling system 500. During the prototyping phase, this platform can automatically convert ASIC designs containing custom SRAM into equivalent behavioral netlists that are user-friendly for FPGA synthesis tools without modifying any of the original ASIC top-level RTL or embedded software code. While ensuring complete consistency of logic functionality, this significantly improves the operating frequency and routing convergence speed of the prototyping platform.

[0098] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An equivalent modeling method for the behavior of ASIC custom SRAM arrays, characterized in that: Interface parsing of ASIC-customized SRAM macros and construction of FPGA behavioral equivalent models; The SRAM address space is divided into multiple local subarrays, the SRAM array is segmented and reconstructed, and the FPGA behavioral equivalent model data is stored in it. The discrete bit-level addition chain of the behavioral equivalent model data is reconstructed into a vector addition expression and mapped to the FPGA-specific carry chain; Timing compensation is performed on the local data path or clock branch of the FPGA-dedicated carry chain using the FPGA delay chain.

2. The method according to claim 1, characterized in that: The timing compensation is applied to local data paths or local clock branches.

3. The method according to claim 1, characterized in that: The FPGA behavioral equivalent model includes the top-level port definition, address width, data width, and control timing relationship of the ASIC SRAM.

4. The method according to claim 1, characterized in that: The discrete bit-level adder chain identification objects include bit-level adder chains composed of cascaded XOR gates, AND gates, OR gates and full adders.

5. The method according to claim 1, characterized in that: The FPGA delay chain includes a multi-level cascaded buffer unit structure, and each level of buffer unit has a selection port at its output.

6. An equivalent modeling system for the behavior of ASIC-customized SRAM, characterized in that, include: The interface parsing module extracts the netlist information of the ASIC SRAM macros and outputs the equivalent model of FPGA behavior. The array reconstruction module divides the SRAM address space into multiple local sub-arrays, outputs a block-based storage structure, and stores the FPGA behavioral equivalent model data. The address logic vectorization module converts the discrete bit-level addition chain of the behavioral equivalent data into a vector addition expression, which is then mapped to the FPGA carry chain. The timing compensation module adjusts the local path timing of the FPGA-dedicated carry chain through the FPGA delay chain.

7. The system according to claim 6, characterized in that: The array reconstruction module selects the storage area using the high-order address and locates it using the low-order address.

8. The system according to claim 6, characterized in that: The address logic vectorization module recognizes XOR, AND, OR and full adder chain structures, and outputs vector addition expressions.

9. The system according to claim 6, characterized in that: The timing compensation module includes an FPGA delay chain and a local clock branch buffer.

10. An FPGA prototype verification platform, characterized in that: An ASIC-customized SRAM behavior equivalent modeling system comprising any one of claims 6 to 9.

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