A power system topology abstraction and SPICE netlist automatic generation method and system

Abstract

The application discloses a kind of power system topology abstraction and SPICE netlist automatic generation method and system, the method includes: obtaining the hierarchical physical wiring model of secondary circuit;The model data is loaded to memory, and group information mapping table and terminal identification mapping table are constructed;Based on the mapping table, the terminal, external connection line and internal connection graph are carried out multi-layer progressive topology synthesis according to fixed order, and circuit edge is added to unified node edge graph intermediate representation layer by layer, wherein each terminal is modeled as two-level structure of external node and internal node, and terminal resistance edge is connected in series between two levels;The node edge graph intermediate representation is traversed, and the node associated with the ground element edge, the direct current source element edge and the alternating current source element edge is taken as the seed node to carry out connectivity search.The application realizes the full-process automation from physical wiring design to SPICE netlist generation by establishing the formal mapping from physical wiring semantics to circuit topology semantics.

Description

Technical Field

[0001] This invention belongs to the field of power system automation technology, specifically relating to a method and system for power system topology abstraction and automatic SPICE netlist generation. Background Technology

[0002] The secondary circuit of a substation is used to realize the electrical connection and signal transmission between equipment such as relay protection devices, measurement and control devices, intelligent terminals, merging units, and terminal blocks. The correctness of its connection, circuit impedance, and secondary load parameters directly affect the reliability of relay protection operation, measurement accuracy, and the operational safety of the substation automation system. Therefore, electrical simulation analysis is usually required during the design and verification phase of the secondary circuit.

[0003] SPICE simulation tools can build computable circuit models based on electrical nodes, branch components, and component parameters, and can be used for electrical simulation of secondary circuits. However, in the current technology, converting secondary circuit design data into SPICE simulation models mainly relies on manual work. Common methods include: manually placing components and connecting nodes using a general SPICE schematic editor; manually extracting terminals, cables, and connection relationships from electrical CAD drawings before building the simulation model; or having engineers directly write SPICE netlists manually.

[0004] The above methods all have shortcomings. For example, general-purpose SPICE schematic editors use circuit components as the basic operation objects, requiring engineers to manually translate the physical wiring relationships in the design drawings into circuit components and node connections one by one. Electrical CAD software is mainly geared towards engineering drawing needs; its data model is centered on graphics and annotations, not designed to generate calculable circuit topologies. Manually writing SPICE netlists requires engineers to master both secondary loop design rules and SPICE syntax, which is inefficient and prone to connection errors when dealing with actual projects containing a large number of devices and terminals.

[0005] The root cause of the above problems lies in the semantic misalignment between the design and simulation of secondary circuits. Engineers operate on "physical wiring," focusing on the actual connections between equipment, terminals, and cables; while existing simulation tools operate on "circuit components," focusing on the electrical properties of nodes, branches, and parts. The gap between these two semantic systems is entirely bridged manually, making the design-to-simulation transition a bottleneck in efficiency and a source of quality risk in the entire engineering process.

[0006] Therefore, to address the aforementioned technical issues, it is necessary to provide a method and system for power system topology abstraction and automatic SPICE netlist generation. Summary of the Invention

[0007] The purpose of this invention is to provide a method and system for power system topology abstraction and automatic SPICE netlist generation, which can solve the technical problems mentioned in the background art.

[0008] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: A method for power system topology abstraction and automatic SPICE netlist generation includes: S1, obtaining a hierarchical physical wiring model of secondary circuits; S2, loading the data of the hierarchical physical wiring model into memory; and S3, constructing the group information mapping table and terminal identifier mapping table based on the group information mapping table and terminal identifier mapping table; S3, performing multi-layer progressive topology synthesis on the terminals, external connections, and internal connections in the hierarchical physical wiring model in a fixed order based on the group information mapping table and terminal identifier mapping table, adding circuit edges layer by layer to a unified node edge graph intermediate representation to generate a unified node edge graph intermediate representation; wherein, in the multi-layer progressive topology synthesis, each terminal is modeled as... The system has a two-level structure of external nodes and internal nodes, with terminal resistors connected in series between the external and internal nodes; S4, iterate through the unified node-edge graph representation, using nodes associated with grounding element edges as first-type seed nodes to perform connectivity search to obtain a first edge set, using nodes associated with DC source element edges as second-type seed nodes to perform connectivity search to obtain a second edge set, and using nodes associated with AC source element edges as third-type seed nodes to perform connectivity search to obtain a third edge set. The intersection of the first edge set and the second edge set is taken as the DC subgraph, and the intersection of the first edge set and the third edge set is taken as the AC subgraph; S5, call the corresponding SPICE element processor to generate netlist statements for the edges in the DC subgraph and AC subgraph respectively, and output the DC netlist and AC netlist.

[0009] In one or more embodiments of the present invention, in S3, the order of the multi-layer progressive topology synthesis is as follows: Terminal self-resistance layer, creating the series resistance edge for terminals with non-zero contact resistance, the series resistance edge being connected between external nodes and internal nodes; External connection line layer, converting the inter-device connection line into a resistance edge connecting the external node of the source terminal and the external node of the target terminal; Dual-terminal control sheet layer, for dual terminals with external connections on both sides and not marked as disconnected, creating an electrical connection edge between the left and right internal nodes of the dual terminals; Connecting sheet layer, creating a short-circuit edge between the internal nodes of consecutive adjacent terminals on the same side of the same group; Internal connection layer, parsing the internal connection diagram data of the device model group, the internal connection diagram data being expressed in a graph data structure and containing node declarations and connection edge declarations, merging electrically equivalent connection ports through an electrically equivalent port merging algorithm, mapping the edges formed by internal circuit elements to the internal nodes of the corresponding terminals, realizing the stitching of the internal sub-circuits of the device with the external wiring network.

[0010] In one or more embodiments of the present invention, when the contact resistance of the terminal is zero, a series resistance edge connecting the external node and the internal node is not created, and the external node and the internal node are treated as the same electrical node and replaced during subsequent topology synthesis.

[0011] In one or more embodiments of the present invention, the internal connection graph data adopts JSON format and includes a node array and a connection array; each node in the node array includes at least a unique identifier, a component type name, and a configuration parameter dictionary; each connection edge in the connection array is used to specify the port type of the outgoing node and the port type of the incoming node; the electrical equivalent port merging algorithm is a disjoint-set data structure algorithm, which is used to merge the ports of components that are in an equipotential relationship through wire connections into the same electrical node.

[0012] In one or more embodiments of the present invention, the node types in the internal connection diagram data include at least DC voltage source, AC voltage source, DC current source, AC current source, resistor, switch, ground, left terminal interface, and right terminal interface; wherein, the nodes of the left terminal interface and right terminal interface types serve as interface nodes between the internal sub-circuit of the device and the external terminal, and are automatically mapped to the internal nodes of the corresponding terminals to realize the stitching between the internal sub-circuit of the device and the unified node edge diagram intermediate representation.

[0013] In one or more embodiments of the present invention, the connectivity search in S4 is a breadth-first search; the breadth-first search includes: constructing an undirected adjacency list based on the node names at both ends of each circuit edge in the unified node edge graph intermediate representation; using the nodes associated with the ground element edge, DC source element edge and AC source element edge as seed nodes respectively; and propagating access markers along the associated edges in the undirected adjacency list to obtain the first edge set, the second edge set and the third edge set respectively.

[0014] In one or more embodiments of the present invention, the SPICE component processor in S5 includes multiple policy processors corresponding to component types; each policy processor has a unified verification interface and a netlist generation interface; when generating netlist statements, the corresponding policy processor is selected from the processor registry according to the component type name of the circuit edge in the unified node edge graph intermediate representation, and the policy processor verifies the component configuration parameters of the circuit edge and generates netlist statements.

[0015] In one or more embodiments of the present invention, before generating the netlist statement in S5, the method further includes: traversing the circuit edges with path binding information in the intermediate representation of the unified node edge graph; when the path binding information is an input binding, obtaining the corresponding real-time excitation value from the external data system, and replacing the placeholder parameter value in the component configuration corresponding to the circuit edge with the real-time excitation value; when a single SPICE component has multiple input binding fields, determining the configuration parameter field corresponding to each input binding field according to the field mapping rule corresponding to the component type, so as to support AC source components to bind amplitude paths and phase paths simultaneously; when the path binding information is an output binding, after the simulation calculation is completed, extracting the calculated value corresponding to the output binding from the simulation results, and writing the calculated value back to the external data system.

[0016] In one or more embodiments of the present invention, the method further includes: polling the change status of external input values ​​at fixed intervals via an independent thread; when a change in external input values ​​is detected, automatically triggering the following steps: re-traversing the circuit edges with input bindings in the unified node edge graph intermediate representation, obtaining the changed real-time excitation values ​​from the external data system and replacing the placeholder parameter values ​​in the corresponding component configuration; re-executing steps S4 and S5 to generate new DC netlists and AC netlists; for circuit edges with output bindings, extracting calculated values ​​from the new simulation results and writing them back to the external data system.

[0017] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: A power system topology abstraction and SPICE netlist automatic generation system is provided for executing the above-mentioned method. The system includes: a GUI client module for providing device model editing, connection relationship visualization, and human-computer interaction management interface; a simulation server module including the ngspice simulation engine, netlist export service, automatic monitoring service, and communication service; and a data management module for storing hierarchical physical wiring models of secondary circuits, device model groups, terminal information, external connection lines, internal connection diagram data, and path binding information. The simulation server module converts the hierarchical physical wiring model into a unified node-edge graph intermediate representation and generates DC and AC netlists based on this unified node-edge graph intermediate representation. The simulation server module also includes a working condition management service for establishing database file snapshots for different simulation working conditions. The database file snapshots include a basic database file and a temporary database file. During working condition switching, the temporary database file is generated or restored through file-level copying and the simulation recalculation is automatically triggered.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: by establishing a formal mapping method from physical wiring semantics to circuit topology semantics, the physical wiring model, in which engineers operate on devices, terminals, external connection lines, and internal connection diagrams, is automatically converted into a unified node-edge graph intermediate representation composed of nodes and edges. Then, through connectivity search, the DC subgraph and AC subgraph are automatically separated and a SPICE netlist is generated. This solves the problem that the design-simulation conversion between secondary circuit design and simulation is completely dependent on manual work due to the misalignment of semantic levels. It enables secondary circuit engineers to work at an abstraction level consistent with the design drawings, realizing full automation from physical wiring design to SPICE simulation netlist generation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a method for power system topology abstraction and automatic SPICE netlist generation in one embodiment of the present invention; Figure 2 This is a schematic diagram of a five-layer progressive topology synthesis in one embodiment of the present invention; Figure 3 This is a schematic diagram of AC / DC graph decomposition driven by connectivity in one embodiment of the present invention; Figure 4This is an architecture diagram of a power system topology abstraction and SPICE netlist automatic generation system according to an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0022] like Figures 1-3 As shown, an embodiment of the present invention provides a method for power system topology abstraction and automatic SPICE netlist generation, which automatically converts the physical wiring model in secondary circuit design into DC and AC netlists that can be used for SPICE simulation. Specific steps include: S1. Obtain the hierarchical physical wiring model of the secondary circuit. This hierarchical physical wiring model can be stored in a relational database, embedded database, JSON file, engineering design file, or other structured data source.

[0023] A hierarchical physical wiring model contains at least four levels of entities: devices, model groups, terminals, and external connection lines. The device table records information such as device name, device type, assigned bay, and installation location. The model group table records information about internal components, functional units, or terminal groups. The terminal table records terminal index, side markings, contact resistance, assigned model group, and terminal functional attributes. The external connection line table records information such as source terminal path, target terminal path, cable number, conductor number, cable length, cable unit resistance, and connection status. Additionally, an internal connection diagram may be included to record the circuit diagram data within the device model group.

[0024] Terminals are key entities in the physical wiring model. Each terminal is globally uniquely identified through a path string. This path string preferably uses the format "device name + group name: index number [side identifier]", for example, "PR01-CPU:5[L]" indicates the left side of terminal number 5 in the CPU model group of device PR01, and "PR01-CPU:5[R]" indicates the right side of the same terminal. By combining the device name, group name, index number, and side identifier into a single string, ambiguity caused by duplicate terminal numbers across different cabinets, devices, or plug-ins in large substation projects can be avoided.

[0025] In this embodiment, the database contains six core tables with the following entity relationships: Device and ModelGroup have a one-to-many relationship; ModelGroup and Terminal have a one-to-many relationship; ModelGroup is also associated with PinRangeConnection and ModelPrivateConnect; TerminalConnection uses two Terminals as endpoints and records the source terminal ID, target terminal ID, side profile, core resistance, material, and color; ModelPrivateConnect stores complete internal circuit diagram data in JSON text fields. All relationships use foreign key constraints and cascading deletes. This hierarchical organization ensures the data structure aligns with the cognitive hierarchy in secondary circuit engineering drawings, allowing engineers to directly match data entry with actual devices and terminals.

[0026] S2. Load the data of the hierarchical physical wiring model into memory and construct the group information mapping table and the terminal identification mapping table.

[0027] The grouping information mapping table is implemented using a hash table. The key is a combination of device identifier and model group identifier, and the values ​​are the terminal set, internal connection diagram, and terminal arrangement information under that model group. The terminal identifier mapping table uses a hash table with the terminal path string as the key, and the values ​​are pointers to terminal objects or terminal structures, including attributes such as the terminal's device, model group, index number, side identifier, contact resistance, whether it is disconnected, and whether it participates in splicing. The purpose of using a memory mapping table is to convert the numerous path lookup operations in the subsequent topology synthesis process from database access to memory queries. For projects containing thousands of terminals and tens of thousands of connection records, this significantly reduces the latency caused by repeated database queries.

[0028] S3. Based on the grouping information mapping table and the terminal identification mapping table, perform multi-layer progressive topology synthesis on the terminals, external connection lines and internal connection diagrams in the hierarchical physical wiring model in a fixed order, and add circuit edges to the unified node edge diagram intermediate representation layer by layer to generate a unified node edge diagram intermediate representation.

[0029] The multi-layer progressive topology synthesis is performed in the following order: terminal resistance layer, external connection line layer, dual-terminal control plate layer, interconnection layer, and internal connection layer. Progressive topology synthesis means that instead of mixing all connections at once, it processes them layer by layer in a fixed order. Five different data sources are used: terminal contact resistance from the terminal table, external cables from the external connection line table, dual-terminal disconnect status from the terminal table, interconnection range from the interconnection table, and the JSON internal circuit diagram from the internal connection diagram. Each of the five layers is processed independently, and the output is a node-edge structure, ultimately converging into three core tables shown in the middle of the diagram: the edge table stores the electrical connection topology, the type table distinguishes between pure connection edges and SPICE component edges, and the configuration table stores component parameters.

[0030] The principle behind this design is that although different physical connection forms are represented differently on engineering drawings, they can all ultimately be abstracted into a single circuit edge between two electrical nodes. By processing various different connection relationships in layers, each layer can be responsible for only one specific physical semantic transformation, which reduces algorithm complexity and facilitates the addition of new connection forms in the future.

[0031] In multi-layer progressive topology synthesis, each terminal is modeled as a two-level structure consisting of an external node and an internal node, with a terminal resistor connected in series between the external and internal nodes. The external node faces the external wiring network, while the internal node faces the internal circuitry of the device. The external node corresponding to the terminal path “PR01-CPU:5[L]” can be named “PR01-CPU:5[L]”, and the internal node can be named “PR01-CPU:5[L]_in”. This two-level structure is key to achieving seamless splicing of multi-layer graphs.

[0032] The unified node-edge graph intermediate representation includes a set of node names, a set of edges, an edge type mapping table, and an edge parameter mapping table. Each edge includes at least an edge identifier, a left-end node name, a right-end node name, a component type, component parameters, and binding information. Component types can be resistors, DC voltage sources, AC voltage sources, current sources, switches, grounding, jumper wires, etc. The purpose of using this intermediate representation is to decouple the front-end physical wiring model from the back-end SPICE netlist generation, allowing subsequent AC / DC decomposition, path binding replacement, component verification, and netlist output to be processed based on the same graph structure.

[0033] The order of multi-layered progressive topology synthesis is as follows: Terminal self-resistance layer: Traverse the terminal table and establish a two-level structure of external nodes and internal nodes for each terminal. For terminals with non-zero contact resistance, create a resistance edge between the external and internal nodes. This resistance edge is of type Resistor, and the corresponding resistance value is recorded in the parameters. In this way, the contact resistance is transformed from a text attribute in traditional drawings into a circuit branch that can participate in SPICE calculations, and the terminal contact impedance can be included in secondary load checks or cable voltage drop calculations.

[0034] When the contact resistance of a terminal is zero, the series resistance edge is not created, and the external node and internal node are treated as the same electrical node and substituted in subsequent processing. This process avoids generating a large number of zero-ohm resistors in the SPICE netlist, reduces the netlist size, and improves the stability of the simulation solution.

[0035] External Connection Layer: The external connection table is read, and the corresponding terminal objects are searched in the terminal identifier mapping table according to the source terminal path and the target terminal path. The external nodes of the source terminal and the target terminal are taken as the two endpoints of the corresponding resistance edge of the connection line. If the external connection line records the cable length and unit resistance, the cable resistance is obtained by multiplying the length by the unit resistance; if the core cross-sectional area and material type are recorded, the resistance value is calculated based on the material resistivity, core length, and cross-sectional area. After this resistance edge is added to the middle of the node edge diagram, the external cable connection is transformed from a physical description to a circuit topology description. Cable voltage drop, loop resistance, and secondary load can all be directly calculated by the SPICE simulator.

[0036] Dual-terminal control layer: Handles dual-terminal structures with left and right sides. When external connections are detected on both the left and right sides of a dual-terminal and the dual-terminal is not marked as disconnected, an electrical connection edge is created between the left and right internal nodes. The reason for using internal nodes to connect the left and right sides is that the conduction of the control layer occurs inside the terminal, and its electrical effect should be after the terminal contact resistance, thus maintaining the correct order of external cables, terminal contact resistance, and internal connectivity at the topology level.

[0037] Connector Layer: Based on the terminal arrangement order, connector configuration, and side markings, locate consecutive adjacent terminals on the same side within the same model group. If these terminals are marked as having a connector relationship, create shorting edges between the internal nodes of adjacent terminals. For example, if consecutive connectors exist to the left of indices 1, 2, and 3 in the same terminal block, shorting edges are created between ":1[L]_in" and ":2[L]_in", and between ":2[L]_in" and ":3[L]_in". This continuous shorting method can express the electrical equivalence of busbars, terminal connectors, or common terminal blocks. Connectors are converted into edges in the graph, enabling subsequent BFS connectivity search and SPICE netlist generation to identify this type of connection.

[0038] Internal Connections Layer: Parses the internal connection diagram data of the device model group. The internal connection diagram describes the internal circuit structure of the device plug-in or functional unit, such as internal resistors, switches, DC sources, AC sources, grounding terminals, and external terminal interfaces. This internal connection diagram is preferably saved in JSON format, where the `nodes` array declares internal component nodes, each node including at least a unique identifier, component type name, and a dictionary of configuration parameters; the `connections` array declares wire connections between ports, each connection record including an outgoing node identifier, outgoing node port type, incoming node identifier, and incoming node port type.

[0039] When parsing the internal connection diagram, a temporary port identifier is created for each internal element's port. Then, based on the wire relationships in the `connections` array, ports with equipotential relationships are merged using a disjoint-set data structure (DFT). Each set in the DFT represents an internal electrical node, and all ports directly connected by wires are merged into the same set. After merging, an internal node name is assigned to each set. For nodes with left and right terminal interfaces, no new isolated nodes are generated; instead, they are automatically mapped to the corresponding terminal's internal node. In this way, the internal sub-circuits of the device are naturally stitched together with the external wiring network in the same node edge diagram through the internal nodes of the terminals.

[0040] The internal connection layer design solves the problem of traditional external wiring diagrams and internal circuit diagrams being independent of each other, requiring manual matching of terminal numbers. Since Terminal interface nodes directly carry terminal indexes or terminal paths, interface matching can be automatically completed during parsing. In addition to JSON, internal connection diagrams can also be stored in XML, YAML, or database side tables; any format that provides component node declarations and port connection declarations can serve as an alternative.

[0041] S4. Traverse the unified node-edge graph intermediate representation. Use the nodes associated with the grounding element edges as the first type of seed nodes to perform connectivity search to obtain the first edge set. Use the nodes associated with the DC source element edges as the second type of seed nodes to perform connectivity search to obtain the second edge set. Use the nodes associated with the AC source element edges as the third type of seed nodes to perform connectivity search to obtain the third edge set. Take the intersection of the first edge set and the second edge set as the DC subgraph, and take the intersection of the first edge set and the third edge set as the AC subgraph.

[0042] Specifically, firstly, an undirected adjacency list is constructed based on the two endpoints of each circuit edge in the node edge graph. The key of the adjacency list is the node name, and the values ​​are the set of edges connected to that node and the set of adjacent nodes. Then, the type labels of all edges are scanned, and the associated nodes of grounding elements are designated as first-type seed nodes, the associated nodes of DC source elements as second-type seed nodes, and the associated nodes of AC source elements as third-type seed nodes. Breadth-first search is performed starting from the three types of seed nodes respectively, resulting in three sets of access labels. The intersection of the first and second edge sets is taken as the DC subgraph, and the intersection of the first and third edge sets is taken as the AC subgraph.

[0043] The principle behind this decomposition method is that the DC operating power supply circuit and the AC CT / PT signal circuit in the secondary circuit are usually electrically isolated. Only the part that is simultaneously connected to the reference ground network and the corresponding excitation source constitutes a valid simulation circuit. Through intersection operations, isolated branches that are neither grounded nor connected to a source can be automatically eliminated, reducing invalid netlist content and avoiding SPICE simulation errors caused by isolated nodes.

[0044] Breadth-first search is implemented using a queue. First, the seed node is enqueued and marked as visited. Each time, a node is taken out of the queue, and all edges associated with that node in the adjacency list are traversed. If the edge is not recorded, it is added to the current edge set, and the nodes at the other end of the edge that have not yet been visited are enqueued, until the queue is empty.

[0045] S5.1 Before generating the netlist, traverse the circuit edges with path binding information in the intermediate representation of the unified node edge graph. Each circuit can have three types: input binding, output binding, or no binding.

[0046] When the path binding information is input binding, the corresponding real-time excitation value is obtained from the external data system, and the placeholder parameter value in the corresponding component configuration of the circuit edge is replaced with the real-time excitation value. When a single SPICE component has multiple input binding fields, the configuration parameter field corresponding to each input binding field is determined according to the field mapping rules corresponding to the component type, so as to support AC source components to bind amplitude paths and phase paths simultaneously. For example, the ACVoltage type can define "ampPath" corresponding to the configuration parameter "amplitude" and "phasePath" corresponding to the configuration parameter "phase", and replace them item by item according to the field mapping rules.

[0047] When the path binding information is output binding, after the simulation calculation is completed, the calculated value corresponding to the output binding is extracted from the simulation results and written back to the external data system. This mechanism forms a closed data loop from external input to simulation calculation and then to the result writing back.

[0048] S5.2. Call the corresponding SPICE component processor to generate netlist statements for the edges in the DC subgraph and AC subgraph respectively, and output the DC netlist and AC netlist.

[0049] SPICE component processors are implemented using the policy pattern. Each component type corresponds to one policy processor, and all policy processors implement a unified verification interface and netlist generation interface. The verification interface checks whether the component parameters are complete, whether the numerical range is reasonable, and whether the endpoint nodes are valid; the netlist generation interface converts the edges in the node edge graph into SPICE statements. Policy processors are managed through a processor registry, which stores the mapping relationship between component type names and policy processor instances. When generating the netlist, the component type name of each edge is read, and the corresponding processor is retrieved from the registry for verification and statement generation.

[0050] S6. A separate thread polls the external input value change status at fixed intervals. The fixed interval can be set according to the project's real-time requirements, such as 10ms, 50ms, 100ms, or 1s. When a change in the external input value is detected, the following steps are automatically triggered: re-traverse the circuit edges with input bindings, obtain the changed real-time excitation values ​​from the external data system and replace the placeholder parameter values ​​in the corresponding component configurations; regenerate the DC netlist and AC netlist; for circuit edges with output bindings, extract the calculated values ​​from the new simulation results and write them back to the external data system. This achieves a fully automatic closed loop from detecting external changes, triggering simulation recalculation to automatically writing back the results. The entire calculation wait can be protected by a 30s timeout; after the timeout, the current simulation task will be terminated and an exception event will be sent.

[0051] This automatic monitoring mechanism transforms the traditional process of "manually modifying parameters - manually regenerating the netlist - manually running the simulation - manually recording the results" into an automatic closed-loop process, improving efficiency in multi-condition verification and parameter scanning scenarios.

[0052] In summary, the method provided in this embodiment allows engineers to perform modeling at the physical wiring level, with the system automatically converting the physical wiring model to a SPICE netlist without requiring manual node numbering or differentiation between AC and DC sub-circuits. Its core advantages lie in: achieving correct isolation and automatic stitching between the external wiring network and the internal circuitry of the device through a two-level terminal node model; unifying the five heterogeneous connection relationships into a node-edge graph intermediate representation through five-layer progressive topology synthesis; automatically separating DC and AC sub-graphs and eliminating isolated branches through connectivity-driven BFS graph decomposition; and forming a fully automated closed loop from change detection and recalculation to result write-back through path binding and independent thread automatic monitoring. This bridges the gap between physical wiring semantics and circuit simulation semantics, significantly reducing the modeling threshold and error probability in the design verification phase.

[0053] like Figure 4 As shown, the present invention also provides a power system topology abstraction and SPICE netlist automatic generation system for performing power system topology abstraction and SPICE netlist automatic generation method.

[0054] The system comprises a GUI client module, a simulation server module, and a data management module. The GUI client module provides a human-machine interface for editing device models, visualizing connection relationships, editing SPICE graphics, and managing operating conditions. Users can select a device and model group in the graphical interface to view its terminal arrangement, external connection lines, and internal connection diagrams; they can also edit terminal contact resistance, cable length, control chip status, and connection configuration. The GUI client does not directly generate SPICE netlists; instead, it submits the user-edited physical wiring model to the simulation server module for processing, thus ensuring decoupling between the front-end interface and the back-end topology algorithm.

[0055] The simulation server module is the core computing component of the system, which includes the ngspice simulation engine, netlist export service, automatic monitoring service, and communication service.

[0056] The netlist export service is responsible for executing the core processing flow in the above method embodiments, including data loading, multi-layer progressive topology synthesis, generation of a unified intermediate representation of the node edge graph, AC / DC subgraph decomposition, and generation of SPICE netlist statements.

[0057] The ngspice simulation engine is responsible for loading the generated DC and AC netlists and performing corresponding analyses, such as DC operating point analysis, AC small-signal analysis, or voltage and current calculations at a specified frequency.

[0058] The automatic monitoring service runs in a separate thread, responsible for polling the change status of external input values ​​at fixed intervals, and triggering the re-acquisition of path binding values ​​and simulation recalculation when a change is detected. The monitoring thread sends recalculation requests to the simulation service main thread through a thread-safe queue or signal-slot mechanism, avoiding race conditions caused by multiple threads accessing database connections, node edge graph caches, or ngspice instances simultaneously.

[0059] The communication service handles message interaction between the GUI client and the simulation server. The simulation server module provides both ZMQ and WebSocket communication interfaces. The ZMQ interface is suitable for local high-performance clients, batch scripts, or background tools, while the WebSocket interface is suitable for browser clients or cross-platform visual interfaces. Internally, the communication service employs a Handler-based message dispatch mechanism, where each message type corresponds to a handler. When the server receives a message from the client, it looks up the corresponding Handler based on the message type name and executes the processing logic.

[0060] The simulation server module also includes a ConnectionManager component to maintain a list of currently connected clients and broadcast events to relevant clients when the model changes, simulation results are updated, operating conditions are switched, or error states occur, ensuring consistent display across multiple interfaces.

[0061] The simulation server module also includes a case management service, used to create database file snapshots for different simulation cases. The case management service uses a dual-file structure: a base database file and a temporary database file. The base database file stores the baseline model data for the current project, while the temporary database file stores modified data for a specific simulation case. When a user switches cases, the case management service generates or restores the corresponding temporary database file through file-level copying, re-establishes the database connection, and then triggers a re-collection of the path binding list, clearing of the node edge graph cache, and simulation recalculation.

[0062] The data management module stores the hierarchical physical wiring model of secondary circuits, equipment model groups, terminal information, external connection lines, internal connection diagram data, and path binding information. The data management module uses an SQLite database as its storage backend.

[0063] The ngspice simulation engine, netlist export service, automatic monitoring service, communication service, data management module, processor registry, and ConnectionManager components in the simulation server module employ the Boost.DI compile-time dependency injection container to manage their instance lifecycles. The dependency injection container establishes the dependencies between components at server startup and ensures that critical services exist as singletons. Alternatively, runtime service locators or the factory pattern can also be used to implement component management.

[0064] The simulation server module also includes a SPICE component policy processor registry, containing multiple policy processors corresponding to component types. Each policy processor has a unified verification interface and netlist generation interface. When support for a new SPICE component type is required, only the corresponding policy processor needs to be added and registered, without modifying the main processes of topology synthesis and graph decomposition.

[0065] The system can be configured with a multi-level caching mechanism. The first level is the original model cache, the second level is the node-side graph cache, and the third level is the netlist cache. When the user only modifies the input binding values ​​without changing the topology, the system can reuse the node-side graph cache, simply replacing the component parameters and generating the netlist. When the user modifies the connection lines, bridging, or internal connection diagrams, the system clears the node-side graph cache and re-executes multi-level topology synthesis. When the user switches operating conditions, the system clears all caches and reloads the database snapshot.

[0066] The system can also add topology consistency checks before generating the netlist. For example, it checks if the DC subgraph has at least one ground reference point, if the AC subgraph has any AC sources with missing frequency parameters, and if all Terminal interfaces in the internal connection diagram can be mapped to actual terminals. When an anomaly is detected, the system highlights the corresponding device, terminal, or connection line in the GUI client and provides diagnostic information.

[0067] The system can also provide standardized output rules for node names and component numbers, convert node names containing Chinese characters, spaces, and special symbols into safe node names, and maintain a mapping table between the original terminal paths and safe node names, ensuring SPICE netlist compatibility without compromising the readability of the engineering semantics.

[0068] In summary, the system provided in this embodiment adopts a separate architecture for the GUI client and the simulation server. The front end is responsible for editing and visualizing the physical wiring model, while the back end is responsible for topology synthesis, graph decomposition, and netlist generation. This decoupling ensures that algorithm upgrades do not affect user operating habits. The simulation server provides both ZMQ and WebSocket dual-protocol communication interfaces, has an integrated ConnectionManager component to support multi-client event broadcasting, uses a SPICE component strategy processor registry for plug-in extension, achieves complete isolation of multi-condition data through a database file snapshot mechanism, and manages the lifecycle of each component's singleton through a compiler dependency injection container. This system integrates the above methods into a workable software platform with advantages such as clear architecture, strong scalability, and convenient multi-condition management.

[0069] Through the above methods and systems, this invention converts the physical wiring model of the secondary circuit into a unified node-edge graph intermediate representation. Then, it automatically separates the DC subgraph and AC subgraph through connectivity search, and outputs the corresponding netlist through a strategy-based SPICE component processor. This allows the system to automatically generate DC and AC netlists that can be used for SPICE simulation while maintaining the engineer's design based on physical objects such as equipment, terminals, and connecting lines. Compared with the traditional manual method, it has a higher degree of automation, model consistency, and engineering maintainability.

[0070] This invention addresses application scenarios such as substation secondary circuit design verification, CT / PT secondary load verification, operating circuit simulation, cable selection simulation, and electrical consistency checks of relay protection-related circuits. Unlike traditional methods, this invention does not require engineers to directly use nodes, branches, and components in SPICE as modeling objects. Instead, it allows engineers to continue modeling according to the physical wiring conventions in secondary circuit design, describing the actual wiring relationships around equipment, model groups, terminals, terminal sides, external connections, connectors, and internal equipment connection diagrams. The system converts the physical wiring semantics into a unified node-side graph intermediate representation in the background, and then converts this node-side graph intermediate representation into a SPICE simulation netlist.

[0071] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0072] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for power system topology abstraction and automatic SPICE netlist generation, characterized in that, include: S1. Obtain the hierarchical physical wiring model of the secondary circuit; S2. Load the data of the hierarchical physical wiring model into memory, and construct a group information mapping table and a terminal identifier mapping table; S3. Based on the grouping information mapping table and the terminal identification mapping table, perform multi-layer progressive topology synthesis on the terminals, external connection lines and internal connection diagrams in the hierarchical physical wiring model in a fixed order, and add circuit edges to the unified node edge diagram intermediate representation layer by layer to generate a unified node edge diagram intermediate representation. In the multi-layer progressive topology synthesis, each terminal is modeled as a two-level structure of external node and internal node, and a terminal resistor edge is connected in series between the external node and the internal node. S4. Traverse the unified node-edge graph intermediate representation, use the nodes associated with the grounding element edges as the first type of seed nodes to perform connectivity search to obtain the first edge set, use the nodes associated with the DC source element edges as the second type of seed nodes to perform connectivity search to obtain the second edge set, use the nodes associated with the AC source element edges as the third type of seed nodes to perform connectivity search to obtain the third edge set, take the intersection of the first edge set and the second edge set as the DC subgraph, and take the intersection of the first edge set and the third edge set as the AC subgraph; S5. Call the corresponding SPICE component processor to generate netlist statements for the edges in the DC subgraph and AC subgraph respectively, and output the DC netlist and AC netlist.

2. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 1, characterized in that, In S3, the order of the multi-layer progressive topology synthesis is as follows: The terminal itself has a resistive layer, which creates the series resistance edge for the terminal with non-zero contact resistance, and the series resistance edge is connected between the external node and the internal node; The external connection layer converts the inter-device connection lines into resistive edges that connect the external nodes of the source terminal and the external nodes of the target terminal; A dual-terminal control layer creates an electrical connection edge between the left and right internal nodes of a dual terminal that has external connections on both sides and is not marked as disconnected. The continuous layer creates shorting edges between internal nodes of consecutive adjacent terminals on the same side of the same group; The internal connection layer parses the internal connection diagram data of the device model group. The internal connection diagram data is expressed in a graph data structure and includes node declarations and connection edge declarations. Electrically equivalent connection ports are merged through an electrical equivalent port merging algorithm. The edges formed by internal circuit elements are mapped to the internal nodes of the corresponding terminals, thereby realizing the stitching of internal sub-circuits and external wiring networks of the device.

3. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 2, characterized in that, When the contact resistance of the terminal is zero, no series resistance edge connecting the external node and the internal node is created, and the external node and the internal node are treated as the same electrical node and replaced in the subsequent topology synthesis process.

4. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 2, characterized in that, The internal connection graph data is in JSON format and contains an array of nodes and an array of connections. Each node in the node array includes at least a unique identifier, a component type name, and a dictionary of configuration parameters; Each connection edge in the connection array is used to specify the port type of the outgoing node and the port type of the incoming node; The electrical equivalent port merging algorithm is a disjoint-set data structure algorithm, which is used to merge component ports that are equipotentially connected by wires into the same electrical node.

5. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 4, characterized in that, The node types in the internal connection diagram data include at least DC voltage source, AC voltage source, DC current source, AC current source, resistor, switch, ground, left terminal interface, and right terminal interface; The nodes of the left and right terminal interfaces serve as interface nodes between the internal sub-circuits of the device and the external terminals, and are automatically mapped to the internal nodes of the corresponding terminals to achieve the stitching between the internal sub-circuits of the device and the unified node edge diagram intermediate representation.

6. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 1, characterized in that, The connectivity search described in S4 is a breadth-first search; The breadth-first search includes: An undirected adjacency list is constructed based on the node names at both ends of each circuit edge in the unified node edge graph intermediate representation. The nodes associated with the grounding element edge, the DC source element edge, and the AC source element edge are respectively used as seed nodes; The access markers are propagated along the associated edges in the undirected adjacency list to obtain the first edge set, the second edge set, and the third edge set, respectively.

7. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 1, characterized in that, The SPICE component processor described in S5 includes multiple policy processors corresponding to component types; Each policy processor has a unified verification interface and netlist generation interface; When generating netlist statements, the corresponding policy processor is selected from the processor registry based on the component type name of the circuit edge in the unified node edge graph intermediate representation, and the policy processor verifies the component configuration parameters of the circuit edge and generates netlist statements.

8. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 1, characterized in that, Before the S5 generates the netlist statement, it also includes: Traverse the circuit edges with path binding information in the intermediate representation of the unified node-edge graph; When the path binding information is an input binding, the corresponding real-time excitation value is obtained from the external data system, and the placeholder parameter value in the corresponding component configuration of the circuit edge is replaced by the real-time excitation value. When a single SPICE element has multiple input binding fields, the configuration parameter field corresponding to each input binding field is determined according to the field mapping rules corresponding to the element type, so as to support AC source elements to bind amplitude path and phase path at the same time; When the path binding information is an output binding, after the simulation calculation is completed, the calculated value corresponding to the output binding is extracted from the simulation results, and the calculated value is written back to the external data system.

9. The method for automatic generation of power system topology abstraction and SPICE netlist according to claim 8, characterized in that, Also includes: The status of changes in external input values ​​is polled at fixed intervals using a separate thread. When a change in an external input value is detected, the following steps are automatically triggered: Re-traverse the circuit edges with input binding in the intermediate representation of the unified node edge graph, obtain the changed real-time excitation values ​​from the external data system, and replace the placeholder parameter values ​​in the corresponding component configuration; Repeat steps S4 and S5 to generate new DC netlists and AC netlists; For circuit edges with output binding, extract calculated values ​​from the new simulation results and write them back to the external data system.

10. A power system topology abstraction and SPICE netlist automatic generation system, characterized in that, The system for performing the method as described in any one of claims 1-9 includes: The GUI client module provides a device model editing, connection relationship visualization, and human-computer interaction management interface. The simulation server module includes the ngspice simulation engine, netlist export service, automatic monitoring service, and communication service. The data management module is used to store the hierarchical physical wiring model of the secondary circuit, equipment model groups, terminal information, external connection lines, internal connection diagram data and path binding information; The simulation server module is used to convert the hierarchical physical wiring model into a unified node-side graph intermediate representation, and to generate DC netlists and AC netlists based on the unified node-side graph intermediate representation. The simulation server module also includes a working condition management service, which is used to create database file snapshots for different simulation working conditions. The database file snapshots include basic database files and temporary database files. When switching working conditions, the temporary database files are generated or restored through file-level copying, and the simulation recalculation is automatically triggered.

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