PEEC micro-model order reduction method and system based on local pseudo-inductance strategy

Abstract

The application discloses a PEEC micro-model order reduction method and system based on a local pseudo-inductance strategy, and the method comprises the following steps: establishing a PEEC equivalent circuit model and initializing a circuit matrix; regarding all nodes as candidate nodes, calculating the low-frequency approximation error of each node, screening out the least important node and removing the same; temporarily constructing a parallel pseudo-inductance branch for an adjacent ordinary capacitance branch, updating the matrix elements through circuit equivalent transformation; combining the two into an equivalent pseudo-inductance branch and updating the coupling relationship; internalizing the equivalent pseudo-inductance into an ordinary inductance and restoring the same into an ordinary capacitance branch; repeating the iteration until the low-frequency approximation error of all candidate nodes is greater than a preset threshold value, and obtaining a reduced micro-model. The application dynamically compensates the low-frequency precision in the order reduction process through the local pseudo-inductance strategy, effectively reduces the circuit size, maintains the modeling precision in the low-frequency band, and is suitable for the rapid simulation of high-frequency electromagnetic field problems.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic modeling and model reduction technology, specifically to a PEEC micromodel reduction method and system based on a local pseudo-inductance strategy. Background Technology

[0002] Signal integrity analysis places both high precision and high efficiency demands on the electromagnetic modeling of high-speed interconnects and packaging structures. With the exponential growth in integrated circuit scale and the rapid increase in the number of transistors on chips, the geometric complexity and electromagnetic coupling effects of high-speed interconnects and packaging structures are significantly enhanced, placing higher demands on the computational efficiency and accuracy of electromagnetic modeling methods.

[0003] Partial Element Equivalent Circuit (PEEC) is a numerical method based on electromagnetic field-circuit equivalence modeling. It transforms electromagnetic problems into equivalent circuit systems and can be solved using Modified Nodal Analysis (MNA) or SPICE-type circuit solvers. It is widely used in signal integrity analysis, package design, and electromagnetic compatibility. However, in large-scale interconnect structures, PEEC models typically contain a large number of partial elements, and their solution process involves repeated calculations of high-dimensional matrices, resulting in significant computational and storage overhead.

[0004] To improve the computational efficiency of large-scale electromagnetic problems, model reduction methods have become an important research direction. Among them, the micro-model method transforms the original high-dimensional system into a low-order, physically meaningful equivalent RLC circuit through a node elimination strategy, preserving the input-output characteristics while maintaining the correspondence with the physical structure.

[0005] In existing technologies, pseudo-inductors are introduced to ensure physical consistency during the node elimination process. This method connects a pseudo-inductor in series with each grounding port in the initial stage of order reduction, forming a pseudo-inductor branch structure. If the number of capacitors in the PEEC model is Ng, then this method introduces Ng additional state variables. However, for complex structures such as multilayer PCBs, Ng can reach thousands of times, causing the size of the intermediate inductor matrix and capacitor matrix to increase rapidly, becoming the main computational and storage bottleneck.

[0006] Therefore, there is an urgent need for a PEEC micromodel reduction method that can significantly reduce the size of intermediate matrices and reduce memory usage while maintaining reduction accuracy. Summary of the Invention

[0007] To address the aforementioned issues, this invention proposes a method and system for reducing the order of PEEC micromodels based on a local pseudo-inductance strategy.

[0008] On the one hand, a method for order reduction of PEEC micromodels based on a local pseudo-inductance strategy includes:

[0009] S1. Establish the PEEC equivalent circuit model and initialize the circuit matrix;

[0010] S2, take the nodes in the initialized circuit matrix as candidate nodes, calculate the low-frequency approximation error of each candidate node, and when the low-frequency approximation error of a candidate node is less than the preset threshold, select the candidate node that minimizes the low-frequency approximation error and record it as the least important node.

[0011] S3, remove the least important node from the circuit matrix, temporarily construct a parallel pseudo-inductor branch for the adjacent ordinary capacitor branch of the least important node, and update the circuit matrix elements through circuit equivalent transformation.

[0012] S4, and combine and adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches to obtain equivalent pseudo-inductor branches, and synchronously update the coupling relationship between inductors / capacitors in the equivalent pseudo-inductor branches and other pseudo-inductor branches.

[0013] S5, internalize the pseudo-inductance in the updated equivalent pseudo-inductance branch into a normal inductance, so that the equivalent pseudo-inductance branch is restored to a normal capacitor branch, and the updated equivalent circuit is obtained.

[0014] S6, determine whether the low-frequency approximation error of all candidate nodes in the updated equivalent circuit is greater than the preset threshold. If yes, the order reduction ends and the reduced micro-model circuit is obtained; otherwise, return to S2 to continue execution.

[0015] Furthermore, in S2, the low-frequency approximation error is calculated using the following formula:

[0016] ;

[0017] in, The highest relevant frequency; This represents the number of nodes connected to candidate node k. and Let represent the changes in inductance and capacitance of the i-th associated branch after eliminating candidate node k, respectively; This indicates the low-frequency approximation error.

[0018] Furthermore, in S3, updating the circuit matrix elements includes updating the temporary pseudo-inductor branch matrix elements, calculated as follows:

[0019] ;

[0020] ;

[0021] ;

[0022] ;

[0023] in, This indicates the coupling between the pseudo-inductor and the other ordinary inductors in the newly added pseudo-inductor branch after power conversion; This indicates the coupling between the inductance of adjacent nodes and the other ordinary inductances before the circuit transformation; This indicates the self-coupling of the pseudo-inductor in the newly added pseudo-inductor branch after circuit transformation; This indicates the self-coupling of inductance between adjacent nodes before the circuit transformation; This indicates the coupling between the capacitor and other capacitors in the newly added pseudo-inductor branch after the circuit transformation; This represents the coupling between the ordinary capacitor and other capacitors connected to the candidate node k before the circuit transformation. This indicates the self-coupling of the capacitor in the newly added pseudo-inductor branch after the circuit transformation; This represents the self-coupling of the ordinary capacitor connected to candidate node k before the circuit transformation; This represents the physical quantity corresponding to the p-th frequency component; Indicates the number of adjacent nodes; for A column vector of all 1s; for The identity matrix.

[0024] Furthermore, in S4, the calculation formula for combining and adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches is as follows:

[0025] ;

[0026] ;

[0027] in, and These represent the equivalent capacitance and pseudo-inductance parameters of the merged branch, respectively. Indicates the current frequency These are the first equivalent transformation coefficients; e4 is the first intermediate calculation parameter; e4 is the fourth intermediate calculation parameter. These are intermediate parameters related to the first frequency;

[0028] Furthermore, in S4, the coupling relationship between inductors and capacitors in the equivalent pseudo-inductor branch and other pseudo-inductor branches is updated synchronously, and the calculation formula is as follows:

[0029] ;

[0030] ;

[0031] in, and This is a constant during the transformation of the microcircuit model; This is to couple the capacitance of the equivalent pseudo-inductor branch after merging with the capacitance of the other pseudo-inductor branches. It is the coupling between the capacitor in the S branch before merging and the capacitors in the other pseudo-inductor branches; It is the coupling between the capacitor in branch I before merging and the capacitors in the other pseudo-inductor branches; It is the coupling between the inductance of the combined equivalent pseudo-inductance branch and the inductance in the other pseudo-inductance branches; It is the coupling between the inductance of the S branch before merging and the inductance in the other pseudo-inductor branches; It is the coupling between the inductance of branch I before merging and the inductance in the other pseudo-inductor branches.

[0032] Furthermore, in S5, the pseudo-inductance in the updated equivalent pseudo-inductance branch is internalized as a normal inductance. Specifically, the pseudo-inductance component in the equivalent pseudo-inductance branch is converted into an equivalent normal inductance component, and its coupling relationship is transferred to the normal inductance matrix, thereby restoring the branch to a normal capacitor branch that only includes capacitance characteristics.

[0033] On the other hand, a PEEC micro-model order reduction system based on a local pseudo-inductance strategy includes:

[0034] The initialization module is used to establish the PEEC equivalent circuit model and initialize the circuit matrix.

[0035] The filtering module is used to select nodes in the initialized circuit matrix as candidate nodes, calculate the low-frequency approximation error of each candidate node, and filter out the candidate node that minimizes the low-frequency approximation error when the low-frequency approximation error of a candidate node is less than a preset threshold. This candidate node is then denoted as the least important node.

[0036] The temporary branch construction module is used to remove the least important node from the circuit matrix, temporarily construct a parallel pseudo-inductor branch for the adjacent ordinary capacitor branch of the least important node, and update the circuit matrix elements through circuit equivalent transformation.

[0037] The parallel module is used to combine adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches to obtain an equivalent pseudo-inductor branch, and synchronously update the coupling relationship between inductors / capacitors in the equivalent pseudo-inductor branch and the other pseudo-inductor branches.

[0038] The update module is used to internalize the pseudo-inductance in the updated equivalent pseudo-inductance branch into a normal inductance, so that the equivalent pseudo-inductance branch is restored to a normal capacitor branch, and the updated equivalent circuit is obtained.

[0039] The order reduction judgment module is used to determine whether the low-frequency approximation error of all candidate nodes in the updated equivalent circuit is greater than a preset threshold. If so, the order reduction is terminated, and the reduced micro-model circuit is obtained; otherwise, the process returns to the filtering module to continue execution.

[0040] The present invention adopts the above technical solution and has the following beneficial effects:

[0041] (1) This invention establishes a PEEC equivalent circuit model and initializes the circuit matrix, takes all nodes as candidate nodes and calculates the low-frequency approximation error one by one, iteratively selects the node with the smallest error as the least important node and removes it from the circuit matrix, thereby achieving a continuous reduction in the size of the circuit matrix, thus effectively reducing the circuit complexity and computational storage while ensuring that the key electrical characteristics remain basically unchanged.

[0042] (2) The present invention achieves dynamic compensation for low-frequency electrical characteristics during the order reduction process by removing the least important node and temporarily constructing a parallel pseudo-inductor branch for its adjacent ordinary capacitor branch, combining the adjacent ordinary capacitor branch with the temporary pseudo-inductor branch to obtain an equivalent pseudo-inductor branch, and internalizing the pseudo-inductance in the equivalent pseudo-inductor branch into an ordinary inductance to restore it to an ordinary capacitor branch.

[0043] (3) The present invention updates the circuit matrix elements by adopting the circuit equivalent transformation method and converts the pseudo-inductance component in the equivalent pseudo-inductance branch into the equivalent ordinary inductance component so that its coupling relationship is transferred to the ordinary inductance matrix. This makes the entire order reduction derivation process not involve any matrix inversion or decomposition operations, which greatly reduces the computational complexity of a single iteration. Attached Figure Description

[0044] Figure 1 This is a flowchart of the PEEC micromodel order reduction method based on the local pseudo-inductance strategy according to an embodiment of the present invention;

[0045] Figure 2(a) is a schematic diagram of the mesh and circuit topology of the PEEC model according to an embodiment of the present invention;

[0046] Figure 2(b) is a schematic diagram of finding min K according to an embodiment of the present invention;

[0047] Figure 2(c) is a schematic diagram of the circuit transformation of the absorption node k in an embodiment of the present invention;

[0048] Figure 2(d) is a schematic diagram of the merging of the coupled branch in an embodiment of the present invention;

[0049] Figure 2(e) is a schematic diagram of using a common inductor to internalize a pseudo-inductor according to an embodiment of the present invention;

[0050] Figure 2(f) shows the mesh and circuit topology after absorbing all unimportant nodes in an embodiment of the present invention;

[0051] Figure 3 This refers to the temporary data stored in the element_removed_mat matrix in the comparison algorithm of this embodiment of the invention;

[0052] Figure 4 shows the temporary data stored in the element_removed_mat matrix in this algorithm according to an embodiment of the present invention;

[0053] Figure 5 This is a diagram of the PEEC micromodel order reduction system based on the local pseudo-inductance strategy in an embodiment of the present invention. Detailed Implementation

[0054] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0055] like Figure 1 As shown, the present invention provides a method for order reduction of PEEC micromodels based on a local pseudo-inductance strategy, comprising:

[0056] S1. Establish the PEEC equivalent circuit model and initialize the circuit matrix.

[0057] Specifically, the first step, as shown in Figure 2(a), is to establish a PEEC model and initialize the circuit matrix. The target interconnect or package structure is discretized to construct a PEEC equivalent circuit model. The PEEC model contains multiple nodes, inductor units, and capacitor units. There is mutual coupling between inductor units and between capacitor units. The micro-model reduction method in this paper directly processes the capacitor matrix and inductor matrix.

[0058] For a quasi-static electromagnetic problem, Kirchhoff's voltage law for a PEEC circuit can be expressed as:

[0059]

[0060] in, Inductor unit and The inductance between them This represents the potential coefficient between capacitor units.

[0061] The target structure includes: high-speed interconnect circuits, multi-layer packaging structure, microwave filter and antenna feed network.

[0062] S2. Take all nodes in the initialized circuit matrix as candidate nodes, calculate the low-frequency approximation error of each candidate node, and select the candidate node that minimizes the low-frequency approximation error. Record this candidate node as the least important node.

[0063] Specifically, in S2, the low-frequency approximation error is calculated using the following formula:

[0064] ;

[0065] in, The highest relevant frequency; This represents the number of nodes connected to candidate node k. and Let represent the changes in inductance and capacitance of the i-th associated branch after eliminating candidate node k, respectively; This indicates the low-frequency approximation error.

[0066] Specifically, the second step, as shown in Figure 2(b), is to find the least important node in the current circuit. For each candidate node k in the current circuit, its importance index is calculated, and the node that minimizes the low-frequency approximation error is selected as the least important node.

[0067] S3 removes the least important node from the circuit matrix, temporarily constructs a parallel pseudo-inductor branch for the adjacent ordinary capacitor branch of the least important node, and updates the circuit matrix elements through circuit equivalent transformation.

[0068] Specifically, in S3, the updated circuit matrix elements include the updated temporary pseudo-inductor branch matrix elements, calculated as follows:

[0069] ;

[0070] ;

[0071] ;

[0072] ;

[0073] in, This indicates the coupling between the pseudo-inductor and the other ordinary inductors in the newly added pseudo-inductor branch after power conversion; This indicates the coupling between the inductance of adjacent nodes and the other ordinary inductances before the circuit transformation; This indicates the self-coupling of the pseudo-inductor in the newly added pseudo-inductor branch after circuit transformation; This indicates the self-coupling of inductance between adjacent nodes before the circuit transformation; This indicates the coupling between the capacitor and other capacitors in the newly added pseudo-inductor branch after the circuit transformation; This represents the coupling between the ordinary capacitor and other capacitors connected to the candidate node k before the circuit transformation. This indicates the self-coupling of the capacitor in the newly added pseudo-inductor branch after the circuit transformation; This represents the self-coupling of the ordinary capacitor connected to candidate node k before the circuit transformation; This represents the physical quantity corresponding to the p-th frequency component; Indicates the number of adjacent nodes; for A column vector of all 1s; for The identity matrix.

[0074] Specifically, in the third step, as shown in Figure 2(c), an equivalent circuit transformation is performed, and temporary pseudo-inductor branches are constructed for the adjacent ordinary capacitor branches of the absorbed node. For each adjacent ordinary capacitor branch of the absorbed node k, a temporary pseudo-inductor branch is created. The pseudo-inductor branch is composed of the capacitor of the original ordinary capacitor branch connected in series with a pseudo-inductor with an initial inductance value of zero. Its value is automatically updated according to the circuit equivalence conditions during subsequent branch merging.

[0075] Perform node absorption transformation on the selected least important node k. Node absorption must satisfy the equivalent Kirchhoff voltage and current laws, and the final formula for the new circuit matrix elements can be given as follows:

[0076] Update the formulas for the newly added pseudo-inductor branch elements:

[0077]

[0078]

[0079]

[0080]

[0081] Update the formula for adding a general-purpose inductor:

[0082]

[0083]

[0084]

[0085] The variables related to other ordinary capacitors and other ordinary inductors remain unchanged:

[0086]

[0087] in It is a column vector of all 1s. It is a matrix of all ones. , , This is a cyclic shift operator. After the transformation, the absorbed node k is removed from the circuit, and several new pseudo-inductor branches and inductor branches are generated, which need to be further merged.

[0088] The pseudo-inductor branch is a temporary data structure, valid only during the current node's absorption process, and is not saved to the global data structure. Since this invention only constructs temporary pseudo-inductor branches within the current node's neighborhood, the number of pseudo-inductors participating in the calculation at any given time is only related to the number of adjacent nodes, deg(k), with a scale of approximately O(deg(k)). In actual PEEC circuits, deg(k) ≪ Ng (where Ng is the total number of capacitors) is typically satisfied. Therefore, the scale of pseudo-inductors introduced in this invention is much smaller than that of traditional global preset methods.

[0089] S4. The adjacent ordinary capacitor branch and the temporarily constructed pseudo-inductor branch are combined in parallel to obtain the equivalent pseudo-inductor branch, and the coupling relationship between the equivalent pseudo-inductor branch and the corresponding circuit element is updated synchronously.

[0090] Specifically, in S4, adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches are combined in parallel, and the calculation formula is as follows:

[0091] ;

[0092] ;

[0093] in, and These represent the equivalent capacitance and pseudo-inductance parameters of the merged branch, respectively. Indicates the current frequency; and This is a constant during the transformation of the microcircuit model.

[0094] Specifically, in S4, the coupling relationship between the equivalent pseudo-inductance branch and the corresponding circuit element is updated synchronously. The calculation formula is as follows:

[0095] ;

[0096] ;

[0097] in, and This is a constant during the transformation of the microcircuit model; This is to couple the capacitance of the equivalent pseudo-inductor branch after merging with the capacitance of the other pseudo-inductor branches. It is the coupling between the capacitor in the S branch before merging and the capacitors in the other pseudo-inductor branches; It is the coupling between the capacitor in branch I before merging and the capacitors in the other pseudo-inductor branches; It is the coupling between the inductance of the combined equivalent pseudo-inductance branch and the inductance in the other pseudo-inductance branches; It is the coupling between the inductance of the S branch before merging and the inductance in the other pseudo-inductor branches; It is the coupling between the inductance of branch I before merging and the inductance in the other pseudo-inductor branches.

[0098] Specifically, in the fourth step, as shown in Figure 2(d), after the circuit transformation is completed, each incremental pseudo-inductor branch forms a parallel connection with a regular capacitor branch. Before absorbing the next node, these parallel branches must be merged into a single equivalent branch, and their coupling relationship with the remaining circuit elements must be updated synchronously.

[0099] Assuming branch S and branch I are merged into branch S, then the equivalent self-impedance of the merged branch is...

[0100]

[0101] in

[0102]

[0103] This represents the self-impedance of the capacitor branch;

[0104]

[0105] This represents the self-impedance of the temporary pseudo-inductor branch;

[0106]

[0107] This represents the mutual impedance between two branches.

[0108] The corresponding admittance matrix is:

[0109]

[0110] The total admittance after parallel connection is defined as:

[0111]

[0112] The self-impedance of the equivalent branch after merging is:

[0113]

[0114] Further definition

[0115]

[0116] Simultaneously define

[0117]

[0118] Therefore, the equivalent capacitance and pseudo-inductance parameters of the merged branch are respectively

[0119]

[0120]

[0121] Update the coupling parameters related to the merged branch;

[0122] Specifically, according to the present invention, several original physical parameters are predefined: The potential coefficient corresponding to branch S before merging; The potential coefficient corresponding to branch I before merging; These are the potential coefficients between SI branches; The inductance coefficient of branch I before merging; This represents the mutual inductance coefficient between SI branches.

[0123] Introduce a set of intermediate calculation parameters e1, e2, e3, e4, e5, e6, and e7, and calculate according to the following formula:

[0124]

[0125] In the formula: e1 is the first intermediate calculation parameter, derived from the potential coefficient. The parameters are calculated together; e4 is the fourth intermediate calculation parameter, derived from the potential coefficient. The calculation characterizes the potential coefficient coupling terms across different grids; e5 is the fifth intermediate calculation parameter, which introduces both the potential coefficient and mutual inductance coefficient to characterize the potential-mutual inductance coupling intermediate term; e7 is the seventh intermediate calculation parameter, derived from the cross-grid mutual inductance coefficient. The calculations yielded e2, e3, and e6, which are the remaining intermediate calculation parameters.

[0126] Introducing intermediate parameters c1, c2, and c3, we further solve for the coefficients k1, k2, and k3, as shown in the following expression:

[0127]

[0128] In the formula: k1 is the first equivalent transformation coefficient, calculated from the intermediate calculation parameter e1 and parameter c1, used for matrix update of the mesh absorption order reduction model; c1, c2, and c3 are frequency-related intermediate parameters, related to the angular frequency. The mutual inductance coefficients are related; k2 and k3 are the second and third equivalent transformation coefficients.

[0129] The mutual impedance between the merged branch and other circuit elements can be expressed as:

[0130]

[0131]

[0132]

[0133] In the above impedance expression Item and By organizing the items separately, we can obtain the corresponding update formulas for the capacitor and inductor parameters:

[0134]

[0135]

[0136]

[0137]

[0138] The above formula provides a method for updating the mutual coupling parameters between the merged branch and the remaining pseudo-inductor branches, the remaining capacitor branches, and the ordinary inductor branches.

[0139] Update of coupling relationships between other branches

[0140] When branch S merges with branch I, it not only changes the coupling parameters associated with the merged branch, but also affects the mutual coupling relationships between the remaining branches. Definition:

[0141]

[0142] For the capacitive coupling between the remaining pseudo-inductor branches, the updated matrix is:

[0143]

[0144] The corresponding inductor matrix is ​​updated to

[0145]

[0146] Regarding the coupling relationship between the remaining pseudo-inductor branches and the ordinary capacitor branches, we have

[0147]

[0148] Regarding the coupling relationship between the remaining pseudo-inductor branches and the ordinary inductor branches, we have

[0149]

[0150] In this circuit, Q1 is a standard capacitor branch connected to the positive terminal of the inductor, and Q2 is a standard capacitor branch connected to the negative terminal of the inductor.

[0151] For the coupling relationship between two ordinary capacitor branches, we have

[0152]

[0153] Finally, the mutual inductance matrix between ordinary inductor branches is updated to

[0154]

[0155] In this circuit, Q1 and Q3 are ordinary capacitor branches connected to the positive terminal of the inductor, and Q2 and Q4 are ordinary capacitor branches connected to the negative terminal of the inductor.

[0156] Equations (13), (15), and (17) to (21) provide all the parameter update formulas required during the parallel connection of the temporary pseudo-inductor branch and the capacitor branch. Through these update relationships, the temporary pseudo-inductor branch and the original capacitor branch can be merged into a single equivalent branch while maintaining the circuit equivalence, and the capacitor matrix and inductor matrix can be updated simultaneously, laying the foundation for the subsequent pseudo-inductor internalization operation.

[0157] S5 internalizes the pseudo-inductance in the updated equivalent pseudo-inductance branch into a normal inductance, restoring the equivalent pseudo-inductance branch to a normal capacitor branch, thus obtaining the updated equivalent circuit.

[0158] Specifically, in S5, the pseudo-inductance in the updated equivalent pseudo-inductance branch is internalized as a normal inductance. Specifically, the pseudo-inductance component in the equivalent pseudo-inductance branch is converted into an equivalent normal inductance component, and its coupling relationship is transferred to the normal inductance matrix, so that the branch is restored to a normal capacitor branch that only includes capacitance characteristics.

[0159] Specifically, in the fifth step, as shown in Figure 2(e), the pseudo-inductance in the equivalent pseudo-inductance branch obtained in the fourth step is internalized into a normal inductance, so that the branch is restored to a normal capacitor branch.

[0160] Let the pseudo-inductance branch to be internalized be kk′, and the ordinary inductance branch connected to node k be jk. Then the internalized mutual inductance is updated according to the following formula:

[0161] For other ordinary inductor branches mn, the mutual inductance is updated as follows:

[0162]

[0163] For the remaining pseudo-inductor branches ll', their coupling is updated as follows:

[0164]

[0165] For a common inductor branch directly connected to node k Its mutual induction update is as follows:

[0166]

[0167] After the above processing, the pseudo-inductance generated during the current node absorption process is completely eliminated, and the circuit is restored to a PEEC network containing only ordinary capacitor branches and ordinary inductor branches.

[0168] Unlike existing technologies, this invention uses a different method for unified internalization after the order reduction is completed. This invention performs internalization immediately after each round of node absorption to avoid the accumulation of pseudo-inductance state variables during the iteration process.

[0169] S6, determine whether the low-frequency approximation error of all candidate nodes in the updated equivalent circuit is greater than the preset threshold. If yes, the order reduction ends and the reduced micro-model circuit is obtained; otherwise, return to S2 to continue execution.

[0170] Specifically, the core idea of ​​this invention is that the pseudo-inductor is only used to ensure circuit equivalence during the local node absorption process, and its contribution can be completely internalized into the ordinary inductor matrix after the node is eliminated, without needing to retain the global pseudo-inductor network throughout the entire order reduction process. Based on this, this invention achieves on-demand generation and immediate elimination of pseudo-inductors by omitting the global pre-setting step, temporarily introducing pseudo-inductors during the local node absorption process, and immediately internalizing them after node absorption, thereby significantly reducing the size of the intermediate matrix.

[0171] Specifically, in step six, the termination condition is determined, and the process is iterated until the order reduction is complete, resulting in the circuit shown in Figure 2(f). Steps two through five are repeated until the error bound ε(k) of all nodes in the current circuit is greater than a preset threshold. The preset threshold is set according to the target frequency range and accuracy requirements; in this example, it is 0.02. When all nodes no longer meet the absorption condition, the order reduction process terminates, yielding the reduced-order micro-model circuit.

[0172] Furthermore, compared with existing technologies (Dou and Wu proposed a micro-model order reduction method based on PEEC), this invention has the following advantages:

[0173] (1) Significantly reduced memory usage: By employing a local pseudo-inductance introduction strategy, the scale of pseudo-inductance introduction is reduced from O(Ng) in the traditional method to O(deg(k)), avoiding the construction and maintenance of the global pseudo-inductance matrix. In existing equivalent circuit transformation methods, five large matrices are required for data storage. The main source of memory optimization is the reduction in the size of the element_removed_mat, Mppmat, and Mpmmat matrices. The specific optimized storage calculation is as follows:

[0174] The space saved in the element_removed_mat matrix is ​​(k_link_num+1)*(ind_num_exit+ k_link_num)-(k_link_num + 2)*(cap_num + ind_num_exit + k_link_num + 1). Here, k_link_num is the number of adjacent cells to the cell k to be absorbed; ind_num_exit is the number of inductors remaining after absorbing cell k, where ind_num_exit = Mnum - k_link_num; and cap_num is the number of cells remaining after absorbing cell k, where cap_num = PPnum - 1.

[0175] The size of the Mppmat matrix called in existing algorithms is (cap_num + k_link_num) * (cap_num + k_link_num), while in the algorithm of this invention, it is reduced to k_link_num * k_link_num.

[0176] The size of the Mpmmat matrix in existing algorithms is (cap_num + k_link_num) * (ind_num_exit + ind_num_new + ind_num_comb), while in the algorithm of this invention, it is reduced to k_link_num * (ind_num_exit + ind_num_new + ind_num_comb).

[0177] Both ind_num_new and ind_num_comb are new inductors generated during the grid absorption process, but they are divided into ind_num_new (which cannot be merged with other inductors) and ind_num_comb (which can be merged with other inductors).

[0178] (2) Maintaining reduced-order accuracy: Through rigorous circuit equivalent transformation and branch merging, memory is reduced without introducing additional approximation errors. The maximum absolute error of the S-parameters is far better than the 0.05 error tolerance usually required for engineering applications, verifying the accuracy maintenance capability of the method of this invention in different topologies.

[0179] (3) Reduced computational complexity: The present invention omits the initialization step of the global pseudo-inductor network, avoiding the initialization overhead of O(Ng²), and the matrix update dimension is always less than or equal to that of the traditional method during the order reduction process, thus significantly reducing the overall computational load.

[0180] (4) Simplified process and strong applicability: This invention does not require the initialization and maintenance of a global pseudo-inductance network. After each iteration, the circuit is restored to the standard PEEC representation. The algorithm structure is clear and easy to implement. At the same time, branch merging and pseudo-inductance internalization are based on strict circuit equivalent transformation and do not depend on specific structural assumptions. They are applicable to the order reduction analysis of various PEEC models and have wide industrial applicability.

[0181] (5) Supports GPU parallel acceleration: The matrix outer product update operation of the branch merging process in this invention can be decomposed into multiple independent parallel tasks, which are suitable for acceleration on GPU and can make full use of the current mainstream computing hardware development trend.

[0182] Specifically, in this embodiment, order reduction verification was performed in the full-wave 5G MIMO antenna feed network structure:

[0183] This embodiment uses a full-wave 5G MIMO antenna feed network structure ( Figure 3 Taking a 5G MIMO antenna feed network structure as an example, the effectiveness of the method of the present invention is verified. 1. Example setup: This embodiment uses a full-wave 5G MIMO antenna feed network structure as the verification object. The structure is made of perfect inductor metal with no resistance loss, and a finite-size metal is added as a finite ground. To characterize the electromagnetic field and radiation effect of the circuit, the circuit includes capacitors and their losses, inductors and their losses, and radiation resistance. The PEEC model contains 866 nodes, 852 capacitors, 1167 inductors, and 7 ports. The frequency domain simulation parameter COND=0.02 is set, and the circuit model is generated using 3 frequency points (3.0 GHz, 3.5 GHz, 4.0 GHz) with a bandwidth of 0.5 GHz. The simulation frequency band is 3–4 GHz, and 351 frequency points are set for frequency sweeping with a frequency point interval of 0.01 GHz. 2. Comparison of order reduction effect: The original PEEC circuit is reduced in order using the method of the present invention. After the order reduction is completed, the circuit scale of the method of this invention is compared with that of the existing technology method (a micro-model order reduction method based on PEEC proposed by Dou and Wu) and the original PEEC model, as shown in Table 1.

[0184] Table 1 Circuit Dimensions;

[0185]

[0186] Specifically, as shown in Table 1, the circuit size after order reduction using the method of this invention is comparable to that of the prior art method, with the number of nodes reduced from 866 to 434, resulting in an order reduction ratio of approximately 2.0 times. To verify the accuracy of the method of this invention, 351 frequency points were set within the 3–4 GHz band for frequency sweeping, and comparison graphs of the S-parameter amplitude, phase, and absolute error of the prior art method, the method of this invention, and the original PEEC model were plotted, as shown in Figures 4(a)-(c). The results show that the S-parameter accuracy of the method of this invention is superior to that of the prior art method within the 3–4 GHz band. The maximum absolute error of S11, S12, S21, and S22 within the 3–4 GHz band is ≤4.7×10⁻⁴, and the average error is ≤1.7221×10⁻⁴. Compared with the prior art method, the improvement in the maximum average error is greater than 3.3×10⁻³.

[0187] Specifically, the memory usage analysis uses the first rectangular grid absorbed in the verification case as an example to analyze the difference in memory usage between the method of this invention and existing technologies. Each matrix stores single-precision complex numbers, and each element occupies 8 bytes of memory.

[0188] Table 2. Comparison of Memory Reduction Percentage;

[0189]

[0190] Specifically, as shown in Table 2, during the absorption of the first grid, the method of this invention reduces memory usage by approximately 45.14% in total, with the reduction of the Mppmat and Mpmmat matrices being the main source of memory optimization. This result effectively verifies the significant effect of the method of this invention in alleviating the memory bottleneck during the equivalent circuit transformation of the PEEC model.

[0191] Specifically, computational efficiency analysis reveals that, in addition to its advantage in memory usage, the method of this invention also shows significant improvement in computational efficiency. The existing global pre-setting step requires initializing Ng pseudo-inductors and updating the corresponding mutual coupling terms, with a complexity of O(Ng²). This invention completely omits this step. During node elimination, the computational cost of a single iteration mainly comes from updating the matrix outer product Z^'=Z+cxy^T during branch merging, with a complexity of O(m²), where m is the current matrix order. Since the matrix order of the method in this invention is always smaller than that of the existing method (without adding global pseudo-inductors), the overall computational cost is correspondingly reduced. The comprehensive simulation results of this embodiment show that, within the set frequency band, the absolute error of the S-parameters is much less than 0.05, meeting the engineering target of "absolute error <0.05"; during the absorption of the first grid, the memory usage is reduced by approximately 45%, successfully alleviating the memory bottleneck in the PEEC model order reduction process; simultaneously, this method possesses good scalability, laying the algorithmic foundation for further large-scale PEEC model order reduction efficiency optimization.

[0192] In summary, the core innovations of this invention compared to existing technologies can be summarized as follows:

[0193] Innovation Point 1: Localized pseudo-inductance introduction strategy.

[0194] Existing technologies pre-install pseudo-inductors globally for all grounding ports in the initial stage of order reduction, with an introduction scale of O(Ng). This invention, through experiments, found that pseudo-inductors are only used to ensure circuit equivalence during the absorption process of local nodes, and global pre-installation is not necessary. Based on this, this invention proposes to temporarily construct pseudo-inductor branches only for the adjacent ordinary capacitor branches when absorbing the least important node, reducing the introduction scale to O(deg(k)). This "on-demand introduction" strategy is the core innovation of this invention.

[0195] Innovation Point Two: The instant internalization mechanism for eliminating pseudo-inductance.

[0196] Existing technologies only internalize pseudo-inductors after all order reduction steps are completed, resulting in the persistent presence of pseudo-inductor state variables throughout the entire reduction process. This invention, however, immediately internalizes the pseudo-inductance in temporary pseudo-inductor branches into ordinary inductors after each round of node absorption, ensuring that the circuit reverts to a standard PEEC network free of pseudo-inductors after each iteration. This "instant elimination" mechanism prevents the accumulation of pseudo-inductance during the iteration process.

[0197] Innovation Point 3: The technology of merging ordinary capacitor branches and temporary pseudo-inductor branches

[0198] In existing technologies, branch merging occurs between two pseudo-inductor branches (a globally preset pseudo-inductor and a newly generated pseudo-inductor). This invention omits the global preset step, transforming the branch merging object into a regular capacitor branch and a temporary pseudo-inductor branch. For this new merging scenario, this invention fully derives the corresponding impedance merging formula and coupling parameter update formula, forming a complete theoretical system.

[0199] Innovation Point 4: Significant Memory Optimization Effect

[0200] Through the synergistic effect of the three innovations mentioned above, this invention reduces the intermediate matrix dimension from five complete matrices to two complete matrices plus three smaller matrices. Real-world testing data shows that, in the process of absorbing the first node, the memory savings rate in all embodiments is 45%, demonstrating significant optimization.

[0201] like Figure 5 As shown, this embodiment also discloses a PEEC micro-model order reduction system based on a local pseudo-inductance strategy, including:

[0202] Initialization module 91 is used to establish the PEEC equivalent circuit model and initialize the circuit matrix;

[0203] The filtering module 92 is used to take the nodes in the initialized circuit matrix as candidate nodes, calculate the low-frequency approximation error of each candidate node, and when the low-frequency approximation error of a candidate node is less than a preset threshold, filter out the candidate node that minimizes the low-frequency approximation error and record it as the least important node.

[0204] Temporary branch construction module 93 is used to remove the least important node from the circuit matrix, update the circuit matrix elements through circuit equivalent transformation, and temporarily construct a parallel pseudo-inductor branch for the adjacent ordinary capacitor branch of the least important node.

[0205] The parallel module 94 is used to combine adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches to obtain an equivalent pseudo-inductor branch, and synchronously update the coupling relationship between inductors / capacitors in the equivalent pseudo-inductor branch and the other pseudo-inductor branches.

[0206] The update module 95 is used to internalize the pseudo-inductance in the updated equivalent pseudo-inductance branch into a normal inductance, so that the equivalent pseudo-inductance branch is restored to a normal capacitor branch, and the updated equivalent circuit is obtained.

[0207] The order reduction judgment module 96 is used to determine whether the low-frequency approximation error of all candidate nodes in the updated equivalent circuit is greater than the preset threshold. If so, the order reduction is terminated and the reduced micro-model circuit is obtained; otherwise, it returns to the filtering module to continue execution.

[0208] A specific implementation of a PEEC micromodel order reduction system based on a local pseudo-inductance strategy is described in this embodiment. The same PEEC micromodel order reduction method based on a local pseudo-inductance strategy will not be described again in this embodiment.

[0209] Although the invention has been specifically shown and described in conjunction with preferred embodiments, those skilled in the art should understand that various changes in form and detail may be made to the invention without departing from the spirit and scope of the invention as defined in the appended claims, all of which shall be within the scope of protection of the invention.

Claims

1. A method for order reduction of PEEC micromodels based on a local pseudo-inductance strategy, characterized in that, Includes the following steps: S1. Establish the PEEC equivalent circuit model and initialize the circuit matrix; S2, take the nodes in the initialized circuit matrix as candidate nodes, calculate the low-frequency approximation error of each candidate node, and when the low-frequency approximation error of a candidate node is less than the preset threshold, select the candidate node that minimizes the low-frequency approximation error and record it as the least important node. S3, remove the least important node from the circuit matrix, temporarily construct a parallel pseudo-inductor branch for the adjacent ordinary capacitor branch of the least important node, and update the circuit matrix elements through circuit equivalent transformation. S4, and combine and adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches to obtain equivalent pseudo-inductor branches, and synchronously update the coupling relationship between inductors / capacitors in the equivalent pseudo-inductor branches and other pseudo-inductor branches. S5, internalize the pseudo-inductance in the updated equivalent pseudo-inductance branch into a normal inductance, so that the equivalent pseudo-inductance branch is restored to a normal capacitor branch, and the updated equivalent circuit is obtained. S6, determine whether the low-frequency approximation error of all candidate nodes in the updated equivalent circuit is greater than the preset threshold. If yes, the order reduction ends and the reduced micro-model circuit is obtained; otherwise, return to S2 to continue execution.

2. The PEEC micro-model order reduction method based on the local pseudo-inductance strategy according to claim 1, characterized in that, In S2, the low-frequency approximation error is calculated using the following formula: ； in, The highest relevant frequency; This represents the number of nodes connected to candidate node k. and Let represent the changes in inductance and capacitance of the i-th associated branch after eliminating candidate node k, respectively; This indicates the low-frequency approximation error.

3. The PEEC micro-model order reduction method based on the local pseudo-inductance strategy according to claim 1, characterized in that, In S3, updating the circuit matrix elements includes updating the temporary pseudo-inductor branch matrix elements, and the calculation formula is as follows: ； ； ； ； in, This indicates the coupling between the pseudo-inductor and the other ordinary inductors in the newly added pseudo-inductor branch after power conversion. This indicates the coupling between the inductance of adjacent nodes and the other ordinary inductances before the circuit transformation; This indicates the self-coupling of the pseudo-inductor in the newly added pseudo-inductor branch after circuit transformation; This indicates the self-coupling of inductance between adjacent nodes before the circuit transformation; This indicates the coupling between the capacitor and other capacitors in the newly added pseudo-inductor branch after the circuit transformation; This represents the coupling between the ordinary capacitor and other capacitors connected to the candidate node k before the circuit transformation. This indicates the self-coupling of the capacitor in the newly added pseudo-inductor branch after the circuit transformation; This represents the self-coupling of the ordinary capacitor connected to candidate node k before the circuit transformation; Indicates the first The physical quantity corresponding to each frequency component; Indicates the number of adjacent nodes; for A column vector of all 1s; for The identity matrix.

4. The PEEC micromodel order reduction method based on the local pseudo-inductance strategy according to claim 1, characterized in that, In S4, the calculation formula is as follows, combining the adjacent ordinary capacitor branch and the temporarily constructed pseudo-inductor branch: ； ； in, and These represent the equivalent capacitance and pseudo-inductance parameters of the merged branch, respectively. Indicates the current frequency These are the first equivalent transformation coefficients; e4 is the first intermediate calculation parameter; e4 is the fourth intermediate calculation parameter. These are intermediate parameters related to the first frequency.

5. The PEEC micromodel order reduction method based on the local pseudo-inductance strategy according to claim 1, characterized in that, In S4, the coupling relationship between inductors and capacitors in the equivalent pseudo-inductor branch and other pseudo-inductor branches is updated synchronously. The calculation formula is as follows: ； ； in, and This is a constant during the transformation of the microcircuit model; This is to couple the capacitance of the equivalent pseudo-inductor branch after merging with the capacitance of the other pseudo-inductor branches; This is to couple the capacitors in the S branch before merging with the capacitors in the other pseudo-inductor branches. This is to couple the capacitors in branch I before merging with the capacitors in the remaining pseudo-inductor branches. To combine the inductance of the equivalent pseudo-inductance branch with the coupling of the inductance in other pseudo-inductance branches; To couple the inductance of the S branch before merging with the inductance in the other pseudo-inductor branches; It is the coupling between the inductance of branch I before merging and the inductance in the other pseudo-inductor branches.

6. The PEEC micromodel order reduction method based on the local pseudo-inductance strategy according to claim 1, characterized in that, In S5, the pseudo-inductance in the updated equivalent pseudo-inductance branch is internalized as a normal inductance. Specifically, the pseudo-inductance component in the equivalent pseudo-inductance branch is converted into an equivalent normal inductance component, and its coupling relationship is transferred to the normal inductance matrix, so that the branch is restored to a normal capacitor branch that only includes capacitance characteristics.

7. A PEEC micro-model order reduction system based on a local pseudo-inductance strategy, characterized in that, include: The initialization module is used to establish the PEEC equivalent circuit model and initialize the circuit matrix. The filtering module is used to select nodes in the initialized circuit matrix as candidate nodes, calculate the low-frequency approximation error of each candidate node, and filter out the candidate node that minimizes the low-frequency approximation error when the low-frequency approximation error of a candidate node is less than a preset threshold. This candidate node is then denoted as the least important node. The temporary branch construction module is used to remove the least important node from the circuit matrix, temporarily construct a parallel pseudo-inductor branch for the adjacent ordinary capacitor branch of the least important node, and update the circuit matrix elements through circuit equivalent transformation. The parallel module is used to combine adjacent ordinary capacitor branches and temporarily constructed pseudo-inductor branches to obtain an equivalent pseudo-inductor branch, and synchronously update the coupling relationship between inductors / capacitors in the equivalent pseudo-inductor branch and the other pseudo-inductor branches. The update module is used to internalize the pseudo-inductance in the updated equivalent pseudo-inductance branch into a normal inductance, so that the equivalent pseudo-inductance branch is restored to a normal capacitor branch, and the updated equivalent circuit is obtained. The order reduction judgment module is used to determine whether the low-frequency approximation error of all candidate nodes in the updated equivalent circuit is greater than a preset threshold. If so, the order reduction is terminated, and the reduced micro-model circuit is obtained; otherwise, the process returns to the filtering module to continue execution.

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