Schematic diagram symbol, schematic diagram generation method, circuit pre-simulation method and medium

Abstract

The application provides a schematic diagram symbol and a schematic diagram generation method, a circuit front simulation method and a medium. The schematic diagram symbol generation method comprises the following steps: confirming a circuit unit to be added to a schematic diagram and confirming whether the circuit unit exists in a preset layout library; if the circuit unit exists in the layout library, obtaining an area of the circuit unit in the layout library as a first area, and generating a first schematic diagram symbol in the schematic diagram based on the first area; if the circuit unit does not exist in the layout library, obtaining a total area of a second subunit and a third subunit as a second area and a third area, and generating the first schematic diagram symbol in the schematic diagram based on the sum of the second area and the third area. The size of the schematic diagram symbol generated by the scheme is close to the shape of the real layout size, the RC delay between modules can be more accurately estimated, and the required area of the chip can be estimated; and the automatic generation of the schematic diagram symbol can also shorten the design time.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular to a schematic symbol and a method for generating schematic diagrams, a pre-simulation method for circuits, and a dielectric. Background Technology

[0002] Before designing a circuit layout, pre-layout simulation is performed based on the existing circuit schematic to determine if the schematic design conforms to standards. A circuit schematic is a visual and effective representation of the electronic circuit structure. A schematic typically includes schematic symbols, the layout of the symbols, and the connections between them. In chip design, schematic symbols are a visual representation of the size and electrical connections of each module (also called a circuit cell).

[0003] During the design process, chip design engineers often need to manually draw schematic symbols as rectangles or squares. Their size usually cannot accurately reflect the actual size of the module, and the distance between modules cannot be accurately estimated. Therefore, the RC delay between modules cannot be accurately added or estimated. In the next stage of chip design, the pre-simulation cannot closely match the actual delay of the post-simulation.

[0004] Existing technologies suggest that the size of the schematic symbol corresponding to a circuit unit can be determined by the layout, but this method relies too much on layout information and cannot handle the case where there is no corresponding circuit unit in the layout.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] One of the objectives of this invention is to provide a method for generating schematic symbols that can accurately reflect the true size of a module, so that chip engineers can place the positions of each symbol according to its actual size, and the RC delay between symbols can be simulated through calculation, thereby improving the accuracy of subsequent pre-simulation delay.

[0007] To address the aforementioned issues, firstly, a method for generating schematic symbols is provided, comprising the following steps: S1. Confirm the circuit unit to be added to the schematic; S2. Confirm whether the circuit unit exists in the preset layout library. If it exists, proceed to step S3; otherwise, proceed to step S4. S3. Obtain the area of ​​the circuit unit in the layout library as the first area, and generate a first schematic symbol in the schematic diagram based on the first area; S4. Obtain the total area of ​​the second sub-unit and the third sub-unit as the second area and the third area, and generate a first schematic symbol in the schematic diagram based on the sum of the second area and the third area; wherein, the second sub-unit and the third sub-unit are respectively the first sub-unit existing in the layout library and the first sub-unit not existing in the layout library, the first sub-unit is the next level sub-unit constituting the circuit unit; the second area is the sum of the areas of all the second sub-units in the layout library; the third area is the sum of the areas of the basic devices constituting all the third sub-units.

[0008] In step S3, when the circuit unit only includes active devices, the process of obtaining the first area includes: obtaining the layout corresponding to the circuit unit from the layout library, and obtaining the first area based on the area of ​​the active layer in the layout; in step S3, when the circuit unit also includes passive devices, the process of obtaining the first area includes: obtaining the layout corresponding to the circuit unit from the layout library, and obtaining the first area based on the areas of the active layer and the passive device layer in the layout, wherein the passive device layer is the layer where the passive device is located.

[0009] In step S3, the process of determining the first area includes: obtaining the layer coordinates of all the active layers and all the passive device layers; performing an OR operation on all the layer coordinates to obtain the first area.

[0010] Step S4 includes: S401, confirming the first sub-unit corresponding to the circuit unit based on a preset schematic library, wherein the first sub-unit is a sub-unit of the next level constituting the circuit unit; S402, confirming whether the first sub-unit exists in the schematic library, if it exists, it is used as the second sub-unit, otherwise it is used as the third sub-unit; S403, obtaining the total area of ​​the second sub-unit in the schematic library as the second area; determining all basic components constituting each third sub-unit based on the schematic library, and calculating the sum of the areas of all the basic components to obtain the third area; generating a first schematic symbol in the schematic based on the sum of the second area and the third area.

[0011] In step S403, the process of obtaining the second area includes: when the second sub-unit only includes active devices, obtaining the layout corresponding to the second sub-unit from the layout library, and obtaining the second area based on the area of ​​the active layer in the layout; when the second sub-unit also includes passive devices, obtaining the layout corresponding to the second sub-unit from the layout library, and obtaining the second area based on the areas of the active layer and the passive device layer in the layout, wherein the passive device layer is the layer where the passive device is located.

[0012] In step S403, the process of obtaining the third area includes: traversing all the basic devices constituting each third sub-unit; calculating the area of ​​each basic device and summing them to obtain the third area.

[0013] When the basic device is a transistor, the area of ​​the basic device is calculated using a first formula: S = L1 * H; L1 = a1*2 + each_m*each_l + (each_l+1)*a2 + 2*a3 + 2*each_m*a4; where S is the area of ​​the basic device, L1 is the length of the transistor, H is the elevation of the transistor, a1 is the distance from the center point of the virtual gate to the edge of the active region, each_m is the number of unit transistors in the transistor, each_l is the length of the unit transistor, a2 is the width of the contact hole, a3 is the minimum distance from the edge of the contact hole to the edge of the active region, and a4 is the minimum distance from the edge of the contact hole to the edge of the gate. When the basic component is a resistor, the area of ​​the basic component is calculated using the second formula: S = W * L2; R_total = R_square * (L2 / W); where S is the area of ​​the basic component, W is the width of the resistor, L2 is the length of the resistor, R_square is the square resistance of the resistor, and R_total is the resistance of the resistor. When the basic component is a capacitor, the area of ​​the basic component is calculated using a third formula: S = C_total / C0; where S is the area of ​​the basic component, C_total is the capacitance value of the capacitor, and C0 is the capacitance value per unit area corresponding to the process layer where the capacitor is located.

[0014] Secondly, this application also provides another method for generating schematic symbols, including the following steps: S10. Confirm the circuit unit to be added to the schematic diagram, and break the circuit unit into a first sub-unit. The first sub-unit is the next level sub-unit that constitutes the circuit unit. S20. Confirm whether the first sub-unit exists in the preset layout library. If it exists, it is used as the second sub-unit; if it does not exist, it is used as the third sub-unit. S30. Obtain the area of ​​each second subunit in the layout library as the fourth area; based on the preset schematic library, recursively search with the third subunit as the top layer to determine all basic components constituting each third subunit, and calculate the sum of the areas of all basic components constituting each third subunit to obtain the fifth area. S40. Based on the fourth area, generate a second schematic symbol corresponding to each of the second sub-units in the schematic diagram, and based on the fifth area, generate a third schematic symbol corresponding to each of the third sub-units in the schematic diagram.

[0015] Thirdly, this application also provides a method for generating a schematic diagram, wherein when drawing the schematic diagram, a schematic diagram symbol is generated in the schematic diagram based on a method for generating schematic diagram symbols according to any one of the first or second aspects.

[0016] Fourthly, this application also provides a circuit pre-simulation method, including: A schematic diagram is generated according to a schematic diagram generation method described in the third aspect; Add a parasitic effect circuit to the schematic diagram to generate the pre-simulation circuit structure; Pre-simulation is performed based on the aforementioned pre-simulation circuit structure.

[0017] Fifthly, this application also provides a computer medium storing a computer program, which, when executed by a processor, implements the steps of a method for generating schematic symbols according to any one of the first or second aspects.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) The size of the schematic symbol is close to the size of the actual layout, which can more accurately predict the RC delay between modules; 2) The required area of ​​the chip can be estimated by the actual symbol size; 3) By breaking down the selected modules, the connection between the next layer modules can be analyzed more accurately and the RC size between them can be pre-evaluated; 4) Automated symbols can shorten the design time; 5) It can handle the situation where there is no corresponding layout for the circuit unit, and has a wider range of applications. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This invention provides a flowchart of a method for generating schematic symbols.

[0021] Figure 2 This is the layout corresponding to a circuit unit provided by the present invention.

[0022] Figure 3 The schematic symbol for generating a circuit unit provided by the present invention.

[0023] Figure 4 A schematic diagram of a transistor structure provided for this invention. Detailed Implementation

[0024] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0025] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0026] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0027] Example 1 like Figure 1 The diagram shown is a flowchart of a method for generating schematic symbols according to the present invention. (Reference) Figure 1This invention provides a method for generating schematic symbols, comprising the following steps: S1, confirming the circuit unit to be added to the schematic; S2, confirming whether the circuit unit exists in a preset layout library; if it exists, proceed to step S3, otherwise proceed to step S4; S3, obtaining the area of ​​the circuit unit in the layout library as a first area, and generating a first schematic symbol in the schematic based on the first area; S4, obtaining the total area of ​​the second sub-unit and the third sub-unit as the second area and the third area, and generating a first schematic symbol in the schematic based on the sum of the second area and the third area; wherein, the second sub-unit and the third sub-unit are respectively the first sub-unit existing in the layout library and the first sub-unit not existing in the layout library, the first sub-unit being the next level sub-unit constituting the circuit unit; the second area is the sum of the areas of all second sub-units in the layout library; the third area is the sum of the areas of the basic devices constituting all third sub-units.

[0028] Specifically, in this first embodiment, a method for generating schematic symbols is provided, including the following steps: Step S1: Confirm the circuit unit to be added to the schematic; As we can understand, a schematic diagram is a way to represent the structure of an electronic circuit. A schematic diagram typically includes schematic symbols, the layout of these symbols, and the connections between them. When drawing or creating schematic symbols, it is necessary to first confirm and select the corresponding circuit units.

[0029] Step S2: Confirm whether the circuit unit exists in the preset layout library. If it exists, proceed to step S3; otherwise, proceed to step S4. In this embodiment, a preset layout library is provided, which stores a large amount of layout data. By searching and comparing within the layout library, it can be determined whether the layout of the circuit unit in question exists in the library. Different processing can be performed based on the comparison result: if it exists in the layout library, a schematic symbol can be generated using the actual area of ​​the corresponding layout; if it does not exist, an area can be obtained through a specific calculation method to generate a schematic symbol, which will be detailed below.

[0030] In this embodiment, the presence of a circuit unit in a preset layout library can be determined by automated scripts or manual checks.

[0031] Step S3: Obtain the area of ​​the circuit unit in the layout library as the first area, and generate the first schematic symbol in the schematic diagram based on the first area; If, in step S2 above, a layout for the desired circuit unit is found in the layout library, a schematic symbol can be generated based on the actual layout size. In this case, the schematic symbol can be generated directly by reading the top-level layout corresponding to the circuit unit. This makes it easy to know the actual area of ​​each circuit unit, allowing designers to lay out the circuit near the top layer based on its actual area, thus giving greater freedom in the layout of the top-level circuit units of the product.

[0032] It is understandable that the schematic symbols generated above can be placed according to the selected target circuit unit's position on the circuit layout, or according to the ideal position of the circuit schematic (such as placing the circuit units from left to right), giving the designer the initiative to place the schematic symbols.

[0033] For details, please refer to Figure 2 The diagram shows the layout of a circuit unit in the layout library. In step S3, when the circuit unit only includes active devices, the process of obtaining the first area includes: obtaining the layout corresponding to the circuit unit in the layout library, and obtaining the first area based on the area of ​​the active layer in the layout; in step S3, when the circuit unit also includes passive devices, the process of obtaining the first area includes: obtaining the layout corresponding to the circuit unit in the layout library, and obtaining the first area based on the areas of the active layer and the passive device layer in the layout, where the passive device layer is the layer where the passive device is located. An example of calculating the area in the layout is: obtaining the layer coordinates of all active layers and all passive device layers; performing an OR operation on all layer coordinates to obtain the first area.

[0034] It is understandable that the above process can be implemented through automated scripts. For example, once the layout of a circuit unit is found, the corresponding first area can be obtained by automatically selecting (by default, selecting a certain layer of the layout) or manually selecting the target layer. For example, the active layer of the layout can be selected as the target layer by default. After automatically reading the layer coordinates of the active layer, the coordinates containing the active layer can be connected to form one or more shapes through shape OR operations. The shape of such one or more shapes will be the physical size of the actual module, and the result is as follows. Figure 3 As shown. Of course, if the actual area also needs to cover passive devices, then the layer name of the passive device (i.e., the passive device layer, such as the identification layer of the corresponding capacitor, CP layer) needs to be provided and its layer coordinates obtained, and then ORed with the previous active layer coordinates.

[0035] Step S4: Obtain the total area of ​​the second sub-unit and the third sub-unit as the second area and the third area, and generate the first schematic symbol in the schematic diagram based on the sum of the second area and the third area; If, in step S2, it is found that the layout of the circuit unit in this application does not exist in the layout library, then the schematic symbol of the corresponding size cannot be obtained with the help of the layout information. Therefore, in this application, the information of each sub-unit can be read according to the schematic of the selected circuit unit, and combined with the calculation method shown below, an area is obtained to generate a schematic symbol of the corresponding actual physical size.

[0036] Specifically, step S4 includes: Step S401: Based on the preset schematic library, confirm the first sub-unit corresponding to the circuit unit. The first sub-unit is the next level sub-unit that constitutes the circuit unit. As we can understand it, a circuit cell is a module in a circuit that has a specific function, and it will be displayed as a schematic symbol in a schematic diagram. Typically, circuit cells have a multi-level structure, with each higher-level cell possibly composed of multiple lower-level sub-cells, and so on, down to the smallest level. The smallest-level sub-cells are usually basic components, including active devices (such as PMOS or NMOS) and passive devices (such as resistors and capacitors). For a circuit cell, there may not be a corresponding layout, but there must be a corresponding schematic diagram. Therefore, the schematic diagram corresponding to this circuit cell can be obtained from a schematic library (i.e., a pre-defined database containing schematic diagrams) to identify its next-level sub-cell, which is denoted as the first sub-cell.

[0037] Step S402: Confirm whether the first sub-unit exists in the layout library. If it exists, it is used as the second sub-unit; if it does not exist, it is used as the third sub-unit. The first subunit can be further divided into two categories: the second subunit, which is the part of the first subunit that exists in the aforementioned map library; and the third subunit, which is the part of the first subunit that does not exist in the aforementioned map library.

[0038] It is understandable that the distinction between the second and third sub-units is whether they exist in the layout library, and how to confirm this can be done by referring to step S2 above.

[0039] Furthermore, for the second sub-unit, its area can be obtained by referring to step S3 above; while for the third sub-unit, an additional method is required to obtain its area, which will be detailed below.

[0040] Step S403: Obtain the total area of ​​the second sub-unit in the layout library as the second area; determine the basic components constituting each third sub-unit based on the schematic library, and calculate the sum of the areas of all basic components to obtain the third area; generate the first schematic symbol in the schematic based on the sum of the second and third areas.

[0041] Specifically, the method for obtaining the second area is as follows: In step S403, when the second sub-unit only includes active devices, the layout corresponding to the second sub-unit is obtained from the layout library, and the second area is obtained based on the area of ​​the active layer in the layout. When the second sub-unit also includes passive devices, the layout corresponding to the second sub-unit is obtained from the layout library, and the second area is obtained based on the area of ​​the active layer and the passive device layer in the layout, where the passive device layer is the layer where the passive device is located.

[0042] Understandably, users can determine whether to use active or passive layers to obtain the corresponding area, or which active / passive layers to use to obtain the corresponding area, as needed.

[0043] Specifically, obtaining the third area requires the help of the basic components that constitute the third unit. Therefore, based on the corresponding schematic diagram, we can recursively query all the basic components included under the third unit to traverse all the basic components constituting each third sub-unit; calculate the area of ​​each basic component and sum them to obtain the third area. This typically includes the following categories: 1) When the basic device of the third sub-unit is a transistor (i.e., PMOS or NMOS), the area reference value of the third sub-unit can be calculated based on the total length * elevation.

[0044] Specifically, refer to Figure 4 As shown, the area is calculated using the first formula, which is: S = L1 * H; L1=a1*2+each_m*each_l+(each_l+1)*a2+2*a3+2*each_m*a4; Where S is the area of ​​the basic device, L1 is the length of the transistor, H is the elevation of the transistor, a1 is the distance from the center point of the virtual gate to the edge of the active region, each_m is the number of unit transistors in the transistor, each_l is the length of the unit transistor, a2 is the width of the contact hole, a3 is the minimum distance from the edge of the contact hole to the edge of the active region, and a4 is the minimum distance from the edge of the contact hole to the edge of the gate. In this embodiment, the distance a1 from the center point of the virtual gate to the edge of the active region is 0.07. This value will vary depending on the manufacturing process.

[0045] When the basic component is a resistor, the area of ​​the basic component is calculated using the second formula, which is: S = W * L2; R_total = R_square * (L2 / W); Where S is the area of ​​the basic component, W is the width of the resistor, L2 is the length of the resistor, R_square is the square resistance of the resistor, and R_total is the resistance of the resistor. When the basic component is a capacitor, the area of ​​the basic component is calculated using the third formula, which is: S = C_total / C0; Where S is the area of ​​the basic device, C_total is the capacitance value of the capacitor, and C0 is the capacitance value per unit area corresponding to the process layer where the capacitor is located. The unit capacitance value C0 is related to the specific process of each project.

[0046] In this solution, by combining two dimensions, the size of the final schematic symbol is determined to be the physical size of the actual circuit unit. If the layout of the selected circuit unit exists, the schematic symbol size is generated based on the actual layout size; if the layout of the selected circuit unit does not exist, the schematic symbol size is estimated. This addresses the issue of existing technologies where circuit units do not have corresponding layouts.

[0047] Example 2 In this second embodiment, a method for generating schematic symbols is provided, including the following steps: S10. Confirm the circuit unit to be added to the schematic diagram, and break the circuit unit into the first sub-unit. The first sub-unit is the next level of sub-unit that constitutes the circuit unit. S20. Confirm whether the first sub-unit exists in the preset layout library. If it exists, it is used as the second sub-unit; if it does not exist, it is used as the third sub-unit. S30. Obtain the area of ​​each second subunit in the layout library as the fourth area; based on the preset schematic library, recursively search with the third subunit as the top layer to determine all the basic devices that constitute each third subunit, and calculate the sum of the areas of all the basic devices that constitute each third subunit to obtain the fifth area. S40. Generate a second schematic symbol corresponding to each second sub-unit in the schematic diagram based on the fourth area, and generate a third schematic symbol corresponding to each third sub-unit in the schematic diagram based on the fifth area.

[0048] The method for generating schematic symbols in this embodiment is similar to that in Embodiment 1. The main difference is that a complete circuit unit is first broken down into the first sub-unit of the next level, so that the area of ​​each sub-unit below the top-level circuit unit can be known more accurately.

[0049] For each first sub-unit obtained by splitting, the individual area can be obtained by referring to steps S402 to S403 in Embodiment 1 (because it is not necessary to obtain the area of ​​the circuit unit, the area of ​​each first sub-unit is calculated separately, and the sum of the areas is not required).

[0050] Example 3 This embodiment provides a method for generating a schematic diagram. When drawing the schematic diagram, based on the method for generating schematic diagram symbols provided in Embodiment 1 or Embodiment 2 above, schematic diagram symbols are generated in the schematic diagram to finally obtain a schematic diagram.

[0051] Example 4 This fourth embodiment provides a circuit pre-simulation method, including: A schematic diagram is generated according to a schematic diagram generation method in Embodiment 3; Add parasitic effect circuitry to the schematic diagram to generate the pre-simulation circuit structure; Pre-simulation is performed based on the pre-simulation circuit structure.

[0052] In this approach, since schematic symbols of actual size can be created, chip engineers can place the positions of each module according to the actual size within the limited space of the chip, and add parasitic effect circuits accordingly. As a result, the RC delay between them can be simulated by calculation, which ultimately helps to improve the accuracy of the pre-simulation delay in the next stage.

[0053] Example 5 Embodiment 5 of this application provides a computer device for implementing the steps of the above-described method for generating schematic symbols, or the steps of the above-described method for generating schematic symbols. This computer device may include: a processor, a communications interface, a memory, and a communication bus. The processor, communications interface, and memory communicate with each other via the communication bus. The processor can call logical instructions from the memory. These logical instructions can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0054] Example 6 Embodiment 6 of this application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer is able to perform the steps of the above-described method for generating schematic symbols, or the steps of the above-described method for generating schematic symbols.

[0055] Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. Based on this understanding, the technical solution described above, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of the various embodiments or certain portions of the embodiments.

[0056] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0057] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for generating schematic symbols, characterized in that, Includes the following steps: S1. Confirm the circuit unit to be added to the schematic; S2. Confirm whether the circuit unit exists in the preset layout library. If it exists, proceed to step S3; otherwise, proceed to step S4. S3. Obtain the area of ​​the circuit unit in the layout library as the first area, and generate a first schematic symbol in the schematic diagram based on the first area; S4. Obtain the total area of ​​the second sub-unit and the third sub-unit as the second area and the third area, and generate a first schematic symbol in the schematic diagram based on the sum of the second area and the third area; wherein, the second sub-unit and the third sub-unit are respectively the first sub-unit existing in the layout library and the first sub-unit not existing in the layout library, the first sub-unit is the next level sub-unit constituting the circuit unit; the second area is the sum of the areas of all the second sub-units in the layout library; the third area is the sum of the areas of the basic devices constituting all the third sub-units.

2. The method for generating schematic symbols according to claim 1, characterized in that, In step S3, when the circuit unit only includes active devices, the process of obtaining the first area includes: obtaining the layout corresponding to the circuit unit from the layout library, and obtaining the first area based on the area of ​​the active layer in the layout; In step S3, when the circuit unit further includes passive devices, the process of obtaining the first area includes: obtaining the layout corresponding to the circuit unit from the layout library, and obtaining the first area based on the area of ​​the active layer and the passive device layer in the layout, wherein the passive device layer is the layer where the passive device is located.

3. The method for generating schematic symbols according to claim 2, characterized in that, In step S3, the process of determining the first area includes: Obtain the layer coordinates of all active layers and all passive device layers; The first area is obtained by performing an OR operation on all the layer coordinates.

4. The method for generating schematic symbols according to claim 1, characterized in that, Step S4 includes: S401. Based on a preset schematic library, the first sub-unit corresponding to the circuit unit is identified. The first sub-unit is the next level sub-unit that constitutes the circuit unit. S402. Confirm whether the first sub-unit exists in the layout library. If it exists, it is used as the second sub-unit; if it does not exist, it is used as the third sub-unit. S403. Obtain the total area of ​​the second subunit in the schematic library as the second area; determine all basic devices constituting each third subunit based on the schematic library, and calculate the sum of the areas of all the basic devices to obtain the third area; generate a first schematic symbol in the schematic based on the sum of the second area and the third area.

5. The method for generating schematic symbols according to claim 4, characterized in that, In step S403, the process of obtaining the second area includes: When the second subunit only includes active devices, the layout corresponding to the second subunit is obtained from the layout library, and the second area is obtained based on the area of ​​the active layer in the layout. When the second subunit also includes a passive device, the layout corresponding to the second subunit is obtained from the layout library, and a second area is obtained based on the area of ​​the active layer and the passive device layer in the layout, wherein the passive device layer is the layer where the passive device is located.

6. The method for generating schematic symbols according to claim 4, characterized in that, In step S403, the process of obtaining the third area includes: Iterate through all the basic components that constitute each of the third sub-units; The area of ​​each of the basic components is calculated separately and summed to obtain the third area.

7. The method for generating schematic symbols according to claim 6, characterized in that, When the basic device is a transistor, the area of ​​the basic device is calculated using a first formula, which is: S = L1 * H; L1=a1*2+each_m*each_l+(each_l+1)*a2+2*a3+2*each_m*a4; Where S is the area of ​​the basic device, L1 is the length of the transistor, H is the elevation of the transistor, a1 is the distance from the center point of the virtual gate to the edge of the active region, each_m is the number of unit transistors in the transistor, each_l is the length of the unit transistor, a2 is the width of the contact hole, a3 is the minimum distance from the edge of the contact hole to the edge of the active region, and a4 is the minimum distance from the edge of the contact hole to the edge of the gate. When the basic component is a resistor, the area of ​​the basic component is calculated using a second formula, which is: S = W * L2; R_total = R_square * (L2 / W); Where S is the area of ​​the basic component, W is the width of the resistor, L2 is the length of the resistor, R_square is the square resistance of the resistor, and R_total is the resistance of the resistor. When the basic component is a capacitor, the area of ​​the basic component is calculated using a third formula, which is: S = C_total / C0; Where S is the area of ​​the basic device, C_total is the capacitance value of the capacitor, and C0 is the capacitance value per unit area corresponding to the process layer where the capacitor is located.

8. A method for generating schematic symbols, characterized in that, Includes the following steps: S10. Confirm the circuit unit to be added to the schematic diagram, and break the circuit unit into a first sub-unit. The first sub-unit is the next level sub-unit that constitutes the circuit unit. S20. Confirm whether the first sub-unit exists in the preset layout library. If it exists, it is used as the second sub-unit; if it does not exist, it is used as the third sub-unit. S30. Obtain the area of ​​each second sub-unit in the layout library as the fourth area; Based on a preset schematic library, the third subunit is used as the top layer for recursive searching to determine all the basic components that constitute each third subunit, and the sum of the areas of all the basic components that constitute each third subunit is calculated to obtain the fifth area. S40. Based on the fourth area, generate a second schematic symbol corresponding to each of the second sub-units in the schematic diagram, and based on the fifth area, generate a third schematic symbol corresponding to each of the third sub-units in the schematic diagram.

9. A method for generating a schematic diagram, characterized in that, When drawing a schematic diagram, a schematic diagram symbol is generated in the schematic diagram based on a method for generating schematic diagram symbols according to any one of claims 1-8.

10. A circuit pre-simulation method, characterized in that, include: A schematic diagram generation method according to claim 9 generates a schematic diagram; Add a parasitic effect circuit to the schematic diagram to generate the pre-simulation circuit structure; Pre-simulation is performed based on the aforementioned pre-simulation circuit structure.

11. A computer medium, characterized in that, The computer medium stores a computer program, which, when executed by a processor, implements the steps in a method for generating schematic symbols according to any one of claims 1-8.

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