Method for true 3d multi-object layout driven core partition and physical implementation

Abstract

The application relates to the technical field of electronic design automation, in particular to a kind of chip partitioning and physical implementation method for true three-dimensional multi-objective layout driving. It includes: obtaining the synthesized gate-level netlist, and performing true three-dimensional multi-objective layout according to the synthesized gate-level netlist to obtain three-dimensional planning result;According to the three-dimensional planning result, obtain the standard delivery file, including the independent netlist file of each die, the initial layout file, the fixed HBT position and the timing constraint file;The delivery file package is input into the two-dimensional layout and routing tool to use the two-dimensional layout and routing tool to perform detailed layout, clock tree synthesis, routing, optimization and corner timing analysis of each die;And after the completion of the review of each die, assemble according to the global net ID and HBT coordinate, and perform review analysis after assembly. The application can solve the system problem of delivering three-dimensional layout result to the industrial back-end process.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a method for core partitioning and physical implementation driven by true 3D multi-objective layout. Background Technology

[0002] In the post-Moore's Law era, 2D chip interconnect latency and power consumption bottlenecks have become prominent, leading the industry to develop two technological directions: pseudo-3D stacking and true 3D placement driven by logic folding. Pseudo-3D processes divide the chip into functional modules before placement, but the partitioning algorithm struggles to fully perceive true 3D coordinates, critical paths, hybrid bonded terminal (HBT) congestion, or power density. True 3D architecture supports standard cell-level logic folding and free cross-layer placement, significantly shortening the critical path, but it has not yet fully solved the system problem of how to deliver the 3D placement results to the industrial back-end process. Summary of the Invention

[0003] The purpose of this invention is to provide a core partitioning and physical implementation method for true 3D multi-objective layout-driven systems, in order to solve the system problem of how to deliver 3D layout results to industrial back-end processes.

[0004] According to the present invention, a method for core-particle partitioning and physical implementation driven by true 3D multi-objective layout is provided, the method comprising the following steps:

[0005] S100: Obtain the synthesized gate-level netlist and perform true 3D multi-objective layout based on the synthesized gate-level netlist to obtain the 3D planning result; the 3D planning result includes the die allocation of each standard cell, the two-dimensional coordinates of each standard cell on the corresponding die, and the physical mapping from the cross-layer network to the hybrid bonding terminal HBT.

[0006] S200: Obtain standard delivery documents based on the 3D planning results; the standard delivery documents include independent netlist files for each die, initial layout files, fixed HBT locations, and timing constraint files; S200 includes: segmenting the 3D netlist at the HBT and generating consistent boundary constraints for each die; for each cross-die path, decomposing the path into transmit die segments, HBT parasitic segments, and receive die segments based on the 3D timing diagram; based on zero margin allocation and timing budget theory, the planner prioritizes protecting near-critical paths, allocating arrival times and required times for each HBT port in each mode and at each corner point; at the timing constraint level, assigning output delay or end-to-end maximum delay budget to the HBT ports of the transmit die, and assigning input delay, transition time, and load assumptions to the receive die ports; and treating cross-die clock skew, HBT parasitic uncertainty, and model errors after planning to routing as independent guard bands.

[0007] S300, the standard delivery package is input into the two-dimensional placement and routing tool to perform detailed placement, clock tree synthesis, routing, optimization, and signature timing analysis at corner points for each die; and after each die has been signed off, it is assembled according to the global net ID and HBT coordinates, and a post-assembly signature analysis is performed.

[0008] Compared with the prior art, the present invention has at least the following beneficial effects:

[0009] After obtaining the 3D planning results, this invention transforms the 3D planning results into a die-by-die netlist, an initial layout file, fixed HBT terminals, and timing constraint files, enabling different logic dies to be independently implemented by mature 2D placement and routing tools. Through post-assembly analysis (such as 3D static timing analysis and thermal analysis), a closed loop is formed, solving the system problem of delivering 3D layout results to the industrial back-end process.

[0010] Furthermore, this invention optimizes the process of obtaining 3D planning results: using standard cells as the basic object, it jointly optimizes line length, timing, 3D congestion, power density, terminal quantity, and area balance in a continuous (x,y,z) space; during the placement process, it explicitly models the capacity of hybrid bonding terminals, local density, and top-level metal access congestion, avoiding post-processing of terminal planning. Therefore, compared to existing technologies, this invention can perceive path-level timing, actual geometric distance, area balance of each die, wiring capacity, power density, vertical thermal coupling, and the number and spatial distribution of hybrid bonding interconnects during the placement and die (i.e., bare die) partitioning process, performing terminal capacity checks and cross-layer mesh to terminal allocation, resulting in high-quality 3D planning results that take into account bus length, critical path timing, global and local wiring congestion, vertical HBT terminal density distribution, inter-die power density, and inter-die area balance. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart of a core partitioning and physical implementation method driven by true 3D multi-object layout provided in an embodiment of the present invention;

[0013] Figure 2 This is a flowchart illustrating the true 3D multi-object layout process provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] According to this embodiment, a method for core-particle partitioning and physical implementation driven by true 3D multi-objective layout is provided. The method includes the following steps, such as... Figure 1 As shown:

[0016] S100: Obtain the synthesized gate-level netlist and perform true 3D multi-objective layout based on the synthesized gate-level netlist to obtain the 3D planning result; the 3D planning result includes the die allocation of each standard cell, the two-dimensional coordinates of each standard cell on the corresponding die, and the physical mapping from the cross-layer network to the hybrid bonding terminal HBT.

[0017] Those skilled in the art will understand that a gate-level netlist includes a list of standard cells (such as AND gates, OR gates, NOT gates, flip-flops, latches, etc.) and their interconnections. The gate-level netlist is obtained by synthesizing RTL (Register Transfer Level). The synthesis process is prior art and will not be described further here.

[0018] In this embodiment, the synthesized gate-level netlist is used as input; module-level or medium-granularity logic blocks are not constructed first, nor are independent hypergraph partitioning results used as fixed partition boundaries. As a preferred implementation, such as... Figure 2 As shown, S100 includes:

[0019] S110, determine the initial x, y coordinates and initial z coordinates of each standard cell in the synthesized gate-level netlist; the initial z coordinates belong to [0,1].

[0020] As a preferred implementation, a two-dimensional prototype layout is used to determine the initial x and y coordinates of each standard cell in the synthesized gate-level netlist. It should be understood that the two-dimensional prototype layout ignores the z-axis, forcibly flattening all standard cells into a single plane. Using the two-dimensional prototype layout allows for a quick and rough determination of the approximate positions of the standard cells on the plane. The two-dimensional prototype layout process does not consider stacking; it only aims to minimize the total number of connected lines and achieve the most uniform density on the plane. Based on the two-dimensional prototype layout, line length estimates and congestion distributions can also be obtained. The line length estimate can inform the 3D planner of the line lengths on the plane when there are no height restrictions, and the congestion distribution can inform the 3D planner of which locations are more congested. Based on this optional implementation, preferred initial x and y coordinates can be obtained, which helps to accelerate the subsequent layout convergence process of the 3D planner.

[0021] As a preferred implementation, the initial z-coordinate satisfies the soft constraint of area balance. This ensures area balance between different dies in the early stages, avoiding convergence difficulties caused by large area imbalances in the early stages. In this embodiment, the z-variable of the standard cell is initialized under the soft constraint of area balance, with a value ranging from 0 to 1, and is continuously optimized in subsequent true 3D analytical layout. It should be understood that a value closer to 0 indicates a closer proximity to the bottom die, and a value closer to 1 indicates a closer proximity to the top die.

[0022] S120, the layout warm-up phase, first optimizes line length, die density and area balance.

[0023] In this embodiment, the layout warm-up phase first optimizes line length, per-die density, and area balance. That is, it initially sets line length, per-die density, and area balance as objectives to achieve a stable global layout of standard cells between the common projection plane and the dies. It should be understood that line length refers to the total length of all interconnects in three-dimensional space, the common projection plane refers to the overall distribution of standard cells projected onto the xy-plane, and per-die refers to the balanced distribution in the vertical direction. The goal of the warm-up phase is to first establish a stable distribution in these two dimensions, laying the foundation for introducing more objectives later. Those skilled in the art will understand that objective functions corresponding to line length, per-die density, and area balance can be constructed using a weighted summation method to achieve the goal of a stable global layout of standard cells between the common projection plane and the dies. Those skilled in the art will understand that existing 3D planners have multi-objective iterative optimization capabilities; therefore, the process of layout with line length, per-die density, and area balance as objectives will not be elaborated here.

[0024] S130, then gradually enable timing, 3D congestion, power density, vertical hotspots and HBT cost; among them, after every corresponding preset iteration interval, incremental static timing analysis is called to update the critical path and network weights, and at the same time, the global routing mesh cell congestion map and per-die power density map of each die and bonding interface are updated; and as the target optimization converges, the z value of each standard cell is pushed to the z value corresponding to the die, completing the discrete die allocation.

[0025] This embodiment optimizes line length, per-die density, and area balancing before gradually enabling timing, 3D congestion, power density, vertical hotspots, and HBT cost. It should be understood that gradual activation means not adding all targets at once, but rather activating them in a step-by-step manner. For example, a new objective is added after several iterations with a lower initial weight, which is then gradually increased to the target weight corresponding to that objective. This avoids the convergence problem caused by adding all objectives to the objective function simultaneously.

[0026] It should be understood that during the above layout iteration process, standard cells are constantly moving, the physical length of the network and the degree of local congestion are constantly changing, and the identity of the critical path may also change. In this embodiment, during the above iterative optimization process, after every n1 iterations, incremental static timing analysis (STA) is called to update the critical path and network weights; after every n2 iterations, the global routing mesh cell congestion map of each die and bonding interface is updated; after every n3 iterations, incremental static timing analysis is called to update the die-by-die power density map; where n1, n2, and n3 are the preset iteration intervals corresponding to the critical path and network weights, congestion map and power density map, respectively, and n1, n2, and n3 are all values ​​greater than or equal to 1, and they can be equal or unequal. Thus, this embodiment can achieve periodic state updates, dynamically respond to layout changes, and is conducive to accurate allocation of optimization resources; moreover, incremental STA only recalculates changed paths, resulting in high computational efficiency.

[0027] It should be understood that during the above optimization iteration process, the z-value of the standard unit is still a continuous value within the range of 0 to 1. For example, the z-value of a standard unit may be 0.3 or 0.7; however, in physical manufacturing, each standard unit needs to be clearly defined as falling on a specific layer. Therefore, in this embodiment, as the target optimization converges, the z-value of each standard unit is pushed towards the z-value corresponding to the die, completing the discrete die allocation. As an optional specific implementation, convergence of the target optimization refers to starting to push the z-value of each standard unit towards the z-value corresponding to the die after the iteration enters a certain stage (e.g., when the number of iterations exceeds a preset number of iterations, or when the 3D layout reaches a certain preset condition, etc.).

[0028] In one specific implementation, only two bare dies are used, with each die corresponding to a z-value of 0 or 1. By introducing a quantization penalty term into the objective function and continuously increasing the weight of the quantization regularization term, the z-value of each standard cell is pushed towards 0 or 1. It should be understood that the quantization regularization term is a penalty term, with the minimum penalty at z=0 or 1 and the maximum penalty at z=0.5. By continuously increasing the weight of the quantization regularization term, any z-value that is not close to 0 or 1 will incur an increasingly larger cost in the objective function, thereby forcing each standard cell to have a z-value of 0 or 1. If a standard cell's z-value is not 0 or 1, it is determined to be 0 or 1 by comparing whether its z-value is closer to 0 or 1.

[0029] S140: After completing the discrete die allocation, check the global and local HBT capacity. If the number of cross-die networks or the local terminal density exceeds the process capacity, perform local cell migration based on line length increment, path criticality, congestion changes, power density and area balance effects, and restore physical quality through incremental true 3D layout.

[0030] In this embodiment, after the discrete die allocation is completed, the global HBT capacity may exceed the process-allowed global HBT capacity, or the local HBT capacity may exceed the process-allowed local HBT capacity. In this case, a local cell migration process is performed. During this process, the migration cost of each standard cell is comprehensively considered based on line length increment, path criticality, congestion variation, power density, and area balance, and the standard cell with the smaller cost is determined as the standard cell that needs to be migrated.

[0031] It should be understood that the physical quality (line length, timing, congestion, density, power density, and area balance) may deteriorate after migration. In this embodiment, incremental true 3D layout refers to: instead of re-performing 3D analytical layout on all standard cells, a small number of iterations of local analytical layout are run only on the migrated standard cells and their affected surrounding areas to quickly restore physical quality.

[0032] As an alternative implementation, if packaging and material parameters are available, the temperature field is further calculated, allowing the partitioner to see the early costs of power density and vertical thermal coupling when moving cells to another layer. This enables thermally sensitive layout, mitigating thermal risks early on.

[0033] As one specific implementation, when the user does not pre-specify the die footprint, a set of minimum die areas that allow for a feasible 3D layout is calculated. Thus, the user does not need to provide the area beforehand, ensuring sufficient space is available.

[0034] As a specific implementation, a capacity-constrained HBT planning process is performed after S140 or after each iteration; the capacity-constrained HBT planning process includes:

[0035] When the number of cross-layer networks does not meet the available HBT capacity constraint, the planner calculates the marginal cost of shrinking each cross-layer network to any layer; and iteratively shrinks based on the calculated marginal cost until the number of cross-layer networks meets the HBT capacity constraint; the marginal cost integrates the effects of line length increment, path criticality, congestion variation, power density, and area balance. It should be understood that "the number of cross-layer networks not meeting the available HBT capacity constraint" means that the number of cross-layer networks is greater than the available HBT capacity.

[0036] As an optional specific implementation, iterative shrinkage based on the calculated marginal cost includes:

[0037] For each current cross-layer network e, calculate the marginal cost cost(e) of placing e on each bare chip, and determine the minimum marginal cost as the marginal cost of shrinking e. As a specific implementation, cost(e) = α × ΔWL e+β×max(0,−slack_min(e)) / T_clk+γ×ΔR e +ω×ΔPD e +λ×ΔB e α, β, γ, ω, and λ are the weights corresponding to the line length increment, path criticality, congestion change, power density change, and area balance change, respectively. ΔWL e The parameter represents the line length increment when e is forced to be a layer intranet of a certain die, slack_min(e) represents the minimum slack time among all timing paths traversed by e before forcing e to be a layer intranet of a certain die, T_clk represents the clock cycle, and ΔR e ΔPD represents the local congestion change when e is forced to be an intranet of a certain bare chip. e ΔB represents the local power density change when e is forced to be an intra-layer mesh of a certain die. e This represents the area balance change when e is forced to be an in-layer mesh of a certain wafer.

[0038] Sort the cells in ascending order of marginal cost of shrinkage, and perform greedy processing based on batch size. After each batch, fix the shrunken cells and perform an incremental Nesterov warm-start to adapt the remaining layout to the changes. The algorithm terminates when the number of cross-layer networks N_HBT ≤ N_max, where N_max is the available HBT capacity. The batch size can be set by the user.

[0039] Given that the number of cross-layer networks satisfies the HBT capacity constraint, the planner generates legal HBT slots conforming to the process rules at the bonding layer and models the mapping from cross-layer networks to HBT slots as a minimum-cost matching problem. The matching cost includes the estimated line length from each layer endpoint to the target slot, the degree of local congestion, and path criticality. As a specific implementation, a bipartite graph is constructed, with the left vertex representing the cross-layer network and the right vertex representing the HBT slot. A cost function is established, taking the estimated line length from each layer endpoint to the target slot, the degree of local congestion, and path criticality as factors. Minimizing this cost function is achieved using an existing bipartite graph matching algorithm to obtain the mapping from cross-layer networks to HBT slots.

[0040] Therefore, this embodiment optimizes the process of obtaining 3D planning results: using standard cells as the basic object, it jointly optimizes line length, timing, 3D congestion, power density, terminal quantity, and area balance in a continuous (x,y,z) space; during the placement process, it explicitly models the capacity of hybrid bonding terminals, local density, and top-level metal access congestion, avoiding post-processing of terminal planning. Thus, compared to existing technologies, this embodiment can perceive path-level timing, actual geometric distance, die area balance, die routing capacity, power density, vertical thermal coupling, and the quantity and spatial distribution of hybrid bonding interconnects during placement and die partitioning. It performs terminal capacity checks and cross-layer mesh to terminal allocation, achieving high-quality 3D planning results that consider bus length, critical path timing, global and local routing congestion, vertical HBT terminal density distribution, inter-die power density, and inter-die area balance.

[0041] S200: Obtain standard delivery documents based on the 3D planning results; the standard delivery documents include independent netlist files for each die, initial layout files, fixed HBT locations, and timing constraint files; S200 includes: segmenting the 3D netlist at the HBT and generating consistent boundary constraints for each die; for each cross-die path, decomposing the path into transmit die segments, HBT parasitic segments, and receive die segments based on the 3D timing diagram; based on zero margin allocation and timing budget theory, the planner prioritizes protecting near-critical paths, allocating arrival times and required times for each HBT port in each mode and at each corner point; at the timing constraint level, assigning output delay or end-to-end maximum delay budget to the HBT ports of the transmit die, and assigning input delay, transition time, and load assumptions to the receive die ports; and treating cross-die clock skew, HBT parasitic uncertainty, and model errors after planning to routing as independent guard bands.

[0042] It should be understood that after executing S100, a complete 3D netlist (including cross-layer connections) and HBT slot coordinates are obtained. In this embodiment, this 3D netlist is divided into independent netlists for each die. For example, a die includes an upper-layer die and a lower-layer die. The die is cut at the HBT location, and the upper layer is placed into one netlist, and the lower layer is placed into another netlist. Consistent boundary constraints refer to the virtual input / output ports generated at the cut point. The corresponding ports of the upper and lower layers must be named in the same way to ensure that subsequent logic equivalence checks can match.

[0043] In this embodiment, the signal path is triggered from one layer to another and captured. The complete path is decomposed into three segments: the transmit raw segment, the HBT parasitic segment, and the receive raw segment. The transmit raw segment refers to the trace delay of the signal from the trigger to the HBT port within the transmit layer; the HBT parasitic segment refers to the resistance-capacitance delay of the signal passing through the HBT via itself; and the receive raw segment refers to the trace delay of the signal from the HBT port to the trigger within the receive layer. As an optional implementation, the parasitic parameters (RLC) of the HBT are extracted using an RC tree model and input as a fixed delay to the static timing analysis engine. For each cross-die path, the static timing analysis engine decomposes the complete path into the transmit raw segment, the HBT parasitic segment, and the receive raw segment by traversing the corresponding timing arcs in the three-dimensional timing diagram.

[0044] In this embodiment, the clock cycle is fixed, and it is necessary to determine how much time each segment (transmit and receive) requires. Zero margin allocation means assuming no time waste and that the total cycle is exactly allocated. Prioritizing protection of near-critical paths means giving more time budget to paths that are almost too late, so that limited timing resources are prioritized for paths that have the greatest impact on the chip's clock frequency. Considering each mode and corner point is to achieve full coverage of different operating modes and corner points, ensuring that the chip can operate normally under any operating conditions. As a specific implementation, linear programming or minimum margin optimization is used to solve for the arrival time and required time allocated to each HBT port in each mode and corner point. As a specific implementation, for each cross-die timing path, its total delay budget is decomposed into the transmit raw segment budget, the HBT parasitic segment fixed delay, and the receive raw segment budget. For each HBT port, each operating mode, and each process corner, the following linear programming constraint is established: the sum of the transmit raw segment budget, the HBT parasitic segment fixed delay, and the receive raw segment budget is less than or equal to the difference between the clock cycle and the reserved timing guard band under that mode / corner. The decision variables are the arrival time and the required time of each HBT port. The objective function is to maximize the minimum timing margin of all cross-die paths, or equivalently, to minimize the total number of timing violations of all paths. Near-critical paths are defined as paths with timing margins less than a preset threshold (which can be set by the user, such as 5% of the clock cycle), and are given higher weight in the optimization.

[0045] In this embodiment, the obtained time values ​​are translated into the industry-standard SDC (Timing Constraint) format. Output delay or end-to-end maximum delay budget is assigned to the HBT port transmitting the die, while input delay, transition time, and load assumptions are assigned to the receiving die port. Simultaneously, considering potential changes in trace length and clock signal arrival time deviations during future fine-tuning, a guard band (i.e., a safety margin) is reserved. This guard band includes: cross-die clock skew (i.e., the arrival time difference of the clock signal to the upper and lower layer flip-flops), HBT parasitic uncertainty (i.e., the deviation between the actual parasitic parameters of the HBT vias and the model), and model error planned to be implemented after routing (i.e., the difference between the current estimate and the actual future routing). This generates an SDC file that can be directly read by 2D placement and routing tools, and the guard band mechanism also reserves engineering tolerances.

[0046] S300, the standard delivery package is input into the two-dimensional placement and routing tool to perform detailed placement, clock tree synthesis, routing, optimization, and signature timing analysis at corner points for each die; and after each die has been signed off, it is assembled according to the global net ID and HBT coordinates, and a post-assembly signature analysis is performed.

[0047] In this embodiment, the standard delivery package includes independent netlists, independent initial layout files, independent fixed HBT locations, and independent SDC files for different dies. The portions of the standard delivery package corresponding to different dies are input into the corresponding 2D place-and-route tools for those dies. These tools can then be used to perform the placement and routing of the corresponding dies. Those skilled in the art will understand that detailed placement, clock tree synthesis, routing, optimization, and timing analysis at corner points are all functions of the 2D place-and-route tools, and will not be elaborated upon here.

[0048] In this embodiment, after each bare die has been signed off, assembly is performed based on the global network ID and HBT coordinates. The assembly process has been verified to ensure proper functioning. Those skilled in the art are familiar with the assembly process and post-assembly analysis, so it will not be elaborated upon here.

[0049] As one specific implementation, the post-assembly analysis includes three-dimensional static timing analysis, HBT alignment check, and thermal analysis. It should be understood that if the post-assembly three-dimensional static timing analysis, HBT alignment check, and thermal analysis fail verification, feedback and remediation can be performed based on the type and severity of the violation. Those skilled in the art are familiar with the feedback and remediation process, which will not be elaborated upon here.

[0050] After obtaining the 3D planning results, this embodiment converts the 3D planning results into a die-by-die netlist, an initial layout file, fixed HBT terminals, and timing constraint files, so that different logic dies can be independently implemented by mature 2D placement and routing tools. By forming a closed loop through post-assembly 3D static timing analysis and thermal analysis, it solves the system problem of delivering the 3D layout results to the industrial back-end process.

[0051] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A method for core-particle partitioning and physical implementation driven by true 3D multi-objective layout, characterized in that, The method includes the following steps: S100, obtain the synthesized gate-level netlist, and perform true 3D multi-objective layout based on the synthesized gate-level netlist to obtain the 3D planning result; the 3D planning result includes the die allocation of each standard cell, the two-dimensional coordinates of each standard cell on the corresponding die, and the physical mapping from the cross-layer network to the hybrid bonding terminal HBT. S200: Obtain standard delivery documents based on the 3D planning results. These standard delivery documents include a die-by-die independent netlist file, an initial layout file, fixed HBT locations, and timing constraint files. S200 includes: segmenting the 3D netlist at the HBT locations and generating consistent boundary constraints for each die; for each cross-die path, decomposing the path into transmit die segments, HBT parasitic segments, and receive die segments based on the 3D timing diagram; based on zero margin allocation and timing budget theory, the planner prioritizes protecting near-critical paths, allocating arrival times and required times for each HBT port in each mode and at each corner point; at the timing constraint level, assigning output delay or end-to-end maximum delay budget to the HBT ports of the transmit die, and assigning input delay, transition time, and load assumptions to the receive die ports; and treating cross-die clock skew, HBT parasitic uncertainty, and model errors after planning to routing as independent guard bands. S300, the standard delivery package is input into the two-dimensional placement and routing tool to perform detailed placement, clock tree synthesis, routing, optimization, and signature timing analysis at corner points for each die; and after each die has been signed off, it is assembled according to the global net ID and HBT coordinates, and a post-assembly signature analysis is performed.

2. The core-particle partitioning and physical implementation method driven by true 3D multi-objective layout according to claim 1, characterized in that, S100 includes: S110, determine the initial x, y coordinates and initial z coordinates of each standard cell in the synthesized gate-level netlist; the initial z coordinates belong to [0,1]; S120, the layout warm-up phase is executed, first optimizing line length, die density and area balance; S130, then gradually enable timing, 3D congestion, power density, vertical hotspot, and HBT cost; among them, after every corresponding preset iteration interval, incremental static timing analysis is called to update the critical path and network weights, and at the same time, the global routing mesh cell congestion map and per-die power density map of each die and bonding interface are updated; and as the target optimization converges, the z-value of each standard cell is pushed to the z-value corresponding to the die, completing the discrete die allocation; S140: After completing the discrete die allocation, check the global and local HBT capacity. If the number of cross-die networks or the local terminal density exceeds the process capacity, perform local cell migration based on line length increment, path criticality, congestion changes, power density and area balance effects, and restore physical quality through incremental true 3D layout.

3. The core-particle partitioning and physical implementation method driven by true 3D multi-objective layout according to claim 2, characterized in that, S100 further includes: performing a capacity-constrained HBT planning process after S140 or after each iteration; the capacity-constrained HBT planning process includes: If the number of cross-layer networks does not meet the available HBT capacity constraint, the planner calculates the marginal cost of shrinking each cross-layer network to any layer; and iterates the shrinkage according to the calculated marginal cost until the number of cross-layer networks meets the HBT capacity constraint; the marginal cost takes into account the effects of line length increment, path criticality, congestion change, power density and area balance. When the number of cross-layer networks meets the HBT capacity constraint, the planner generates legal HBT slots that conform to the process rules in the bonding layer and models the mapping from cross-layer networks to HBT slots as a minimum cost matching problem, where the matching cost includes: the estimated line length from each layer endpoint to the target slot, the degree of local congestion, and the path criticality.

4. The core-particle partitioning and physical implementation method driven by true 3D multi-objective layout according to claim 3, characterized in that, The iterative contraction based on the calculated marginal cost includes: For each current cross-layer network e, calculate the marginal cost cost(e) of placing e on each bare chip, and determine the minimum marginal cost as the marginal cost of shrinking e. Sort the cells in ascending order of marginal cost of shrinkage, and perform greedy processing based on batch size. After each batch, fix the shrunken cells and perform an incremental Nesterov hot start to adapt the remaining layout to the changes. The algorithm terminates when the number of cross-layer networks N_HBT ≤ N_max, where N_max is the available HBT capacity.

5. The core-particle partitioning and physical implementation method driven by true 3D multi-objective layout according to claim 2, characterized in that, cost(e) = α × ΔWL e +β×max(0,−slack_min(e)) / T_clk+γ×ΔR e +ω×ΔPD e +λ×ΔB e α, β, γ, ω, and λ are the weights corresponding to the line length increment, path criticality, congestion change, power density change, and area balance change, respectively. ΔWL e The parameter represents the line length increment when e is forced to be a layer intranet of a certain die, slack_min(e) represents the minimum slack time among all timing paths traversed by e before forcing e to be a layer intranet of a certain die, T_clk represents the clock cycle, and ΔR e ΔPD represents the local congestion change when e is forced to be an intranet of a certain bare chip. e ΔB represents the local power density change when e is forced to be an intra-layer mesh of a certain die. e This represents the area balance change when e is forced to be an in-layer mesh of a certain wafer.

6. The core-particle partitioning and physical implementation method driven by true 3D multi-objective layout according to claim 2, characterized in that, S110 includes: using a two-dimensional prototype layout to determine the initial x and y coordinates of each standard element in the synthesized gate-level netlist, with the initial z coordinates satisfying the soft constraint of area balance.

7. The core-particle partitioning and physical implementation method driven by true 3D multi-objective layout according to claim 2, characterized in that, In S130, the z-value of each standard unit is pushed toward 0 or 1 by continuously increasing the weight of the quantization regularization term.

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