A thermoelectric cooperative design method and device of a complementary double-chip co-packaged power MOSFET

Abstract

The application relates to the technical field of chip packaging, and discloses a thermoelectricity collaborative design method and device of a complementary double-chip co-packaged power MOSFET, wherein the application comprises the following steps: creating a packaging thermal network of N chips and P chips in a co-packaged device, and taking a first power consumption function of the N chips and the P chips as an excitation source of the packaging thermal network; establishing a first compensation model of the N chips and a second compensation model of the P chips; in each simulation time step, driving the packaging thermal network by the first power consumption function, inputting a first real-time junction temperature of the N chips into the first compensation model and inputting a second real-time junction temperature of the P chips into the second compensation model, and iteratively simulating to obtain a first current waveform of the N chips and a second current waveform of the P chips; and the application solves the problem of systematic absence of the thermal crosstalk effect caused by neglecting the transverse thermal coupling path in the prior art, and further realizes bidirectional coupling iteration of circuit solving and thermal network solving.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a thermoelectric co-design method and apparatus for complementary dual-chip co-packaged power MOSFETs. Background Technology

[0002] Thermoelectric co-simulation of power MOSFET devices is a core component of package design and reliability assessment. Existing simulation methods typically establish a vertical thermal resistance network for a single-chip package, using the average power dissipation over one switching cycle as the static excitation source for the thermal network. Circuit simulation and thermal analysis are performed step-by-step in sequence, lacking real-time bidirectional data exchange between the two.

[0003] Complementary dual-chip co-packaging integrates an N-channel MOSFET and a P-channel MOSFET into a single package, sharing a DBC copper layer and a heat dissipation substrate. A significant lateral heat conduction path exists between the two chips. Existing simulation methods only establish the vertical thermal path of a single chip, completely ignoring the lateral thermal coupling resistance and lateral thermal capacitance between the DBC copper layer nodes of the two chips. This results in the inability to capture the thermal crosstalk effect between the two chips. Furthermore, the majority carriers of N-channel and P-channel MOSFETs are electrons and holes, respectively, and their mobility temperature coefficients differ fundamentally. This leads to different increases in on-resistance and threshold voltage drift rates for the two transistors under the same temperature rise, causing the drain current calculation error to accumulate continuously with increasing junction temperature. Summary of the Invention

[0004] This invention provides a thermoelectric co-design method and apparatus for complementary dual-chip co-packaged power MOSFETs. This invention solves the problem of systematic lack of thermal crosstalk effect caused by neglecting the lateral thermal coupling path in the prior art, and thus realizes bidirectional coupled iteration of circuit solution and thermal network solution.

[0005] In a first aspect, the present invention provides a thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs, the thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs comprising: Create a packaged thermal network for N-chip and P-chip in a co-packaged device, and use the first power consumption function of the N-chip and the P-chip as the excitation source of the packaged thermal network; Establish a first compensation model for the N chip and a second compensation model for the P chip; Within each simulation time step, the packaged thermal network is driven by the first power consumption function. The first real-time junction temperature of the N chip is substituted into the first compensation model, and the second real-time junction temperature of the P chip is substituted into the second compensation model. The simulation is iterative to obtain the first current waveform of the N chip and the second current waveform of the P chip.

[0006] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, the step of creating a packaged thermal network for the N-chip and the P-chip in a co-packaged device, and using a first power consumption function of the N-chip and the P-chip as the excitation source of the packaged thermal network, includes: Cauer-type thermal resistance and thermal capacity calculations are performed on the N-chip and P-chip in the co-packaged device to obtain the first thermal resistance network of the N-chip and the second thermal resistance network of the P-chip. Calculate the lateral thermal coupling resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip, and connect the lateral thermal coupling resistance and the lateral thermal capacity between the DBC copper layer nodes of the first thermal resistance network and the second thermal resistance network to obtain the packaged thermal network. Modeling is performed on N-channel transistors and P-channel transistors respectively to obtain the first power consumption function of the N-chip and the P-chip, and the first power consumption function is used as the excitation source of the packaged thermal network.

[0007] In conjunction with the first aspect, in a second implementation of the first aspect of the present invention, the step of calculating the lateral thermal coupling resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip, and connecting the lateral thermal coupling resistance and the lateral thermal capacity between the DBC copper layer nodes of the first thermal resistance network and the second thermal resistance network to obtain the packaged thermal network, includes: The effective heat transfer width of the transverse heat flow is calculated based on the N chip and the P chip; The lateral thermal coupling thermal resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip are calculated based on the effective heat transfer width of the lateral heat flow. The lateral thermal coupling thermal resistor and the lateral thermal capacitance are connected between the DBC copper layer node of the first thermal resistance network and the DBC copper layer node of the second thermal resistance network to obtain the encapsulated thermal network.

[0008] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, the step of modeling the N-channel transistor and the P-channel transistor respectively to obtain the first power consumption functions of the N-chip and the P-chip, and using the first power consumption function as the excitation source of the packaged thermal network, includes: Within one switching cycle, transient power consumption modeling is performed on the N-transistor to obtain the first transient power consumption of the N-transistor; steady-state power consumption modeling is performed on the N-transistor to obtain the first steady-state power consumption of the N-transistor; transient power consumption modeling is performed on the P-transistor to obtain the second transient power consumption of the P-transistor; steady-state power consumption modeling is performed on the P-transistor to obtain the second steady-state power consumption of the P-transistor. Based on the first transient power consumption, the first steady-state power consumption, the second transient power consumption, and the second steady-state power consumption of the N-transistor, a first power consumption function for the N-chip and the P-chip is constructed, and the first power consumption function is used as the excitation source for the packaged thermal network.

[0009] In conjunction with the first aspect, in the fourth implementation of the first aspect of the present invention, the step of performing transient power consumption modeling on the N-transistor within one switching cycle to obtain the first transient power consumption of the N-transistor; performing steady-state power consumption modeling on the N-transistor to obtain the first steady-state power consumption of the N-transistor; performing transient power consumption modeling on the P-transistor to obtain the second transient power consumption of the P-transistor; and performing steady-state power consumption modeling on the P-transistor to obtain the second steady-state power consumption of the P-transistor includes: Within one switching cycle, the first transient power consumption of the N-transistor is calculated based on the linear decrease of the drain-source voltage from the bus voltage to the N-transistor's on-state voltage drop and the linear increase of the drain current from zero to the load current. Obtain the on-resistance of the N-transistor and multiply the on-resistance of the N-transistor by the square of the load current to obtain the first steady-state power consumption of the N-transistor. Within one switching cycle, the second transient power consumption of the P-transistor is calculated based on the linear decrease of the drain-source voltage of the P-transistor from the bus voltage to the P-transistor on-state voltage drop and the linear increase of the drain current of the P-transistor from zero to the load current. Obtain the on-resistance of the P-tube and multiply it by the square of the load current to obtain the second steady-state power consumption of the P-tube.

[0010] In conjunction with the first aspect, in the fifth implementation of the first aspect of the present invention, establishing the first compensation model of the N chip and the second compensation model of the P chip includes: A temperature model for an N-channel MOSFET is constructed based on the electron mobility temperature coefficient; a temperature model for a P-channel MOSFET is constructed based on the hole mobility temperature coefficient. An N-channel voltage model is constructed based on the linear drift slope of the N-chip threshold voltage; a P-channel voltage model is constructed based on the linear slope of the P-chip threshold voltage. The N-channel temperature model and the N-channel voltage model are combined to obtain the first compensation model for the N-chip; the P-channel temperature model and the P-channel voltage model are combined to obtain the second compensation model for the P-chip.

[0011] In conjunction with the first aspect, in the sixth implementation of the first aspect of the present invention, the construction of the N-transistor voltage model based on the linear drift slope of the N-chip threshold voltage and the construction of the P-transistor voltage model based on the linear slope of the P-chip threshold voltage include: The first voltage temperature coefficient is fitted based on the linear drift slope of the N-chip threshold voltage, and an N-transistor voltage model is constructed based on the first voltage temperature coefficient and the N-transistor threshold voltage. The second voltage temperature coefficient is fitted with a linear slope based on the threshold voltage of the P-chip, and a P-tube voltage model is constructed based on the second voltage temperature coefficient and the threshold voltage of the P-tube.

[0012] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, the step of driving the packaged thermal network by the first power consumption function in each simulation time step, substituting the first real-time junction temperature of the N chip into the first compensation model and the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulating to obtain the first current waveform of the N chip and the second current waveform of the P chip, includes: Within each simulation time step, the packaged thermal network is driven by the first power consumption function to solve for the first real-time junction temperature of the N chip and the second real-time junction temperature of the P chip; Substitute the first real-time junction temperature of the N chip into the first compensation model and the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulate to obtain the first current waveform of the N chip and the second current waveform of the P chip.

[0013] In conjunction with the first aspect, in the eighth implementation of the first aspect of the present invention, the step of substituting the first real-time junction temperature of the N chip into the first compensation model and the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulating to obtain the first current waveform of the N chip and the second current waveform of the P chip, includes: Substitute the first real-time junction temperature into the first compensation model to calculate the first on-resistance and the first threshold voltage; substitute the second real-time junction temperature into the second compensation model to calculate the second on-resistance and the second threshold voltage. The first on-resistance, the first threshold voltage, the second on-resistance, and the second threshold voltage are fed back to the first power consumption function to generate the second power consumption function; The packaged thermal network is driven by the second power consumption function, and the simulation is iterated in the next simulation time step. The simulation is repeated until the simulation time ends, and the first current waveform of the N chip and the second current waveform of the P chip are obtained.

[0014] Secondly, the present invention provides a thermoelectric synergistic design device for complementary dual-chip co-packaged power MOSFETs, the thermoelectric synergistic design device for complementary dual-chip co-packaged power MOSFETs comprising: A creation module is used to create a packaged thermal network for N-chips and P-chips in a co-packaged device, and the first power consumption function of the N-chips and P-chips is used as the excitation source of the packaged thermal network. The compensation model establishment module is used to establish a first compensation model for the N chip and a second compensation model for the P chip. The iterative simulation module is used to drive the packaged thermal network by the first power consumption function in each simulation time step, substitute the first real-time junction temperature of the N chip into the first compensation model and substitute the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulate to obtain the first current waveform of the N chip and the second current waveform of the P chip.

[0015] The technical solution provided by this invention explicitly introduces lateral thermal coupling resistance and lateral thermal capacitance between the DBC copper layer nodes of the N-chip and the P-chip, incorporating the lateral thermal conduction path between the two chips into the packaged thermal network. This allows the simulation model to accurately capture the lateral thermal accumulation effect transmitted to the P-chip during the N-channel MOSFET's conduction and its periodic reversal pattern with alternating conduction timing, solving the problem of systematic missing thermal crosstalk effects caused by neglecting the lateral thermal coupling path in existing technologies. The first power consumption function of the alternating conduction of the N-channel and P-channel MOSFETs replaces the average power consumption excitation of existing technologies, incorporating both the peak power consumption during the transition phase and the temperature-dependent power consumption during the steady-state conduction phase into the thermal network excitation source, thus accurately restoring the junction temperature peak calculation and thermal crosstalk periodic characteristics. Based on the physical difference in the majority carrier mobility temperature coefficients of N-channel and P-channel MOSFETs, independent power-law temperature compensation models for conduction resistance and linear temperature compensation models for threshold voltage are established for the two chips respectively. By feeding back the junction temperature to the device parameter update in real time at each simulation time step, bidirectional coupled iteration of circuit solution and thermal network solution is achieved.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an embodiment of the thermoelectric co-design method for complementary dual-chip co-packaged power MOSFETs in this invention. Figure 2 This is a schematic diagram of the packaging thermal network for creating a co-packaged device in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the establishment of a compensation model in an embodiment of the present invention; Figure 4 This is a schematic diagram of iterative simulation in an embodiment of the present invention; Figure 5This is a schematic diagram of an embodiment of the thermoelectric co-design device for complementary dual-chip co-packaged power MOSFETs in this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0021] To facilitate understanding of this embodiment, a detailed description of the thermoelectric synergistic design method for a complementary dual-chip co-packaged power MOSFET disclosed in this embodiment of the invention will be provided first. For example... Figure 1 As shown, this method includes the following steps: 101. Create a thermal network for N-chip and P-chip in a co-packaged device, and use the first power consumption function of N-chip and P-chip as the excitation source of the thermal network. 102. Establish the first compensation model for the N-chip and the second compensation model for the P-chip; 103. In each simulation time step, the packaged thermal network is driven by the first power consumption function. The first real-time junction temperature of the N chip is substituted into the first compensation model and the second real-time junction temperature of the P chip is substituted into the second compensation model. The first current waveform of the N chip and the second current waveform of the P chip are obtained by iterative simulation.

[0022] In this embodiment of the invention, by explicitly introducing lateral thermal coupling resistance and lateral thermal capacitance between the DBC copper layer nodes of the N-chip and the P-chip, the lateral thermal conduction path between the two chips is incorporated into the packaged thermal network. This allows the simulation model to accurately capture the lateral thermal accumulation effect transmitted to the P-chip during the N-channel MOSFET's conduction and its periodic reversal pattern with alternating conduction timing, solving the problem of systematic missing thermal crosstalk effects caused by neglecting the lateral thermal coupling path in existing technologies. The first power consumption function of the alternating conduction of the N-channel and P-channel MOSFETs replaces the average power consumption excitation of existing technologies. Both the peak power consumption during the transition phase and the temperature-dependent power consumption during the steady-state conduction phase are incorporated into the thermal network excitation source, enabling accurate reconstruction of the junction temperature peak calculation and thermal crosstalk periodic characteristics. Based on the physical difference in the majority carrier mobility temperature coefficient between N-channel and P-channel MOSFETs, independent power-law temperature compensation models for conduction resistance and linear temperature compensation models for threshold voltage are established for the two chips respectively. By feeding back the junction temperature to the device parameter update in real time at each simulation time step, bidirectional coupled iteration of circuit solution and thermal network solution is achieved.

[0023] In one specific embodiment, such as Figure 2 The process of executing step 101 may specifically include the following steps: 201. Perform Cauer-type thermal resistance and thermal capacity calculations on the N-chip and P-chip in the co-packaged device to obtain the first thermal resistance network of the N-chip and the second thermal resistance network of the P-chip. 202. Calculate the lateral thermal coupling resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip, and connect the lateral thermal coupling resistance and lateral thermal capacity between the DBC copper layer nodes of the first thermal resistance network and the second thermal resistance network to obtain the packaged thermal network. 203. Model the N-channel transistor and the P-channel transistor respectively to obtain the first power consumption function of the N-chip and the P-chip, and use the first power consumption function as the excitation source of the packaged thermal network.

[0024] Specifically, vertical Cauer-type thermal networks are established for both the N-chip and P-chip based on the actual layered structure of the co-packaged device. The chip silicon junction nodes, silicon / solder interface nodes, solder / DBC copper layer interface nodes, copper layer / ceramic substrate interface nodes, and substrate underside nodes are sequentially used as thermal network nodes, allowing heat to be transferred from the chip junction region through the solder layer, DBC copper layer, and ceramic substrate to the housing or heat sink. Before calculation, the planar dimensions, thickness, effective heat transfer area, thickness of each packaging layer, thermal conductivity, density, and specific heat capacity of the N-chip and P-chip are extracted. The ambient temperature is preset to 298K, and the thermal conductivity of the DBC copper layer is retained as 385 W·m. -1 ·K -1If measured cross-sectional parameters are lacking in the initial modeling stage of the project, the solder layer thickness can be preset to 80μm, the DBC copper layer thickness to 300μm, the ceramic substrate thickness to 630μm, and the horizontal distance between the centers of the N chip and the P chip to 3.0mm. These can then be replaced with measured values ​​of the package cross-section later. For each layer, the thermal resistance and thermal capacity are calculated according to the physical hierarchy of the Cauer network, using the following expressions:

[0025]

[0026] in, For the first Layer thickness, For the first Layer thermal conductivity, For the first Effective heat transfer cross-sectional area of ​​the layer For the first Layer density, For the first The specific heat capacity of each layer is used only for the calculation of thermal resistance and heat capacity of that layer. After the calculation is completed, the thermal resistance and heat capacity of each layer of the N chip are connected in series in the direction from the junction node to the shell node to form the first thermal resistance network. The thermal resistance and heat capacity of each layer of the P chip are connected in series in the same way to form the second thermal resistance network, thereby ensuring that the two vertical thermal branches are consistent in terms of structural level, node meaning and thermal boundary conditions.

[0027] The DBC copper layer nodes in the two vertical thermal networks are selected as the lateral coupling access points because this layer has strong in-plane thermal conductivity and can represent the main lateral heat diffusion channel between the two chips. During the calculation, the effective width of the lateral heat flow is determined based on the side length of the N chip and the P chip in the direction perpendicular to the chip center connection. Then, the lateral thermal coupling thermal resistance is calculated by combining the center distance between the two chips, the thickness of the DBC copper layer and the thermal conductivity of the copper layer. The lateral heat capacity is calculated by combining the copper layer density, specific heat capacity and lateral heat diffusion volume. Then, the lateral thermal coupling thermal resistance and the lateral heat capacity are connected between the DBC copper layer nodes of the first thermal resistance network and the DBC copper layer nodes of the second thermal resistance network. This allows the heat generated when the N chip is turned on and heated up to be transferred to the P chip side through the internal copper layer of the package. When the P chip is turned on and heated up, it can also affect the N chip side in the reverse direction. This forms a package thermal network that simultaneously contains two vertical heat transfer branches and one lateral coupling branch.

[0028] After the thermal network is established, the alternating conduction process of N-channel and P-channel transistors is used as the excitation source for the thermal network. Power consumption is modeled for the N-channel transistor turn-on transition, N-channel transistor steady-state conduction, P-channel transistor turn-on transition, P-channel transistor steady-state conduction, and dead-time freewheeling process within one switching cycle. The transient power consumption of each time period is then concatenated in chronological order to form the first power consumption function of the N-chip and P-chip. For example, the switching frequency can be preset to 100kHz, the N-channel transistor duty cycle to be 0.5, the dead time to be 100ns, and the forward voltage drop of the body diode to be 0.9V. The load current, bus voltage, on-resistance, and switching transition time are used as configurable inputs, allowing the power consumption function to be updated according to changes in device specifications and operating conditions. The first power consumption function is a heat source input that varies with time. Therefore, during simulation, the N-chip power consumption function is loaded onto the junction of the first thermal resistance network, and the P-chip power consumption function is loaded onto the junction of the second thermal resistance network. The real-time junction temperature output by the thermal network is used to inversely affect the on-resistance and subsequent power consumption calculations.

[0029] In one specific embodiment, the process of performing step 202 may specifically include the following steps: Calculate the effective heat transfer width of transverse heat flow based on N-chip and P-chip; The lateral thermal coupling thermal resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip are calculated based on the effective heat transfer width of the lateral heat flow. The lateral thermal coupling thermal resistance and lateral thermal capacitance are connected between the DBC copper layer nodes of the first thermal resistance network and the DBC copper layer nodes of the second thermal resistance network to obtain the encapsulated thermal network.

[0030] Specifically, the main direction of lateral heat flow is determined based on the relative positions of the N-chip and P-chip within the package plane. This means the line connecting the center points of the two chips is used as the heat flow path direction, and the effective side lengths of the two chips perpendicular to this line are taken as the basic parameter for the width of the lateral heat flow cross-section. In the initial modeling stage, the side length of the N-chip perpendicular to the line can be preset to 3.2 mm, the side length of the P-chip perpendicular to the line to 3.0 mm, the horizontal distance between the centers of the two chips to 3.0 mm, the DBC copper layer thickness to 300 μm, and the thermal conductivity of the DBC copper layer to 385 W·m. -1 ·K -1 The effective heat transfer width of the transverse heat flow is calculated as the arithmetic mean of the corresponding side lengths of the two chips, i.e.:

[0031] in, and These represent the side lengths of the N-chip and the P-chip perpendicular to the line connecting their centers. This represents the equivalent width of the lateral heat flow within the DBC copper layer. Using the horizontal distance between the centers of the two chips as the lateral heat conduction path length, and the product of the DBC copper layer thickness and the effective heat transfer width as the lateral heat flow cross-sectional area, the lateral thermal coupling resistance between the DBC copper layer nodes of chips N and P is calculated. Simultaneously, the lateral heat capacity is calculated based on the density, specific heat capacity, and lateral heat diffusion region volume of the copper layer material. The expression is:

[0032]

[0033] in, This indicates the horizontal distance between the centers of the N-chip and the P-chip. This indicates the thermal conductivity of the DBC copper layer. Indicates the thickness of the DBC copper layer. and These represent the copper layer density and specific heat capacity, respectively.

[0034] After completing the parameter calculation, the DBC copper layer node of the N chip in the first thermal resistance network and the DBC copper layer node of the P chip in the second thermal resistance network are used as connection ends. The lateral thermal coupling thermal resistance and lateral thermal capacitance are connected between these two nodes, so that they together with the two vertical Cauer thermal networks form the package thermal network. When the N tube is in the conduction and heating stage, the temperature of the N chip DBC copper layer node rises, and the heat can be transferred to the P chip side through the lateral coupling branch. When the P tube is in the conduction and heating stage, the heat flow direction will reverse with the temperature difference between the two nodes. Thus, the package thermal network can not only reflect the vertical heat dissipation process from the chip to the shell, but also reflect the lateral thermal crosstalk process in the package caused by the alternating conduction of complementary chips.

[0035] In one specific embodiment, the process of performing step 203 may specifically include the following steps: Within one switching cycle, transient power consumption modeling is performed on the N-transistor to obtain the first transient power consumption of the N-transistor; steady-state power consumption modeling is performed on the N-transistor to obtain the first steady-state power consumption of the N-transistor; transient power consumption modeling is performed on the P-transistor to obtain the second transient power consumption of the P-transistor; steady-state power consumption modeling is performed on the P-transistor to obtain the second steady-state power consumption of the P-transistor. Based on the first transient power consumption, the first steady-state power consumption, the second transient power consumption, and the second steady-state power consumption of the N-transistor, a first power consumption function for the N-chip and the P-chip is constructed, and the first power consumption function is used as the excitation source for the packaged thermal network.

[0036] Specifically, using a complete switching cycle as the basic time unit, the operation of the complementary dual-chip co-packaged power MOSFET is divided into an N-channel-dominated heat generation region and a P-channel-dominated heat generation region. Within each region, states such as transition, steady-state conduction, and dead-time freewheeling are distinguished. This ensures that the power consumption of the N-channel and P-channel is no longer treated as a single average value, but rather as a transient heat source that varies with the switching sequence. For example, in the initial simulation parameter settings, the switching frequency can be preset to 100kHz, resulting in a switching cycle of 10μs. The duty cycle of the N-channel is set to 0.5, with the N-channel and P-channel each occupying half of the main conduction period. The dead time is set to 100ns. The forward voltage drop of the body diode can be selected within the range of 0.7V to 1.2V, with an initial value of 0.9V. The duration of the transition can be set according to 3% to 8% of the switching cycle, with an initial value of 5% of the switching cycle, in order to cover the short-term interval where peak power consumption occurs. When modeling the transient power consumption of the N-channel MOSFET, its turn-on transition process is regarded as a dynamic process in which the drain current gradually rises from zero to the load current and the drain-source voltage gradually decreases from the bus voltage to the on-state voltage drop, thus obtaining the first transient power consumption of the N-channel MOSFET. When modeling the steady-state power consumption of the N-channel MOSFET, after the N-channel MOSFET is in the stable conduction stage, the first steady-state power consumption is determined based on the load current and the real-time on-resistance of the N-channel MOSFET. Moreover, this on-resistance is not a fixed value, but is updated with the real-time junction temperature of the N-chip during the thermoelectric coupling iteration. Correspondingly, the same timing decomposition idea is used when modeling the P-type transistor, except that the power consumption period is complementary to that of the N-type transistor. That is, the P-type transistor is basically in the off or low-loss state during the N-type transistor's dominant conduction period, while the N-type transistor is basically in the off or low-loss state during the P-type transistor's dominant conduction period. Therefore, the second transient power consumption of the P-type transistor is determined by the synchronous change of the drain current and drain-source voltage during the P-type transistor's turn-on transient period, and the second steady-state power consumption of the P-type transistor is determined by the load current and the real-time on-resistance of the P-type transistor when it is stably conducting. At the same time, both transistors are turned off during the dead zone, and the freewheeling loss of the body diode can be included as a short-term additional heat source on the corresponding chip side.

[0037] The first transient power consumption of the N-channel transistor, the first steady-state power consumption of the N-channel transistor, the second transient power consumption of the P-channel transistor, and the second steady-state power consumption of the P-channel transistor are concatenated according to their temporal relationship within the switching cycle to form the first power consumption function of the N-chip and the P-chip. The N-chip power consumption function is the main input during the turn-on and steady-state conduction phases of the N-channel transistor, and its value is reduced to low loss or turn-off loss during the conduction phase of the P-channel transistor. The P-chip power consumption function complements it. The first power consumption function can retain the peak power consumption, steady-state conduction loss, and dead-zone freewheeling loss caused by the alternating conduction of the N / P-channel transistors, and can reflect the characteristic that the lateral heat flow direction periodically reverses with the temperature difference between the two chips. The first power consumption function of the N-chip is loaded into the junction node of the first thermal resistance network, and the first power consumption function of the P-chip is loaded into the junction node of the second thermal resistance network. These functions serve as a dual excitation source for the thermal resistance and thermal capacitance network to solve for the real-time junction temperature, and the junction temperature is fed back to the on-resistance and threshold voltage compensation model at each simulation time step.

[0038] In one specific embodiment, within one switching cycle, transient power consumption modeling is performed on the N-transistor to obtain the first transient power consumption of the N-transistor; steady-state power consumption modeling is performed on the N-transistor to obtain the first steady-state power consumption of the N-transistor; transient power consumption modeling is performed on the P-transistor to obtain the second transient power consumption of the P-transistor; steady-state power consumption modeling is performed on the P-transistor to obtain the second steady-state power consumption of the P-transistor, including: Within one switching cycle, the first transient power consumption of the N-transistor is calculated based on the linear decrease of the drain-source voltage from the bus voltage to the N-transistor's on-state voltage drop and the linear increase of the drain current from zero to the load current. Obtain the on-resistance of the N-transistor and multiply it by the square of the load current to get the first steady-state power dissipation of the N-transistor. Within one switching cycle, the second transient power consumption of the P-transistor is calculated based on the linear decrease of the drain-source voltage of the P-transistor from the bus voltage to the P-transistor on-state voltage drop and the linear increase of the drain current of the P-transistor from zero to the load current. Obtain the on-resistance of the P-tube and multiply it by the square of the load current to get the second steady-state power dissipation of the P-tube.

[0039] Specifically, the alternating conduction boundary between the N-channel and P-channel transistors is determined within one switching cycle. The switching cycle is preset to be determined by the switching frequency. An initial switching frequency of 100kHz can be used, corresponding to a switching cycle of 10μs. The duty cycle is set to 0.5, with the N-channel and P-channel transistors occupying the main conduction intervals respectively. The dead time is set to 100ns. The forward voltage drop of the body diode is selected within the range of 0.7V to 1.2V, with an initial value of 0.9V. During the transition period of the N-channel transistor, the process of the drain-source voltage of the N-channel transistor gradually decreasing from the bus voltage to the conduction voltage drop is considered a linear decrease. Simultaneously, the process of the drain current of the N-channel transistor gradually increasing from zero to the load current is considered a linear increase. The product of voltage and current is calculated moment by moment during the transition period to obtain the first transient power dissipation of the N-channel transistor, expressed as:

[0040] in, Bus voltage For load current, for On-resistance of the tube for Pipeline opening and transition time. For the relative time within the segment, the physical meaning of the above formula is to multiply the gradually decreasing drain-source voltage by the gradually increasing drain current to preserve the short-term peak power consumption during the turn-on pass segment. After the transistor enters the steady-state conduction phase, the drain-source voltage is no longer calculated according to the linear decrease process of the bus voltage, but is determined by the load current and the real-time on-resistance. At this point, the... The on-resistance of the transistor at the current junction temperature is calculated by multiplying it by the square of the load current. First steady-state power consumption of the tube:

[0041] in, for The chip's real-time junction temperature affects its power consumption, which varies with the junction temperature; therefore, it can serve as a dynamic heat source in the thermoelectric closed-loop iteration. For The pipe, within its opened ferry section, adopts the same... Using the same modeling ideas, The drain-source voltage of the tube decreases linearly from the bus voltage to The voltage drop during pipe conduction, and The absolute value of the drain current rises linearly from zero to the load current, obtained by multiplying the voltage and current. The second transient power consumption is controlled by simply replacing the corresponding parameter with On-resistance of the tube Pipe opening and transition time Real-time junction temperature of the chip; After the tube enters the steady-state conduction phase, it obtains... The on-resistance of the transistor at the current junction temperature is calculated by multiplying it by the square of the load current. Second steady-state power consumption of the tube:

[0042] in, for tube follow The on-resistance of the chip as the junction temperature changes in real time. for Real-time junction temperature of the chip.

[0043] The first transient power consumption of the N-channel transistor is arranged in the turn-on transition section, and the first steady-state power consumption of the N-channel transistor is arranged in the stable conduction section. The second transient power consumption of the P-channel transistor is arranged in the turn-on transition section, and the second steady-state power consumption of the P-channel transistor is arranged in the stable conduction section. Short-term heat sources are included in the dead zone according to the freewheeling loss of the body diode, so that the N-chip and P-chip form a power consumption sequence that switches over time. The power consumption sequence is used as the excitation source of the packaged thermal network and is applied to the junction nodes of the N-chip and P-chip respectively, so that the thermal network can calculate the real-time junction temperature according to the power consumption input at each time step, and feed back the junction temperature change to update the on-resistance.

[0044] In one specific embodiment, such as Figure 3 The process of executing step 102 may specifically include the following steps: 301. Construct a temperature model for an N-channel MOSFET based on the electron mobility temperature coefficient; construct a temperature model for a P-channel MOSFET based on the hole mobility temperature coefficient. 302. Construct an N-channel transistor voltage model based on the linear drift slope of the N-chip threshold voltage; construct a P-channel transistor voltage model based on the linear slope of the P-chip threshold voltage. 303. Combine the N-channel temperature model with the N-channel voltage model to obtain the first compensation model for the N-chip; combine the P-channel temperature model with the P-channel voltage model to obtain the second compensation model for the P-chip.

[0045] Specifically, the real-time junction temperatures of the N-chip and P-chip, output from the thermal network, are used as inputs to the compensation model, with 298K as the reference temperature. This allows the on-resistance and threshold voltage to be dynamically updated as the junction temperature changes. For N-channel MOSFETs, since the majority carriers are electrons, the electron mobility decreases power-lawfully with increasing temperature. The electron mobility temperature index of 2.42 is retained, and the on-resistance temperature index of the N-channel MOSFET is preset to 2.42, with an adjustable range of 2.3 to 2.5. This establishes the N-channel MOSFET temperature model.

[0046] in, This represents the on-resistance of the N-transistor at the real-time junction temperature of the N-chip. This represents the on-resistance of the N-transistor at the reference temperature. This indicates the real-time junction temperature of the N-chip. Take 298K, This represents the temperature index of the on-resistance of an N-channel MOSFET. For a P-channel MOSFET, since the majority carriers are holes, the absolute value of the temperature index of hole mobility is smaller than that of electrons. Therefore, the hole mobility temperature index of 2.20 is retained, and the on-resistance temperature index of the P-channel MOSFET is preset to 2.20, with an adjustable range of 2.0 to 2.3 in engineering applications. This establishes the temperature model for the P-channel MOSFET.

[0047] in, This represents the on-resistance of the P-transistor at the real-time junction temperature of the P-chip. This represents the on-resistance of the P-transistor at the reference temperature. This indicates the real-time junction temperature of the P chip. This represents the temperature coefficient of conduction resistance of the P-type transistor. Based on this, a voltage model is constructed according to the approximately linear temperature drift of the threshold voltages of the N-type and P-type transistors, where the temperature coefficient of the threshold voltage of the N-type transistor is negative. to Select from the range, initial preset is The threshold voltage of a P-type transistor is defined as negative and drifts towards zero as temperature increases; its temperature coefficient is positive. to Select from the range, initial preset is The linear drift slope is written into the model as a configurable parameter, so that the real-time junction temperature change can correct the corresponding threshold voltage.

[0048] The real-time on-resistance output from the N-channel temperature model is combined with the real-time threshold voltage output from the N-channel voltage model to form the first compensation model for the N-chip. The real-time on-resistance output from the P-channel temperature model is combined with the real-time threshold voltage output from the P-channel voltage model to form the second compensation model for the P-chip. In each simulation time step, the packaged thermal network first calculates the junction temperature of the two chips based on the current power consumption of the N / P-channels. Then, the junction temperature is substituted into the first and second compensation models respectively to obtain the updated N-channel on-resistance, N-channel threshold voltage, P-channel on-resistance, and P-channel threshold voltage. These parameters are then fed back into the power consumption function of the next time step, so that the temperature coefficient difference caused by the different carrier types of the N / P-channels can be directly reflected in the conduction loss, switching process, and current waveform.

[0049] In one specific embodiment, the process of performing step 302 may specifically include the following steps: The first voltage temperature coefficient is fitted based on the linear drift slope of the N-chip threshold voltage, and an N-transistor voltage model is constructed based on the first voltage temperature coefficient and the N-transistor threshold voltage. The second voltage temperature coefficient is fitted with a linear slope based on the threshold voltage of the P-chip, and a P-tube voltage model is constructed based on the second voltage temperature coefficient and the threshold voltage of the P-tube.

[0050] Specifically, the threshold voltage data of N-chips and P-chips at different temperature points are organized into a temperature-threshold voltage correspondence, with 298K as the reference temperature. Since the threshold voltage can drift approximately linearly within the common operating temperature range of power MOSFETs, the corresponding threshold voltages can be read at low temperature, room temperature, and high temperature calibration points. Then, a linear slope fitting is performed on these data. The slope of the threshold voltage change of the N-chip with temperature is determined as the first voltage temperature coefficient, and the slope of the threshold voltage change of the P-chip with temperature is determined as the second voltage temperature coefficient. For N-channel MOSFETs, since their threshold voltage typically drifts towards lower voltages with increasing temperature, the first voltage temperature coefficient is negative. The first voltage temperature coefficient and the N-channel MOSFET threshold voltage at the reference temperature are then incorporated into the N-channel MOSFET voltage model.

[0051] For P-type transistors, since the threshold voltage is defined as negative, its absolute value decreases and drifts towards zero as the temperature increases. Therefore, the second voltage temperature coefficient is taken as positive, and it is written together with the P-type threshold voltage at the reference temperature into the P-type voltage model.

[0052] in, and These are the real-time junction temperatures of the N-chip and the P-chip, respectively. and These are the threshold voltages of the N-type and P-type transistors at 298K respectively. and These are the first and second voltage temperature coefficients, respectively. In actual simulation, at each time step, the real-time junction temperature of the two chips is first obtained from the package thermal network. Then, the real-time junction temperature is substituted into the corresponding voltage model to obtain the threshold voltage of the N-channel transistor and the threshold voltage of the P-channel transistor at the current temperature. This result is fed back to the device electrical model and power consumption calculation process, so that the gate drive margin, conduction state judgment, and subsequent current waveform calculation during the turn-on transition stage can be synchronously corrected with the junction temperature change.

[0053] In one specific embodiment, such as Figure 4 The process of executing step 103 may specifically include the following steps: 401. In each simulation time step, the packaged thermal network is driven by the first power consumption function to solve for the first real-time junction temperature of the N chip and the second real-time junction temperature of the P chip. 402. Substitute the first real-time junction temperature of the N chip into the first compensation model and the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulate to obtain the first current waveform of the N chip and the second current waveform of the P chip.

[0054] Specifically, the packaged thermal network is converted into a thermal equivalent network solvable in transient simulation. The first power consumption functions of the N-chip and P-chip are respectively used as two thermal excitation sources and loaded onto the corresponding junction nodes. The power consumption input changes with the alternating conduction sequence within the switching cycle, rather than using a fixed average power consumption. Therefore, the intensity of the heat source received by the thermal network will be continuously updated with time steps during different time periods such as N-chip turn-on, N-chip steady-state conduction, P-chip turn-on, P-chip steady-state conduction, and dead-time freewheeling. The ambient temperature is used as the reference node of the thermal network. The initial condition is set to the first real-time junction temperature of the N-chip and the second real-time junction temperature of the P-chip are both equal to the ambient temperature, for example, the ambient temperature is preset to 298K. Each thermal resistance and thermal capacitance unit is connected to the junction node, solder layer node, DBC copper layer node, ceramic substrate node, and shell node according to the Cauer type hierarchy. At the same time, the lateral thermal coupling thermal resistance and lateral thermal capacitance are connected between the DBC copper layer nodes of the N-chip and P-chip, so that the temperature solutions of the two chips are no longer independent, but are jointly affected by the vertical heat dissipation path and the lateral thermal crosstalk path in the same packaged thermal network. The simulation starts at t=0 and progresses in time steps. At each time step, the first power consumption function value at the current moment is read, and the power consumption of the N chip is input to the node of the first thermal resistance network, and the power consumption of the P chip is input to the node of the second thermal resistance network. Then, the thermal responses of the two vertical thermal branches and the intermediate transverse coupling branch are solved simultaneously to obtain the first real-time junction temperature of the N chip and the second real-time junction temperature of the P chip at the current time step. The time step of the transition segment can be taken as one-twentieth of the turn-on transition time, and the time step of the steady-state conduction segment can be taken as one-hundredth of the switching period. If the preset switching frequency is 100kHz, the switching period is 10μs. The basic sampling interval of the steady-state conduction segment can be set to 0.1μs, while the turn-on transition segment is further refined according to the actual turn-on time so that the thermal network can receive a sufficiently dense number of transient power consumption sampling points.

[0055] The first real-time junction temperature of the N-chip is input into the first compensation model, and the second real-time junction temperature of the P-chip is input into the second compensation model. The first compensation model outputs the on-resistance and threshold voltage of the N-chip at the current time step, and the second compensation model outputs the on-resistance and threshold voltage of the P-chip at the current time step. The updated device parameters are then fed back to the power consumption calculation process for the next time step. Since the majority carrier types of the N-chip and the P-chip are different, the first compensation model and the second compensation model use different temperature response parameters. Therefore, even if the two chips are in the same package, their on-resistance increase, threshold voltage drift, and current change will be independently corrected according to their respective real-time junction temperatures. Through time-step loops, the first power consumption function drives the packaged thermal network to generate a real-time junction temperature. The real-time junction temperature then corrects the device electrical parameters, and the corrected electrical parameters affect the power consumption function of the next time step. This forms a closed-loop process of "power consumption input - thermal network solution - junction temperature feedback - parameter compensation - power consumption update" until the preset simulation time is reached. For example, the total simulation time can be set from 10ms to 100ms to cover the temperature rise changes under multiple thermal time constants. After the simulation is completed, the first current waveform of the N chip and the second current waveform of the P chip are output in chronological order.

[0056] In one specific embodiment, the process of performing step 402 may specifically include the following steps: Substitute the first real-time junction temperature into the first compensation model to calculate the first on-resistance and the first threshold voltage; substitute the second real-time junction temperature into the second compensation model to calculate the second on-resistance and the second threshold voltage. The first on-resistance, the first threshold voltage, the second on-resistance, and the second threshold voltage are fed back to the first power consumption function to generate the second power consumption function; The packaged thermal network is driven by the second power consumption function. The simulation is iterated in the next simulation time step and executed repeatedly until the simulation time ends, so as to obtain the first current waveform of the N chip and the second current waveform of the P chip.

[0057] Specifically, in the Within each simulation time step, the first real-time junction temperature and the second real-time junction temperature output from the packaged thermal network are received. The first real-time junction temperature is input into the first compensation model of the N-chip, and the second real-time junction temperature is input into the second compensation model of the P-chip. The first compensation model calculates the first on-resistance and the first threshold voltage based on the first real-time junction temperature, as follows:

[0058]

[0059] Obtain the N-tube electrical parameters at the current time step; the second compensation model calculates the second on-resistance and the second threshold voltage based on the second real-time junction temperature, which can be done as follows:

[0060]

[0061] The electrical parameters of the P-tube at the current time step are obtained, where and These correspond to the real-time junction temperatures of the two chips, , , , These correspond to the on-resistance and threshold voltage at the reference temperature, respectively. The first on-resistance and first threshold voltage are written back to the N-transistor power consumption calculation branch, and the second on-resistance and second threshold voltage are written back to the P-transistor power consumption calculation branch. This updates the original first power consumption function from the power consumption expression using the initial device parameters to the second power consumption function using the current temperature compensation parameters. During the update process, the drain-source voltage drop endpoint of the N-transistor's turn-on transient, the on-state voltage drop, and the conduction loss are all corrected according to the first on-resistance. The turn-on transient and steady-state conduction of the P-transistor are also synchronously corrected according to the second on-resistance. Simultaneously, changes in the threshold voltage affect the turn-on boundary, drive margin, and current rise process, thus enabling the second power consumption function to reflect the impact of the previous time step temperature rise on the current electrical parameters.

[0062] Using the second power consumption function as the heat source input for the next simulation time step, the thermal networks of the packages containing the N-chip junction nodes and the P-chip junction nodes are driven respectively. The vertical Cauer thermal branch and the lateral thermal coupling branch of the DBC copper layer are solved simultaneously to obtain the new junction temperatures of the two chips in the next time step. The new junction temperatures are then fed into the first compensation model and the second compensation model to recalculate the on-resistance and threshold voltage, and generate the updated power consumption function again. This process is repeated until the preset simulation duration is reached. For example, the total simulation duration can be set from 10ms to 100ms. The time step is set to one-twentieth of the transition time in the turn-on transition phase and one-hundredth of the switching cycle in the steady-state conduction phase. Finally, the drain current values ​​of the N-chip and P-chip at each time step can be recorded in chronological order, forming the first current waveform of the N-chip and the second current waveform of the P-chip.

[0063] The above describes the thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs in embodiments of the present invention. The following describes the thermoelectric synergistic design device for complementary dual-chip co-packaged power MOSFETs in embodiments of the present invention. Please refer to [link to relevant documentation]. Figure 2 One embodiment of the thermoelectric co-design device for complementary dual-chip co-packaged power MOSFETs in this invention includes: Create module 501 to create the packaged thermal network of N chip and P chip in co-packaged device, and use the first power consumption function of N chip and P chip as the excitation source of packaged thermal network. The compensation model establishment module 502 is used to establish the first compensation model of the N chip and the second compensation model of the P chip. The iterative simulation module 503 is used to drive the packaged thermal network by the first power consumption function in each simulation time step, substitute the first real-time junction temperature of the N chip into the first compensation model and substitute the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulate to obtain the first current waveform of the N chip and the second current waveform of the P chip.

[0064] Through the collaborative efforts of the aforementioned components, by explicitly introducing lateral thermal coupling resistance and lateral thermal capacitance between the DBC copper layer nodes of the N-chip and P-chip, the lateral thermal conduction path between the two chips is incorporated into the packaged thermal network. This allows the simulation model to accurately capture the lateral heat accumulation effect transmitted to the P-chip during N-channel conduction and its periodic reversal pattern with alternating conduction timing, solving the systematic lack of thermal crosstalk effect caused by neglecting the lateral thermal coupling path in existing technologies. The first power consumption function of the alternating N-channel and P-channel conduction is used to replace the average power consumption excitation of existing technologies. Both the peak power consumption during the transition phase and the temperature-dependent power consumption during the steady-state conduction phase are incorporated into the thermal network excitation source, enabling accurate reconstruction of the junction temperature peak calculation and thermal crosstalk periodic characteristics. Based on the physical difference in the majority carrier mobility temperature coefficients of N-channel and P-channel MOSFETs, independent power-law temperature compensation models for conduction resistance and linear temperature compensation models for threshold voltage are established for the two chips respectively. By feeding the junction temperature back to the device parameter update in real time at each simulation time step, bidirectional coupled iteration of circuit solution and thermal network solution is achieved.

[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0066] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0067] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs, characterized in that, include: Create a packaged thermal network for N-chip and P-chip in a co-packaged device, and use the first power consumption function of the N-chip and the P-chip as the excitation source of the packaged thermal network; Establish a first compensation model for the N chip and a second compensation model for the P chip; Within each simulation time step, the packaged thermal network is driven by the first power consumption function. The first real-time junction temperature of the N chip is substituted into the first compensation model, and the second real-time junction temperature of the P chip is substituted into the second compensation model. The simulation is iterative to obtain the first current waveform of the N chip and the second current waveform of the P chip.

2. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 1, characterized in that, The creation of a packaged thermal network for the N-chip and P-chip in a co-packaged device, using a first power consumption function of the N-chip and P-chip as the excitation source for the packaged thermal network, includes: Cauer-type thermal resistance and thermal capacity calculations are performed on the N-chip and P-chip in the co-packaged device to obtain the first thermal resistance network of the N-chip and the second thermal resistance network of the P-chip. Calculate the lateral thermal coupling resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip, and connect the lateral thermal coupling resistance and the lateral thermal capacity between the DBC copper layer nodes of the first thermal resistance network and the second thermal resistance network to obtain the packaged thermal network. Modeling is performed on N-channel transistors and P-channel transistors respectively to obtain the first power consumption function of the N-chip and the P-chip, and the first power consumption function is used as the excitation source of the packaged thermal network.

3. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 2, characterized in that, The calculation of the lateral thermal coupling thermal resistance and lateral thermal capacitance between the DBC copper layer nodes of the N chip and the P chip, and the connection of the lateral thermal coupling thermal resistance and the lateral thermal capacitance between the DBC copper layer nodes of the first thermal resistance network and the second thermal resistance network to obtain the packaged thermal network, includes: The effective heat transfer width of the transverse heat flow is calculated based on the N chip and the P chip; The lateral thermal coupling thermal resistance and lateral thermal capacity between the DBC copper layer nodes of the N chip and the P chip are calculated based on the effective heat transfer width of the lateral heat flow. The lateral thermal coupling thermal resistor and the lateral thermal capacitance are connected between the DBC copper layer node of the first thermal resistance network and the DBC copper layer node of the second thermal resistance network to obtain the encapsulated thermal network.

4. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 3, characterized in that, The step of modeling the N-channel and P-channel transistors respectively to obtain the first power consumption functions of the N-chip and the P-chip, and using the first power consumption function as the excitation source of the packaged thermal network, includes: Within one switching cycle, transient power consumption modeling is performed on the N-transistor to obtain the first transient power consumption of the N-transistor; steady-state power consumption modeling is performed on the N-transistor to obtain the first steady-state power consumption of the N-transistor; transient power consumption modeling is performed on the P-transistor to obtain the second transient power consumption of the P-transistor; steady-state power consumption modeling is performed on the P-transistor to obtain the second steady-state power consumption of the P-transistor. Based on the first transient power consumption, the first steady-state power consumption, the second transient power consumption, and the second steady-state power consumption of the N-transistor, a first power consumption function for the N-chip and the P-chip is constructed, and the first power consumption function is used as the excitation source for the packaged thermal network.

5. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 4, characterized in that, Within one switching cycle, transient power consumption modeling is performed on the N-transistor to obtain the first transient power consumption of the N-transistor; steady-state power consumption modeling is performed on the N-transistor to obtain the first steady-state power consumption of the N-transistor. Transient power consumption modeling of P-transistor is performed to obtain the second transient power consumption of P-transistor; Steady-state power consumption modeling of the P-transistor yields its second steady-state power consumption, including: Within one switching cycle, the first transient power consumption of the N-transistor is calculated based on the linear decrease of the drain-source voltage from the bus voltage to the N-transistor's on-state voltage drop and the linear increase of the drain current from zero to the load current. Obtain the on-resistance of the N-transistor and multiply the on-resistance of the N-transistor by the square of the load current to obtain the first steady-state power consumption of the N-transistor. Within one switching cycle, the second transient power consumption of the P-transistor is calculated based on the linear decrease of the drain-source voltage of the P-transistor from the bus voltage to the P-transistor on-state voltage drop and the linear increase of the drain current of the P-transistor from zero to the load current. Obtain the on-resistance of the P-tube and multiply it by the square of the load current to obtain the second steady-state power consumption of the P-tube.

6. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 5, characterized in that, The establishment of the first compensation model for the N chip and the second compensation model for the P chip includes: A temperature model for an N-channel MOSFET is constructed based on the electron mobility temperature coefficient; a temperature model for a P-channel MOSFET is constructed based on the hole mobility temperature coefficient. An N-channel voltage model is constructed based on the linear drift slope of the N-chip threshold voltage; a P-channel voltage model is constructed based on the linear slope of the P-chip threshold voltage. The N-channel temperature model and the N-channel voltage model are combined to obtain the first compensation model for the N-chip; the P-channel temperature model and the P-channel voltage model are combined to obtain the second compensation model for the P-chip.

7. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 6, characterized in that, The construction of the N-channel voltage model based on the linear drift slope of the N-chip threshold voltage; and the construction of the P-channel voltage model based on the linear slope of the P-chip threshold voltage, including: The first voltage temperature coefficient is fitted based on the linear drift slope of the N-chip threshold voltage, and an N-transistor voltage model is constructed based on the first voltage temperature coefficient and the N-transistor threshold voltage. The second voltage temperature coefficient is fitted with a linear slope based on the threshold voltage of the P-chip, and a P-tube voltage model is constructed based on the second voltage temperature coefficient and the threshold voltage of the P-tube.

8. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 7, characterized in that, In each simulation time step, the packaged thermal network is driven by the first power consumption function. The first real-time junction temperature of the N chip is substituted into the first compensation model, and the second real-time junction temperature of the P chip is substituted into the second compensation model. Iterative simulation is performed to obtain the first current waveform of the N chip and the second current waveform of the P chip, including: Within each simulation time step, the packaged thermal network is driven by the first power consumption function to solve for the first real-time junction temperature of the N chip and the second real-time junction temperature of the P chip; Substitute the first real-time junction temperature of the N chip into the first compensation model and the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulate to obtain the first current waveform of the N chip and the second current waveform of the P chip.

9. The thermoelectric synergistic design method for complementary dual-chip co-packaged power MOSFETs according to claim 8, characterized in that, The step of substituting the first real-time junction temperature of the N chip into the first compensation model and the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulating to obtain the first current waveform of the N chip and the second current waveform of the P chip, includes: Substitute the first real-time junction temperature into the first compensation model to calculate the first on-resistance and the first threshold voltage; substitute the second real-time junction temperature into the second compensation model to calculate the second on-resistance and the second threshold voltage. The first on-resistance, the first threshold voltage, the second on-resistance, and the second threshold voltage are fed back to the first power consumption function to generate the second power consumption function; The packaged thermal network is driven by the second power consumption function, and the simulation is iterated in the next simulation time step. The simulation is repeated until the simulation time ends, and the first current waveform of the N chip and the second current waveform of the P chip are obtained.

10. A thermoelectric synergistic design device for complementary dual-chip co-packaged power MOSFETs, characterized in that, A thermoelectric co-design method for performing complementary dual-chip co-packaged power MOSFETs as described in any one of claims 1-9, comprising: A creation module is used to create a packaged thermal network for N-chips and P-chips in a co-packaged device, and the first power consumption function of the N-chips and P-chips is used as the excitation source of the packaged thermal network. The compensation model establishment module is used to establish a first compensation model for the N chip and a second compensation model for the P chip. The iterative simulation module is used to drive the packaged thermal network by the first power consumption function in each simulation time step, substitute the first real-time junction temperature of the N chip into the first compensation model and substitute the second real-time junction temperature of the P chip into the second compensation model, and iteratively simulate to obtain the first current waveform of the N chip and the second current waveform of the P chip.

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