Constraint determination method, circuit size adjustment method, device, apparatus and medium

Abstract

The application provides a constraint determination method, a circuit size adjustment method, a device, equipment and a medium. It relates to the technical field of circuit layout design. The constraint determination method comprises: obtaining circuit data to be processed; wherein the circuit data comprises netlist data and text description information corresponding to the circuit to be adjusted; determining the size adjustment constraint corresponding to the circuit to be adjusted according to the circuit data; wherein the size adjustment constraint is used as the adjustment constraint when the circuit to be adjusted is adjusted in size. The method of the application solves the problem of time-consuming and low efficiency in the existing circuit size adjustment process, and improves the adjustment efficiency of circuit size adjustment.

Description

Technical Field

[0001] This application relates to the field of circuit layout design technology, and in particular to a constraint determination method, a circuit size adjustment method, an apparatus, a device, and a medium. Background Technology

[0002] As electronic devices become increasingly complex, optimizing circuit design to improve performance, reduce power consumption, and enhance stability has become a significant challenge for engineers.

[0003] In circuit layout design, adjusting circuit dimensions is a crucial step in ensuring circuit performance, manufacturability, and cost control. Currently, dimension adjustment methods can be manual, relying on experience to gradually change component dimensions and observe performance changes; or automatic optimization algorithms, such as genetic algorithms and simulated annealing algorithms, can be used to search for the optimal combination of dimensions in the design space.

[0004] However, existing size adjustment methods have significant drawbacks, namely, they are time-consuming and inefficient. Therefore, there is an urgent need for a more efficient and intelligent method for circuit size adjustment to overcome the limitations of existing technologies. Summary of the Invention

[0005] This application provides a constraint determination method, a circuit size adjustment method, an apparatus, a device, and a medium to solve the problems of time-consuming and inefficient circuit size adjustment processes in the past, thereby improving the adjustment efficiency of circuit size adjustment.

[0006] In a first aspect, this application provides a method for determining size adjustment constraints, including:

[0007] Acquire the circuit data to be processed; wherein, the circuit data includes the netlist data and text description information corresponding to the circuit to be adjusted;

[0008] Based on the circuit data, the size adjustment constraint corresponding to the circuit to be adjusted is determined; wherein, the size adjustment constraint is used as the adjustment constraint when the circuit to be adjusted is sized.

[0009] In one optional implementation, determining the size adjustment constraint corresponding to the circuit to be adjusted based on the circuit data includes:

[0010] The circuit data is input into a preset constraint extraction model to obtain the size adjustment constraints corresponding to the circuit to be adjusted; wherein, the size adjustment constraints include the size constraint range of each component in the circuit to be adjusted, and the size constraint relationship between each component.

[0011] In one alternative implementation, the constraint extraction model consists of multiple sub-models, forming a multi-agent team; the multi-agent team includes an expert model and multiple assistant models.

[0012] The circuit data is input into a preset constraint extraction model to obtain the size adjustment constraints corresponding to the circuit to be adjusted, including:

[0013] The circuit data is input into the expert model to obtain at least one constraint to be verified, and the constraint extraction basis corresponding to the constraint to be verified.

[0014] For any assistant model, input any constraint to be verified, the constraint extraction basis, and the circuit data into the assistant model to obtain the constraint verification result of the constraint to be verified, and the constraint verification basis corresponding to the constraint verification result;

[0015] For any constraint to be verified, if the constraint verification result output by each of the assistant models indicates that the constraint to be verified has passed verification, then the constraint to be verified is used as the output of the constraint extraction model.

[0016] In one optional implementation, if the constraint verification result output by each of the assistant models indicates that the constraint to be verified has failed verification, then supplementary verification is performed cyclically.

[0017] If, after any supplementary verification, each of the assistant models indicates that the constraint to be verified has passed the verification, the loop process is immediately terminated, and the constraint to be verified is determined as a size adjustment constraint and output.

[0018] If the constraint to be verified still fails to pass the supplementary verification of each of the assistant models after the preset number of iterations, the verification process will stop, and the constraint to be verified will no longer be considered as a candidate for size adjustment constraint.

[0019] The supplementary verification process includes:

[0020] The circuit data, the constraint to be verified, the constraint extraction basis, the verification results of each constraint, and the constraint verification basis are input into the expert model to obtain the verification supplementary constraint corresponding to the constraint to be verified, and the verification supplementary constraint extraction basis corresponding to the verification supplementary constraint.

[0021] For any assistant model, the constraint to be verified, the constraint extraction basis, the verification supplementary constraint, the verification supplementary constraint extraction basis, and the circuit data are input into the assistant model to obtain the supplementary verification result of the constraint to be verified, and the supplementary constraint verification basis corresponding to the supplementary verification result.

[0022] In one alternative implementation, the method further includes:

[0023] When the circuit data, the constraint to be verified, the constraint extraction basis, the constraint verification results, and the constraint verification basis are input into the expert model, and the expert model outputs empty data, the circuit data, the constraint to be verified, the constraint extraction basis, the constraint verification results, and the constraint verification basis are input into a preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified.

[0024] If the final verification result indicates that the constraint to be verified has passed verification, the constraint to be verified is used as the output of the constraint extraction model.

[0025] In one alternative implementation, the method further includes:

[0026] If the supplementary verification results output by each of the assistant models indicate that the constraint to be verified has failed verification, then the constraint to be verified, the constraint extraction basis, the constraint verification result, the constraint verification basis, the verification supplementary constraint, the verification supplementary constraint extraction basis, the supplementary verification result, the supplementary constraint verification basis, and the circuit data are input into the preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified.

[0027] If the final verification result indicates that the constraint to be verified has passed verification, the constraint to be verified is used as the output of the constraint extraction model.

[0028] In one alternative implementation, the method further includes:

[0029] When the constraint to be verified is used as the output of the constraint extraction model, the circuit data is input into the expert model again to obtain at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified.

[0030] If the verification result of the supplementary constraint to be verified output by each of the assistant models indicates that the supplementary constraint to be verified has passed the verification, then the supplementary constraint to be verified is used as the output of the constraint extraction model.

[0031] In one alternative implementation, the method further includes:

[0032] For any assistant model, when the assistant model outputs the constraint verification result of the constraint to be verified and the constraint verification basis corresponding to the constraint verification result, the assistant model also outputs at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified.

[0033] If the verification result of the supplementary constraint to be verified corresponding to the supplementary constraint output by other assistant models indicates that the supplementary constraint to be verified has passed the verification, the supplementary constraint to be verified will be used as the output of the constraint extraction model.

[0034] In one alternative implementation, the expert model is a deep reasoning large language model, the assistant model is a lightweight large language model, and the constraint verification model is a lightweight large language model.

[0035] In one optional implementation, the circuit data includes text description information corresponding to the circuit to be adjusted and netlist data of the circuit to be adjusted;

[0036] Acquire the circuit data to be processed, including:

[0037] Acquire the raw circuit data to be processed;

[0038] The original circuit data is parsed to obtain the graphic description information corresponding to the circuit to be adjusted; the graphic description information includes the circuit diagram and text description information corresponding to the circuit to be adjusted.

[0039] The circuit diagram is analyzed to identify components and their parameters, thereby obtaining the netlist data corresponding to the circuit to be adjusted.

[0040] Secondly, this application provides a method for adjusting circuit dimensions, including:

[0041] Obtain the original search space corresponding to the circuit to be adjusted;

[0042] The original search space is updated according to the size adjustment constraint, and the size of the circuit to be adjusted is adjusted according to the updated search space; wherein the size adjustment constraint is determined according to the size adjustment constraint determination method described in any one of the first aspects.

[0043] Thirdly, this application provides a size adjustment constraint determination device, comprising:

[0044] A circuit data acquisition module is used to acquire circuit data to be processed; wherein, the circuit data includes netlist data and text description information corresponding to the circuit to be adjusted;

[0045] The size adjustment constraint determination module is used to determine the size adjustment constraint corresponding to the circuit to be adjusted based on the circuit data; wherein, the size adjustment constraint is used as the adjustment constraint when the circuit to be adjusted is subjected to size adjustment.

[0046] Fourthly, this application provides a circuit size adjustment device, comprising:

[0047] The original search space acquisition module is used to acquire the original search space corresponding to the circuit to be adjusted;

[0048] A size adjustment module is used to update the original search space according to size adjustment constraints, and to adjust the size of the circuit to be adjusted according to the updated search space; wherein the size adjustment constraints are determined according to the size adjustment constraint determination method according to any one of the first aspects.

[0049] Fifthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0050] The memory stores computer-executed instructions;

[0051] The processor executes computer execution instructions stored in the memory to implement the method as described in the first aspect.

[0052] In a sixth aspect, this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method described in the first aspect.

[0053] In a seventh aspect, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0054] The size adjustment constraint determination technology provided in this application obtains the potential constraint conditions corresponding to the circuit to be adjusted by acquiring circuit data containing netlist data and text description information. This overcomes the limitation of insufficient utilization of prior knowledge in traditional adjustment schemes. Furthermore, the extracted size adjustment constraints provide precise guidance for subsequent circuit size adjustments, enabling efficient pruning of the design space, reducing redundant parameter searches, and improving the efficiency of circuit size adjustment. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0056] Figure 1 An application scenario diagram of the size adjustment constraint determination method provided in this application;

[0057] Figure 2 A flowchart illustrating a method for determining size adjustment constraints provided in an embodiment of this application;

[0058] Figure 3 A flowchart illustrating a constraint extraction and verification process provided in an embodiment of this application;

[0059] Figure 4 A flowchart illustrating another constraint extraction and verification process provided for an embodiment of this application;

[0060] Figure 5 A flowchart illustrating another constraint extraction and verification process provided for an embodiment of this application;

[0061] Figure 6 A flowchart illustrating another constraint extraction and verification process provided for an embodiment of this application;

[0062] Figure 7 A flowchart illustrating a method for determining size adjustment constraints provided in an embodiment of this application;

[0063] Figure 8 This is a schematic diagram of a size adjustment constraint determination device provided in an embodiment of this application;

[0064] Figure 9 This is a schematic diagram of the structure of a circuit size adjustment device provided in an embodiment of this application;

[0065] Figure 10 This is a block diagram illustrating an electronic device provided in an embodiment of this application.

[0066] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0067] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0068] The collection, storage, use, processing, transmission, provision, and disclosure of financial data or user data involved in the technical solution of this application all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0069] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. The collection, use and processing of the relevant data shall comply with relevant laws, regulations and standards, and corresponding operation entry points shall be provided for users to choose to authorize or refuse.

[0070] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0071] Terminology Explanation

[0072] Circuit layout design is the process of arranging the various components and modules in a circuit on a printed circuit board (PCB) or chip according to certain rules and requirements. The purpose is to optimize the space utilization of the circuit, facilitate manufacturing, debugging and maintenance, and reduce costs while meeting the requirements of electrical performance, signal integrity and electromagnetic compatibility.

[0073] In circuit layout design, circuit size adjustment is a crucial step in ensuring circuit performance, manufacturability, and cost control. In other words, circuit size adjustment involves determining the optimal size parameters of each component (such as transistors, resistors, and capacitors) in the circuit based on circuit performance indicators (such as gain, bandwidth, and power consumption) and constraints (such as chip area and process limitations) to ensure stable and efficient operation of the circuit under different operating conditions.

[0074] In practical applications, circuit size adjustment schemes primarily rely on prior information such as circuit topology characteristics, process constraints, and historical design experience from the circuit design field to adjust component dimensions. However, these schemes fail to fully utilize the design principles described in the relevant resources of the circuit to be adjusted, or the constraints such as the connection relationships and dimensional relationships of various components in the circuit diagram, as prior knowledge. This deficiency leads to the inability to effectively utilize the aforementioned prior knowledge for pruning and optimization of the design space of the circuit to be adjusted when searching for the optimal size combination, resulting in a blind search within a large range of redundant parameters. This not only wastes computational resources but also reduces the efficiency of circuit size adjustment.

[0075] The size adjustment constraint determination method provided in this application aims to solve the above-mentioned technical problems in the implementation process. Specifically, by acquiring circuit data containing netlist data and text description information corresponding to the circuit to be adjusted, the potential constraint conditions corresponding to the circuit to be adjusted are obtained. This overcomes the limitation of insufficient utilization of prior knowledge in traditional adjustment schemes. Furthermore, the extracted size adjustment constraints provide precise guidance for subsequent circuit size adjustments, achieving efficient pruning of the design space, reducing redundant parameter searches, and improving the efficiency of circuit size adjustment.

[0076] The technical solution provided in this application can be applied to circuit layout design scenarios. In an integrated circuit design project, engineers face the challenge of optimizing circuit performance to meet stringent power consumption and performance requirements. When initial simulation of the current circuit design is performed based on circuit performance indicators, if the simulation results show that there are components and parameters in the current circuit design that need adjustment, the circuit is identified as the circuit to be adjusted. Based on this, the size constraint determination method provided in this application is used to extract circuit data from resources such as netlist data and text description information indicating the circuit to be adjusted, literature, requirement documents, and forum posts, and to determine the size adjustment constraints corresponding to the circuit to be adjusted based on the circuit data. Through these extracted size adjustment constraints, precise guidance is provided for subsequent circuit size adjustments, achieving efficient pruning of the design space, reducing the search for redundant parameters, and significantly improving the efficiency of circuit size adjustments.

[0077] Figure 1 This diagram illustrates an application scenario of the size adjustment constraint determination method provided in this application. For ease of understanding, the following is based on… Figure 1 The application scenarios applicable to the embodiments of this application are described below. See also... Figure 1 The information extraction technology provided in this application involves a data acquisition device 101, a size adjustment constraint determination device 102, and a size adjustment device 103. Specifically, in the data acquisition device 101, circuit data including netlist data and text description information corresponding to the circuit to be adjusted can be obtained through optical character recognition (OCR) technology, and the circuit data is transmitted to the size adjustment constraint determination device for size constraint determination processing.

[0078] In the size adjustment constraint determination device 102, the circuit data is processed through a series of methods such as preset algorithms and neural network models to obtain the size adjustment constraints corresponding to the circuit to be adjusted, and the obtained size adjustment constraints are output to the size adjustment device 103 for adjustment processing.

[0079] In the size adjustment device 103, the performance indicators of the designed circuit can be predetermined, and initial simulations can be performed based on these indicators. When the simulation results show that there are components and parameters in the current circuit design that need adjustment, the circuit is marked as a circuit to be adjusted. Based on this, the received size adjustment constraints can be used as precise guidance for subsequent circuit size adjustments, thereby achieving efficient pruning of the design space, reducing the search for redundant parameters, and significantly improving the efficiency of circuit size adjustment.

[0080] It should be understood that the size adjustment constraint determination method provided in this application can be applied not only to circuit layout optimization scenarios, but also to various other scenarios such as chip design, microelectronic device development, system-level integration, signal processing optimization, automated control system design, and other engineering fields requiring precise parameter adjustment and optimization. This application does not specifically limit the application scenarios of the provided information extraction technology.

[0081] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0082] Figure 2 This is a flowchart illustrating a method for determining size adjustment constraints according to an embodiment of this application. The method can be executed by a size adjustment constraint determining device, which can be a server or an electronic device. The following description uses an electronic device as an example. The method in this embodiment can be implemented through software, hardware, or a combination of both. Figure 2 As shown, the method includes the following steps:

[0083] S201. Obtain the circuit data to be processed; wherein, the circuit data includes the netlist data and text description information corresponding to the circuit to be adjusted.

[0084] Circuit data can be understood as a set of data containing information describing the circuit to be adjusted. In this application, circuit data may specifically include netlist data corresponding to the circuit to be adjusted and textual description information.

[0085] In this context, the netlist data of the circuit to be adjusted refers to a textual representation describing the various components in the circuit and their connections. Netlist data typically includes information such as component type, name, connection nodes, and related electrical parameters. The textual description information, on the other hand, is used to elaborate on the circuit's function, structure, and other relevant characteristics. This textual description information may include, but is not limited to, textual descriptions, tabular data, and related formulas.

[0086] Using the data contained in the text description information and netlist data as prior knowledge for subsequent size adjustment, that is, accurately extracting size constraints from the above data, and pruning and optimizing the size space of the circuit to be adjusted based on this prior knowledge when searching for the optimal size space of the circuit, avoiding blind searching within a large range of redundant parameters, and improving the efficiency of circuit size adjustment.

[0087] Optionally, the circuit data may also include module category data of the circuit to be adjusted. Module category data of the circuit to be adjusted refers to information used to classify and identify different functional modules in the circuit. It is worth noting that, in this application, the presence of target modules, such as differential modules and current mirror modules, in the circuit to be adjusted can be determined based on the module category data. These modules have specific size limitations on the components they contain.

[0088] During the identification process, once the target module is detected, the dimensional constraints of each component within that module can be directly determined. This effectively avoids repetitive identification of components within the module, reducing the workload and improving identification efficiency.

[0089] Optionally, the circuit data may also include the circuit diagram corresponding to the circuit to be adjusted. A circuit diagram is a graphical representation of the various components in a circuit and their connections. The circuit diagram details the type identification, name symbol, connection node layout, and key electrical parameters such as voltage, current, and resistance of each component, fully demonstrating the connection relationships and operating characteristics between the components in the circuit.

[0090] During the identification process, circuit diagrams can be used as supplementary data to netlist data. They can present the abstract connection relationships and component parameters in the netlist in an intuitive and visual way, making up for the shortcomings of netlist data in displaying circuit structure. This makes the circuit information more complete and comprehensive, providing a more sufficient basis for accurately extracting dimensional constraints, thereby improving the accuracy and efficiency of circuit size adjustment.

[0091] It should be understood that a circuit to be adjusted can be a circuit whose components and parameters require adjustment. That is, in circuit layout design, an initial circuit structure can be designed based on circuit performance specifications, and an initial simulation of the designed circuit can be performed based on these specifications. When the simulation results show that there are components and parameters in the currently designed circuit that require adjustment, the circuit is marked as a circuit to be adjusted.

[0092] In one optional implementation, the acquired circuit data can be presented in two forms: one is preprocessed circuit data, which is directly applicable to the extraction of size adjustment constraints, thereby improving the efficiency of determining size adjustment constraints; the other is raw graphic data, which is then processed by graphic analysis to generate circuit data that can be used to extract size adjustment constraints. By acquiring raw graphic data and performing data analysis and constraint extraction on its own, the accuracy of constraint extraction results can be improved.

[0093] The two data formats obtained each have their own advantages, focusing on efficiency and accuracy respectively, and can meet the needs of different application scenarios. Therefore, this application does not impose specific limitations on the data format of the obtained circuit data during implementation.

[0094] In this application, the above information collectively provides a comprehensive understanding of the circuit, supporting the identification and analysis of parts that need adjustment, thereby providing the necessary foundation for circuit optimization and sizing.

[0095] Optionally, if the circuit data obtained in this application is in the form of raw graphic data, then this application may provide a data processing method for obtaining processed circuit data. This data processing method may include, but is not limited to: obtaining the raw graphic data to be processed; performing graphic parsing on the raw graphic data to obtain graphic description information corresponding to the circuit to be adjusted; the graphic description information includes the circuit diagram and text description information corresponding to the circuit to be adjusted; and identifying components and component parameters in the circuit diagram to obtain netlist data corresponding to the circuit to be adjusted.

[0096] Optionally, the original graphic data can be resources such as literature, requirement documents, and forum posts that contain circuit diagrams and textual descriptions of the circuit to be adjusted.

[0097] For example, the process of obtaining circuit data can be illustrated below using the original graphic data as a reference:

[0098] When a document containing circuit diagrams and textual descriptions is available, an OCR tool (such as Mathpix) can be used to extract the textual and graphic descriptions from the document, resulting in information such as text, formulas, tables, and circuit diagrams.

[0099] The extracted circuit diagram can be identified and analyzed using computer vision (CV) algorithms (such as YOLO-V8) to obtain the components (transistors, resistors, etc.), component connections, and annotation text in the circuit diagram. The identification results are then converted to obtain the netlist of the circuit to be adjusted.

[0100] In this application, the converted netlist includes, but is not limited to, device type, connection nodes, and initial parameters.

[0101] When the circuit data also includes module category data, when obtaining the netlist data of the circuit to be adjusted based on the above implementation method, the module category of the netlist data can also be identified to obtain the module category data corresponding to the circuit to be adjusted.

[0102] Optionally, a preset module detection algorithm can be used to identify each module in the netlist to obtain module category data. This module category data can then be used to identify preset target modules, such as modules with clearly defined size constraints on their internal components (e.g., differential modules, current mirror modules, etc.). Based on these characteristics of the target modules, the identified target modules can be used as the basis for subsequent size constraint extraction. This avoids repeated identification of some components within the module during the identification process, reducing the workload and improving identification efficiency.

[0103] Of course, in addition to the data processing methods described above, the same or different data processing methods can be used for different forms of raw image and text data. The embodiments of this application do not limit the specific data processing methods.

[0104] S202. Based on the circuit data, determine the size adjustment constraints corresponding to the circuit to be adjusted; wherein, the size adjustment constraints are used as adjustment constraints when the circuit to be adjusted is sized.

[0105] In this application, after obtaining the preprocessed circuit data, it can be used as the data basis for extracting size adjustment constraints.

[0106] Optionally, predefined rule sets can be used to automatically identify and extract dimensional constraints contained in circuit data; supervised or unsupervised machine learning models can be trained to automatically identify dimensional features in circuit data and extract corresponding constraints; image processing algorithms can be used to analyze the image portion of circuit data to extract corresponding constraints, and natural language processing techniques can be used to extract key information describing dimensional constraints from text data. It should be understood that the above methods can be used individually or in combination to improve the accuracy and efficiency of dimensional constraint extraction. This application does not specifically limit the method of constraint extraction.

[0107] In the above technical solution, by acquiring circuit data containing netlist data and text description information, the potential constraints corresponding to the circuit to be adjusted are obtained, which overcomes the limitation of insufficient utilization of prior knowledge in traditional adjustment schemes. Furthermore, by extracting the size adjustment constraints, precise guidance is provided for subsequent circuit size adjustment, achieving efficient pruning of the design space, reducing redundant parameter searches, and improving the efficiency of circuit size adjustment.

[0108] Next, we will describe in detail the process of determining the dimensional adjustment constraints of the circuit to be adjusted based on the circuit data.

[0109] As an optional implementation, the process of determining the size adjustment constraints may include: obtaining a preset constraint extraction model, inputting circuit data into the preset constraint extraction model, and obtaining the size adjustment constraints corresponding to the circuit to be adjusted; wherein, the size adjustment constraints include the size constraint range of each component in the circuit to be adjusted and the size constraint relationship between each component.

[0110] When determining size adjustment constraints, a pre-defined constraint extraction model is first obtained. It should be understood that the constraint extraction model can be, but is not limited to, a general large language model, a machine learning model, etc.

[0111] Specifically, circuit data, including netlist data and text description information of the circuit to be adjusted, is input into the model. The model analyzes and processes the circuit data, identifying component layout, connection relationships, and component annotations in the netlist data, as well as design requirements, performance indicators, and process limitations in the text description information. From this, it extracts the dimensional constraints of each component in the circuit to be adjusted, such as the minimum and maximum channel lengths of a transistor. Simultaneously, it determines the dimensional constraints between components, such as the resistance ratio requirements between two resistors, ultimately outputting complete dimensional adjustment constraints to provide an accurate basis for subsequent circuit dimensional adjustments.

[0112] It is worth noting that in the field of circuit design, general-purpose large language models are typically used to directly perform circuit size adjustment tasks. However, because these general-purpose large language models have not been fine-tuned for analog circuit design, they face significant obstacles in analyzing complex circuit topologies or novel circuit structures. This makes it difficult for them to output efficient and accurate adjustment schemes when providing circuit size adjustment solutions, severely limiting the adjustment efficiency and effectiveness.

[0113] Nevertheless, large language models, with their powerful natural language processing capabilities and ability to accurately understand and generate complex textual information, can be applied to deeply extract dimensional adjustment constraints from circuit data. By first mining dimensional adjustment constraints from the text using large language models, and then performing circuit dimensional adjustment tasks based on these accurately extracted constraints, adjustment efficiency and optimization quality can be significantly improved, providing more reliable support for circuit layout design.

[0114] Building upon the above, in the process of extracting dimensional adjustment constraints using a general large language model, the number of models can be one or more. Multiple models can extract constraints through collaboration and verification. Specifically, multiple models collaborating to extract dimensional adjustment constraints provides a more comprehensive coverage of constraints compared to a single model. Furthermore, when multiple models experience conflicts in constraint extraction, constraint verification can encourage models to extract stronger evidence based on circuit data, thereby improving the reliability of constraint extraction.

[0115] For example, multiple models can be viewed as a multi-agent team to extract dimensional constraints. Each model plays a specific role in the team, responsible for different tasks or data processing steps. Through collaboration and coordination, these models can efficiently analyze input circuit data, identify the dimensional constraint ranges of each component in the circuit, and the dimensional constraint relationships between components.

[0116] When the constraint extraction model contains multiple sub-models, it can be designed as a multi-agent team, meaning it can include one expert model and multiple assistant models. The expert model is a deep reasoning language model, capable of supporting long text reasoning and accurately and deeply handling complex problems. The assistant models are lightweight language models, characterized by low cost and low resource consumption.

[0117] Therefore, when a multi-agent team completes the task of extracting size adjustment constraints, the expert model is responsible for extracting the constraints to ensure their comprehensiveness and accuracy; the assistant model works in collaboration with the expert model, specifically verifying the constraints proposed by the expert model. By identifying potential errors or inconsistencies, the assistant model provides support and supplementation to the expert model, ensuring the reliability and consistency of the extracted constraints.

[0118] This allocation of expert and assistant roles enables multi-agent teams to collaborate efficiently, fully leveraging the strengths of each model. Expert models specialize in complex, high-level tasks, while assistant models are responsible for verification and support, ensuring the accuracy and reliability of the entire extraction process.

[0119] Based on this, the process of determining size adjustment constraints through a multi-agent team can include: inputting circuit data into an expert model to obtain at least one constraint to be verified and the constraint extraction basis corresponding to the constraint to be verified; for any assistant model, inputting any constraint to be verified, the constraint extraction basis, and circuit data into the assistant model to obtain the constraint verification result of the constraint to be verified, and the constraint verification basis corresponding to the constraint verification result; for any constraint to be verified, if the constraint verification results output by each assistant model indicate that the constraint to be verified has passed verification, then the constraint to be verified is used as the output of the constraint extraction model.

[0120] Within a multi-agent team framework, determining size adjustment constraints is a flexible collaborative verification process with multiple verification paths and diverse processing scenarios for different constraint extraction and verification needs. For one particular constraint extraction and verification scenario, combined with... Figure 3 The process of extracting and validating constraints is explained in detail. Figure 3 This is a flowchart illustrating a constraint extraction and verification process provided in an embodiment of this application.

[0121] See Figure 3 The circuit data is input into the expert model. This circuit data specifically includes the textual description information and netlist data extracted through the preceding implementation methods. In some cases, it may also include module category data and circuit diagrams. Leveraging its ability to support long text reasoning and its image analysis and recognition capabilities, the expert model extracts and outputs at least one constraint to be verified from the circuit data, such as the size range of a component or the proportional relationship between components. It also provides the basis for extracting this constraint, such as annotations in the corresponding circuit or design requirement descriptions in the text.

[0122] It should be noted that the multi-agent team provided in this application also includes a data sharing pool, that is, the data output by each agent is output to the shared data pool. In this way, other agents can read the data they need from the shared data pool when performing their respective tasks, which promotes efficient collaboration and information sharing among agents.

[0123] Next, the assistant model can read the data needed to verify the constraints output by the expert model from the data sharing pool and perform the verification.

[0124] It should also be noted that in this application, for each constraint to be verified output by the expert model, each assistant model can verify all the constraints to be verified, or it can verify only the constraint it is interested in. This application does not limit the number of constraints verified by the assistant model or the order of the constraints.

[0125] For example, taking any constraint to be verified, the constraint and its corresponding extraction criteria are input into the verification assistant model. Further, the verification assistant model combines the constraint extraction criteria with the circuit data used by the expert to extract the constraint, analyzing and verifying it from multiple perspectives. For example, it checks whether the component connection relationships in the netlist data support the constraint, or whether there are other constraints in the text that conflict with the constraint. Finally, the assistant model outputs the constraint verification result (pass or fail), and simultaneously outputs the constraint verification criteria, explaining the specific reasons for the judgment.

[0126] For each constraint to be verified, if all verification results output by its verification assistant model indicate that the constraint has passed verification, it means that the rationality and accuracy of the constraint have been recognized from different dimensions. At this time, the constraint to be verified will be adopted as the final size adjustment constraint output, providing a reliable basis for subsequent circuit size adjustments.

[0127] It should also be noted that preset conditions for passing verification can be set during implementation. For example, the constraint is considered to have passed verification only when all the assistant models that are verifying the constraint outputs "pass verification". Alternatively, it can be set in advance that the constraint is considered to have passed verification when more than a preset number of assistant models output "pass verification". This application does not make specific limitations on the conditions for constrained verification to be considered to have passed verification.

[0128] In another scenario of constraint extraction and verification, it can be combined with Figure 4 The process is explained in detail. Figure 4 This is a flowchart illustrating another constraint extraction and verification process provided in an embodiment of this application.

[0129] See Figure 4 In cases where any constraint to be verified fails verification based on the aforementioned implementation method, the technical solution of this application provides a further multi-round deep verification mechanism. Thus, through multiple verifications, the problem of misjudgment or incorrect extraction of constraint conditions caused by factors such as data ambiguity and model misjudgment is effectively avoided, ensuring that the final output size adjustment constraints are accurate and reliable.

[0130] Optionally, based on the aforementioned implementation method, the process of determining size adjustment constraints through a multi-agent team may further include: if the constraint verification results output by each assistant model indicate that the constraint to be verified has failed verification, then supplementary verification is performed cyclically.

[0131] If, after any supplementary verification, all assistant models indicate that the constraint to be verified has passed the verification, the loop process is terminated immediately, and the constraint to be verified is determined as a size adjustment constraint and output. If, after a preset number of loop executions, the constraint to be verified still fails the supplementary verification of each assistant model, the verification process is stopped, and the constraint to be verified is no longer considered as a candidate for size adjustment constraint.

[0132] The supplementary verification process includes: inputting circuit data, constraints to be verified, constraint extraction basis, verification results of each constraint, and verification basis of each constraint into the expert model to obtain the supplementary verification constraints corresponding to the constraints to be verified, and the extraction basis of the supplementary verification constraints corresponding to the supplementary verification constraints; for any assistant model, inputting the constraints to be verified, constraint extraction basis, supplementary verification constraints, extraction basis of the supplementary verification constraints, and circuit data into the assistant model to obtain the supplementary verification results of the constraints to be verified, and the supplementary constraint verification basis corresponding to the supplementary verification results.

[0133] During the collaborative determination of size adjustment constraints by a multi-agent team, if a constraint fails verification, a cyclical supplementary verification mechanism is initiated. This mechanism sets a clear upper limit on the number of verifications, aiming to deeply optimize the constraints through a finite number of iterations.

[0134] For example, the supplementary verification process is illustrated using any round as an example: In the current round, when all assistant models for verifying any constraint to be verified determine that the constraint to be verified fails verification, the expert model can output the circuit data on which the constraint to be verified is based, the constraint to be verified, the constraint extraction basis, and the verification results and corresponding verification basis output by each assistant model, and feed them back to the expert model. Based on all the above information, the expert model re-evaluates and analyzes the previously extracted constraints to be verified, and generates verification supplementary constraints based on the analysis results, that is, the correction or supplement to the aforementioned constraints to be verified, and also provides the verification supplementary constraint extraction basis corresponding to the supplementary constraint.

[0135] Subsequently, each assistant model will conduct a new round of verification. Each assistant model will combine the circuit data, the constraint to be verified and its verification extraction basis, as well as the newly generated verification supplementary constraint and its corresponding verification supplementary constraint extraction basis, to verify the constraint to be verified again, and output the supplementary verification result (pass or fail), and simultaneously output the supplementary constraint verification basis for the conclusion.

[0136] If, in the current round of supplementary verification, the results of all helper models indicate that the constraint to be verified has passed verification, it means that after iterative optimization, the constraint has met the circuit design requirements. At this time, the constraint will be adopted as the final size adjustment constraint, serving as an important basis for subsequent circuit size optimization.

[0137] It should be understood that if the constraint to be verified still fails verification after all the preset number of supplementary verifications are completed, it will no longer be included in the scope of size adjustment constraints, thereby effectively avoiding interference from invalid parameters and improving overall design efficiency.

[0138] In another scenario of constraint extraction and verification, it can be combined with Figure 5 The process is explained in detail. Figure 5 This is a flowchart illustrating another constraint extraction and verification process provided in an embodiment of this application.

[0139] See Figure 5 In the process of supplementing the verification of any constraint to be verified based on the aforementioned implementation method, the technical solution provided by this application further includes: inputting circuit data, constraint to be verified, constraint extraction basis, verification results of each constraint, and verification basis of each constraint into the expert model, and when the expert model outputs empty data, inputting circuit data, constraint to be verified, constraint extraction basis, verification results of each constraint, and verification basis of each constraint into a preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified; when the final verification result indicates that the constraint to be verified has passed the verification, the constraint to be verified is used as the output of the constraint extraction model.

[0140] Based on the above implementation method, if the verification results output by each assistant model indicate that the current constraint to be verified has failed verification, in order to avoid factors such as misjudgment, a deep verification of the constraint to be verified can be performed. Specifically, the circuit data on which the constraint to be verified is based, the constraint to be verified, the basis for constraint extraction, and the verification results and corresponding verification basis output by each assistant model can be fed back to the expert model. Based on all the above information, the expert model re-evaluates and analyzes the previously extracted constraints to be verified.

[0141] In one possible scenario, after analysis, the expert model outputs "empty data," meaning it fails to generate any valid validation constraints or corresponding extraction criteria. This could be due to contradictory input information, missing key content, or the current constraints to be validated being difficult to improve through further supplementation and correction.

[0142] To achieve in-depth verification in the current situation, circuit data, constraints to be verified, basis for constraint extraction, and verification results of each constraint can be input into a preset constraint verification model.

[0143] In this application, the constraint verification model can employ a lightweight, large language model independent of the multi-agent team. Leveraging its advanced comprehensive analysis and decision-making capabilities, this model performs a deep evaluation of the constraints to be verified based on all input information. For example, it obtains the final verification result by mining potential design rules from circuit data and comparing multiple verification results with industry standards, thereby determining whether the constraints to be verified can pass verification.

[0144] In some scenarios, the constraint verification model can also adopt a lightweight large language model preset within the multi-agent team. This application does not impose specific restrictions on the selection of the constraint verification model.

[0145] Optionally, if the final verification result output by the constraint verification model indicates that the constraint to be verified has passed the verification, it means that although the expert model has not been able to provide effective supplementary corrections, the constraint to be verified is considered to be reasonable and accurate under the current information and conditions after comprehensive analysis by the constraint verification model. In this case, the constraint to be verified can be used as a size adjustment constraint and output for subsequent circuit size adjustment work.

[0146] Optionally, if the final verification result output by the constraint verification model indicates that the constraint to be verified has failed verification, then the constraint to be verified is completely excluded from the scope of size adjustment constraints, thus avoiding the application of invalid or incorrect constraints to the circuit design.

[0147] In another scenario of constraint extraction and verification, it can be combined with Figure 6 The process is explained in detail. Figure 6 This is a flowchart illustrating another constraint extraction and verification process provided in an embodiment of this application.

[0148] See Figure 6 Furthermore, if any constraint to be verified fails verification based on the aforementioned implementation methods, this application also provides a final verification mechanism. This effectively avoids misjudgments of constraints caused by data conflicts, model limitations, or other factors, significantly improving the accuracy and reliability of size adjustment constraints.

[0149] Optionally, based on the aforementioned implementation method, the process of determining size adjustment constraints through a multi-agent team may further include: if the supplementary verification results output by each assistant model indicate that the constraint to be verified has failed verification, then the constraint to be verified, the constraint extraction basis, the constraint verification result, the constraint verification basis, the verification supplementary constraint, the verification supplementary constraint extraction basis, the supplementary verification result, the supplementary constraint verification basis, and the circuit data are input into a preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified; if the final verification result indicates that the constraint to be verified has passed verification, then the constraint to be verified is used as the output of the constraint extraction model.

[0150] During the process of determining size adjustment constraints, if after one round of supplementary verification, the supplementary verification results output by all assistant models still indicate that a certain constraint to be verified has not passed verification, the verification process will enter the final verification stage.

[0151] Specifically, all key information generated during the entire verification process can be integrated, including the original constraints to be verified and their extraction basis, the results and basis of the first verification, the verification supplementary constraints generated by the expert model and their extraction basis, as well as the results and basis generated in the supplementary verification stage, and together with the original circuit data, input into the preset constraint verification model.

[0152] Optionally, if the final verification result shows that the constraint to be verified has passed the verification, it means that although it failed in the previous multiple rounds of verification, its rationality and accuracy have been finally confirmed after a more comprehensive review and verification. At this time, the constraint to be verified will be adopted as the final size adjustment constraint output, providing a reliable basis for subsequent circuit size adjustment work.

[0153] Optionally, if the final verification result is still unsuccessful, the constraint to be verified is completely excluded from the scope of size adjustment constraints to avoid applying invalid or incorrect constraints to the circuit design.

[0154] Based on the above embodiments, the technical solution provided by this application further includes: when the constraint to be verified is used as the output of the constraint extraction model, the circuit data is input to the expert model again to obtain at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified; when the supplementary constraint verification results corresponding to the supplementary constraint to be verified output by each assistant model indicate that the supplementary constraint to be verified has passed the verification, the supplementary constraint to be verified is used as the output of the constraint extraction model.

[0155] To avoid missing constraints, the circuit data initially used to generate the constraint to be verified can be input again into the expert model. Based on the constraints and circuit data already verified by the team, the expert model can further mine and analyze the data to obtain at least one supplementary constraint to be verified. This supplementary constraint further supplements or optimizes the confirmed constraints, making them more complete and accurate. Simultaneously, the expert model will also output the basis for extracting the supplementary constraint.

[0156] Based on this, each assistant model in the team verifies the extracted supplementary constraints to be verified according to the above implementation method. When the supplementary constraint to be verified passes the verification, the new constraint conditions can be output, thereby realizing the dynamic supplementation of the size adjustment constraint conditions and providing more accurate and complete constraint condition support for subsequent circuit design.

[0157] Based on the above embodiments, the technical solution provided by this application further includes: for any assistant model, when the assistant model outputs the constraint verification result of the constraint to be verified and the constraint verification basis corresponding to the constraint verification result, the assistant model also outputs at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified; when the supplementary constraint verification result corresponding to the supplementary constraint to be verified output by other assistant models indicates that the supplementary constraint to be verified has passed the verification, the supplementary constraint to be verified is used as the output of the constraint extraction model.

[0158] In the workflow of a multi-agent team determining size adjustment constraints, if the assistant model, based on its analysis of the constraints to be verified, discovers new constraints in the circuit data that were not extracted by the expert model and which play a role in perfecting or correcting the original constraints to be verified, these can be output as supplementary constraints to be verified. Simultaneously, the assistant model will also provide the corresponding basis for extracting these supplementary constraints.

[0159] It should be noted that the supplementary constraints proposed by the assistant model also need to be verified before they will be adopted. Specifically, they can be input into other assistant models in the multi-agent team. The other assistant models will carefully analyze and verify the supplementary constraints to be verified and their extraction basis, and output the supplementary verification result (pass or fail), and simultaneously output the verification basis for the conclusion of the supplementary constraints.

[0160] Optionally, if the verification results of the supplementary constraints output by the other assistant models being verified all indicate that the supplementary constraint to be verified has passed verification, then the supplementary constraint is subsequently deemed reasonable and usable. In this case, the supplementary constraint to be verified will be determined as the final size adjustment constraint and output.

[0161] In the above scheme, in addition to outputting the verification results of the constraints to be verified, the assistant model also provides supplementary constraints to be verified and their basis. In this way, the sources of constraints can be enriched and the comprehensiveness and accuracy of the size adjustment constraints can be improved.

[0162] Based on the above embodiments, this application further illustrates the above-described size adjustment constraint determination process with specific examples. The method includes:

[0163] First, the paper to be processed is obtained and parsed to obtain circuit data;

[0164] Step 1: Parse the PDF paper to obtain the text description information and circuit diagram of the circuit to be adjusted contained in the paper;

[0165] Step 2: Identify components in the circuit diagram and convert the netlist to obtain the netlist data corresponding to the adjustment circuit;

[0166] Step 3: Identify the target modules in the above netlist data to obtain the identified target modules, such as "differential pair M1-M2" and "current mirror M3-M4";

[0167] Next, the expert model and assistant model in the multi-agent team are used to extract and verify the constraints from the above circuit data, resulting in size adjustment constraints; the extraction and verification process includes:

[0168] Expert model: Extract “(W / L_{M3}=0.5μm / 0.1μm\) ,(W / L_{M4}=0.25μm / 0.1μm\) ” from the parameter table, and infer that “the aspect ratio of M3 is twice that of M4”.

[0169] Assistant Model A: Agrees that "the aspect ratio of M3 is twice that of M4"; Reason: This is consistent with the design concept in the paper.

[0170] Assistant Model B: Disagrees with "the width-to-length ratio of M3 is twice that of M4"; Reason: Although the paper describes the numerical relationship between M3 and M4, this ratio can only be used as an initial reference under different processes, and the actual ratio may vary.

[0171] Since the assistant model disagrees with the verification proposed by the expert model, the expert model can re-output the supplementary constraints to be verified: extract "(W / L)M3:(W / L)M4=2:1" from "IM3:IM4=2:1" and consider possible process mismatch, and then infer "the width-to-length ratio of M3 to M4 is 2:1, ±5%".

[0172] Assistant Model A: Agrees with "the width-to-length ratio of M3 to M4 is 2:1, ±5%"; Reason: M3 and M4 form a current mirror. From IOUT≈ID∝(W / L), it can be seen that in order to obtain double the bias current under the same driving voltage, W / L must be 2:1; the ±5% window is left for process variance and matching margin.

[0173] Assistant Model B: Agrees with "the width-to-length ratio of M3 to M4 is 2:1, ±5%"; Reason: When W / L is precisely maintained at 2:1, the current mirror error is <5%, and the gain and slew rate simultaneously meet the specifications; if it deviates from this ratio, the IOUT error will increase rapidly, so the constraint of 2:1 ±5% is agreed.

[0174] Therefore, the constraint condition "the width-to-length ratio of M3 to M4 is 2:1, ±5%" has been verified and can be used as the output constraint for size adjustment.

[0175] Assistant Model B: In verifying the dimensional relationship between M3 and M4, the design formula is used to deduce that "M1 and M2 need to be symmetrical". Since the expert model did not propose this relationship, it is proposed that "\(W / L_{M1}=W / L_{M2}\)".

[0176] Assistant Model A: Agrees that "M1 and M2 must be symmetrical"; Reason: M1 and M2 are differential pairs, and gm and VOS are directly related to the (W / L) matching degree; The size is completely equal and a common center layout can maximize CMRR and minimize offset voltage, so agree that the two must be symmetrical.

[0177] Assistant Model C: Agrees that "M1 and M2 must be symmetrical"; Reason: As can be seen from gm=√(2μCox ID W / L), unequal W / L will lead to gm mismatch, introducing differential gain drift and zero offset; Keeping W / L_M1=W / L_M2 can ensure the stability of the transmission zero position and loop gain, so the symmetry requirement is agreed.

[0178] Therefore, "M1 = M2" is a verified constraint and can be used as a size adjustment constraint output.

[0179] Expert model: The current mirror section was not mentioned, so the following has been added: "The bias current ratio of M5 to M6 is 1:1.5".

[0180] Employee Model C: Questions whether the “M5-M6 ratio” is implicit in the power consumption analysis of the paper, and cites Section 5 to revise it to “1:1.5±10%”.

[0181] To facilitate search space pruning in subsequent optimization algorithms, the size adjustment constraints input by the multi-intelligence team can be preprocessed; this includes, but is not limited to, redundancy filtering and format conversion.

[0182] For example, merge equivalent relationships (such as merging "M1=M2" and "M2=M3" into "M1=M2=M3").

[0183] For example: Format conversion: Store by triples (device name, related parameters, quantitative relationship).

[0184] For example, based on the above processing, the output dimensional constraints may include:

[0185] (M3, W / L, 2×M4, W / L ± 5%)

[0186] (M1, W / L, = M2, W / L)

[0187] (M5,I_bias,1.5×M6.I_bias±10%).

[0188] Based on the above embodiments, this application also provides a method for adjusting circuit dimensions. Figure 7This is a flowchart illustrating a method for determining size adjustment constraints according to an embodiment of this application. The method can be executed by a size adjustment constraint determining device, which can be a server or an electronic device. The following description uses an electronic device as an example. The method in this embodiment can be implemented through software, hardware, or a combination of both. Figure 7 As shown, the method includes the following steps:

[0189] S701. Obtain the original search space corresponding to the circuit to be adjusted.

[0190] In this application, the circuit to be adjusted can be understood as a circuit whose components and their parameters need to be adjusted. The original search space can be understood as the set of all possible values ​​of the circuit's dimensional parameters. It defines the range of values ​​for the circuit's dimensional parameters and is the basis for subsequent dimensional adjustment operations.

[0191] For example, the dimensional parameters of a simple resistive circuit might include the resistance value, the capacitance value, and the inductance value. The original search space then contains the possible range of values ​​for these parameters; for example, the resistance value might be between 10 ohms and 100 ohms, and the capacitance value might be between 1 picofarad and 100 picofarads.

[0192] By obtaining the original search space corresponding to the circuit to be adjusted, it becomes clear within which range the circuit size can be adjusted, thereby enabling the circuit performance to reach the expected target.

[0193] S702. Update the original search space according to the size adjustment constraints, and adjust the size of the circuit to be adjusted according to the updated search space.

[0194] In this application, the size adjustment constraint can be understood as the constraint determination method described in the above embodiments. This constraint can provide precise guidance for subsequent circuit size adjustments, achieve efficient pruning of the design space, reduce redundant parameter searches, and improve the efficiency of circuit size adjustments.

[0195] Based on this, the original search space can be updated according to the size adjustment constraints. Specifically, some values ​​in the original search space may not meet the requirements of the size adjustment constraints, and these values ​​will be excluded from the search space. For example, if the size adjustment constraint stipulates that the resistance value must be between 10 ohms and 50 ohms, while the resistance value range in the original search space is 1 ohm to 100 ohms, then the resistance value range in the updated search space will become 10 ohms to 50 ohms.

[0196] After obtaining the updated search space, the dimensions of the circuit to be adjusted can be made based on this new search space. Appropriate dimensional parameter values ​​are selected within the updated search space to adjust the circuit so that its performance meets design requirements, such as ensuring that the circuit's power, frequency, and stability meet expectations.

[0197] In the above scheme, before making size adjustments, the received size adjustment constraints are used as precise guides for subsequent circuit size adjustments, achieving efficient pruning of the design space. This reduces blind parameter searches during the circuit size adjustment process and significantly improves the efficiency of circuit size adjustments.

[0198] Figure 8 This is a schematic diagram of a size adjustment constraint determination device provided in an embodiment of this application. See also... Figure 8 The size adjustment constraint determination device 80 includes: a circuit data acquisition module 801 and a size adjustment constraint determination module 802; wherein,

[0199] The circuit data acquisition module 801 is used to acquire circuit data to be processed; wherein, the circuit data includes netlist data and text description information corresponding to the circuit to be adjusted;

[0200] The first size adjustment constraint determination module 802 is used to determine the size adjustment constraint corresponding to the circuit to be adjusted based on the circuit data; wherein, the size adjustment constraint is used as the adjustment constraint when the circuit to be adjusted is subjected to size adjustment.

[0201] In one alternative embodiment, the first size adjustment constraint determination module 802 includes:

[0202] The size adjustment constraint determination submodule is used to input circuit data into a preset constraint extraction model to obtain the size adjustment constraints corresponding to the circuit to be adjusted; wherein, the size adjustment constraints include the size constraint range of each component in the circuit to be adjusted, as well as the size constraint relationship between each component.

[0203] In one alternative implementation, the constraint extraction model consists of multiple sub-models, forming a multi-agent team; the multi-agent team includes an expert model and multiple assistant models.

[0204] The size adjustment constraint determination submodule includes:

[0205] The constraint extraction unit is used to input circuit data into the expert model to obtain at least one constraint to be verified, and the constraint extraction basis corresponding to the constraint to be verified.

[0206] The constraint verification unit is used to input any constraint to be verified, the constraint extraction basis, and circuit data into any assistant model to obtain the constraint verification result of the constraint to be verified, and the constraint verification basis corresponding to the constraint verification result.

[0207] The size adjustment constraint determination unit is used to determine the constraint to be verified as the output of the constraint extraction model if the constraint verification results output by each assistant model indicate that the constraint to be verified has passed the verification.

[0208] In one alternative embodiment, the device further includes:

[0209] The first supplementary verification module is used to perform supplementary verification in a loop if the constraint verification results output by each assistant model indicate that the constraint to be verified has failed the verification.

[0210] If, after any supplementary verification, all assistant models indicate that the constraint to be verified has passed the verification, the loop process is terminated immediately, and the constraint to be verified is determined as a size adjustment constraint and output.

[0211] If the constraint to be verified still fails to pass the supplementary verification of each assistant model after the preset number of iterations, the verification process will stop, and the constraint to be verified will no longer be considered as a candidate for size adjustment constraint.

[0212] The supplementary verification process includes:

[0213] Input the circuit data, the constraints to be verified, the basis for constraint extraction, the verification results of each constraint, and the basis for verification of each constraint into the expert model to obtain the verification supplementary constraints corresponding to the constraints to be verified, and the basis for extraction of the verification supplementary constraints corresponding to the verification supplementary constraints.

[0214] For any assistant model, input the constraint to be verified, the basis for constraint extraction, the supplementary constraint for verification, the basis for extracting the supplementary constraint for verification, and the circuit data into the assistant model to obtain the supplementary verification result of the constraint to be verified, and the supplementary constraint verification basis corresponding to the supplementary verification result.

[0215] In one alternative embodiment, the device further includes:

[0216] The second supplementary verification module is used to input circuit data, constraints to be verified, constraint extraction basis, verification results of each constraint, and verification basis of each constraint into the expert model. When the expert model outputs empty data, the module inputs circuit data, constraints to be verified, constraint extraction basis, verification results of each constraint, and verification basis of each constraint into the preset constraint verification model to obtain the corresponding final verification results of the constraints to be verified.

[0217] The second size adjustment constraint determination module is used to output the constraint to be verified as the constraint extraction model when the final verification result indicates that the constraint to be verified has passed the verification.

[0218] In one alternative embodiment, the device further includes:

[0219] The third supplementary verification module is used to input the constraint to be verified, the constraint extraction basis, the constraint verification result, the constraint verification basis, the verification supplementary constraint, the verification supplementary constraint extraction basis, the supplementary verification result, the supplementary constraint verification basis, and the circuit data into the preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified.

[0220] The third size adjustment constraint determination module is used to output the constraint to be verified as the constraint extraction model when the final verification result indicates that the constraint to be verified has passed the verification.

[0221] In one alternative embodiment, the device further includes:

[0222] The fourth supplementary verification module is used to input the circuit data back into the expert model when the constraint to be verified is the output of the constraint extraction model, so as to obtain at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified.

[0223] The fourth size adjustment constraint determination module is used to take the supplementary constraint to be verified as the output of the constraint extraction model when the verification result of the supplementary constraint to be verified corresponding to the output of each assistant model indicates that the supplementary constraint to be verified has passed the verification.

[0224] In one alternative embodiment, the device further includes:

[0225] The fifth supplementary verification module is used to, for any helper model, output at least one supplementary constraint to be verified and the corresponding supplementary constraint extraction basis, when the helper model outputs the constraint verification result of the constraint to be verified and the constraint verification basis for the constraint verification result.

[0226] The fifth size adjustment constraint determination module is used to take the supplementary constraint to be verified as the output of the constraint extraction model when the supplementary constraint to be verified is verified as the output of the supplementary constraint corresponding to the supplementary constraint to be verified output by other assistant models.

[0227] In one alternative implementation, the expert model is a deep reasoning large language model, the assistant model is a lightweight large language model, and the constraint verification model is a lightweight large language model.

[0228] In one alternative implementation, the circuit data includes text description information corresponding to the circuit to be adjusted and netlist data of the circuit to be adjusted;

[0229] Circuit data acquisition module 801 includes:

[0230] The raw circuit data acquisition submodule is used to acquire the raw graphic data to be processed;

[0231] The image and text parsing module is used to parse the original image and text data to obtain the image and text description information corresponding to the circuit to be adjusted; the image and text description information includes the circuit diagram and text description information corresponding to the circuit to be adjusted.

[0232] The netlist data acquisition submodule is used to identify components and component parameters in the circuit diagram and obtain the netlist data corresponding to the circuit to be adjusted.

[0233] Figure 9 This is a schematic diagram of a circuit size adjustment device provided in an embodiment of this application. See also... Figure 9 The circuit size adjustment device 90 includes: an initial search space acquisition module 901 and a size adjustment module 902; wherein,

[0234] The original search space acquisition module 901 is used to acquire the original search space corresponding to the circuit to be adjusted.

[0235] The size adjustment module 902 is used to update the original search space according to the size adjustment constraints, and to adjust the size of the circuit to be adjusted according to the updated search space; wherein, the size adjustment constraints are determined according to the size adjustment constraint determination method in the above embodiments.

[0236] Figure 10 This is a block diagram illustrating an electronic device provided in an embodiment of this application. The device may be a computer, a digital broadcasting terminal, etc. See also... Figure 10 The device 1000 may include one or more of the following components: processing component 1002, memory 1004, power supply component 1006, multimedia component 1008, audio component 1010, input / output interface 1012, sensor component 1014, and communication component 1016.

[0237] Processing component 1002 typically controls the overall operation of device 1000, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 1002 may include one or more processors 1020 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1002 may include one or more modules to facilitate interaction between processing component 1002 and other components. For example, processing component 1002 may include a multimedia module to facilitate interaction between multimedia component 1008 and processing component 1002.

[0238] Memory 1004 is configured to store various types of data to support the operation of device 1000. Examples of this data include instructions for any application or method operating on device 1000, contact data, phonebook data, messages, pictures, videos, etc. Memory 1004 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0239] Power supply component 1006 provides power to various components of device 1000. Power supply component 1006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 1000.

[0240] Multimedia component 1008 includes a screen that provides an output interface between device 1000 and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1008 includes a front-facing camera and / or a rear-facing camera. When device 1000 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0241] Audio component 1010 is configured to output and / or input audio signals. For example, audio component 1010 includes a microphone (MIC) configured to receive external audio signals when device 1000 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1004 or transmitted via communication component 1016. In some embodiments, audio component 1010 also includes a speaker for outputting audio signals.

[0242] Input / output interface 1012 provides an interface between processing component 1002 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0243] Sensor assembly 1014 includes one or more sensors for providing state assessments of various aspects of device 1000. For example, sensor assembly 1014 may detect the on / off state of device 1000, the relative positioning of components such as the display and keypad of device 1000, changes in the position of device 1000 or a component of device 1000, the presence or absence of user contact with device 1000, the orientation or acceleration / deceleration of device 1000, and temperature changes of device 1000. Sensor assembly 1014 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1014 may also include an optical sensor, such as a Complementary Metal Oxide Semiconductor (CMOS) sensor or a Charge-coupled Device (CCD) sensor, for use in imaging applications. In some embodiments, sensor assembly 1014 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0244] Communication component 1016 is configured to facilitate wired or wireless communication between device 1000 and other devices. Device 1000 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 1016 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1016 also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra Wide Band (UWB), Bluetooth (BT), and other technologies.

[0245] In an exemplary embodiment, device 1000 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processors (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0246] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1004 including instructions, which can be executed by a processor 1020 of device 1000 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0247] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by the processor of a server, enables the server to perform the physical backup method of the aforementioned database.

[0248] This application also provides a chip for executing instructions, which is used to execute the technical solutions in the above embodiments.

[0249] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed on a computer, cause the computer to perform the technical solutions described above.

[0250] This application also provides a computer program product, which includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium, and when the at least one processor executes the computer program, it can implement the technical solutions in the above embodiments.

[0251] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0252] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0253] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0254] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for determining size adjustment constraints, characterized in that, The method includes: Acquire the circuit data to be processed; wherein, the circuit data includes the netlist data and text description information corresponding to the circuit to be adjusted; Based on the circuit data, the size adjustment constraint corresponding to the circuit to be adjusted is determined; wherein, the size adjustment constraint is used as the adjustment constraint when the circuit to be adjusted is sized.

2. The method according to claim 1, characterized in that, Based on the circuit data, determine the size adjustment constraints corresponding to the circuit to be adjusted, including: The circuit data is input into a preset constraint extraction model to obtain the size adjustment constraints corresponding to the circuit to be adjusted; wherein, the size adjustment constraints include the size constraint range of each component in the circuit to be adjusted, and the size constraint relationship between each component.

3. The method according to claim 2, characterized in that, The constraint extraction model consists of multiple sub-models, forming a multi-agent team; the multi-agent team includes an expert model and multiple assistant models. The circuit data is input into a preset constraint extraction model to obtain the size adjustment constraints corresponding to the circuit to be adjusted, including: The circuit data is input into the expert model to obtain at least one constraint to be verified, and the constraint extraction basis corresponding to the constraint to be verified. For any assistant model, input any constraint to be verified, the constraint extraction basis, and the circuit data into the assistant model to obtain the constraint verification result of the constraint to be verified, and the constraint verification basis corresponding to the constraint verification result; For any constraint to be verified, if the constraint verification result output by each of the assistant models indicates that the constraint to be verified has passed verification, then the constraint to be verified is used as the output of the constraint extraction model.

4. The method according to claim 3, characterized in that, The method further includes: If the constraint verification result output by each of the assistant models indicates that the constraint to be verified has failed verification, then supplementary verification is performed in a loop. If, after any supplementary verification, each of the assistant models indicates that the constraint to be verified has passed the verification, the loop process is immediately terminated, and the constraint to be verified is determined as a size adjustment constraint and output. If the constraint to be verified still fails to pass the supplementary verification of each of the assistant models after the preset number of iterations, the verification process will stop, and the constraint to be verified will no longer be considered as a candidate for size adjustment constraint. The supplementary verification process includes: The circuit data, the constraint to be verified, the constraint extraction basis, the verification results of each constraint, and the constraint verification basis are input into the expert model to obtain the verification supplementary constraint corresponding to the constraint to be verified, and the verification supplementary constraint extraction basis corresponding to the verification supplementary constraint. For any assistant model, the constraint to be verified, the constraint extraction basis, the verification supplementary constraint, the verification supplementary constraint extraction basis, and the circuit data are input into the assistant model to obtain the supplementary verification result of the constraint to be verified, and the supplementary constraint verification basis corresponding to the supplementary verification result.

5. The method according to claim 4, characterized in that, The method further includes: When the circuit data, the constraint to be verified, the constraint extraction basis, the constraint verification results, and the constraint verification basis are input into the expert model, and the expert model outputs empty data, the circuit data, the constraint to be verified, the constraint extraction basis, the constraint verification results, and the constraint verification basis are input into a preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified. If the final verification result indicates that the constraint to be verified has passed verification, the constraint to be verified is used as the output of the constraint extraction model.

6. The method according to claim 4, characterized in that, The method further includes: If the supplementary verification results output by each of the assistant models indicate that the constraint to be verified has failed verification, then the constraint to be verified, the constraint extraction basis, the constraint verification result, the constraint verification basis, the verification supplementary constraint, the verification supplementary constraint extraction basis, the supplementary verification result, the supplementary constraint verification basis, and the circuit data are input into the preset constraint verification model to obtain the corresponding final verification result of the constraint to be verified. If the final verification result indicates that the constraint to be verified has passed verification, the constraint to be verified is used as the output of the constraint extraction model.

7. The method according to claim 3, characterized in that, The method further includes: When the constraint to be verified is used as the output of the constraint extraction model, the circuit data is input into the expert model again to obtain at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified. If the verification result of the supplementary constraint to be verified output by each of the assistant models indicates that the supplementary constraint to be verified has passed the verification, then the supplementary constraint to be verified is used as the output of the constraint extraction model.

8. The method according to claim 3, characterized in that, The method further includes: For any assistant model, when the assistant model outputs the constraint verification result of the constraint to be verified and the constraint verification basis corresponding to the constraint verification result, the assistant model also outputs at least one supplementary constraint to be verified and the supplementary constraint extraction basis corresponding to the supplementary constraint to be verified. If the verification result of the supplementary constraint to be verified corresponding to the supplementary constraint output by other assistant models indicates that the supplementary constraint to be verified has passed the verification, the supplementary constraint to be verified will be used as the output of the constraint extraction model.

9. The method according to any one of claims 3-8, characterized in that, The expert model is a deep reasoning large language model, the assistant model is a lightweight large language model, and the constraint verification model is a lightweight large language model.

10. The method according to any one of claims 1-8, characterized in that, The circuit data includes the text description information corresponding to the circuit to be adjusted and the netlist data of the circuit to be adjusted; Acquire the circuit data to be processed, including: Obtain the raw image and text data to be processed; The original graphic data is parsed to obtain graphic description information corresponding to the circuit to be adjusted; the graphic description information includes the circuit diagram and text description information corresponding to the circuit to be adjusted. The circuit diagram is analyzed to identify components and their parameters, thereby obtaining the netlist data corresponding to the circuit to be adjusted.

11. A method for adjusting circuit dimensions, characterized in that, The method includes: Obtain the original search space corresponding to the circuit to be adjusted; The original search space is updated according to the size adjustment constraint, and the size of the circuit to be adjusted is adjusted according to the updated search space; wherein the size adjustment constraint is determined by the size adjustment constraint determination method according to any one of claims 1-10.

12. A size adjustment constraint determining device, characterized in that, The device includes: A circuit data acquisition module is used to acquire circuit data to be processed; wherein, the circuit data includes netlist data and text description information corresponding to the circuit to be adjusted; The size adjustment constraint determination module is used to determine the size adjustment constraint corresponding to the circuit to be adjusted based on the circuit data; wherein, the size adjustment constraint is used as the adjustment constraint when the circuit to be adjusted is subjected to size adjustment.

13. A circuit size adjustment device, characterized in that, The device includes: The original search space acquisition module is used to acquire the original search space corresponding to the circuit to be adjusted; A size adjustment module is used to update the original search space according to size adjustment constraints, and to adjust the size of the circuit to be adjusted according to the updated search space; wherein the size adjustment constraints are determined by the size adjustment constraint determination method according to any one of claims 1-10.

14. An electronic device, characterized in that, include: A processor and a memory communicatively connected to the processor; The memory stores computer-executed instructions; When executing the computer execution instructions, the processor is used to implement the size adjustment constraint determination method as described in any one of claims 1-10, and / or the circuit size adjustment method as described in claim 11.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the size adjustment constraint determination method as described in any one of claims 1-10, and / or the circuit size adjustment method as described in claim 11.

16. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the size adjustment constraint determination method as described in any one of claims 1-10, and / or the circuit size adjustment method as described in claim 11.

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