A MOS transistor layout variant with high-frequency performance and flexible wiring

Abstract

The application relates to the field of integrated circuit layout design and discloses a MOS transistor layout variant considering high-frequency performance and wiring flexibility, which solves the problems of limited wiring density of analog circuit layout and poor high-frequency circuit performance caused by insufficient unit size flexibility and missing sensitive area protection of the existing MOS transistor layout. A variable height structure or a wiring blocking structure is additionally arranged in a standard unit, the standard unit is divided into a standard NMOS unit and a standard PMOS unit, each unit has a layout wiring boundary, a virtual polysilicon, a power rail and a ground rail; the layout wiring boundary of the variable height structure has a variable integer multiple of the standard wiring track spacing in the longitudinal length, and the longitudinal size range of the active area is determined by the track number; the wiring blocking structure is provided with a wiring blocking layer at the overlapping position of the active area and the gate polysilicon, the source-drain port is a rectangle and extends to the transition area outside the blocking layer in the horizontal direction, and the side edge is located between the side edge of the blocking layer and the side edge of the layout wiring boundary.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout design, and provides a MOS transistor layout variant that balances high-frequency performance and wiring flexibility. Background Technology

[0002] To overcome the shortcomings of parameterized cells, such as low automation and poor area utilization due to irregular shapes and non-fixed ports, a standard cell-modular MOS transistor layout structure has been previously proposed (see patent document CN119808692A, hereinafter referred to as "basic modular structure"). This technology, by introducing regular layout and routing boundaries, standard cell structure, and modular design, initially realizes the automated layout and splicing of analog circuit layouts, enabling MOS transistor layouts to be recognized by EDA tools and participate in the automatic layout and routing process.

[0003] The core scheme of the basic modular structure: The main layout is divided into NMOS modules, PMOS modules, and other device modules; each standard cell includes virtual polysilicon, placement and routing boundaries, power rails (VDD), and ground rails (VSS); the standard cells are modularly arranged according to predetermined rules to form a splicable layout structure. The placement and routing boundaries are used to define the geometric range of the standard cells, ensuring that the standard cells maintain regularity in shape and size, and supporting the splicing of multiple standard cells in the horizontal and vertical directions.

[0004] However, as analog circuit design expands into specialized fields such as high frequency and high integration, the basic modular structure has revealed the following core technical bottlenecks in practical applications, necessitating optimization through variant structures:

[0005] 1. The contradiction between fixed height limitations and wiring resource allocation and layout area utilization: High-performance analog cells require a wide range of transistor size adjustments, while the fixed number of traces in standard cells of basic modular structures not only limits the upper limit of device size but also easily leads to wiring congestion under complex logic connections. Although existing technologies have proposed standard cells of various heights, there is a lack of a design methodology that links the power / ground track spacing, active area size, and track number for coordinated scaling. This makes it difficult to achieve fine-grained coordinated optimization of device size and wiring resources while ensuring the regularity of standard cells. Especially when the design system contains both small-sized digital logic cells and large-sized analog driver cells, the mixed arrangement of cells of different heights places higher demands on the overall layout utilization.

[0006] 2. The Need for High-Frequency Parasitic Coupling and Sensitive Area Protection: In high-frequency analog circuits, critical components are highly sensitive to parasitic effects. If metal traces directly cross the active region or above the gate, the introduced parasitic capacitance and signal crosstalk will severely degrade the frequency response. Basic modular structures struggle to actively avoid such sensitive areas. Although existing technologies employ wiring barrier layers, ensuring electrical connection between source and drain ports while maintaining compatibility with EDA tool wiring rules presents a new technical challenge. Existing solutions typically involve increasing cell width or using high-layer metal bridging; the former increases area overhead, while the latter consumes high-layer wiring resources. Currently, there is a lack of integrated structural designs that, without disrupting the standard cell framework and while maintaining compatibility with EDA tool wiring rules, simultaneously achieve sensitive area protection and port electrical connectivity through port extension. Summary of the Invention

[0007] The purpose of this invention is to solve the technical problems of limited wiring density and degraded high-frequency circuit performance caused by insufficient flexibility in cell size and lack of protection for sensitive areas in existing MOS transistor layouts.

[0008] To achieve the above objectives, the present invention employs the following technical means:

[0009] This invention provides a MOSFET layout variant that balances high-frequency performance and wiring flexibility, based on a standard cell-modular structure, characterized in that...

[0010] The standard cells are divided into standard NMOS cells and standard PMOS cells. Each cell includes a layout and wiring boundary, a virtual polysilicon, a power rail, and a ground rail, and are combined into NMOS modules and PMOS modules, respectively. In this invention, the above-mentioned standard cells without added variant structures are defined as basic standard cells.

[0011] The standard unit also includes at least one of the following variant structures:

[0012] Variable height structure: The longitudinal length of the layout wiring boundary is a variable integer multiple of the standard trace track spacing under the process node. The longitudinal dimension range of the active area is determined by the number of tracks. The longitudinal spacing between the power track and the ground track adaptively expands and contracts with the number of tracks to provide an optimized device size range and a wider internal wiring channel. The longitudinal length of each part in the cell (including the active area, gate polysilicon, N-type implanted area (or P-type implanted area and N-well), and metal layer 1) adaptively expands and contracts with the number of tracks. The number of contact holes and vias increases or decreases with the size change.

[0013] Wiring blocking structure: A wiring blocking layer is provided at the intersection of the active region and the gate polysilicon to indicate to the EDA tool that a specific metal layer in this region should not be routed.

[0014] The source and drain ports corresponding to the wiring barrier structure are rectangular and extend laterally outward to the transition area outside the coverage of the wiring barrier layer.

[0015] Under the layout projection relationship, the sides of the source port and the drain port are located between the side of the wiring barrier layer and the side of the layout wiring boundary, and the spacing conforms to the design rules and does not affect the electrical interconnection.

[0016] In the above scheme, in the variable height structure, the longitudinal length of the layout wiring boundary is a variable integer multiple of the standard trace track spacing (standard trace tracks are a basic concept in the back end of digital circuits and are the same in the same process. The existing technology generally uses a track spacing of 0.1um, and the track itself can be regarded as a line); when configured as an M-track unit or an N-track unit, M and N are different positive integers, and the longitudinal length of the active area adaptively expands and contracts according to the change in the number of tracks, which can adapt to the different size requirements of the device.

[0017] In the above scheme, if the power rail VDD, ground rail VSS, layout routing boundary, routing barrier layer, source port, and drain port are projected onto the same plane:

[0018] The wiring barrier layer is entirely located within the layout wiring boundary;

[0019] The left sides of the source port and the drain port are flush and located in the middle area between the left side of the wiring barrier layer and the left side of the layout wiring boundary.

[0020] The right sides of the source port and the drain port are flush and located in the middle area between the right side of the wiring barrier layer and the right side of the layout wiring boundary.

[0021] In the above scheme, when the standard unit includes the wiring blocking structure, under the layout projection relationship,

[0022] The left side of the power rail VDD, the left side of the ground rail VSS, and the left side of the layout wiring boundary are on the same straight line.

[0023] The right side of the power rail VDD, the right side of the ground rail VSS, and the right side of the layout wiring boundary are on the same straight line.

[0024] The lateral extension length of the source and drain ports toward the transition region allows external wiring to complete electrical connection without crossing the wiring barrier layer.

[0025] In the above scheme, the variants are divided into NMOS variants and PMOS variants;

[0026] The NMOS variant includes only NMOS devices, and the PMOS variant includes only PMOS devices;

[0027] The variant includes two virtual polysilicon cells, which are respectively disposed on both sides of the effective device region to isolate adjacent variant cells. The virtual polysilicon cells do not participate in electrical connection. The effective device region is a channel region formed by the overlap of the active region and the gate polysilicon.

[0028] In the above scheme, the NMOS variant includes an N-type injection region, and the active region is located within the N-type injection region;

[0029] The PMOS variant includes an N-well and a P-type injection region, wherein the P-type injection region is located within the N-well and the active region is located within the P-type injection region;

[0030] Under the layout projection relationship, the active region of the NMOS variant is located within the corresponding injection region, and the active region of the PMOS variant is located within the corresponding injection region and N-well.

[0031] In the above scheme, the device size parameters of the variant include at least the channel length, channel width, and number of interpolation gates;

[0032] The gate port is implemented using a metal layer 1 and is connected to the gate polysilicon via a contact hole;

[0033] The source and drain ports are implemented using two metal layers and connected to the active region through contact holes;

[0034] The plurality of gate polysilicon cells are arranged laterally, and their spacing conforms to the design rules of the process node.

[0035] In the above scheme, the layout and routing boundary is a closed boundary structure set around the standard cell, which is used to limit the area occupied by the standard cell in the layout.

[0036] The power rails and ground rails are located in the edge region of the standard cell and are consistent with the power rails and ground rails of the digital standard cell under the process node.

[0037] Both the variable height structure and the wiring blocking structure follow the grid alignment logic of the layout wiring boundary, enabling the variant to be recognized by EDA tools and automatically spliced ​​with standard cells of the same type.

[0038] This invention also provides a method for using a MOSFET layout variant that balances high-frequency performance and wiring flexibility, comprising the following steps:

[0039] Step S1: Based on the performance requirements of each MOSFET in the circuit design, select the corresponding variable height structure or wiring barrier structure, set the layout parameters, and generate the GDS file and LEF file describing the variant;

[0040] Step S2: Divide the circuit diagram into NMOS modules and PMOS modules, describe them using a hardware description language and generate corresponding netlist files;

[0041] Step S3: Input the GDS file, LEF file and netlist file into the EDA tool and run automatic placement and routing;

[0042] The EDA tool automatically calls variants containing the performance adaptation structure for array placement and splicing based on the grid alignment logic of the layout and routing boundaries to obtain a complete circuit layout.

[0043] In the above scheme, in step S3:

[0044] The EDA tool first performs automatic placement and routing on the NMOS module to generate the NMOS module layout, then performs automatic placement and routing on the PMOS module to generate the PMOS module layout, and finally performs cross-module automatic routing based on the connection relationship between the modules.

[0045] During the automatic placement and routing process, for variants that include the aforementioned routing barrier structure, the EDA tool prohibits routing in the area covered by the routing barrier layer according to the LEF file, and uses source and drain ports extending to the transition region for signal interconnection.

[0046] For variants containing the variable height structure, the EDA tool strictly follows the alignment logic of an integer multiple of the standard trace track spacing based on the layout routing boundary, thereby achieving automated splicing of units with different height variants within the same type of module.

[0047] Because the present invention employs the above-mentioned technical means, it has the following beneficial effects:

[0048] 1. This invention employs a variable height structure, specifically configuring the longitudinal length of the layout wiring boundary as a variable integer multiple of the standard trace track spacing under the process node. Furthermore, it adaptively expands and contracts the longitudinal spacing between the power and ground tracks, as well as the longitudinal length of the active area, with the number of tracks. This solves the technical problems of existing automatically generated MOS transistor layouts, which are limited by fixed-height cells, resulting in restricted device size and prone to wiring congestion under complex connections. It achieves the coordinated optimization of the effective channel width and internal wiring resources while ensuring standard cell grid alignment rules, thereby significantly improving layout area utilization and eliminating local wiring bottlenecks.

[0049] In existing technologies, changing transistor size or cell height is usually an independent design behavior without a linkage mechanism. However, this invention uses an "adaptive scaling" rule to treat the number of rails as a single variable, synchronously driving the proportional change of power supply rail spacing and device area size. This ensures that increasing the cell height is not only to accommodate larger devices, but also automatically transforms it into a usable horizontal wiring channel. This avoids the scarcity of wiring resources caused by simply increasing the size of the device, or the waste of device performance caused by simply increasing the number of wiring channels. It realizes the automated generation basis for fine-tuning of PPA (performance, power consumption, area).

[0050] 2. This invention employs a wiring blocking structure combined with a specific port shape. Specifically, a wiring blocking layer is set at the intersection of the active region and the gate polysilicon to prevent specific metal layer traces from running. At the same time, the source and drain ports are set as rectangles and extend laterally outward to the transition area outside the coverage of the wiring blocking layer. The side of the port is located between the side of the wiring blocking layer and the side of the layout wiring boundary. This solves the technical problems of severe parasitic coupling and large signal crosstalk caused by metal traces crossing the sensitive area of ​​the device in high-frequency applications, and the difficulties in connection or significant increase in area caused by conventional blocking schemes. It achieves compatibility between the device and EDA tools without destroying the standard cell frame size or introducing additional high-layer metal bridging costs.

[0051] If only a barrier layer is set without changing the port shape, those skilled in the art usually face two choices: "widening the unit connection area" or "high-layer metal crossing the barrier." The former sacrifices area, while the latter occupies high-layer wiring resources. This invention cleverly creates a safe connection space within the existing unit boundary by reconstructing the S / D port itself into a rectangular transition structure extending beyond the barrier area. It integrates "barrier" and "connection" into a unified layout geometry definition, so that anti-interference design no longer comes at the cost of sacrificing wiring or area. It is a non-obvious structured solution.

[0052] 3. This invention combines a variable height structure with a wiring blocking structure to produce a synergistic effect, solving the technical problem that when building a standard cell library covering multiple performance specifications, it is difficult to simultaneously take into account high-frequency noise immunity and diverse PPA options, which leads to designers being limited by underlying physical constraints when making performance trade-offs.

[0053] Variable height structures offer a variety of size options, from low-power, small-area to high-performance, large-drive structures, solving the "flexibility" problem; wiring blocking structures provide built-in signal integrity guarantees, solving the "reliability" problem; when the two are combined, it is not a simple superposition of their respective functions, but rather forms a unified architecture in which "every variable-size unit can have noise immunity." This means that designers can freely choose units with different track heights according to PPA requirements when designing circuits, without worrying about whether the selected units require additional shielding measures or special layout constraints in high-frequency environments. This synergistic effect eliminates the design challenges of "high-performance units needing to consider interference immunity" and "layout area and design complexity" in traditional designs, enabling automatically generated layouts to have greater design freedom and robustness at the top-level planning level—a system-level technical effect that cannot be achieved by a single feature. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of a variable-height variant structure according to Embodiment 1 of the present invention;

[0055] Figure 2 This is a schematic diagram of a variant structure of wiring obstruction according to Embodiment 2 of the present invention.

[0056] 1-Layout and wiring boundary, 2-Contact hole, 3-Gate polysilicon, 4-N-type implantation region, 5-Active region, 6-Dummy polysilicon, 7-Metal layer 1, 8-Source via, 9-Drain via, 10-Contact hole, 11-Extension port, 12-Wiring barrier layer, 13-G-Gate port, S-Source port, D-Drain port. Detailed Implementation

[0057] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0058] The purpose of this invention is to solve the problems of limited wiring density and degraded high-frequency circuit performance caused by insufficient flexibility in cell size and lack of protection for sensitive areas in existing MOS transistor layouts.

[0059] Core innovative technology point 1: Adaptive scaling

[0060] Those skilled in the art will know that changing the active region (OD) and polysilicon (Poly) dimensions of a transistor can alter its performance;

[0061] Those skilled in the art also know that the total height of the cell is determined by the power / ground rails, the NMOS / PMOS regions, and the spacing between them.

[0062] However, does existing technology offer any insights into linking these elements together through an "adaptive scaling" rule?

[0063] Reference 1 [Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes] mentions that the power / ground widths may differ for cells of different heights (8T and 12T), but this describes a result rather than a design methodology of "adaptive scaling".

[0064] Reference 2 [High-Density Standard Cell Libraries with Backside PowerOptions in A14 Nanosheet Node] mentions "standard cell track height scaling" as a scaling method, but does not specifically explain how the internal components "adaptively" change accordingly. It also does not mention that "the longitudinal spacing between the power and ground tracks, and the longitudinal length of the active area adaptively expand and contract with the number of tracks" (the purpose of this invention is to adjust the layout size according to the device parameters, resulting in higher area utilization; it can also plan the cell height within the region as a whole, improving the overall layout area utilization. This overcomes the problem of irregular cell size and shape in the original invention).

[0065] Core innovative technology point 2: Use of a barrier layer

[0066] 1. As disclosed in reference 3 [RTL to GDS-II Implementation of VLSI Design in 'nm' Technology] regarding the prior art of "using a blocking layer", once a person skilled in the art makes the decision to "set a blocking layer", he will immediately face a new problem caused by his own actions: "I have blocked the wiring, how should I now connect to the source and drain of this cell?"

[0067] Those skilled in the art might think of (a) making the cells wider, leaving dedicated connection areas on the left and right sides; or (b) using higher-layer metals (such as M5, M6) to "cross" the barrier layer through multiple vias (VIAs) for connection. However, both of these methods would result in significant area or parasitic costs.

[0068] This invention proposes an extremely ingenious solution—making the S / D port itself into a specific "rectangle" and "extending laterally" to the "transition zone" outside the barrier layer. The cleverness of this solution lies in:

[0069] High space utilization efficiency: It does not significantly increase the width of the unit, but creates a safe and usable connection area within the existing unit frame by redesigning the port geometry.

[0070] Good process compatibility: It still allows EDA tools to use standard wiring methods (e.g., placing M1 contacts and VIA in the transition area) to connect units without the need for complex special wiring rules.

[0071] Structural integrity: It integrates the two behaviors of "blocking" and "connecting" into a unified, structured layout design, rather than a temporary, patchwork fix.

[0072] While the concept of "wiring obstruction" exists in existing technologies, it offers no technical guidance or inspiration regarding "solving connectivity issues by designing a specific-shaped port extending beyond the obstruction area after setting up the obstruction." The "obstruction and extended port" combination structure provided by this invention offers a non-obvious engineering solution to the contradiction between "protection" and "connectivity." It is not a simple patchwork of existing technological features, because patchwork (obstruction layer, standard port) itself does not work and instead creates new problems. The specific port design proposed by this invention to solve this new problem is precisely the key manifestation of its inventiveness.

[0073] This invention comprises two main variant configurations, which are achieved through distinguishing feature core innovation point 1 and distinguishing feature core innovation point 2, respectively. The above analysis shows that neither of these two distinguishing features is obvious to those skilled in the art.

[0074] The first core innovative technology introduces an innovative rule-based methodology for generating cell libraries, which solves the problems of PPA fine-tuning and design automation.

[0075] Core innovative technology point 2 provides a sophisticated signal integrity solution built into the layout, which resolves the contradiction between noise coupling and routing in advanced nodes.

[0076] These two features can be implemented independently or in combination. When combined, they create a synergistic effect: a standard cell library not only provides a variety of PPA options, ranging from low-power, small-area to high-performance, large-drive (through multi-tracking and adaptive scaling), but each cell itself can be configured with interference immunity (through wiring blocking structures). This allows chip designers to confidently make PPA trade-offs at a higher level without worrying too much about underlying physical effects undermining their design intent.

[0077] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0078] This invention relates to automated generation technology for analog and mixed-signal circuit layouts, and more particularly to a variant of a MOSFET layout that balances high-frequency performance and routing flexibility, as well as its usage method. The purpose of this invention is to address the problems of limited wiring density and degraded high-frequency circuit performance in existing MOSFET layouts due to insufficient cell size flexibility and lack of sensitive area protection. The main solution includes a standard cell design supporting variable height and wiring blocking: each standard cell includes virtual polysilicon, standard layout wiring boundaries, power rails and ground rails, and other necessary structures. Variable height allows for flexible scaling of the standard cell height by adjusting the number of wiring rails; the wiring blocking structure achieves optimized high-frequency interference immunity by setting a blocking layer in the device's working area and extending outwards laterally through ports. Furthermore, this invention provides a usage method that uses EDA tools to first complete the automatic placement and routing of NMOS and PMOS modules, and finally achieves automatic placement and routing between modules. This invention not only efficiently adapts to EDA tools and improves layout generation efficiency, but also significantly enhances the flexibility of layout design in terms of circuit performance and wiring planning.

[0079] To facilitate understanding of the technical solution of the present invention by those skilled in the art, a detailed description is provided below for a MOSFET layout that balances high-frequency performance and wiring flexibility:

[0080] The main layout is divided into NMOS modules, PMOS modules and other device modules, with isolation areas between adjacent modules;

[0081] The NMOS module and PMOS module are each composed of multiple standard units of the same type. The standard units are modularly arranged according to a predetermined rule to form a layout structure that can be spliced ​​together.

[0082] The structure of the standard cell includes two virtual polysilicon 6, a layout and wiring boundary 1, a power rail VDD and a ground rail VSS. The virtual polysilicon 6 is used to separate adjacent standard cells.

[0083] The placement and routing boundaries, power rails, and ground rails work together to enable the MOSFET layout structure to be recognized by EDA tools and participate in placement and routing, and to support adjacent placement with digital standard cells under the same process node. The placement and routing boundaries are used to define the geometric range of the standard cells, ensuring that the standard cells maintain regularity in shape and size, and supporting the splicing of multiple standard cells in the horizontal and vertical directions;

[0084] The standard cells in the NMOS module include only NMOS devices, and the standard cells in the PMOS module include only PMOS devices.

[0085] The other device module includes devices other than NMOS and PMOS, including at least one of diodes, transistors, capacitors, and resistors.

[0086] The main layout structure of the standard NMOS cell includes an active region 5, a source port S, a gate port G, a drain port D, an N-type injection region 4, and n identical gate polysilicon cells 3, as well as the transistor's channel length, channel width, and interpolation gate number parameters.

[0087] The main layout structure of the standard PMOS cell includes an active region 5, a source port S, a gate port G, a drain port D, an N-well, a P-type injection region, and n identical gate polysilicon cells 3, as well as the transistor's channel length, channel width, and interpolation gate number parameters.

[0088] The device size parameters of the standard cell include at least the channel length, channel width, and number of interpolated gates, and these parameters can be configured according to circuit design requirements.

[0089] The standard cell in the NMOS module includes an injection region structure for forming an NMOS device; the standard cell in the PMOS module includes an N-well structure and an injection region structure for forming a PMOS device.

[0090] The injection region structure and N-well structure are used to meet the electrical characteristic requirements of MOS transistor devices.

[0091] The layout and routing boundary is a closed boundary structure set around the standard cell, used to define the area occupied by the standard cell in the layout; the size of the layout and routing boundary is determined according to the height of the standard cell and the routing rules under the process node.

[0092] The standard NMOS cell includes an N-type injection region, and the active region is located within the N-type injection region;

[0093] The standard PMOS cell includes an N-well and a P-type injection region, wherein the P-type injection region is located within the N-well and the active region is located within the P-type injection region.

[0094] Under the layout projection relationship, the active region of the NMOS cell is located within the corresponding injection region; the active region of the PMOS cell is located within the corresponding injection region and N-well.

[0095] The power rails and ground rails are located in the edge region of the standard cell and are consistent with the power rail hierarchy of the digital standard cell under the process node.

[0096] The power rail and ground rail are used to provide power to the MOS transistor device.

[0097] The plurality of gate polysilicon cells are arranged laterally, and their spacing conforms to the design rules of the process node.

[0098] The gate port G is implemented using a single metal layer, and the gate port is connected to each of the gate polysilicon 3 through at least one contact hole.

[0099] Both the source port S and the drain port D are implemented using a single metal layer and are connected to the corresponding active region 5 through at least one contact hole.

[0100] The standard cell includes a virtual polysilicon structure disposed on both sides of the effective device region, the virtual polysilicon structure being used to isolate adjacent standard cells;

[0101] The virtual polycrystalline silicon structure does not participate in electrical connections.

[0102] Furthermore, while maintaining the regular layout and wiring boundaries, standard unit structure, and modular design, the present invention further includes the following two variant designs for specific application scenarios:

[0103] Variation of wiring blocking: To address the interference immunity requirements of high-frequency analog circuits, the standard unit is configured with a working area wiring blocking structure.

[0104] Above the active region and gate polysilicon of the standard cell, a wiring barrier layer of a specific metal level is provided to instruct automated placement and routing tools to prohibit cross-traffic in this area.

[0105] In order to achieve electrical connection under obstruction conditions, the source and drain ports of the standard cell extend laterally into the transition region.

[0106] Variable Height Variation: To accommodate different device sizes and routing complexities, the standard cell employs a variable height structure. The vertical height of the layout routing boundary is configured as a variable integer multiple of the standard routing track spacing defined by the process node.

[0107] At variable height, the longitudinal spacing between the power rail and the ground rail adaptively adjusts with the cell height to accommodate active region structures with larger longitudinal dimensions, thereby significantly increasing the effective channel width of the transistor.

[0108] Meanwhile, the increased vertical space provides additional internal horizontal wiring channels to address local wiring congestion issues in complex circuit topologies.

[0109] Specifically, this invention provides a MOSFET layout variant that balances high-frequency performance with wiring flexibility. The layout structure is divided into NMOS modules, PMOS modules, and other device modules. The modules have regular shapes and are composed of standard cells of the same type. Different variant structures can be selected according to circuit performance requirements. This design, by defining a unified splicing logic and mesh specification, enables the direct adjacency of any two standard cells within the same type of module without violating design rules. This structure is not only fully compatible with existing EDA tools, enabling the automated generation of analog mixed-signal circuits, but also significantly optimizes the area utilization and electrical performance of the layout while ensuring automation efficiency by utilizing different variant cells.

[0110] In one possible implementation, a variant of the MOS transistor layout that balances high-frequency performance and wiring flexibility includes a standard cell comprising a variable-height structure.

[0111] The standard unit includes a variable height structure implemented through the following scheme:

[0112] The longitudinal length of the cross-section of the layout wiring boundary 1 is adjustable, and its length is determined by the number of standard wiring tracks;

[0113] The standard unit can be configured as an M-track unit or an N-track unit, where M and N are different positive integers; when configured with different numbers of tracks, the longitudinal spacing between the power track VDD and the ground track VSS changes accordingly to accommodate different numbers of standard wiring tracks.

[0114] The longitudinal length of the active region 5 and the longitudinal length of the gate polysilicon 3 are adaptively stretched according to the change in the number of tracks, supporting a range of devices of different sizes and more suitable wiring space.

[0115] The maximum longitudinal dimension of the active region varies depending on the number of tracks, and this maximum dimension is directly related to the number of tracks. Therefore, the M-track unit and the N-track unit each have their own corresponding maximum width value. When the size of the active region exceeds this maximum width value, the height of the active region on a single polysilicon strip is reduced by increasing the number of polysilicon strips, while keeping the device W unchanged, until the size of the active region on a single polysilicon strip falls within the allowable limit range.

[0116] Furthermore, during the above-mentioned active region size adjustment process, the spacing and size of the remaining parts (such as gate polysilicon, N-type implantation region (or P-type implantation region and N-well), and metal layer 1) are all modified accordingly based on the adjusted active region geometric parameters to ensure that the overall layout fully complies with the preset design rules and maintains the electrical isolation and connection reliability between each layer.

[0117] The standard unit includes a wiring barrier layer structure for high-frequency circuit design;

[0118] The standard cell layout structure has a wiring barrier layer at the intersection of the active region 5 and the gate polysilicon 3. The wiring barrier layer is used to indicate to the EDA tool that it is prohibited to make wiring in a specific metal layer in this area.

[0119] The source port S and the drain port D are rectangular, with their two adjacent sides being horizontal and vertical, respectively.

[0120] If the power rail VDD, the ground rail VSS, the layout and routing boundary, the routing barrier layer, the source port S, and the drain port D are projected onto the same plane, the left side of the power rail VDD and the left side of the ground rail VSS are aligned with the left side of the layout and routing boundary, the right side of the power rail VDD and the right side of the ground rail VSS are aligned with the right side of the layout and routing boundary, the routing barrier layer is completely located within the layout and routing boundary, the left sides of the source port S and the drain port D are flush and located between the left side of the routing barrier layer and the left side of the layout and routing boundary, the right sides of the source port (S) and the drain port (D) are flush and located between the right side of the routing barrier layer and the right side of the layout and routing boundary, and the spacing conforms to the design rules.

[0121] This invention discloses a variant of a MOS transistor layout that balances high-frequency performance and wiring flexibility. The basic structure and its variant structures of this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0122] Example 1:

[0123] like Figure 1 As shown in the figure, this embodiment demonstrates a comparison of standard units with different numbers of orbits.

[0124] One configuration is a 9-track standard cell, with its vertical height containing 9 standard trace tracks. This structure is suitable for small to medium-sized MOSFETs and maintains a high area utilization rate. Another configuration is a 12-track standard cell, with the vertical length of its layout wiring boundary (1) increased by 3 tracks compared to the 9-track cell. The distance between the power track VDD and the ground track VSS is increased. In the 12-track cell, the vertical length of the active area (5) can be designed to be longer, achieving a larger channel width. The increased number of tracks provides more metal trace resources for complex interconnections within the cell, alleviating local wiring congestion and improving the success rate of automatic routing.

[0125] Example 2:

[0126] like Figure 2 As shown, this embodiment demonstrates a standard cell structure with wiring barriers suitable for high-frequency circuits. In this standard cell, one or more wiring barriers are provided at the overlap of the active region (5) and the gate polysilicon (3). This barrier layer is defined in the LEF file, ensuring that the EDA tool will not place metal lines above the active region of the MOS transistor during automatic routing, greatly reducing the parasitic capacitance coupling of the metal traces to the gate and active region, and avoiding crosstalk of high-frequency signals. In this embodiment, the source port (S) and drain port (D) adopt an extended port structure. Unlike the rectangular port in Embodiment 1, the extended port extends laterally outward, passing through the area covered by the wiring barrier layer, and directly extends to the reserved trace channel, allowing external connections to be electrically connected without crossing the device's operating area.

[0127] The present invention also discloses a method for using a MOS transistor layout variant that balances high-frequency performance and wiring flexibility, which will be further described in detail below with reference to the accompanying drawings and embodiments.

[0128] Example 3:

[0129] A method for using a MOSFET layout variant that balances high-frequency performance and wiring flexibility includes the following steps:

[0130] Step (1): Set the relevant parameters of the layout structure according to the parameter requirements of each MOS transistor in the circuit structure composed of MOS transistors in the simulation and hybrid circuit of automatic placement and routing as needed, and describe the layout structure of each MOS transistor in GDS format and LEF format to obtain the corresponding GDS file and LEF file.

[0131] Step (2): Divide the circuit diagram of the circuit structure composed of MOS transistors in the analog and hybrid circuits that need to be automatically placed and routed into two parts. One part is composed entirely of NMOS, called the NMOS module, and the other part is composed entirely of PMOS, called the PMOS module. Both circuit diagrams are described using Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described using Verilog language to form a third Verilog file.

[0132] Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool;

[0133] Step (4): Run the EDA tool to perform automatic placement and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout;

[0134] Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool;

[0135] Step (6): Run the EDA tool to perform automatic placement and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout;

[0136] Step (7): Input all the previously obtained GDS files, LEF files, and Verilog files describing the connection relationship between the two circuit parts into the EDA tool;

[0137] Step (8): Run the EDA tool to automatically place and route the circuit to obtain the complete circuit layout.

Claims

1. A MOSFET layout variant that balances high-frequency performance and wiring flexibility, characterized in that, The standard cell is divided into standard NMOS cell and standard PMOS cell. Each cell contains layout and wiring boundaries, virtual polysilicon, power rails and ground rails, and is combined into NMOS module and PMOS module respectively. The above standard cell without the addition of variant structure is defined as the basic standard cell. The standard unit also includes at least one of the following variant structures: Variable height structure: The longitudinal length of the layout wiring boundary is a variable integer multiple of the standard wiring track spacing under the process node. The longitudinal dimension range of the active area is determined by the number of tracks. The longitudinal spacing between the power track and the ground track, as well as the longitudinal length of each part in the unit, adaptively expand and contract with the number of tracks. Wiring blocking structure: A wiring blocking layer is provided at the intersection of the active region and the gate polysilicon to indicate to the EDA tool that a specific metal layer in the region should not be routed. The source and drain ports corresponding to the wiring barrier structure are rectangular and extend laterally outward to the transition area outside the coverage of the wiring barrier layer. The routing area reserved inside the layout wiring boundary and on the lateral outer side of the wiring barrier layer is defined as the transition area. Under the layout projection relationship, the sides of the source port and the drain port are located between the side of the wiring barrier layer and the side of the layout wiring boundary, and the spacing conforms to the design rules and does not affect the electrical interconnection.

2. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 1, characterized in that, In the variable height structure, the longitudinal length of the layout wiring boundary is a variable integer multiple of the standard wiring track spacing; when configured as an M track unit or an N track unit, M and N are different positive integers, and the longitudinal length of the active area is adaptively stretched according to the change in the number of tracks to accommodate different size requirements of the device.

3. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 1, characterized in that, When the standard unit includes the wiring barrier structure, if the power rail VDD, ground rail VSS, layout wiring boundary, wiring barrier layer, source port and drain port are projected onto the same plane: The wiring barrier layer is entirely located within the layout wiring boundary; The left sides of the source port and the drain port are flush and located in the middle area between the left side of the wiring barrier layer and the left side of the layout wiring boundary. The right sides of the source port and the drain port are flush and located in the middle area between the right side of the wiring barrier layer and the right side of the layout wiring boundary.

4. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 3, characterized in that, When the standard unit includes the wiring blocking structure, under the layout projection relationship... The left side of the power rail VDD, the left side of the ground rail VSS, and the left side of the layout wiring boundary are on the same straight line. The right side of the power rail VDD, the right side of the ground rail VSS, and the right side of the layout wiring boundary are on the same straight line. The lateral extension length of the source port and drain port into the transition region allows external wiring to complete electrical connection without crossing the wiring barrier layer.

5. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 1, characterized in that, The variants are divided into NMOS variants and PMOS variants; The NMOS variant includes only NMOS devices, and the PMOS variant includes only PMOS devices; The variant includes two virtual polysilicon cells, which are respectively disposed on both sides of the effective device region to isolate adjacent variant cells. The virtual polysilicon cells do not participate in electrical connection. The effective device region is a channel region formed by the overlap of the active region and the gate polysilicon.

6. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 5, characterized in that, The NMOS variant includes an N-type injection region, and the active region is located within the N-type injection region; The PMOS variant includes an N-well and a P-type injection region, wherein the P-type injection region is located within the N-well and the active region is located within the P-type injection region; Under the layout projection relationship, the active region of the NMOS variant is located within the corresponding injection region, and the active region of the PMOS variant is located within the corresponding injection region and N-well.

7. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 1, characterized in that, The device size parameters of the variant include at least the channel length, channel width, and number of intercalation gates; The gate port is implemented using a metal layer 1 and is connected to the gate polysilicon via a contact hole; The source and drain ports are implemented using two metal layers and connected to the active region through contact holes; The plurality of gate polysilicon cells are arranged laterally, and their spacing conforms to the design rules of the process node.

8. The MOSFET layout variant that balances high-frequency performance and wiring flexibility according to claim 1, characterized in that, The layout routing boundary is a closed boundary structure set around the standard cell, used to define the area occupied by the standard cell in the layout; The power rails and ground rails are located in the edge region of the standard cell and are consistent with the power rails and ground rails of the digital standard cell under the process node. Both the variable height structure and the wiring barrier structure follow the grid alignment logic of the layout wiring boundary, enabling the variant to be recognized by EDA tools and seamlessly and automatically spliced ​​with standard cells of the same type.

9. A method of using a MOSFET layout variant that balances high-frequency performance and wiring flexibility as described in any one of claims 1 to 8, characterized in that, Includes the following steps: Step S1: Based on the performance requirements of each MOSFET in the circuit design, select the corresponding variable height structure or wiring barrier structure, set the layout parameters, and generate the GDS file and LEF file describing the variant; Step S2: Divide the circuit diagram into NMOS modules and PMOS modules, describe them using a hardware description language and generate corresponding netlist files; Step S3: Input the GDS file, LEF file and netlist file into the EDA tool and run automatic placement and routing; The EDA tool automatically calls variants containing the performance adaptation structure for array placement and splicing based on the grid alignment logic of the layout and routing boundaries to obtain a complete circuit layout.

10. The method of use according to claim 9, characterized in that, In step S3: The EDA tool first performs automatic placement and routing on the NMOS module to generate the NMOS module layout, then performs automatic placement and routing on the PMOS module to generate the PMOS module layout, and finally performs cross-module automatic routing based on the connection relationship between the modules. During the automatic placement and routing process, for variants that include the aforementioned routing barrier structure, the EDA tool prohibits routing in the area covered by the routing barrier layer according to the LEF file, and uses source and drain ports extending to the transition region for signal interconnection. For variants containing the variable height structure, the EDA tool strictly follows the alignment logic of an integer multiple of the standard trace track spacing based on the layout routing boundary, thereby achieving automated splicing of units with different height variants within the same type of module.

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