A three-dimensional integrated circuit fixed profile layout planning method, system and medium

Abstract

The application discloses a three-dimensional integrated circuit fixed contour layout planning method, system and medium, relates to the field of three-dimensional integrated circuit layout design, and comprises the following steps: acquiring module size, line network, layer number and fixed contour information of each layer; constructing a three-dimensional layout planning state containing module layer distribution, module orientation and relative sequence in the layer; searching the state space based on a search algorithm, locking the optimal layout state when feasibility stagnation occurs; determining the bottleneck module and its accompanying module according to the bottleneck score; removing the bottleneck module and the accompanying module in the optimal layout state, and performing local layout reconstruction, and outputting a three-dimensional layout planning result. The method effectively solves the feasibility conflict under the multi-layer constraint through accurate positioning of the bottleneck and local directional reconstruction, improves the solving efficiency while ensuring the area utilization rate and the line length optimization, and is suitable for automatic physical design of large-scale three-dimensional integrated circuits.

Description

Technical Field

[0001] This application relates to the field of three-dimensional integrated circuit layout design, and in particular to a method, system and medium for planning fixed contour layout of three-dimensional integrated circuits. Background Technology

[0002] Layout planning is a crucial step in integrated circuit physical design. It aims to determine the location, orientation, and interconnection relationships of functional modules within a given boundary of a chip or device layer. The results directly impact placement, routing, timing, power consumption, heat dissipation, and yield. Three-dimensional integrated circuits increase integration density and shorten interconnection distances through vertical stacking of multiple layers, but their layout planning is more complex: modules require simultaneous planar arrangement and layer assignment; cross-layer interconnections introduce additional costs such as through-silicon vias (TSVs); and while inter-layer migration may alleviate area pressure, it increases interconnection costs or affects heat distribution. Fixed-profile layout planning requires each layer to be strictly within predetermined boundaries. Exceeding the contour forces significant adjustments in subsequent stages, disrupting the design budget. Therefore, fixed-profile constraints are a crucial prerequisite for the smooth progress of early-stage design.

[0003] Existing methods mostly employ simulated annealing, sequence pairing, and B... -Tree, analytical optimization, electrostatic field models, or post-processing legalization are used to implement module layout. In 2D scenes, local movement, rotation, swapping, and insertion can improve contour feasibility; 3D scenes also need to consider layer allocation, intra-layer order, and interconnection costs. Sequence pairs determine compact layout through positive and negative sequences, which is a commonly used representation method. When dealing with fixed contours, contour overflow is often introduced as a penalty term into the cost function, and residual overflow is corrected through post-processing legalization at the end of the search; some methods also introduce random destruction and repair strategies to escape local optima through large perturbations. However, these methods are effective when utilization is low or constraints are relaxed, and face serious challenges in high-utilization fixed contour scenarios.

[0004] In high-utilization fixed-profile 3D layout planning, the search often stalls near feasibility, meaning the optimal overflow is still positive, but conventional perturbations cannot further reduce it. This is not due to a single overly large module, but rather the combined effect of the local ordering structure, layer allocation, and empty distribution within the congestion layer. Taking sequence pairs as an example, the local sequential relationship determined by the positive and negative sequences forms a critical chain. Even if the bottleneck module is removed, if the neighboring ordering relationship is preserved, a similar overflow will reappear after re-insertion. Traditional post-processing only corrects after the search ends, failing to promptly change the local structure; while random perturbations expand the neighborhood, they lack targeted identification of the congestion layer, overflow direction, and sequence pair relationships, often inadvertently damaging good interconnect locality or failing to sever the key ordering relationships that truly support the overflow. In summary, existing technologies lack a solution that can identify stalled states during the search, locate the congestion layer and its local structure, and perform targeted disruption and reconstruction. Summary of the Invention

[0005] The purpose of this application is to provide a three-dimensional integrated circuit fixed contour layout planning method, system and medium, which can dynamically identify the feasibility stagnation state during the search process, accurately locate the contour overflow problem to the congestion layer and its local relative order structure, and break the critical order chain by targeted destruction and reconstruction of the local structure, thereby effectively reducing the remaining contour overflow while retaining the interconnection optimization effect, and finally obtaining a feasible layout scheme that meets the fixed contour constraints.

[0006] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a method for planning the fixed contour layout of a three-dimensional integrated circuit, including: Obtain module size information, mesh information, layer number information, and fixed contour information of each layer of a 3D integrated circuit; A three-dimensional layout planning state is constructed based on the module size information, mesh information, layer number information, and fixed contour information of each layer; the three-dimensional layout planning state includes module layer allocation, module orientation, and relative order representation within layers; Based on the module layer allocation, module orientation, and relative order representation within the layer, a global search algorithm is used to perform a global search on the 3D layout planning state, and the layout state at which feasibility stall occurs is determined as the optimal layout state. Based on the optimal layout state, bottleneck modules are determined according to the bottleneck scores of each module; and accompanying modules are determined according to the bottleneck modules. In the optimal layout state, the bottleneck module and the accompanying module are removed, and the local layout is reconstructed through a local reconstruction search algorithm to output the optimal repair state. When the optimal repair state meets the preset acceptance criteria, the global search continues with the optimal repair state as the current layout state, and the 3D layout planning result is output; otherwise, the global search continues with the optimal layout state as the current layout state, and the 3D layout planning result is output.

[0007] Optionally, the intra-layer relative order representation includes sequence pair representation, B... -Tree representation, constraint graph representation, or equivalent representation that can characterize the relative positional relationships of modules at the same level.

[0008] Optionally, a global search algorithm is used to perform a global search on the 3D layout planning state, and the layout state at which feasibility stall occurs is determined as the optimal layout state, specifically: The 3D layout planning state is globally searched using a global search algorithm. In each iteration of the global search algorithm, the following steps are performed: Based on the module layer allocation, module orientation, and relative order within the layer, the modules of each layer are arranged compactly to obtain the coordinates of each module, the width of each layer, and the height of each layer. Based on the coordinates of each module, the width and height of each layer, calculate the outline overflow of each layer, the global maximum outline overflow, the total outline overflow, the line length and the estimated value of the through-silicon via requirements. Based on the estimated values ​​of each layer's outline overflow, the global maximum outline overflow, the total outline overflow, the line length, and the via requirements, determine whether a feasibility stagnation state has occurred. If a feasibility stagnation state has occurred, output the optimal layout state; otherwise, continue the global search.

[0009] Optionally, based on the optimal layout state, the bottleneck module is determined according to the bottleneck score of each module, specifically as follows: Based on the optimal layout state, the congestion layer is determined; Calculate the bottleneck score for each module in the congestion layer; The bottleneck scores of each module are sorted, and the modules that meet the preset score threshold are identified as bottleneck modules.

[0010] Optionally, based on the bottleneck module, an accompanying module is determined, specifically: Based on the relative order of the bottleneck modules within the layer, the modules within a preset distance of the bottleneck module are identified as accompanying modules.

[0011] Optionally, in the optimal layout state, the bottleneck module and the accompanying module are removed, and a local layout reconstruction is performed to output the optimal repair state, specifically: Remove all bottleneck modules and all accompanying modules from the optimal layout state to obtain the current layout state; Insert all bottleneck modules and all accompanying modules into the current layout state using a local reconstruction search algorithm, and output candidate repair states; Calculate the repair evaluation key of the candidate repair state; if the repair evaluation key of the candidate repair state is better than the repair evaluation key of the current layout state, then take the candidate repair state as the current layout state and continue the local reconstruction search, and output the optimal repair state.

[0012] Optionally, the local reconstruction search includes bundle search, greedy re-insertion search, candidate queue search, dynamic programming search, local enumeration search, and combinations thereof.

[0013] Optionally, the repair evaluation key is described as follows: in, Indicates the repair rating key; A flag indicating whether a candidate state is infeasible; This represents a combination of feasibility indicators; Indicates line length. This represents the estimated demand for through-silicon vias. This indicates the weight of the estimated demand for through-silicon vias. This represents the scalar objective function in the local reconstruction search.

[0014] Secondly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the three-dimensional integrated circuit fixed contour layout planning method described above.

[0015] Thirdly, this application provides a three-dimensional integrated circuit fixed contour layout planning system, comprising: The data acquisition module acquires the module size information, mesh information, layer number information, and fixed contour information of each layer of the 3D integrated circuit. The three-dimensional state construction module constructs a three-dimensional layout planning state based on the module size information, mesh information, layer number information, and fixed contour information of each layer; the three-dimensional layout planning state includes module layer allocation, module orientation, and relative order representation within layers. The global search module, based on the module layer allocation, module orientation and relative order representation within the layer, performs a global search algorithm to search the three-dimensional layout planning state and determines the layout state when feasibility stalls as the optimal layout state. The local damage determination module, based on the optimal layout state, determines the bottleneck module according to the bottleneck score of each module; and determines the accompanying module according to the bottleneck module. The local reconstruction and repair module removes the bottleneck module and the accompanying module in the optimal layout state, and performs local layout reconstruction through a local reconstruction search algorithm to output the optimal repair state. The result output module, when the optimal repair state meets the preset acceptance criteria, uses the optimal repair state as the current layout state to continue the global search and outputs the 3D layout planning result; otherwise, it uses the optimal layout state as the current layout state to continue the global search and outputs the 3D layout planning result.

[0016] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a method, system, and medium for three-dimensional integrated circuit fixed contour layout planning. By constructing a three-dimensional layout planning state including module layer allocation, module orientation, and relative order within layers, and performing global optimization based on a search algorithm, the optimal layout state is locked when feasibility stalls. This effectively avoids wasting computational resources due to excessive searching, significantly improving the efficiency and convergence speed of layout planning. Simultaneously, this application accurately identifies bottleneck modules that restrict the overall layout feasibility based on bottleneck scoring, and further determines accompanying modules with strong coupling relationships to the bottleneck modules. This enables accurate location and local isolation of defective modules in the optimal layout state, avoiding destructive adjustments to the global layout structure, thereby significantly reducing reconstruction complexity while ensuring optimization quality. Quantitative evaluation of each module based on bottleneck scoring accurately identifies bottleneck modules that restrict the overall layout feasibility, and further determines accompanying modules with strong coupling constraints to the bottleneck modules. This enables accurate location and directional isolation of problematic modules in the locked optimal layout state, avoiding blind adjustments to the global layout structure, thereby significantly reducing the complexity and risk of repair operations while maintaining the original high-quality layout framework. A local reconstruction search algorithm is employed to perform targeted optimization and reconstruction of the remaining layout state after removing bottleneck and adjoint modules. This local reconstruction strategy only searches and adjusts areas with dense conflicts, and the search space is much smaller than that of a global search. It can quickly eliminate critical violations that restrict feasibility while avoiding disturbance to the globally converged structure, and has the outstanding advantages of low computational cost and high repair efficiency.

[0017] Furthermore, after obtaining the optimal repair state, this application comprehensively evaluates it using a preset acceptance criterion. When the optimal repair state meets the acceptance criterion, it indicates that the local reconstruction has successfully improved performance, and it is used as the current layout state to continue the global search, thereby fully utilizing the dual advantages of the repaired feasibility and the objective function to accelerate convergence. When the optimal repair state does not meet the acceptance criterion, it indicates that the repair effect has failed to surpass the original optimal state, and the optimal layout state is retained to continue the global search, effectively preventing performance regression caused by adopting a poor repair state. This conditional optimal update mechanism ensures that the current layout state is never inferior to the previous optimal state, achieving a strictly non-degrading evolution in the optimization process, while also possessing good fallback performance. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an application environment diagram of a three-dimensional integrated circuit fixed contour layout planning method according to an embodiment of this application; Figure 2 A flowchart illustrating a three-dimensional integrated circuit fixed contour layout planning method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a partial bottleneck repair process provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application.

[0020] 102 - Terminal; 104 - Server. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The three-dimensional integrated circuit fixed contour layout planning method provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be set up independently, integrated into server 104, or placed in the cloud or on other servers. Terminal 102 can send the 3D integrated circuit design data to be processed to server 104. After receiving the design data, server 104, based on information such as module dimensions, net connections, and contour constraints extracted for the 3D integrated circuit, executes a fixed contour layout planning process. Based on the obtained layout planning status, it performs bottleneck identification and local reconstruction repair to obtain a 3D layout planning result that meets the fixed contour constraints. Server 104 can feed back the obtained layout planning result for the 3D integrated circuit to terminal 102. Furthermore, in some embodiments, the 3D integrated circuit fixed contour layout planning method can also be implemented independently by server 104 or terminal 102. For example, terminal 102 can directly perform layout planning processing on the design data to be processed, or server 104 can obtain the design data to be processed from the data storage system and perform layout planning processing on the design data to be processed.

[0024] The terminal 102 can be, but is not limited to, various desktop computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, and smart in-vehicle devices. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted devices. The server 104 can be implemented using a standalone server or a server cluster composed of multiple servers, or it can be a cloud server.

[0025] In one exemplary embodiment, such as Figure 2 As shown, a method for planning the fixed contour layout of a three-dimensional integrated circuit is provided. This method is executed by a computer device, specifically by a terminal or server alone, or by both a terminal and a server. In this embodiment, the method is applied to... Figure 1 Taking server 104 as an example, the explanation includes the following steps S1 to S6. Wherein: Step S1: Obtain the module size information, mesh information, number of layers information, and fixed contour information of each layer of the three-dimensional integrated circuit.

[0026] Specifically, this information can be obtained through netlist files, module description files, process configuration files, or intermediate representations from electronic design automation tools. Module size information is modeled as a set of modules. , These represent different modules, where each module contains a module width. Module height Module area And rotatable information; net information describes the electrical connections between modules or between module pins, including net sets. The connections between modules or pins are used to calculate the half-perimeter wirelength (HPWL) and through-silicon via (TSV) requirements; the layer number is determined as an integer. This limits the number of vertically stacked device layers; the fixed contour information of each layer defines the maximum boundary that modules can be placed on each layer, which is usually expressed as a fixed width. and height This constitutes a hard boundary constraint. This structured data representation provides a precise numerical basis for subsequent state construction.

[0027] Step S2: Construct a 3D layout planning state based on module size information, mesh information, layer number information, and fixed contour information of each layer; the 3D layout planning state includes module layer allocation, module orientation, and relative order representation within layers.

[0028] Specifically, a 3D layout planning state is initialized based on the acquired module size information, net information, layer number information, and fixed contour information of each layer. The 3D layout planning state includes module layer allocation, module orientation, and intra-layer relative order representation; this state is a mathematical abstraction of all current module arrangement schemes. Module layer allocation determines which device layer each module is placed on; module orientation determines whether the module has been rotated or flipped; and the intra-layer relative order representation is a topological data structure used to describe the left-right or up-down relative positional relationships between modules within the same layer, without directly relying on specific geometric coordinates. This representation method can transform the complex geometric layout problem into a discrete combinatorial optimization problem, facilitating efficient state traversal and perturbation operations in subsequent search algorithms.

[0029] For example, a state vector is initialized containing representations of module layer assignment, module orientation, and relative order within the layer. For any module, its state is represented by a quadruple. Characterization, in which For planar coordinates, For layer numbering, In a rotated state, module layer allocation can be initialized using random allocation or a balanced allocation strategy based on module area; module orientation is typically initialized to a default orientation or random rotation. Relative order within a layer is represented through topological relationships (such as sequence pairs, B...). Implicit left-right and top-bottom constraints between modules (such as -tree) are defined. The advantage of this representation method is that it can transform complex geometric overlap detection into the validity verification of discrete structures, ensuring that the intermediate states generated during the search process always satisfy the non-overlapping constraint, thereby significantly reducing the search overhead of the invalid solution space.

[0030] Step S3: Based on module layer allocation, module orientation, and relative order representation within the layer, a global search algorithm is used to perform a global search on the 3D layout planning state, and the layout state at which feasibility stall occurs is determined as the optimal layout state.

[0031] Specifically, a pre-defined global search algorithm (such as simulated annealing, genetic algorithm, or large neighborhood search algorithm) is used to iteratively optimize the 3D layout planning state. During the search process, perturbations are continuously applied to the current module layer allocation, module orientation, or relative order representation within layers to generate new candidate states. The feasibility stall is then assessed based on the global maximum contour overflow and the improvement magnitude of the optimal contour overflow. If feasibility stall occurs, i.e., both the global maximum contour overflow and the improvement magnitude of the optimal contour overflow meet preset thresholds, the candidate state is recorded as the optimal layout state. This step aims to leverage the global search capability to quickly approximate the feasible solution region.

[0032] For example, taking the Simulated Annealing (SA) algorithm, in each iteration, the algorithm applies random perturbation operations to the current layout state. These random perturbation operations include intra-layer module swapping, intra-layer module insertion, module rotation, inter-layer module movement, and inter-layer module swapping. For the generated candidate layout states, the actual coordinates are first decoded using a compact arrangement algorithm (such as the longest path method) based on the intra-layer relative order representation. Then, the contour overflow, line length, and TSV requirement are calculated. The global maximum contour overflow and the optimal contour overflow improvement are also calculated. If the candidate layout state is better than the current layout state, it is accepted unconditionally; if it is worse than the current layout state, it is accepted with a certain probability according to the Metropolis criterion, and this probability decreases as the temperature parameter decreases. Through this mechanism, the algorithm can extensively explore the solution space in the early stages and finely converge in the later stages. Finally, the state in which both the global maximum contour overflow and the optimal contour overflow improvement satisfy the preset thresholds is recorded as the optimal layout state.

[0033] Step S4: Based on the optimal layout state, determine the bottleneck module according to the bottleneck score of each module; and determine the accompanying module according to the bottleneck module.

[0034] Specifically, when the optimal layout state determined by the search algorithm reaches a feasible stagnation state, a bottleneck identification mechanism is activated. First, a bottleneck score is calculated for each module in the congestion layer. This score comprehensively considers factors such as the module's contribution to boundary overflow, its occupancy in the dominant overflow direction, its mobility, and the cost of perturbation to the overall structure. Modules with higher scores are identified as the core cause of the current overflow, i.e., the bottleneck module. Subsequently, based on the topological proximity relationships in the relative order representation within the layer, modules with strong constraint associations with the bottleneck module are identified as companion modules. This mechanism ensures that not only geometrically large modules are identified, but also the set of key nodes maintaining the current poor topology, thus avoiding the repair failure problem caused by traditional methods selecting repair targets based on a single indicator.

[0035] For example, when the optimal layout reaches a feasible stagnation state, contour overflow still exists. First, the congested layer with overflow is located, and the dominant overflow direction is determined. Then, each module in the congested layer is traversed, and its bottleneck score is calculated. This score is a multi-factor weighted index that comprehensively considers the module's contribution to boundary overflow, its size proportion in the dominant direction, the flexibility of re-insertion, and the disturbance cost to the overall structure. Modules with scores higher than a preset threshold are marked as bottleneck modules. Next, companion modules are found based on topological proximity in the relative order representation within the layer. For example, in the sequence pair representation, companion modules are the predecessor or successor nodes of the bottleneck module within a preset neighborhood in the positive and negative sequences. This selection strategy based on topology rather than simple geometric distance can accurately identify module groups that jointly maintain a locally compact span or key constraint chain, avoiding the problem of rapid overflow recovery after removing only a single bottleneck module because the constraint chain is not broken.

[0036] Step S5: Remove the bottleneck module and the accompanying module in the optimal layout state, and perform local layout reconstruction through the local reconstruction search algorithm to output the optimal repair state.

[0037] Specifically, the identified bottleneck modules and their associated modules are temporarily removed from the current optimal layout state to form the current layout state. Then, a local reconstruction search strategy is used to re-insert these removed modules into the current layout state. During re-insertion, different layer assignments, insertion positions, and orientation combinations are tried, and a dedicated repair evaluation key is used to filter candidate repair states. This evaluation key prioritizes the restoration of the fixed contour feasibility while also considering interconnection quality metrics such as line length and TSV requirements. Only when the repair evaluation key of a candidate repair state is superior to that of the current layout state will it be adopted and updated as the new current layout state, serving as the starting point for subsequent local reconstruction searches. Finally, when the termination condition is met, the optimal repair state is output.

[0038] S6. When the optimal repair state meets the preset acceptance criteria, the global search continues with the optimal repair state as the current layout state, and the three-dimensional layout planning result is output; otherwise, the global search continues with the optimal layout state as the current layout state, and the three-dimensional layout planning result is output.

[0039] The preset acceptance criterion can be configured such that the repair evaluation key of the optimal repair state is superior to the repair evaluation key of the optimal layout state. When the optimal repair state meets the preset acceptance criterion, it indicates that the local reconstruction operation has successfully broken the feasibility deadlock, and the obtained repair state has surpassed the original optimal layout state in terms of overall performance. At this point, the optimal repair state is taken as the current layout state, and the global search continues from there. This strategy can fully utilize the dual advantages of the repaired state in terms of feasibility and objective function, accelerating the convergence of subsequent searches towards the global optimum.

[0040] When the optimal repair state does not meet the acceptance criterion, it indicates that although the local reconstruction improved feasibility, the cost (such as area degradation, increased line length, or intensified interlayer coupling) has led to a decline in overall performance, or the repair effect is insufficient to surpass the original optimal state. In this case, this application does not replace the current layout state with the repair state, but retains the original optimal layout state as the current layout state to continue the global search. This rejection mechanism effectively prevents the objective function from degenerating due to the adoption of inferior repair states, ensuring the monotonicity and stability of the overall optimization process.

[0041] By implementing steps S1 to S6, this application effectively overcomes the technical shortcomings of traditional three-dimensional integrated circuit layout planning methods, which are prone to getting trapped in local extrema and struggling to converge to a feasible solution under high utilization and strict fixed contour constraints. On the one hand, this method effectively alleviates the feasibility stagnation phenomenon that easily occurs when a single search algorithm deals with complex combinatorial optimization problems by organically combining global search with a local destruction-reconstruction mechanism, significantly improving the overall feasibility of the layout scheme under boundary constraints. On the other hand, by introducing a bottleneck scoring mechanism based on multi-factor weighted indices and an accompanying module identification mechanism based on topological proximity, it can accurately locate the key module groups that cause contour overflow, rather than relying solely on random perturbations or single size indices for trial and error. This effectively breaks down the key constraint chains that maintain the local poor topology and fundamentally reduces the probability of repeated overflows. At the same time, in the process of repairing contour overflow, this method constructs a repair evaluation key that takes into account contour feasibility, line length, and the number of through-silicon vias, ensuring that the final output layout scheme has both superior interconnect quality and lower manufacturing cost while meeting physical boundary constraints, achieving effective synergistic optimization of area utilization and electrical performance indicators. Furthermore, the intra-layer relative order representation method based on topological data structures avoids the computational overhead of frequent geometric overlap detection. Combined with diverse perturbation strategies and temperature annealing mechanisms, the algorithm exhibits good robustness and search efficiency in design scenarios with different scales and layer counts. Therefore, this application provides a practical solution with high success rate, high performance, and low computational overhead for automated layout planning of 3D integrated circuits.

[0042] In an exemplary embodiment, the intra-layer relative order representation includes sequence pair representation, B... -Tree representation, constraint graph representation, or equivalent representation that can characterize the relative positional relationships of modules at the same level.

[0043] Specifically, the core function of the intra-layer relative order representation is to map the continuous geometric coordinates of modules in a two-dimensional plane into discrete topological data structures. This allows the search algorithm to efficiently traverse the valid layout solution space without directly handling geometric overlap detection. In this application, this representation is not limited to a single specific data structure, but encompasses multiple topological models that can fully describe the relative positional relationships between modules in the same layer. These models are interchangeable in the technical solution of this application and can be flexibly selected according to the specific design scale, search strategy preferences, or computational resource constraints.

[0044] When using sequence pairs (SP) representation, the intra-layer relative order is represented by two module permutations, called the positive and negative sequences. These two sequences together encode the horizontal and vertical relative relationships between all modules in that layer. The specific decoding rules are as follows: The layer has a positive sequence and negative sequences Both are The arrangement of modules. If modules exist and All are located in the module Previously, lie in Left side; if exist Central Previously but Central After that, lie in Below; in other cases, left-right or top-bottom constraints are obtained according to the corresponding rules. Besides sequence pair representation, B can also be used. -tree, constraint graph, or other equivalent representations that can characterize relative order within a layer.

[0045] For example, when using B When represented by `-tree`, the relative order within a layer is modeled as an ordered binary tree structure. Each node in the tree corresponds to a module, the left child of a node represents the module immediately to its right, and the right child represents the module immediately above it. -tree indicates compact storage characteristics, and the decoding process from the tree structure to the actual physical coordinates can be completed in linear time with a single depth-first traversal. This significantly reduces the computational overhead of the evaluation function when dealing with large-scale module sets. Furthermore, for B... The perturbation operations of the tree (such as subtree rotation and node swapping) can also ensure that the generated new state always corresponds to a valid compact arrangement, avoiding invalid search.

[0046] For example, when using constraint graph representation, the relative order within a layer is explicitly expressed as two directed acyclic graphs: a horizontal constraint graph and a vertical constraint graph. Vertices in the graph represent modules, and directed edges represent the relative positional constraints between modules. The weight of the edges typically corresponds to the module's size or minimum spacing requirements. For instance, in a horizontal constraint graph, an edge pointing from module A to module B indicates that module A must be placed to the left of module B, and the center-to-edge distance or edge-to-center distance between them must satisfy specific constraints. The advantage of constraint graph representation lies in its semantic intuitiveness, directly reflecting the critical path that causes contour overflow, facilitating rapid location of constraint chains causing width or height exceedances during the bottleneck identification stage. In the local reconstruction and repair process of this application, constraint graph representation can also conveniently support incremental updates; that is, when removing or inserting a small number of modules, only the affected edges and paths need to be locally adjusted, without requiring full graph reconstruction.

[0047] In addition to the three specific forms mentioned above, equivalent representations that can characterize the relative positional relationships of modules in the same layer also fall within the scope of protection of this application. For example, O-tree representation, Corner Block List (CBL) representation, or Transitive Closure Graph (TCG) representation, as long as they can uniquely determine the relative orientation between modules through discrete topological relationships and support effective state perturbation and decoding during the search process, can all be applied to the three-dimensional integrated circuit fixed contour layout planning method of this application.

[0048] In an exemplary embodiment, a global search algorithm is used to perform a global search on the 3D layout planning state, and the layout state at which feasibility stall occurs is determined as the optimal layout state. Specifically, based on the module layer allocation, module orientation, and relative order within the layer, the modules of each layer are arranged compactly to obtain the coordinates of each module, the width of each layer, and the height of each layer. Based on the coordinates of each module, the width of each layer, and the height of each layer, the outline overflow of each layer, the global maximum outline overflow, the total outline overflow, the line length, and the estimated value of the through-silicon via (TSV) requirement are calculated. A global search is performed on the current 3D layout planning state until a feasibility stall occurs, thus obtaining the optimal layout state.

[0049] Specifically, in each iteration of the global search algorithm, the following steps are performed: S301, the first step is to decode the abstract relative order representation within the layer into specific geometric layout information. This process typically employs compact arrangement algorithms, such as the longest path method or a constraint graph-based topology sorting algorithm. Taking sequence pair representation as an example, a horizontal constraint graph is constructed based on the positive sequence, and a vertical constraint graph is constructed based on the negative sequence. Nodes in the graphs represent modules, directed edges represent the relative positional constraints between modules, and the edge weights correspond to the module dimensions. By performing the longest path calculation on these two constraint graphs respectively, the horizontal and vertical coordinates of each module within its layer can be determined, thereby calculating the actual boundary range occupied by all modules in that layer, i.e., the width used by each layer. and the height of each floor This compact arrangement mechanism ensures that there are no unnecessary blank areas between modules under a given topological order, thus enabling subsequent overflow assessments to accurately reflect the matching relationship between the compactness of the current topology and the fixed contour constraints.

[0050] S302, after obtaining the coordinates of each module and the width and height of each layer, further calculates the outline overflow of each layer, the global maximum outline overflow, the total outline overflow, the line length, and the estimated value of the through-silicon via (TSV) requirement. For the first... Layer, its lateral profile overflow and longitudinal profile overflow The calculation formula is as follows: in, and The first The fixed width and fixed height of the layer; let , This represents the positive truncation function, i.e. or This is used to retain only the portion exceeding the fixed outline. When the actual usage size is smaller than the fixed outline, the overflow is recorded as 0; when the actual usage size exceeds the fixed outline, the overflow is recorded as 0. These represent the excess amount in the width or height direction, respectively.

[0051] Based on the overflow amount of each layer's contour, the global maximum contour overflow amount and the total contour overflow amount can be further derived as follows: in, Indicates the global maximum profile overflow; This represents the total outline overflow. These two global metrics quantify the degree of violation of the fixed outline constraint by the current state from two dimensions: worst-case scenario and overall violation level. When the horizontal and vertical outline overflow of all layers is not greater than the preset feasibility tolerance, and there is no overlap between modules in the same layer, the current layout planning state satisfies the feasibility of the fixed outline.

[0052] Simultaneously, to ensure interconnect quality, estimates for wire length and through-silicon via (TSV) requirements are calculated. Wire length is typically estimated using the half-perimeter wirelength (HPWL) model, which involves taking half the perimeter of the bounding box for each net and summing the results. The formula is as follows: Among them, wire mesh This represents a specific net in the current layout state during a feasibility search. Indicates wire mesh Pins, module center point, or equivalent connection point Its planar coordinates.

[0053] The total line length is: For any wire network The TSV demand estimate is determined based on the difference between the maximum and minimum layer numbers of the modules connected by the cross-layer network, and its expression is: in, Indicates wire mesh Estimates of the demand for through-silicon vias; This indicates the layer number where the module resides.

[0054] Therefore, the total estimated demand for through-silicon vias is: .

[0055] These metrics together form the basis of the objective function of the search algorithm and provide data support for subsequent judgments on whether the search has stalled.

[0056] S303 determines whether a feasibility stall state has occurred based on the overflow amount of each layer's contour, the global maximum contour overflow amount, the total contour overflow amount, the line length, and the estimated value of the through-silicon via and via requirements. If a feasibility stall state has occurred, the optimal layout state is output; otherwise, the search continues.

[0057] Specifically, during the feasibility search process, a preset monitoring window will be continuously monitored. The trend of improvement in inner contour overflow. Let... The optimal global maximum profile overflow at time t is The optimal contour overflow improvement within the monitoring window. = .

[0058] A feasibility stall is determined to occur when both of the following conditions are met simultaneously: First, the extent of improvement in optimal contour overflow. Less than the preset overflow improvement threshold This indicates that in recent search history, conventional perturbation operations have become insufficient to further reduce contour overflow. Second, the optimal global maximum profile overflow. Still greater than the preset feasibility tolerance This indicates that the current state does not yet meet the fixed contour constraint requirements.

[0059] When the aforementioned feasibility stagnation state is triggered, the currently recorded optimal layout state is determined as the input object for the subsequent bottleneck repair process. In this application, the optimal layout state specifically refers to a stage convergence point reached when conventional search capabilities are exhausted but the problem remains unsolved. Using this state as the starting point for repair can accurately capture the structural obstacles that cause the search to get stuck in local minima, making subsequent bottleneck identification and local reconstruction operations more targeted. In this way, this embodiment effectively solves the problem of conventional search easily stagnation in high-utilization fixed contour layout planning, ensuring that the repair mechanism can be activated at the most needed moment, thereby significantly improving the algorithm's ability to escape local traps and find feasible solutions.

[0060] In an exemplary embodiment, bottleneck modules are determined based on the optimal layout state and the bottleneck scores of each module. Specifically, this involves: determining the congestion layer based on the optimal layout state; calculating the bottleneck score of each module in the congestion layer; sorting the bottleneck scores of each module; and identifying the module that meets a preset score threshold as the bottleneck module. The specific steps include the following: S401, after obtaining the optimal layout state, the first step is to determine the congestion layer from the 3D stacked structure. The identification of the congestion layer is based on a comprehensive evaluation of the overflow amount of each layer's profile. This involves traversing all device layers and obtaining the lateral profile overflow amount of each layer. and longitudinal profile overflow To account for both unidirectional extreme overflow and bidirectional compound overflow, a lexicographical comparison strategy is used to determine the congestion layer number. The calculation formula is as follows: Among them, the first term of the tuple Prioritize matching the most severe overflow case in one direction, the second item Used to distinguish layers with a higher overall overflow level when the first item is the same. Identify congested layers. Then, further comparisons are made of this congestion layer. lateral overflow With longitudinal overflow :like If the direction of overflow is determined to be horizontal, then the dominant overflow direction is determined to be vertical; otherwise, it is determined to be vertical. This step transforms the global feasibility stagnation signal into specific local repair targets, ensuring that subsequent bottleneck identification has clear directional guidance.

[0061] S402, such as Figure 3 As shown, residual overflows in fixed-profile 3D layout planning are usually not caused by isolated individual modules, but rather by local relative order structures within the congestion layer. For example... Figure 3 As shown in (a), the diagram contains two layers, Tier 1 and Tier 2, with multiple modules such as M1, M2, and M3 distributed within each layer. Fixed outlines are marked to define the deployable areas of each layer. In the optimal layout state, due to the strict constraints of the fixed outlines, residual overflow is usually concentrated within a certain congestion layer (marked as the overflow area in the diagram). This overflow is not caused by a single isolated module, but is supported by the local relative order structure of multiple modules within that layer. Therefore, this application first determines the bottleneck core module within the congestion layer based on bottleneck scoring (or sorting rules, threshold rules, classification rules). This module is the key obstacle restricting the feasibility of the current layout.

[0062] Specifically, after determining the congestion layer and the dominant overflow direction, a bottleneck score is calculated for each module within the congestion layer. In this embodiment, the bottleneck score... The calculation is performed using a multi-factor weighted model, as shown in the following formula: in, Represents the boundary pressure term, used to characterize the module. The degree of correlation with violations of fixed contour boundaries. Specifically, this factor is higher if the module is located on the critical path that causes the contour to exceed limits, or if its position directly determines the used width / height of the current layer. This factor ensures that the selected bottleneck module is indeed the geometric root cause of the overflow, rather than simply a large, irrelevant module.

[0063] This represents the contribution item in the dominant direction, used to characterize the module. The effect of size occupancy in the dominant overflow direction. For example, when the dominant overflow direction is horizontal, this factor is proportional to the width of the module; when the dominant overflow direction is vertical, it is proportional to the height of the module. The significance of introducing this factor is to guide the repair algorithm to prioritize the processing of modules that occupy resources in the direction, thereby increasing the marginal contribution rate of a single repair operation to reducing the amount of contour overflow.

[0064] The module mobility term characterizes the degree of flexibility in re-inserting a module into a candidate layer or position. This factor is typically inversely proportional to the module's area or related to the cross-layer connectivity complexity of the net to which the module belongs. Modules with smaller areas or simpler connectivity scores higher. This design reflects considerations of repair feasibility: selecting a module that is easy to relocate as a bottleneck for removal ensures a higher success rate for local reconfiguration than selecting a large module that is difficult to place.

[0065] This represents a penalty term for large module disturbances, used to reduce the possibility of excessive damage to the existing structure. This term measures the degree to which removing a module might disrupt the existing layout structure, thus avoiding excessive structural disturbances during local repairs. This is because in 3D layout planning, the location of large modules often has far-reaching consequences; blindly removing them could lead to a significant increase in line length or a surge in TSV requirements. By suppressing the misselection of large modules through the penalty term, existing interconnect quality can be protected while pursuing outline feasibility.

[0066] , , and These are the weighting coefficients for the four items mentioned above, which can be configured according to actual needs. For example, they can be appropriately increased in the initial stage of the search. To encourage exploration, the search intensity is increased in the later stages. and To strengthen the precise crackdown on spillover.

[0067] S403, after calculating the bottleneck scores of all modules within the congestion layer, these scores are sorted according to a ranking rule (e.g., descending order). Bottleneck modules are determined based on threshold or classification rules; for example, modules with high rankings and scores higher than a preset score threshold are identified as bottleneck modules. It should be understood that the preset score threshold can be a fixed value or a dynamically calculated statistical value (such as the average score plus standard deviation, or Top-K percentage). By marking these structural nodes that truly cause overflow as bottlenecks, this embodiment provides high-quality input for subsequent determination of accompanying modules and local reconstruction, fundamentally improving the breakthrough capability of fixed contour layout planning in a stagnant state.

[0068] For example, such as Figure 3 As shown in (b), after identifying the bottleneck core module, its strongly related companion modules are further identified based on their relative order within the layer and the tightness of their interconnection coupling with surrounding modules. Subsequently, the bottleneck core module and its companion modules are removed from the current optimal layout state, forming a locally disrupted set. At this point, other modules remain unchanged in the diagram, while the original overflow area is removed, thus avoiding a complete disturbance to the global layout structure. The Core region in the diagram represents the unaffected core layout area.

[0069] In an exemplary embodiment, based on the intra-layer relative representation of the bottleneck module, modules within a preset distance of the bottleneck module are determined as accompanying modules, specifically: After identifying bottleneck modules through bottleneck scoring, instead of directly removing and repairing these individual modules, we further search for accompanying modules based on the topological structure represented by the relative order within the layer. It is important to emphasize that the preset distance in this application specifically refers to the topological proximity within this discrete data structure represented by the relative order within the layer, rather than the geometric Euclidean distance between the center points or edges of the modules on the physical layout. This is because in the fixed contour layout planning of 3D integrated circuits, the root cause of contour overflow is often not the excessive size of a single module, but rather the compact span or critical constraint chain formed by a group of modules under a specific topological order. If only the geometrically largest or highest-scoring bottleneck module is removed, while its topological neighbors maintain their original relative order, these remaining modules are highly likely to re-form similar constraint structures during subsequent reconstruction, leading to a rapid recovery of the overflow problem and failure of the repair. Therefore, by including topologically adjacent modules as accompanying modules in the repair set, we can fundamentally sever the local constraint chains that maintain the poor layout structure, significantly improving the success rate of the repair.

[0070] Taking the relative order representation within a layer as an example, using sequence pairs, the layout state of each layer consists of two permutations: a positive sequence and a negative sequence. When determining the accompanying module, first consider the positive sequence in the congestion layer. and negative sequences The bottleneck module's index position is located. Then, using this index position as the center, predecessor and successor modules within a preset distance range are searched forward and backward. For example, if the preset distance is set to k, all modules in the positive sequence whose absolute difference between their index value and the bottleneck module's index value is less than or equal to k, and modules in the negative sequence that meet the same condition, are all candidate companion modules. The final set of companion modules is determined. Typically, it is the union of the positive sequence candidate set and the negative sequence candidate set, and the specific configuration can be adjusted according to the aggressiveness of the repair strategy. Then, it represents the local destruction set. It can be represented as: in, This represents the set of bottleneck modules.

[0071] It should be understood that although the above examples are described in detail using sequence pairs, the technical solutions of this application are also applicable to other relative order representations within layers, and the definition of the preset distance is adapted accordingly. For example, when using B... When represented as a tree, the accompanying module can be the parent, child, or sibling node of the bottleneck module in the tree structure, because these nodes directly determine their left-right or top-bottom adjacent relationships during the decoding process. When represented as a constraint graph, the accompanying module can be a predecessor or successor node directly connected to the bottleneck module in the horizontal or vertical constraint graph, or an adjacent node located on the same critical path that causes the contour to exceed the limit. Regardless of the specific representation used, the core logic is to identify and remove those module groups that are tightly coupled in the topology and jointly maintain the current overflow state.

[0072] Furthermore, the specific value of the preset distance is not fixed and can be dynamically adjusted based on the design scale, the total number of modules, or the convergence status of the current search phase. In the early stages of the search or when the number of modules is large, the preset distance can be appropriately increased to expand the local damage range and enhance the ability to escape local minima. In the later stages of the search or when the number of modules is small, the preset distance can be decreased to avoid excessive damage to existing high-quality interconnect structures. Through this accompanying module determination mechanism based on topological proximity, this embodiment achieves a shift from single-point repair to structured repair, enabling local reconstruction operations to precisely target the structural root causes of feasibility stagnation. While ensuring the effectiveness of the repair, it maximizes the preservation of layout stability and interconnect quality in non-overflow areas.

[0073] In an exemplary embodiment, bottleneck modules and accompanying modules are removed from the optimal layout state, and a local layout reconstruction is performed using a local search algorithm to output the optimal repair state. Specifically, this involves: removing all bottleneck modules and all accompanying modules from the optimal layout state to obtain the current layout state; inserting all bottleneck modules and all accompanying modules into the current layout state through a local reconstruction search to output candidate repair states; calculating the repair evaluation key of the candidate repair states; and if the repair evaluation key meets a preset criterion, using the candidate repair state as the current layout state to continue the local reconstruction search until the global search termination condition is met, at which point the optimal repair state is output. Figure 3As shown in (c), after removing the localized destruction set, the vacated blank area and adjacent space are locally rearranged. The bottleneck core module and its companion modules are inserted back into Tier 1, Tier 2, and adjacent layers with a new layer allocation, orientation, and relative order (M1, M2, and M3 are redistributed in the figure). During the reconstruction process, under the premise of strictly satisfying the fixed contour constraints of each layer, the conflicts of the original overflow area are eliminated first, while also taking into account the optimization of interconnect length and interlayer vias. Ultimately, the inserted structure no longer has overflow areas, the module distribution within the fixed contour is more uniform, and other modules and the Core area maintain their original structure, thus achieving a feasible and effective repair with a lower computational cost.

[0074] Specifically, during this step, a local repair loop, independent of the global main search loop, is constructed. This loop is not a simple post-processing legitimization operation, but rather a dynamic intervention mechanism in the global optimization process, designed to guide the search out of the feasibility stagnation region through structural disruption and reconstruction. Specifically, it includes the following steps: S501, Remove all bottleneck modules and all accompanying modules in the optimal layout state to obtain the current layout state.

[0075] Specifically, firstly, based on a defined set of local destructions, a removal operation is performed from the currently recorded optimal layout state. This operation not only erases module coordinates at the geometric level, but more importantly, it removes the relative order representation within the layer (such as sequence pairs, B...). Remove the corresponding topological nodes from the tree or constraint graph. For example, when using sequence pairs, remove all module identifiers belonging to the local destruction set from both the positive and negative sequences, while maintaining the original relative order of the remaining modules in the sequence. The resulting current layout state is an intermediate state with several topological holes, denoted as the current layout state. It retains the existing layout structure on non-congested areas and non-critical paths, releasing only the resource space occupied by the local constraint chains that caused the overflow. Compared to a complete reset, this partial deconstruction strategy can maximize the inheritance of high-quality interconnections and layer allocation results accumulated in the previous search, reducing the blindness of the repair process.

[0076] S502 inserts all bottleneck modules and all accompanying modules into the current layout state through local reconstruction search, and outputs candidate repair states.

[0077] Specifically, all modules in the locally damaged set are treated as the insertion set, and a local reconstruction search algorithm is used to re-insert them into the current layout state. The search space of the local reconstruction search is limited to the insertion set, and the search content includes: the target layer assignment of each module, the module orientation selection, and the insertion position in the relative order representation within the layer. Each complete re-insertion combination generates a candidate repair state.

[0078] Local refactoring search involves traversing multiple possible combinations, including attempting to put the module back into its original layer or migrate it to another low-stress layer, adjusting the module's orientation, and inserting it at different index positions represented by relative order within the layer. Each completed re-insertion combination generates a candidate repair state.

[0079] Optionally, the local reconstruction search algorithm can employ various strategies such as bundle search, greedy re-insertion, and candidate queue search. Its core objective is to explore as many potential solutions as possible that can eliminate contour overflow without severely compromising interconnect quality within a limited computational budget. Since incremental insertion is performed on a fixed background layout, the evaluation efficiency of this process is much higher than that of full rearrangement, making it possible to evaluate a large number of candidate solutions in a short time.

[0080] S503, calculate the repair evaluation key of the candidate repair state; if the repair evaluation key of the candidate repair state is better than the repair evaluation key of the current layout state, then take the candidate repair state as the current layout state and continue the local reconstruction search, and output the optimal repair state.

[0081] For example, taking beam search as an example, for each generated candidate repair state, its repair evaluation key is calculated. The repair evaluation key is calculated as follows: in, A flag indicating whether a candidate state is infeasible; The combination of feasibility indicators is expressed as follows: ; Indicates the normalized line length. This represents the normalized estimate of the through-silicon via (TSV) demand. This indicates the weight of the estimated demand for through-silicon vias. This represents the scalar objective function in the search framework and serves as the tiebreaker.

[0082] The repair evaluation key is a multi-dimensional, ordered sequence of evaluation metrics designed with feasibility as the absolute priority. Specifically, the repair evaluation key first examines whether the candidate state meets the fixed profile constraints (or the degree of improvement in overflow). Only when the feasibility metrics meet or exceed the current state are further compared with interconnect quality metrics such as line length and through-silicon via (TSV) requirement estimates. This lexicographical comparison mechanism ensures that the repair process will not sacrifice hard-won profile feasibility in pursuit of line length optimization, nor will it cause the search to oscillate ineffectively within the infeasible region by accepting a state that still overflows.

[0083] When the repair evaluation key of a candidate repair state is better than that of the current layout state, the candidate repair state is accepted as the new current layout state, and the local reconstruction search continues until the optimal repair state is found. This step is a key technical feature that distinguishes this application from traditional post-processing legitimization. Traditional methods usually correct the final result only after the search is completed, and the correction result cannot reflect the impact on the previous search trajectory; while this application uses the repaired state as a new starting point for the search, allowing subsequent searches to continue exploring based on the new layout state.

[0084] In an exemplary embodiment, when the optimal repair state meets the preset acceptance criteria, the optimal repair state is used as the current layout state to continue the global search; otherwise, the optimal layout state is used as the current layout state to continue the global search until all search conditions are met, and the three-dimensional layout planning result is output.

[0085] Termination conditions may include, but are not limited to: reaching the preset time budget, reaching the maximum number of iterations, the global maximum profile overflow falling below the preset feasibility tolerance, or the objective function not showing substantial improvement within a certain number of consecutive rounds. When the search terminates, the final 3D layout planning result is output. The output includes the final layer number, planar coordinates, orientation information, and key indicators such as the used width, used height, profile overflow, bus length, and total TSV demand estimate for each module.

[0086] Optionally, the preset acceptance criterion is that the repair evaluation key of the optimal repair state is better than the repair evaluation key of the optimal layout state.

[0087] For example, when the global search uses the annealing algorithm, in each iteration step, a random perturbation operation is applied to the current layout state to generate candidate layout states. The types of random perturbation operations include intra-layer module swapping, intra-layer module insertion, module rotation, inter-layer module movement, and inter-layer module swapping. For the generated candidate layout states, they are first decoded using a compact layout algorithm based on their intra-layer relative order representation to obtain the actual planar coordinates of each module within the corresponding layer; the compact layout algorithm uses the longest path method. Then, based on the decoded planar coordinates, the contour overflow amount, half-perimeter line length, and estimated through-silicon via (TSV) requirements of the candidate states are calculated, and the global maximum contour overflow amount and optimal contour overflow improvement margin are determined accordingly. During the state acceptance determination process, when a new state... objective function Not greater than the current state objective function When, accept the new state; when Greater than When accepting a new state, the expression for the acceptance probability is: in, This is the current temperature.

[0088] The objective function can be based primarily on contour overflow, with interconnect or layer equalization terms added as auxiliary terms. For example, the objective function can be expressed as: .

[0089] The objective function, weights, and temperature scheduling described above are all optional implementation methods and do not constitute a limitation on the scope of protection of this application.

[0090] When the search termination condition is met, the 3D layout planning results are output. The search termination condition may include meeting the time budget, reaching the maximum number of iterations, reaching the target feasibility tolerance, or no further improvement or satisfaction of user-defined quality requirements within a preset number of iterations. The output results may include the layer number, planar coordinates, orientation, width and height used for each layer, profile overflow for each layer, global maximum profile overflow, total profile overflow, line length, and estimated through-silicon via (TSV) requirements for each module.

[0091] Optionally, local reconstruction search algorithms include bundle search, greedy re-insertion search, candidate queue search, dynamic programming search, local enumeration search, and combinations thereof.

[0092] Specifically, when performing step S502 to reinsert the bottleneck module and the accompanying module into the current layout state, the above-mentioned multiple search strategies can be flexibly selected or combined according to the design scale, the size of the destruction set and the remaining computational budget, so as to obtain the candidate repair state with the best quality within a limited time.

[0093] As a preferred implementation, local reconstruction search employs bundle search. Bundle search is a heuristic graph search algorithm that achieves a good balance between the breadth of the solution space exploration and computational resource consumption. When applying bundle search for local reconstruction, the order of modules to be inserted is first determined, which can be based on descending order of module area, descending order of bottleneck score, or descending order of network connectivity. Subsequently, the algorithm maintains a candidate state list of fixed size K, called the bundle width. In each insertion stage, for each subset of candidate states in the current list, all possible next insertion actions are generated (including selecting the target layer, target orientation, and insertion position in the relative order representation within the layer), thereby expanding a batch of new intermediate candidate states. Next, the repair evaluation key of each new intermediate candidate state is calculated, and only the top K states with the best repair evaluation keys are retained for the next stage of expansion, while the remaining states are pruned and discarded. This process continues iterating until all modules in the locally damaged set have been successfully inserted. By adjusting the beam width K, the thoroughness of the search and its runtime can be dynamically controlled: a larger K value covers more potential solution paths, increasing the probability of finding a globally better repair solution, but it increases memory usage and computation time; a smaller K value accelerates convergence and is suitable for scenarios with high real-time requirements. The advantage of beam search lies in its avoidance of the short-sightedness of greedy strategies and its overcoming of the combinatorial explosion problem of full enumeration, making it particularly suitable for handling medium-sized local damage set repair tasks.

[0094] As an alternative implementation, local reconstruction search can employ a greedy re-insertion search. In this mode, modules to be inserted are processed sequentially according to a preset order. For each module, all legal candidate insertion positions are traversed, the corresponding repair evaluation key is calculated, and the position with the best current evaluation is immediately selected for insertion, without backtracking to modify the positions of already inserted modules. The greedy re-insertion search has the lowest computational complexity and can generate a feasible candidate repair state extremely quickly. Although its results may not be as refined as bundle search or global optimization algorithms, it can quickly provide a baseline repair solution in the early stages of feasibility stagnation or when the corrupted set contains a large number of small modules, or serve as the initial starting point for other complex search algorithms.

[0095] In other embodiments, local reconstruction search can also employ candidate queue search. This approach maintains a priority queue, where elements are partially completed candidate repair states, with priority determined by a repair evaluation key. Each time, the best-rated state is retrieved from the head of the queue for expansion, and the generated new state is inserted into the corresponding position in the queue according to its evaluation key. Unlike bundle search, candidate queue search does not limit the number of expansions at each level, but rather globally prioritizes exploring the most promising paths. This mechanism is similar to best-first search, enabling faster approximation of high-quality solutions, but in the worst case, the queue length can grow significantly. Therefore, it is usually necessary to use a queue length cap or state access records to prevent memory overflow.

[0096] Furthermore, when strong topological constraints or interconnection dependencies exist between modules in a local destruction set, dynamic programming can be used for local reconstruction search. The re-insertion process is modeled as a multi-stage decision problem, defining the state as the subset of inserted modules and their topological configuration in the current layout state. The state transition cost is the sum of the contour overflow increment introduced by the new module and the interconnection cost increment. The optimal transition path is solved through bottom-up or memoized recursion, ultimately obtaining the insertion sequence and position combination that optimizes the overall repair evaluation key. Dynamic programming search can guarantee finding the theoretically optimal solution for a given module order, but its state space grows exponentially with the number of modules, thus it is only suitable for cases where the destruction set is small (e.g., less than 6 modules).

[0097] For extremely small sets of locally damaged components, local reconstruction search can also employ Local Enumeration Search. This method exhaustively enumerates all legal combinations of candidate layers, candidate orientations, and candidate insertion positions for all modules to be inserted, calculates the repair evaluation key for each, and selects the optimal one. While this method involves the largest computational load, it ensures that no possible repair scheme is overlooked, thus achieving absolutely optimal local repair at the microscopic level. In practical engineering, Local Enumeration Search is often used as a supplement to Bundle Search or Dynamic Programming Search, automatically switching to and activating when the number of damaged components falls below a preset threshold (e.g., 3).

[0098] It should be understood that the various search algorithms mentioned above are not mutually exclusive and can be combined and used according to actual working conditions. For example, an initial candidate repair state can be quickly generated through a greedy re-insertion search, and then this state can be used as a seed to start a bundle search for fine-tuning; or in the later stages of the bundle search, a local enumeration search can be switched to the remaining few uninserted modules to ensure the quality of the finalization. This adaptive algorithm combination strategy enables this application to maintain efficient and robust local repair capabilities under different design constraints and resource conditions, thereby effectively supporting the overall convergence performance of fixed contour layout planning for 3D integrated circuits.

[0099] In one exemplary embodiment, the specific construction method of the repair evaluation key is further described in detail. Optionally, the repair evaluation key is described as follows: in, Indicates the repair rating key; A flag indicating whether a candidate state is infeasible; This represents a combination of feasibility indicators; Indicates line length. This represents the estimated demand for through-silicon vias. This indicates the weight of the estimated demand for through-silicon vias. This represents the scalar objective function in the local reconstruction search.

[0100] Specifically, fix the rating button It is an ordered tuple consisting of four components. Its core design lies in establishing a strict priority order for multi-objective optimization through lexicographical comparison. Unlike traditional weighted summation evaluation functions, the lexicographical comparison mechanism ensures that the quality of high-priority components completely dominates the sorting result; only when high-priority components are equal are lower-priority components compared sequentially. This mathematical construction fundamentally guarantees the absolute priority of fixed contour constraints in the local reconstruction and repair process, effectively avoiding the risk that improper adjustment of weight parameters might lead to the algorithm sacrificing contour feasibility to optimize line length or the number of through-silicon vias (TSVs).

[0101] First component This flag indicates whether a candidate state is infeasible. In practice, this flag is typically a Boolean variable with a value of 0 or 1. When the horizontal or vertical contour overflow of any layer in the candidate repair state exceeds the preset feasibility tolerance, Setting it to 1 indicates that the state is infeasible; otherwise, it is set to 0. Because Located at the beginning of the tuple, any feasible candidate state ( During the sorting process, all will be unconditionally preferred over any infeasible candidate state. This mechanism is equivalent to establishing a hard filter in the search space, forcing the local reconstruction search algorithm to prioritize exploring solution regions that satisfy fixed contour constraints, and only as a last resort to retaining the state with the minimum overflow as a transition when no feasible solution can be found.

[0102] Second component This is a combination of feasibility indicators used to further quantify the quality of a candidate profile when all candidate states are feasible or all are infeasible. = ,in This represents the global maximum profile overflow. This indicates the total outline overflow. When comparing, first compare... If they are the same, then compare them. This layered refinement design enables the algorithm to distinguish between different violation patterns, such as severe overflow in a single layer and slight overflow in multiple layers, guiding the repair process towards eliminating the worst-case violation. When the candidate state is fully feasible (i.e., all overflows are zero), Once the theoretical optimal value is reached, the comparison logic automatically moves on to the next component.

[0103] The third component The interconnect quality cost of the candidate repair states is characterized. The normalized wire length is usually calculated using the Half-Perimeter Wirelength (HPWL) model and then divided by the initial wire length or the theoretical lower bound. This represents the normalized estimate of the through-silicon via (TSV) requirement, which has also been normalized to eliminate the significant difference in magnitude between the TSV and the line length. This represents the weight of the estimated through-silicon via (TSV) requirement, reflecting the manufacturing cost or parasitic effect of TSV relative to line length under a specific process. Linearly weighting both into a single scalar value simplifies the comparison while retaining the comprehensive optimization capability for interconnect performance under contour constraints. It should be understood that the normalized baseline value and weights... It can be configured according to specific process nodes and design rules, and this application does not limit it.

[0104] The fourth component This represents the scalar objective function in the local reconstruction search, serving as a tie-breaker. Tie-breakers occur when two candidate repair states are identical in the first three components (e.g., both are feasible solutions with the same interconnection cost). It provides the final basis for distinction. It can be a comprehensive objective function used in a global search framework, or other auxiliary metrics (such as power density, thermal distribution uniformity, or module dispersion). (Introduction) The component ensures that the repair evaluation key can generate a total order relation under any circumstances, avoiding uncertainty in search decisions due to unequal evaluation results, thereby improving the stability and reproducibility of the algorithm execution.

[0105] Through the aforementioned four-tuple structure of the repair evaluation key, this embodiment constructs a hierarchical and logically rigorous state evaluation system. In each step of the local reconstruction search, candidate states are sorted and pruned based on this evaluation key. This evaluation system minimizes interconnect overhead while ensuring strict adherence to chip area budget and packaging constraints. Compared to the common single scalar weighted evaluation method in existing technologies, the repair evaluation key provided in this application can more robustly handle multi-objective conflict problems in high-utilization scenarios, significantly improving the success rate of bottleneck repair and the overall quality of the final layout planning results.

[0106] Based on the same inventive concept, this application also provides a system for implementing the aforementioned three-dimensional integrated circuit fixed contour layout planning system. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations of one or more embodiments of the three-dimensional integrated circuit fixed contour layout planning system provided below can be found in the limitations of the three-dimensional integrated circuit fixed contour layout planning method described above, and will not be repeated here.

[0107] In one exemplary embodiment, a three-dimensional integrated circuit fixed contour layout planning system is provided, comprising: The data acquisition module acquires the module size information, mesh information, layer number information, and fixed contour information of each layer of the 3D integrated circuit. The three-dimensional state construction module constructs a three-dimensional layout planning state based on the module size information, mesh information, layer number information, and fixed contour information of each layer; the three-dimensional layout planning state includes module layer allocation, module orientation, and relative order representation within layers. The global search module, based on the module layer allocation, module orientation and relative order representation within the layer, performs a global search algorithm to search the three-dimensional layout planning state and determines the layout state when feasibility stalls as the optimal layout state. The local damage determination module, based on the optimal layout state, determines the bottleneck module according to the bottleneck score of each module; and determines the accompanying module according to the bottleneck module. The local reconstruction and repair module removes the bottleneck module and the accompanying module in the optimal layout state, and performs local layout reconstruction through a local reconstruction search algorithm to output the optimal repair state. The result output module, when the optimal repair state meets the preset acceptance criteria, uses the optimal repair state as the current layout state to continue the global search and outputs the 3D layout planning result; otherwise, it uses the optimal layout state as the current layout state to continue the global search and outputs the 3D layout planning result.

[0108] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 4 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network. When executed by the processor, the computer program implements a three-dimensional integrated circuit fixed contour layout planning method.

[0109] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0110] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0111] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0112] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0113] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0114] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0115] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for planning the fixed contour layout of a three-dimensional integrated circuit, characterized in that, The three-dimensional integrated circuit fixed contour layout planning method includes: Obtain module size information, mesh information, layer number information, and fixed contour information of each layer of a 3D integrated circuit; A three-dimensional layout planning state is constructed based on the module size information, mesh information, layer number information, and fixed contour information of each layer; the three-dimensional layout planning state includes module layer allocation, module orientation, and relative order representation within layers; Based on the module layer allocation, module orientation, and relative order representation within the layer, a global search algorithm is used to perform a global search on the 3D layout planning state, and the layout state at which feasibility stall occurs is determined as the optimal layout state. Based on the optimal layout state, bottleneck modules are determined according to the bottleneck scores of each module; and accompanying modules are determined according to the bottleneck modules. In the optimal layout state, the bottleneck module and the accompanying module are removed, and the local layout is reconstructed through a local reconstruction search algorithm to output the optimal repair state. When the optimal repair state meets the preset acceptance criteria, the global search continues with the optimal repair state as the current layout state, and the 3D layout planning result is output; otherwise, the global search continues with the optimal layout state as the current layout state, and the 3D layout planning result is output.

2. The three-dimensional integrated circuit fixed contour layout planning method according to claim 1, characterized in that, The intra-layer relative order representation includes sequence pair representation, B... -Tree representation, constraint graph representation, or equivalent representation that can characterize the relative positional relationships of modules at the same level.

3. The three-dimensional integrated circuit fixed contour layout planning method according to claim 1, characterized in that, A global search algorithm is used to perform a global search on the 3D layout planning state, and the layout state at which feasibility stall occurs is determined as the optimal layout state. Specifically: The 3D layout planning state is globally searched using a global search algorithm. In each iteration of the global search algorithm, the following steps are performed: Based on the module layer allocation, module orientation, and relative order within the layer, the modules of each layer are arranged compactly to obtain the coordinates of each module, the width of each layer, and the height of each layer. Based on the coordinates of each module, the width and height of each layer, calculate the outline overflow of each layer, the global maximum outline overflow, the total outline overflow, the line length and the estimated value of the through-silicon via requirements. Based on the estimated values ​​of each layer's outline overflow, the global maximum outline overflow, the total outline overflow, the line length, and the via requirements, determine whether a feasibility stagnation state has occurred. If a feasibility stagnation state has occurred, output the optimal layout state; otherwise, continue the global search.

4. The three-dimensional integrated circuit fixed contour layout planning method according to claim 1, characterized in that, Based on the optimal layout state, the bottleneck modules are determined according to the bottleneck scores of each module, specifically as follows: Based on the optimal layout state, the congestion layer is determined; Calculate the bottleneck score for each module in the congestion layer; The bottleneck scores of each module are sorted, and the modules that meet the preset score threshold are identified as bottleneck modules.

5. The three-dimensional integrated circuit fixed contour layout planning method according to claim 1, characterized in that, Based on the bottleneck module, the accompanying module is determined as follows: Based on the relative order of the bottleneck modules within the layer, the modules within a preset distance of the bottleneck module are identified as accompanying modules.

6. The three-dimensional integrated circuit fixed contour layout planning method according to claim 1, characterized in that, In the optimal layout state, the bottleneck module and the accompanying module are removed, and a local layout reconstruction is performed to output the optimal repair state, specifically: Remove all bottleneck modules and all accompanying modules from the optimal layout state to obtain the current layout state; Insert all bottleneck modules and all accompanying modules into the current layout state using a local reconstruction search algorithm, and output candidate repair states; Calculate the repair evaluation key for the candidate repair states; If the repair evaluation key of the candidate repair state is better than the repair evaluation key of the current layout state, then the candidate repair state is used as the current layout state to continue the local reconstruction search, and the optimal repair state is output.

7. The three-dimensional integrated circuit fixed contour layout planning method according to claim 6, characterized in that, The local reconstruction search includes bundle search, greedy re-insertion search, candidate queue search, dynamic programming search, local enumeration search, and combinations thereof.

8. The three-dimensional integrated circuit fixed contour layout planning method according to claim 6, characterized in that, The repair evaluation key is described as follows: in, Indicates the repair rating key; A flag indicating whether a candidate state is infeasible; This represents a combination of feasibility indicators; Indicates line length. This represents the estimated demand for through-silicon vias. This indicates the weight of the estimated demand for through-silicon vias. This represents the scalar objective function in the local reconstruction search.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the three-dimensional integrated circuit fixed contour layout planning method as described in any one of claims 1-8.

10. A three-dimensional integrated circuit fixed contour layout planning system, characterized in that, The three-dimensional integrated circuit fixed contour layout planning system includes: The data acquisition module acquires the module size information, mesh information, layer number information, and fixed contour information of each layer of the 3D integrated circuit. The three-dimensional state construction module constructs a three-dimensional layout planning state based on the module size information, mesh information, layer number information, and fixed contour information of each layer; the three-dimensional layout planning state includes module layer allocation, module orientation, and relative order representation within layers. The global search module, based on the module layer allocation, module orientation and relative order representation within the layer, performs a global search algorithm to search the three-dimensional layout planning state and determines the layout state when feasibility stalls as the optimal layout state. The local damage determination module, based on the optimal layout state, determines the bottleneck module according to the bottleneck score of each module; and determines the accompanying module according to the bottleneck module. The local reconstruction and repair module removes the bottleneck module and the accompanying module in the optimal layout state, and performs local layout reconstruction through a local reconstruction search algorithm to output the optimal repair state. The result output module, when the optimal repair state meets the preset acceptance criteria, uses the optimal repair state as the current layout state to continue the global search and outputs the 3D layout planning result; otherwise, it uses the optimal layout state as the current layout state to continue the global search and outputs the 3D layout planning result.

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