Semiconductor lead frame and electronic component package layout processing method

Abstract

The application relates to a semiconductor lead frame and an electronic component packaging layout processing method in the field of information technology, and comprises the following steps: obtaining initial position coordinates of a target electronic component and initial thickness parameters of a support substrate; extracting a shear stress field of an interface between the support substrate and packaging material along a thickness direction from a thermal coupling simulation result; determining a target heat dissipation area according to the shear stress field; calculating a stress gradient vector field for the shear stress field in the target heat dissipation area; judging whether a translation amount of the first position coordinates relative to the initial position coordinates exceeds a preset bonding process window; expanding a local heat conduction expansion area to a connection area between a root of the displacement terminal group and a base body of the support substrate; performing power thermal coupling checking on the local heat conduction expansion area according to a bearing current of the displacement terminal group; forming a heat conduction bridge connecting two terminals on the support substrate through thinning processing to obtain a shared conduction path.

Description

Technical Field

[0001] This invention relates to the field of information technology, and in particular to a semiconductor lead frame and electronic component packaging layout processing method. Background Technology

[0002] In electronic packaging, when the chip needs to be moved due to excessive interface shear stress, the functional terminal groups of the pins directly bonded to the chip must be moved synchronously with the same vector displacement to maintain electrical connection. However, the pin displacement will cause the connection area between its root and the lead frame substrate to bear additional mechanical stress concentration.

[0003] To alleviate this stress concentration, a local copper-spreading area needs to be extended at the root of the displacement pin. However, the introduction of the copper-spreading area will change the heat flux density distribution in this area, causing the Joule heat generated by the current carrying the displacement pin, originally designed for signal transmission, to accumulate locally, resulting in a temperature rise exceeding the material's tolerance. If adjacent redundant signal pins are redefined as parallel heat dissipation pins and thermal bridges are formed through half-etching to distribute the heat flux, the geometry and orientation of the thermal bridges will create a new stress gradient concentration zone on the back of the leadframe. This stress gradient concentration zone superimposes with the shear stress field generated at the interface between the leadframe and the molding compound after chip translation, resulting in a complex multi-peak distribution of the stress gradient vector field along the thickness direction at the interface.

[0004] To suppress this stress superposition effect, when constructing a locally thickened boss on the back of the lead frame, the tangent direction of the stress gradient vector field must be used as the contour extension constraint to ensure that the angle between the stress gradient direction at the boundary of the thickened area and the boundary normal direction does not exceed a preset acute angle threshold. This ensures that the boundary of the thickened area is as parallel as possible to the direction of the local stress contour lines, avoiding the generation of secondary stress concentration points at the edge of the boss due to the intersection of the boundary and the stress field direction. Summary of the Invention

[0005] This invention provides a semiconductor lead frame and electronic component packaging layout processing method, mainly including:

[0006] The process involves: obtaining the initial position coordinates of the target electronic component and the initial thickness parameters of the supporting substrate; extracting the shear stress field along the thickness direction at the interface between the supporting substrate and the packaging material from the thermal coupling simulation results; determining the target heat dissipation area based on the shear stress field; calculating the stress gradient vector field for the shear stress field within the target heat dissipation area; extracting features from the stress gradient vector field using a pre-established stress prediction model to obtain the interface shear stress parameters at the contact interface between the target electronic component and the supporting substrate; if the interface shear stress parameters are greater than a preset stress threshold, performing spatial translation processing on the initial position coordinates to obtain the first position coordinates; determining whether the translation amount of the first position coordinates relative to the initial position coordinates exceeds a preset bonding process window; if the translation amount exceeds the bonding process window, performing the same vector displacement along the translation direction on the signal terminal group directly bonded to the target electronic component to obtain the displacement terminal group; extending a local thermally conductive extension area from the connection area between the root of the displacement terminal group and the supporting substrate; and determining the current carrying capacity of the displacement terminal group based on the... Power thermal coupling verification is performed on the local thermally extended area. If the operating temperature rise of a certain displacement terminal exceeds the allowable value, the function of the redundant signal terminal adjacent to the displacement terminal is redefined to obtain a parallel heat dissipation terminal. A thermally conductive bridge connecting the two terminals is formed on the support substrate by thinning, resulting in a distributed conduction path. Based on the distributed conduction path and the direction of the stress gradient vector field, an iterative smooth approximation of the thickened area extension contour is performed using a continuous curvature inscribed circular arc sequence to obtain a smooth thickened contour. A pre-established interface state classification model is used to perform feature fusion processing on the smooth thickened contour and the first position coordinates to output the first interface health status category of the contact interface between the target electronic component and the support substrate. If the first interface health status category belongs to a preset failure status category, a thinning process is performed on the back of the support substrate using a gradient mask pattern based on the smooth thickened contour, and the initial thickness parameter is reduced in size to obtain a first thickness parameter. A target packaging layout scheme is generated based on the first thickness parameter, the distributed conduction path, and the first position coordinates.Further, determining the target heat dissipation area based on the shear stress field includes: obtaining the coordinate position parameters of the target electronic component and the frame thickness of the supporting substrate; extracting thermal coupling data from a preset thermal coupling simulation model based on the coordinate position parameters and the frame thickness; extracting the interface shear stress between the supporting substrate and the packaging material using the thermal coupling data; obtaining the stress gradient distribution based on the rate of change of the interface shear stress along the thickness direction; calculating the packaging deformation displacement by spatial integration of the stress gradient distribution; obtaining the node temperature gradient by multiplying the packaging deformation displacement by a preset material thermal expansion coefficient; calculating the local heat density by multiplying the node temperature gradient by a preset material thermal conductivity; if the local heat density exceeds a preset density threshold, determining the boundary of the heat dissipation area with a risk of interface delamination; obtaining the geometric center point within the boundary of the heat dissipation area; and determining the target heat dissipation area based on the relative distance between the geometric center point and the coordinate position parameters. Furthermore, the step of using a pre-established stress prediction model to extract features from the stress gradient vector field to obtain the interface shear stress parameters of the contact interface between the target electronic component and the supporting substrate includes: acquiring the shear stress field within the target heat dissipation area; calculating the spatial partial derivative of the shear stress field to obtain the stress gradient vector field; extracting the vector divergence and curl distribution based on the stress gradient vector field; constructing a stress tensor matrix based on the vector divergence and curl distribution; performing eigenvalue decomposition on the stress tensor matrix to determine the principal stress axis direction; performing a decomposition operation on the stress gradient vector field along the principal stress axis direction to obtain the normal gradient component and the tangential gradient component; acquiring a pre-established stress prediction model; and extracting features from the normal gradient component and the tangential gradient component using the pre-established stress prediction model to obtain the interface shear stress parameters of the contact interface between the target electronic component and the supporting substrate. Furthermore, determining whether the translation amount of the first position coordinates relative to the initial position coordinates exceeds a preset bonding process window includes: obtaining the initial position coordinates of the target electronic component; if the interface shear stress parameter is greater than a preset stress threshold, performing spatial translation processing on the initial position coordinates to obtain the first position coordinates; calculating a translation variable based on the first position coordinates and the initial position coordinates; determining whether the translation variable exceeds a preset bonding process window; if the translation variable does not exceed the bonding process window, generating an offset vector based on the first position coordinates and the initial position coordinates; obtaining a pre-constructed pad boundary coordinate system; performing a vector superposition operation on the offset vector and the pre-constructed pad boundary coordinate system to obtain superimposed trajectory coordinates; determining an out-of-bounds flag in the pad boundary coordinate system based on the trajectory coordinates; and determining that the translation amount exceeds the bonding process window if the translation variable exceeds the bonding process window.Furthermore, the step of extending a local thermally conductive expansion region from the connection area between the root of the displacement terminal group and the supporting substrate includes: obtaining an initial terminal group corresponding to the target electronic component and an offset direction corresponding to the translation amount; constructing a displacement vector value based on the offset direction and the translation amount; performing a spatial coordinate transformation on the initial terminal group using the displacement vector value to obtain the displacement terminal group; obtaining the root region coordinates of the displacement terminal group and a preset supporting substrate coordinate; calculating the spatial intersection based on the root region coordinates and the supporting substrate coordinate to determine the initial connection area; extracting peripheral contour nodes for the initial connection area; performing nonlinear fitting on the peripheral contour nodes using a support vector regression algorithm to obtain a smooth peripheral trajectory; performing normal extension processing outward based on the smooth peripheral trajectory to obtain an extended peripheral coordinate set; generating the local thermally conductive expansion region based on the extended peripheral coordinate set and the initial connection area; obtaining the area parameter of the local thermally conductive expansion region; if the area parameter is greater than a preset area threshold, performing meshing segmentation on the local thermally conductive expansion region to obtain multiple sub-thermally conductive expansion blocks. Furthermore, the step of forming a thermal bridge connecting the two terminals on the support substrate through thinning to obtain a distributed conduction path includes: obtaining the carrying current of the displacement terminal group and the material thermal resistance parameters of the local thermal expansion area; performing power thermal coupling verification on the local thermal expansion area based on the carrying current and the material thermal resistance parameters to obtain the operating temperature rise of each displacement terminal in the displacement terminal group; if the operating temperature rise of a target displacement terminal is greater than a preset temperature rise tolerance value, extracting a redundant signal terminal adjacent to the target displacement terminal on the support substrate; redefining the function of the redundant signal terminal, modifying the signal transmission attributes of the redundant signal terminal to obtain grounding heat dissipation attributes, and obtaining the parallel heat dissipation terminal; obtaining the spacing parameters between the target displacement terminal and the parallel heat dissipation terminal; calculating the target etching depth and the target bridging width based on the spacing parameters and the operating temperature rise; generating a thinning process trajectory on the support substrate based on the target etching depth and the target bridging width; forming the thermal bridge connecting the target displacement terminal and the parallel heat dissipation terminal through the thinning process trajectory; and determining the distributed conduction path based on the thermal bridge.Furthermore, the iterative smooth approximation of the thickened region's extended contour using a sequence of inscribed circular arcs with continuous curvature to obtain a smoothed thickened contour includes: acquiring the distributed transmission path and the stress gradient vector field; determining the thickened region based on the distributed transmission path; extracting the thickened region boundary; calculating the boundary normal direction of the thickened region boundary; extracting the stress gradient direction at the thickened region boundary based on the stress gradient vector field; calculating the angle between the stress gradient direction and the boundary normal direction; if the angle is greater than a preset acute angle threshold, then the thickened region is smoothed. The thick region boundary is resampled to obtain an updated boundary; the stress field tangent direction at the updated boundary is extracted based on the stress gradient vector field; the updated boundary is extended based on the stress field tangent direction to generate the thickened region extended contour; the contour curvature radius of the thickened region extended contour is calculated; the thickened region extended contour is curve-fitted using a cubic spline interpolation algorithm based on the contour curvature radius to generate the inscribed circular arc sequence; the thickened region extended contour is iteratively smoothed using the inscribed circular arc sequence to obtain the smoothed thickened contour. Furthermore, the step of using a pre-established interface state classification model to perform feature fusion processing on the smoothed thickened contour and the first position coordinates, and outputting the first interface health status category of the contact interface between the target electronic component and the supporting substrate, includes: obtaining the smoothed thickened contour and the first position coordinates; extracting a contour node set based on the smoothed thickened contour; calculating the Euclidean distance between each contour node in the contour node set and the first position coordinates to obtain a node distance sequence; obtaining the node distance sequence; if the maximum distance value in the node distance sequence is greater than a preset distance threshold, performing a truncation operation on the contour node set to obtain a target contour node set; obtaining the target contour node set; performing a dimensionality reduction operation on the target contour node set using a principal component analysis algorithm to obtain a contour principal component vector; obtaining the contour principal component vector and the first position coordinates; performing a vector concatenation operation on the contour principal component vector and the first position coordinates to obtain a joint feature vector; obtaining the joint feature vector; and performing a classification operation on the joint feature vector using a pre-established interface state classification model to output the first interface health status category of the contact interface between the target electronic component and the supporting substrate.Furthermore, the step of performing a classification operation on the joint feature vector using a pre-established interface state classification model to output the first interface health state category of the contact interface between the target electronic component and the supporting substrate includes: acquiring the pre-established interface state classification model; performing feature mapping processing on the joint feature vector through the pre-established interface state classification model to obtain a state classification probability distribution; determining the first interface health state category based on the state classification probability distribution; acquiring the first interface health state category; if the first interface health state category is an abnormal state category, extracting the abnormal dimension index from the joint feature vector; determining the abnormal contact surface region of the target electronic component based on the abnormal dimension index; extracting local stress concentration features for the abnormal contact surface region; performing secondary translation compensation on the first position coordinates based on the local stress concentration features to obtain second position coordinates; updating the first position coordinates based on the second position coordinates and returning to perform the feature fusion processing operation until the first interface health state category is no longer the abnormal state category. Furthermore, the step of performing thinning processing on the back side of the support substrate using a gradient mask pattern based on the smooth thickened contour, and performing size reduction processing on the initial thickness parameter to obtain a first thickness parameter, includes: obtaining the first interface health status category; if the first interface health status category belongs to a preset failure status category, then extracting the smooth thickened contour corresponding to the first interface health status category; performing pattern generation processing on the back side of the support substrate using a random forest algorithm based on the smooth thickened contour, obtaining the gradient mask pattern corresponding to the pattern generation processing; performing the thinning processing based on the gradient mask pattern, obtaining the initial thickness parameter corresponding to the thinning processing; performing a size reduction operation on the initial thickness parameter, obtaining the size reduction amount corresponding to the size reduction operation; generating a boss with a smooth transition edge based on the size reduction amount; obtaining the first thickness parameter corresponding to the boss with a smooth transition edge; obtaining the allocated conduction path and the first position coordinates based on the first thickness parameter; and determining the target packaging layout scheme based on the allocated conduction path and the first position coordinates.

[0007] A semiconductor lead frame includes a base, electronic components and a chip disposed on the base, wherein the electronic components and the chip are manufactured using an electronic component packaging layout processing method for optimized manufacturing.

[0008] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0009] This invention discloses a method for electronic component packaging layout processing. Addressing the problem of shear stress concentration at the interface between the lead frame and molding compound due to thermal coupling during electronic component packaging, leading to bonding failure and heat dissipation bottlenecks, the method extracts the shear stress field along the thickness direction from thermal coupling simulation results, identifies the target heat dissipation area with heat density exceeding a threshold, calculates the stress gradient vector field, and extracts features of the interface shear stress parameters using a pre-established stress prediction model. When the shear stress exceeds the threshold and the positional translation exceeds the bonding process window, a unidirectional vector displacement is performed on the directly bonded pin functional terminal group to form a displacement pin group. Furthermore, a local copper expansion area is extended at the root of the substrate. At the same time, redundant signal pins are introduced for pins with excessive Joule heating, and the pins are redefined as parallel heat dissipation pins. A distributed conduction path is formed by half-etching thermal bridges. Then, with the constraint that the angle between the stress gradient and the boundary normal does not exceed the acute angle threshold, a series of inscribed circular arcs with continuous curvature is used to smoothly approximate the contour of the thickened area, so that the thickening extends along the stress tangent. Finally, the health category is determined by the interface state classification model, and a smooth transition boss is formed by half-etching with a gradient mask. This generates a packaging layout scheme that takes into account stress dissipation, heat flow distribution and bonding reliability, which significantly improves interface reliability and heat dissipation balance. Attached Figure Description

[0010] Figure 1 This is a flowchart of an electronic component packaging layout processing method according to the present invention.

[0011] Figure 2 This is a schematic diagram of an electronic component packaging layout processing method according to the present invention.

[0012] Figure 3 This is another schematic diagram of an electronic component packaging layout processing method according to the present invention.

[0013] Figure 4 This is a schematic diagram of the semiconductor lead frame of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0015] like Figures 1-3 This embodiment of a semiconductor lead frame and electronic component packaging layout processing method may specifically include:

[0016] S101. Obtain the initial position coordinates of the target electronic component and the initial thickness parameters of the lead frame. Extract the shear stress field along the thickness direction of the interface between the lead frame and the molding compound from the thermo-coupling simulation results. Determine the target heat dissipation area with a heat density exceeding a preset density threshold based on the shear stress field.

[0017] The coordinate position parameters of the target electronic component and the frame thickness of the lead frame are obtained. Based on these parameters, thermo-coupling data is extracted from a pre-defined thermo-coupling simulation model. The molding deformation displacement u is calculated by spatial integration of the stress gradient distribution. The dimensionless nodal strain ε is obtained by taking the first partial derivative of u along the thickness direction. The nodal temperature increment ΔT is then calculated by dividing ε by the pre-defined material thermal expansion coefficient α, where α is in 1 / degree Celsius and ΔT is in degrees Celsius. The first partial derivatives of ΔT along both the thickness and in-plane directions are calculated, and the combined modulus is obtained to obtain the nodal temperature gradient G, in degrees Celsius / meter. G is multiplied by the pre-defined material thermal conductivity k according to Fourier's law to calculate the local heat flux density q = k * G, in watts per square meter. When k is taken as a typical value of 150 for silicon-based chips and G is in the range of 1000 to 5000, q falls approximately between 1.5*10^5 and 7.5*10^5. If q exceeds the preset heat flux density threshold of 5*10^5, the node is included in the high-risk set of interface peeling, and the closed contour is extracted along the adjacent high-risk nodes as the boundary of the heat dissipation area with interface peeling risk.

[0018] In one implementation, it is first necessary to obtain the initial position coordinates of the target electronic component and the initial thickness parameters of the lead frame.

[0019] Specifically, the initial position coordinates of the target electronic component are typically provided by package design drawings or 3D geometric models, used to accurately locate the spatial distribution of key structures such as chips, pads, and pins in virtual space. The initial thickness parameters of the leadframe refer to the original geometric thickness of the metal substrate of the leadframe before any thermal deformation or mechanical stress loading occurs. These basic geometric data provide the necessary spatial boundary conditions and structural dimensional references for subsequently building an accurate physical simulation model. Based on the aforementioned basic geometric parameters, the system further imports these parameters into a pre-built finite element analysis environment to conduct thermo-mechanical coupling simulation. Thermo-mechanical coupling simulation is a numerical analysis method that comprehensively considers the interaction between the temperature field and the structural stress field. Its core purpose is to simulate the overall temperature rise caused by the continuous heating of the internal chip in the actual powered-on working state of electronic components, and the resulting thermal expansion and deformation process of the various layers of materials.

[0020] It should be noted that in electronic component packaging structures, lead frames are typically made of highly thermally conductive metals such as copper alloys, while molding compounds are mostly epoxy resin-based composites. These two materials have extremely significant differences in their coefficients of thermal expansion. When the target electronic component is in a heating state, heat is conducted from the chip outwards, causing the temperature of the entire package to rise sharply. Due to the severe mismatch in the coefficients of thermal expansion between the lead frame and the molding compound, they exhibit drastically different expansion or contraction trends at the interface when the temperature changes. This inconsistency in deformation is constrained by the interfacial adhesive forces, thus inducing complex internal stresses at the interface between the lead frame and the molding compound, especially shear stress along the thickness direction. The magnitude and spatial distribution of this shear stress directly reflect the temperature gradient and heat accumulation in the local area.

[0021] For example, extracting the shear stress field along the thickness direction at the interface between the leadframe and the molding compound from the thermo-coupling simulation results is a multi-dimensional physical quantity data analysis process. In specific implementation, the system first filters out all target nodes belonging to the contact interface between the leadframe and the molding compound from the mesh node set of the simulation model. Then, for these target nodes, specific components in the three-dimensional stress tensor are extracted, namely, the shear stress values ​​parallel to the interface and along the thickness direction of the package. By spatially interpolating and smoothing the shear stress values ​​of these discrete nodes, a continuous two-dimensional or three-dimensional stress distribution cloud map, i.e., the shear stress field, is constructed. This stress field accurately records the magnitude of the shear force borne by each tiny region on the interface in the thickness direction, providing extremely reliable mechanical data support for subsequent thermal inversion. After obtaining the high-precision shear stress field...

[0022] Understandably, areas of high stress concentration often correspond to severe thermal expansion mismatch, which is physically driven by the excessively high heat density in that specific area.

[0023] In one possible implementation, a target heat dissipation region with a heat density exceeding a preset density threshold is determined based on the shear stress field.

[0024] Specifically, the system incorporates a stress-to-heat mapping strategy. This strategy, based on the thermal stress constitutive equation in materials mechanics, reverse-engineers the extracted shear stress field into a local heat density distribution at the interface. Heat density characterizes the amount of heat accumulated per unit volume or unit area. The system iterates through each grid region in the shear stress field, calculates its corresponding heat density value, and compares it item by item with a preset density threshold. When the calculated heat density value of a continuous region is greater than or equal to the preset density threshold, the system marks that region as the target heat dissipation area.

[0025] For example, the preset density threshold is a safety limit value calibrated based on physical limit parameters such as the glass transition temperature of the packaging material and the critical stress of interface peeling. Suppose that in the packaging scenario of a high-power power management chip, the system, through the above mapping strategy, discovers that the heat density obtained from the inversion in the central region of the interface between the lead frame and the molding compound directly below the chip reaches an extremely high value, far exceeding the set safety threshold. At this point, this central region is accurately identified as the target heat dissipation area. This means that in subsequent packaging structure optimization design, it is necessary to add heat dissipation vias, adjust the lead frame pattern, or replace the molding compound with a high thermal conductivity one for this specific area to alleviate localized thermal stress concentration. Through the above steps, cross-physics field analysis can be achieved by inferring microscopic heat distribution from macroscopic mechanical response, effectively avoiding the shortcomings of traditional methods that rely solely on temperature field simulation to accurately locate interface failure risk areas, and significantly improving the targeting of heat dissipation design for electronic component packaging.

[0026] S102. Calculate the stress gradient vector field for the shear stress field in the target heat dissipation area, and use a pre-established stress prediction model to extract features from the stress gradient vector field to obtain the interface shear stress parameters of the contact interface between the target electronic component and the lead frame.

[0027] Based on the shear stress field of the target heat dissipation region obtained in S101, 3 to 5 grid layers near the contact interface between the target electronic component and the lead frame are selected as the analysis zone. The stress components within this zone are subjected to first-order partial derivatives along the x, y, and z coordinates to obtain a 3*3 stress gradient tensor field, which is used to characterize the rate of stress change with position near the interface. Eigenvalue decomposition is performed on the stress gradient tensor at each grid point. The eigenvector corresponding to the largest eigenvalue is taken as the principal stress axis direction at that point, and the other two eigenvectors span a tangential plane orthogonal to the principal stress axes. The stress gradient tensor at this point is projected onto the principal stress axis direction to obtain the normal gradient component, and projected onto the tangential plane to obtain the tangential gradient component. The normal component reflects the interface compression and pull-out tendency, while the tangential component reflects the interface slip and displacement tendency. The two types of components are concatenated into a feature vector in grid order and input into a pre-trained stress prediction model for feature extraction and regression. The model adopts a one-dimensional convolutional and fully connected structure. The output layer provides the peak value and mean value of the shear stress along the tangential direction of the contact interface, as well as the slope of the stress gradient along the normal direction of the interface, as interface shear stress parameters. Unlike the macroscopic field-level shear stress output by S101, what is obtained here is a local quantitative index focused on a thin layer of tens of micrometers at the interface, which is used for subsequent assessment of interface failure risk.

[0028] In one implementation, after determining a target heat dissipation area where the heat density exceeds a preset density threshold, the system further calculates the stress gradient vector field for the shear stress field within the target heat dissipation area.

[0029] It is understandable that the shear stress field only reflects the absolute magnitude of the stress at each point on the interface, while the stress gradient vector field can accurately characterize the degree of change of stress in spatial distribution and the direction of the fastest change, which plays a key role in capturing local stress concentration phenomena.

[0030] Specifically, calculating the stress gradient vector field is a spatial differentiation process based on discrete mesh data. The system first extracts the shear stress values ​​and corresponding three-dimensional spatial coordinates of all finite element mesh nodes within the target heat dissipation area. For each central node, the system searches for its topologically adjacent surrounding nodes and uses central difference or forward difference algorithms to calculate the partial derivatives of the shear stress along two orthogonal directions in the interface plane. These partial derivative values ​​reflect the magnitude of the shear stress increment per unit distance. Subsequently, the system combines the partial derivatives in these two orthogonal directions into a two-dimensional vector. The magnitude of this vector represents the steepness of the stress change at that node, i.e., the gradient magnitude, while the direction of the vector points to the spatial orientation where the stress increases most rapidly. By traversing all nodes within the target heat dissipation area and performing the above differentiation calculations, the system constructs a continuous and directional stress gradient vector field. This vector field not only contains static stress distribution information but also reveals the dynamic evolution trend of stress at the interface, providing high-dimensional mechanical characteristic data for subsequent identification of potential interface delamination initiation points. Based on the stress gradient vector field constructed above, the system further employs a pre-established stress prediction model to extract features from the stress gradient vector field. The stress prediction model is a deep learning architecture specifically designed for complex mechanical field data. Its core capability lies in its ability to automatically mine nonlinear mechanical feature patterns highly correlated with interface failure from massive amounts of underlying vector data, thereby avoiding the subjectivity and limitations of traditionally manually set feature thresholds.

[0031] It should be noted that the stress prediction model needs to undergo a rigorous pre-establishment and training process before it can be put into practical application.

[0032] In one possible implementation, the model employs a graph neural network architecture. This is because the finite element mesh of electronic component packaging interfaces typically exhibits an irregular non-Euclidean spatial distribution, and graph neural networks can perfectly adapt to such complex topologies. During the model construction phase, the system first collects a large amount of historical packaging design data under different operating conditions, extracting the corresponding stress gradient vector fields as training samples. For each training sample, the system transforms it into graph-structured data, where the nodes of the graph correspond to the mesh nodes on the interface, the initial feature of the node is the stress gradient vector at that point, and the edges of the graph are established based on the physical connection relationship or spatial distance threshold between mesh nodes. During training, the model continuously aggregates the gradient features of each node and its neighboring nodes through multi-layer graph convolution operations. Specifically, each layer of graph convolution weights and sums the gradient information of surrounding nodes according to the edge weights, updating the central node. This ensures that each node not only contains its own local stress change information but also perceives the stress distribution over a wider area. Through this information transmission mechanism, the model can gradually learn the complex spatial relationships hidden in the stress gradient vector field, such as the morphological characteristics of stress concentration regions and the divergence or convergence patterns of gradient vectors.

[0033] For example, during actual feature extraction, the system inputs the stress gradient vector field of the current target heat dissipation area into the trained stress prediction model. The forward propagation process of the model is the feature extraction process. The input vector field data is first normalized through the model's input layer to eliminate numerical bias caused by different dimensions. Subsequently, the data enters multi-layer graph convolutional hidden layers. In these hidden layers, the model uses pre-learned convolutional kernel weights to perform high-dimensional mapping of the stress gradient vector in the local region.

[0034] For example, when the model detects a highly convergent gradient vector pattern with extremely large magnitudes within a small region, the hidden layer activates specific neurons, encoding this physical phenomenon as a high-dimensional stress singularity feature vector. This feature vector has dimensions ranging from 128 to 512, with the first 64 dimensions encoding the convergence direction and intensity of local gradients, the middle portion encoding the spatial distribution characteristics of the stress concentration region, and subsequent dimensions representing the peak proportion of the gradient magnitudes. The model quantifies the singularity by calculating the ratio of the standard deviation σ to the mean μ of the gradient magnitudes within the target region. A significant stress singularity is considered to exist when σ / μ is greater than 2.5, and a higher ratio corresponds to a greater activation intensity of the peak dimensions in the feature vector. As the network depth increases, the features extracted by the model gradually abstract from local gradient changes to global mechanical response patterns. Finally, through global pooling, the model compresses and fuses the high-dimensional features of all nodes, outputting a comprehensive feature vector that fully characterizes the mechanical state of the target heat dissipation region. This feature vector filters out redundant noise from the original vector field, retaining the core mechanical information that is most crucial for assessing interface reliability.

[0035] Preferably, the system obtains the interfacial shear stress parameters at the contact interface between the target electronic component and the lead frame based on the extracted high-dimensional feature vector. These interfacial shear stress parameters are not simple raw stress values, but comprehensive indicators with clear engineering guidance significance after model analysis.

[0036] For example, these parameters may include the interface delamination risk index, the local maximum shear stress concentration factor, and the proportion of the critical failure area. The interface delamination risk index is calculated as follows: First, regions with stress gradients exceeding 5 MPa / μm are identified as stress abrupt change zones. The spatial proportion w1 = N1 / N0 is obtained by calculating the ratio of the number of mesh nodes N1 to the total number of nodes N0 within these zones. Simultaneously, the stress amplitude ratio w2 = τ1 / τ0 is obtained by extracting the ratio of the average stress amplitude τ1 in the abrupt change zone to the global average stress τ0. The risk index R is calculated as R = 0.6 × w1 + 0.4 × w2, which directly reflects the likelihood of delamination at the contact interface under the current thermal load. The local maximum shear stress concentration factor is calculated by directly extracting stress field data, i.e., the ratio of the peak value of the maximum shear stress to the regional average shear stress, used to accurately locate the weakest points most prone to mechanical failure. By acquiring these in-depth interface shear stress parameters, the system can provide extremely accurate data support for subsequent reliability assessments of the encapsulated structure.

[0037] S103. If the interface shear stress parameter is greater than the preset stress threshold, then perform spatial translation processing on the initial position coordinates to obtain the first position coordinates, and determine whether the translation amount of the first position coordinates relative to the initial position coordinates exceeds the preset bonding process window.

[0038] The initial position coordinates of the target electronic component are obtained. If the interface shear stress parameter is greater than a preset stress threshold, spatial translation is performed on the initial position coordinates to obtain first position coordinates. A translation variable is calculated based on the first position coordinates and the initial position coordinates, and it is determined whether the translation variable exceeds a preset bonding process window. If the translation variable does not exceed the bonding process window, an offset vector is generated based on the first position coordinates and the initial position coordinates. The offset vector is then superimposed with a pre-constructed pad boundary coordinate system to obtain the superimposed trajectory coordinates. An out-of-bounds flag in the pad boundary coordinate system is determined based on the trajectory coordinates.

[0039] After obtaining the interface shear stress parameters at the contact interface between the target electronic component and the lead frame, the system compares the extracted parameters with the stress thresholds pre-stored in the database.

[0040] It should be noted that the preset stress threshold is not a single fixed constant, but a multi-dimensional boundary set comprehensively calibrated based on a large number of historical packaging failure cases and material mechanical property test data. When the value of any one or more of the interface shear stress parameters exceeds the corresponding preset stress threshold, the system determines that the initial mounting position of the target electronic component on the lead frame has an extremely high risk of thermomechanical failure and requires position optimization. In one embodiment, if the interface shear stress parameter is determined to be greater than the preset stress threshold, the system then performs spatial translation processing on the initial position coordinates of the target electronic component.

[0041] Understandably, initial position coordinates typically refer to the absolute coordinates of the component's geometric center in the two-dimensional plane or three-dimensional space of the leadframe in the initial package design drawings. The core purpose of spatial translation processing is to change the contact area between the component's bottom surface and the leadframe by finely adjusting the component's mounting position in physical space, thereby avoiding areas with high local heat concentration or abrupt changes in structural stiffness and redistributing the thermal stress distribution on the interface.

[0042] Specifically, the spatial translation process is a dynamic optimization process based on mechanical feedback. The system first calls the global stress gradient vector field constructed by S102 for the target heat dissipation area. A spherical neighborhood subfield with a radius of 3mm, centered on the initial position coordinates, is extracted as the data source for this optimization. If the initial position of the component is outside the boundary of the target heat dissipation area, the coordinates are first projected along the center direction of the heat dissipation area to within 0.5mm of the nearest field coverage boundary before extraction, thus ensuring that the vector field data is consistent with the spatial range of the positioning area. Subsequently, the system runs a gradient-guided local optimization algorithm within this subfield. This algorithm is a custom algorithm for this scheme, taking the stress value S and gradient vector g of each grid point within the subfield as input and the updated first position coordinates as output. Its core process is to first determine the search direction by reverse gradient in each iteration, and then determine the step size by the stress over-limit difference, until the stress value falls below the threshold or the maximum number of iterations (20) is reached. When determining the translation direction, the system filters out all grid points within the subfield whose stress values ​​exceed the preset threshold S0 = 1.2 MPa. The gradient vectors of these points are inverted, and a weighted sum is calculated using the stress excess of each point as a weight: w_i = (S_i - S0) / sum(S_i - S0). The sum vector is then normalized to obtain the guiding direction for this iteration, ensuring that points farther from the threshold have a greater influence on the direction. When determining the translation step size, the system uses the difference between the current stress value S_c and the threshold S0, ΔS = S_c - S0, as the adaptive criterion. When ΔS is greater than 0.5 MPa, it is identified as an extreme stress singularity point, and a step size L = 0.20 mm is used to quickly move out of the danger zone. When ΔS is between 0.1 MPa and 0.5 MPa, L = 0.08 mm is used for routine adjustments. When ΔS is less than 0.1 MPa, L = 0.02 mm is used for refined convergence, with the upper limit of the step size not exceeding 1 / 10 of the intercept radius. The displacement increment is synthesized by multiplying the aforementioned directional unit vector with the step size scalar. The system then performs coordinate transformation calculations on the initial position coordinates to obtain the updated first position coordinates.

[0043] For example, in some complex asymmetric leadframe designs, the system incorporates a combined rotation-translation operation when performing spatial translation. The system combines the translation vector with a small in-plane rotation angle to perform an affine transformation on the initial position coordinates, obtaining first position coordinates containing position and orientation information. Further, after obtaining the first position coordinates, the system must determine whether the translation amount of these first position coordinates relative to the initial position coordinates exceeds a preset bonding process window. It should be explained that the bonding process window refers to the maximum allowable offset range of the component mounting position during actual microelectronic packaging manufacturing, limited by physical conditions such as the precision of the wire bonding equipment, the maximum stretching radius of the gold or copper wire, and the safe spacing between adjacent components. This window is typically represented as a polygonal or elliptical geometrically constrained area centered on the initial position coordinates. If the component translation amount is too large, exceeding this window, even if the interface shear stress is effectively reduced, subsequent wire bonding processes may be impossible to implement, for example, due to the risk of wire breakage caused by excessively long leads, or short circuit hazards caused by leads crossing other pads.

[0044] Preferably, during the judgment process, the system first calculates the translation variable based on the first position coordinates and the initial position coordinates. This translation variable includes two parts: first, the Euclidean distance d, representing the total displacement; and second, the projected offsets Δx, Δy, and Δz on each coordinate axis, representing the directional components of the translation. The system calculates the Euclidean distance d, where d represents the linear distance between the first position coordinates and the initial position coordinates, and simultaneously extracts the three projected offsets Δx, Δy, and Δz. The system compares the Euclidean distance d with the radius threshold r of the bonding process window, and simultaneously compares the projected offsets Δx, Δy, and Δz with the boundary limits of each coordinate axis direction. If d is less than or equal to r, and all projected offsets are within the boundary limits, the system confirms that the translation is valid and outputs the first position coordinates as the optimized final mounting position. If the translation exceeds the preset bonding process window, the system triggers a boundary penalty mechanism. The specific steps are as follows: First, the system reduces the current translation step size by 0.5. If the reduced step size is less than 0.001 mm, the iteration is terminated and the current optimal position is output. The system calculates the directional component that exceeds the boundary, reduces the offset of that direction by a weight of 0.7, and keeps the offset of the non-boundary direction unchanged. The system recalculates the first position coordinates based on the adjusted offset and performs spatial translation processing and window judgment again. If the boundary constraints cannot be met after 5 consecutive iterations, the system terminates the optimization process and returns the initial position coordinates as the mounting position.

[0045] S104. If the translation amount exceeds the bonding process window, the same vector displacement is performed on the pin functional terminal group directly bonded to the target electronic component along the translation direction to obtain the displacement pin group, and a local copper expansion area is extended in the connection area between the root of the displacement pin group and the lead frame substrate.

[0046] If the translation amount is greater than a preset bonding process window, the initial pin terminal group corresponding to the target electronic component and the offset direction corresponding to the translation amount are obtained. A displacement vector value is constructed based on the offset direction and the translation amount. A spatial coordinate transformation is performed on the initial pin terminal group using the displacement vector value to obtain a displaced pin group. The root region coordinates of the displaced pin group and the preset lead frame body coordinates are obtained. The spatial intersection of the root region coordinates and the lead frame body coordinates is calculated to determine the initial connection area. Outer contour nodes are extracted for the initial connection area. A support vector regression algorithm is used to perform nonlinear fitting on the outer contour nodes to obtain a smooth outer trajectory. A normal extension process is performed outwards based on the smooth outer trajectory to obtain an extended outer coordinate set. A local copper expansion area is generated based on the extended outer coordinate set and the initial connection area. The area parameter of the local copper expansion area is obtained. If the area parameter is greater than a preset area threshold, the local copper expansion area is meshed to obtain multiple sub-copper expansion blocks.

[0047] When the translation of a component exceeds a first threshold of a preset bonding process window, synchronous adjustment of the pin terminals is triggered. This first threshold is set to 100 to 200 micrometers. An initial set of spatial coordinates for several pin functional terminal groups directly electrically connected to the target electronic component is extracted from the packaging design database. The number of pin functional terminal groups is N, where N is a positive integer greater than or equal to 8. The current three-dimensional translation vector of the component is obtained. Using a spatial affine transformation algorithm, this translation vector is precisely mapped to the coordinate set of the aforementioned N pin functional terminal groups, driving these terminals to perform vector displacement calculations along the same spatial direction and distance, thereby generating an updated displacement pin group geometric model in virtual space. The overall displacement of the pin terminals will cause a change in the mechanical conduction path at the interface between their root and the lead frame substrate. The lead frame substrate layer is a two-dimensional vector data layer describing the geometric contour of the lead frame substrate. Local stress field simulation is performed on this interface area, and a mechanical model is established using a finite element mesh reconstruction program. When the calculated maximum principal stress at the root of the displacement pin group exceeds a second threshold, an automatic local copper expansion area generation mechanism is triggered. The second threshold is set to 50 MPa to 80 MPa. A non-uniform rational spline curve algorithm is used to generate the copper pour profile. This algorithm takes the geometric center coordinates of the displacement pin root and the boundary constraints of the lead frame substrate as input and outputs a sequence of control points for a fan-shaped copper pour polygon. Using the geometric center of the root of each displacement pin as a reference point, a fan-shaped copper pour polygon profile with an outward radius of R is dynamically calculated and extended towards the lead frame substrate. R is set to 30 μm to 60 μm. These newly generated fan-shaped copper pour polygon data are then subjected to a two-dimensional Boolean union operation with the original lead frame substrate layer. This seamlessly integrates the expanded local copper pour area into the overall frame manufacturing data package, increasing the physical connection area at the pin root and dispersing concentrated stress.

[0048] S105. Perform power thermal coupling verification on the local copper expansion area according to the carrying current of the displacement pin group. If the Joule temperature rise of a certain displacement pin exceeds the allowable value, redefine the function of the redundant signal pin adjacent to the displacement pin to obtain a parallel heat dissipation pin. Then, form a thermal bridge connecting the two pins on the lead frame by half etching to obtain a distributed conduction path.

[0049] The carrying current of the displacement pin group and the material thermal resistance parameters of the local copper expansion area are obtained. Power thermal coupling verification is performed on the local copper expansion area based on the carrying current and the material thermal resistance parameters to obtain the Joule thermal rise of each displacement pin in the displacement pin group. If the Joule thermal rise of a target displacement pin exceeds a preset allowable temperature rise value, a redundant signal pin adjacent to the target displacement pin is extracted from the lead frame. The redundant signal pin is functionally redefined, modifying its signal transmission attribute to a grounding heat dissipation attribute, resulting in a parallel heat dissipation pin. The spacing parameter between the target displacement pin and the parallel heat dissipation pin is obtained. The target etching depth and target bridging width are calculated based on the spacing parameter and the Joule thermal rise. A semi-etched processing trajectory is generated on the lead frame based on the target etching depth and target bridging width. A thermal bridge connecting the target displacement pin and the parallel heat dissipation pin is formed through the semi-etched processing trajectory, and the thermal bridge is used as a distributed conduction path.

[0050] In one implementation, after expanding the local copper area of ​​the lead frame substrate, the system will further conduct an in-depth analysis of the heat distribution under high power operation.

[0051] Specifically, the system activates the thermal assessment module to ensure that the expanded physical structure does not cause local overheating under electrical loads.

[0052] For example, the system performs power thermal coupling verification on the local copper expansion area based on the carrying current of the displacement pin group. This power thermal coupling verification is a multi-physics collaborative analysis process that integrates electromagnetics and heat transfer, specifically executed in three steps: current parameter extraction, volume heat source density solution, and transient heat conduction simulation. The system first calls the circuit design netlist file generated and stored in the engineering database during the previous layout design stage. This netlist file records the pin number, connection relationship, rated peak current Ip of each pin under full load condition, and fundamental frequency, duty cycle, and harmonic components of the current waveform in the form of structured fields for the target electronic components. The system extracts the Ip and waveform characteristics assigned to each displacement pin according to the pin number index, with a typical value range of 0.5 amps to 5 amps. Subsequently, based on the geometric contour data of the local copper-exposed region, the system discretizes it into a hexahedral mesh with side lengths ranging from 20 to 50 micrometers. Combining this with the resistivity ρ0 and resistivity temperature coefficient α of the copper alloy material used in the lead frame at 25 degrees Celsius, a three-dimensional distributed parametric resistance model is constructed according to ρ = ρ0 * [1 + α * (T - 25)], where T is the node temperature. By applying the extracted Ip to this model, the system calculates the volume heat source density distribution within the local copper-exposed region and its connected pin areas according to the differential form of Joule's law, q = J * J * ρ, where q is the heat generation power per unit volume, and J is the magnitude of the current density vector. Based on this, the system inputs q as the thermal load into the pre-established finite element model of the package thermal conduction. Combining the thermal conductivity of the encapsulation material, the surface convection heat transfer coefficient of 10 W / m² Kelvin to 25 W / m² Kelvin, and the initial ambient temperature of 25 degrees Celsius, the system performs transient thermal conduction solution with a time step of 1 millisecond. This allows for the accurate acquisition of the Joule temperature rise curve and steady-state temperature field distribution of each displacement pin under continuous power-on conditions. The steady-state peak temperature not exceeding 125 degrees Celsius is used as the pass criterion.

[0053] It should be noted that the system has a strictly preset Joule temperature rise tolerance threshold. This tolerance is typically set based on the glass transition temperature of the packaging material and the junction temperature limits of the electronic components. The system will compare the steady-state maximum temperature of each pin with this tolerance value.

[0054] In one possible implementation, if the Joule temperature rise of a displacement pin exceeds the allowable value, the function of adjacent redundant signal pins is redefined. The system scans the pin layout topology around the overheated displacement pin, searching for redundant signal pins that are not assigned electrical signals or are only used as backup test points. Once a redundant signal pin that meets the spatial distance requirements is identified, the system modifies its attribute label in the pin function mapping table, forcibly changing it from a floating or spare state to a parallel heat dissipation pin. This redefinition process involves not only changes to logical attributes but also removes the original signal isolation restrictions on the pin in the routing rule base, allowing it to be directly connected to the overheated displacement pin at the physical layer.

[0055] Understandably, simply redefining the pin functions logically is insufficient for effective heat transfer; a low thermal resistance conduction path must be established in the physical structure. Therefore, the system plan involves constructing physical connections in specific areas of the leadframe.

[0056] Specifically, the system forms a thermal bridge connecting the two pins on the leadframe through semi-etching. Semi-etching is a precise chemical thinning process designed to fabricate microstructures of specific thickness and shape without completely cutting away the metal substrate of the leadframe. The system first automatically generates a bridging polygonal profile spanning the overheat displacement pin and the newly defined parallel heat dissipation pin on a two-dimensional planar layer, based on their spatial relative positions. Then, in the leadframe's manufacturing data package, the system defines the area containing this bridging polygonal profile as the semi-etching processing area. In actual manufacturing simulation or process instruction generation, this process involves coating the back or non-bonded surface of the leadframe with photoresist and exposing and developing it using a customized mask to expose the metal surface corresponding to the bridging polygonal profile. Subsequently, a specific acidic etchant isotropically etches the exposed copper alloy. By strictly controlling the concentration, temperature, and spraying time of the etchant, the system ensures that the etching depth precisely reaches half the total thickness of the leadframe. This structure, retaining half the metal thickness, is the thermal bridge. The thickness of the thermal bridge ensures sufficient lateral cross-sectional area for heat conduction while avoiding excessive inter-pin parasitic capacitance or poor subsequent molding compound filling caused by full-thickness metal connections. Furthermore, the thermal bridge formed through the aforementioned semi-etching process physically appears as a concave metal corridor, seamlessly integrated at both ends with the sidewalls of the overheat displacement pin and the parallel heat dissipation pin, respectively. This structural design allows Joule heat accumulated on the overheat displacement pin to be rapidly conducted laterally to the parallel heat dissipation pin through the metal lattice vibration and free electron movement of the thermal bridge. Based on these steps, the system ultimately obtains a distributed conduction path. This distributed conduction path evenly distributes the heat load originally concentrated on a single pin to two or more pins. The system then synchronously updates the complete data package containing the thermal bridge geometry and new pin attributes to the package design database, completing the closed-loop design of the entire thermal compensation structure.

[0057] S106. Based on the distribution transmission path and the direction of the stress gradient vector field, with the constraint that the angle between the stress gradient direction and the boundary normal direction at the boundary of the thickened area does not exceed a preset acute angle threshold, the extended contour of the thickened area is iteratively smoothed by a sequence of inscribed circular arcs with continuous curvature to obtain a smooth thickened contour extending along the tangent of the stress field.

[0058] Obtain the distributed conduction path and the stress gradient vector field, extract the stress values ​​of each node on the distributed conduction path, and statistically analyze the node regions where the stress values ​​exceed 0.7 times the allowable stress of the material. Mark these regions as thickened areas, extract the boundary of the thickened areas, and calculate the boundary normal direction of the thickened area boundary. Extract the stress gradient direction at the boundary of the thickened area based on the stress gradient vector field, and calculate the angle between the stress gradient direction and the boundary normal direction. If the angle is greater than 65 degrees, insert a new sampling point on the boundary curve, reducing the distance between adjacent sampling points to 0.5 times the original distance. Recalculate the angle at the interpolated boundary points, iteratively refining until the angle at all boundary points is no greater than 65 degrees, thus obtaining the updated boundary. Based on the stress gradient vector field, the tangent direction of the stress field at the updated boundary is extracted. The extension distance is calculated along the tangent direction using d = k × σ / σmax, where d is the extension distance, σ is the stress value at the boundary point, σmax is the maximum stress value in the thickened area, and k is the extension coefficient, ranging from 3.0 to 5.0 mm. The boundary point is moved along the tangent direction to generate the extended profile of the thickened area. The radius of curvature of the extended profile of the thickened area is calculated. Control points are densified in high-curvature regions with a radius of curvature less than 10 mm. Control points are selected every 2 to 5 mm on the profile curve. A piecewise cubic polynomial is constructed using a cubic spline interpolation algorithm for the control point coordinates. The curvature center is extracted on each curve segment. An inscribed arc is constructed with this curvature center as the center and the local curvature radius as the radius. The inscribed arcs are sequentially connected to generate a sequence of inscribed arcs. Calculate the maximum deviation distance between the inscribed arc sequence and the extended contour. If the deviation distance is greater than 0.2 mm, adjust the arc radius to make it closer to the original contour. At the same time, constrain the curvature change rate at the connection of adjacent arcs to not exceed 0.15 per millimeter. Repeat the adjustment until the deviation distance is less than 0.2 mm and the curvature change rate meets the constraint to obtain a smooth and thickened contour.

[0059] In one possible implementation, the system obtains the distributed transmission path and the stress gradient vector field, determines the thickened area and extracts the boundary of the thickened area, and calculates the boundary normal direction.

[0060] Specifically, the system extracts the stress gradient direction at the boundary of the thickened area, calculates the angle between the gradient and the normal direction of the boundary, and if the angle is greater than a preset acute angle threshold, the boundary of the thickened area is resampled to obtain an updated boundary.

[0061] The stress gradient vector field characterizes the rate of change of the spatial distribution of thermomechanical stress within the package. The tangent direction of the stress field is extracted along the updated boundary, and the boundary is extrapolated and extended accordingly to obtain a discrete control point sequence of the extended profile of the thickened area. Cubic spline interpolation is used to fit the curve to this sequence. The node arrangement strategy uses the reciprocal of the local radius of curvature as the weight, densifying the nodes in high curvature segments with a radius of curvature less than 0.2 mm, with a node spacing of 0.05 to 0.1 mm; and widening the spacing to 0.3 to 0.5 mm in smooth segments with a radius of curvature greater than 1 mm. The total number of nodes for the entire profile is controlled between 60 and 120, resulting in a smooth and continuous fitted profile and its radius of curvature distribution.

[0062] Based on the fitted contour, an inscribed circular arc sequence is further generated: several fitting points are sampled at equal intervals along the curve according to the arc length. At each fitting point, an arc segment is constructed with the local radius of curvature of that point as the radius and the corresponding curvature center as the center. Adjacent arc segments maintain the same tangent direction at the sampling points, thus forming an arc sequence that is inscribed in the fitted contour and smoothly connected from beginning to end, serving as the final geometric boundary of the thickened area.

[0063] In one possible implementation, the system uses the inscribed circular arc sequence to iteratively smooth the extended contour of the thickened area to obtain a smooth thickened contour.

[0064] S107. Using a pre-established interface state classification model, feature fusion processing is performed on the smoothed and thickened contour and the first position coordinates to output the first interface health state category of the contact interface between the target electronic component and the lead frame.

[0065] The process involves: acquiring the smoothed and thickened contour and the first position coordinates; extracting a set of contour nodes based on the smoothed and thickened contour; calculating the Euclidean distance between each contour node in the set and the first position coordinates to obtain a node distance sequence; acquiring the node distance sequence; if the maximum distance value in the node distance sequence is greater than a preset distance threshold, performing a truncation operation on the contour node set to obtain a target contour node set; acquiring the target contour node set; performing a dimensionality reduction operation on the target contour node set using principal component analysis to obtain a contour principal component vector; acquiring the contour principal component vector and the first position coordinates; performing a vector concatenation operation on the contour principal component vector and the first position coordinates to obtain a joint feature vector; acquiring the joint feature vector; performing a classification operation on the joint feature vector using a pre-established interface state classification model to output a first interface health status category of the contact interface between the target electronic component and the lead frame; acquiring the first interface health status category; if the first interface health status category is an abnormal status category, extracting the abnormal dimension index from the joint feature vector; and determining the abnormal contact surface region of the target electronic component based on the abnormal dimension index.

[0066] After extracting the discrete point set of the smoothed and thickened contour, the two-dimensional discrete Fourier transform of this point set is calculated. Based on the principle that the cumulative contribution rate of the spectral energy reaches 92%, the first 16 low-frequency components are truncated to construct the morphological feature vector. Simultaneously, the X and Y components of the first position coordinates are obtained, and the Z-axis height value of 0 of the plane where the lead frame is located is introduced to complete the mapping to the three-dimensional Cartesian coordinate system. The Euclidean distance d between this coordinate and the reference point of the center of the lead frame and the spatial azimuth angle θ relative to the positive X-axis are calculated. Combined with the Z-axis height difference Δz, a 3-dimensional spatial position feature vector is generated. The bilinear pooling algorithm is used to perform an outer product operation on the morphological feature vector and the spatial position feature vector to generate a 16×3 fusion feature matrix. The dimensionality is reduced and flattened into a 48-dimensional global feature vector through a global average pooling operation. This global feature vector is input into a pre-established deep residual network classification model. This model includes an input layer, three residual blocks, a fully connected layer, and a normalized exponential function layer, where each residual block contains two convolutional layers and one skip connection. The model outputs predicted probability distributions for five interface states: intact adhesion, micro-delamination, local delamination, interface voids, and complete detachment. When the output probability of the micro-delamination state reaches 0.85, exceeding the preset classification threshold of 0.75, the health status of the contact interface between the target electronic component and the lead frame is determined to be micro-delamination.

[0067] S108. If the first interface health status category belongs to the preset failure status category, then according to the smooth thickened contour, a gradient mask pattern is used to perform half etching on the back of the lead frame to reduce the size of the initial thickness parameter, thereby obtaining a first thickness parameter with a smooth transition edge boss. A target package layout scheme is generated according to the first thickness parameter, the distributed conduction path and the first position coordinate.

[0068] The first interface health status category is obtained. If the first interface health status category belongs to a preset failure status category, the smooth and thickened contour corresponding to the first interface health status category is extracted. Based on the smooth and thickened contour, a random forest algorithm is used to generate a pattern on the back of the lead frame to obtain a gradient mask pattern corresponding to the pattern generation process. A half-etching process is performed based on the gradient mask pattern to obtain the initial thickness parameter corresponding to the half-etching process. A size reduction operation is performed on the initial thickness parameter to obtain the size reduction amount corresponding to the size reduction operation. A boss with a smooth transition edge is generated based on the size reduction amount, and the first thickness parameter corresponding to the boss with a smooth transition edge is obtained. The allocated conduction path and the first position coordinate are obtained based on the first thickness parameter, and the target package layout scheme is determined based on the allocated conduction path and the first position coordinate.

[0069] An ultrasonic probe emits sound waves at the first interface of the lead frame, collects the reflected echo signals, and converts them into spectral feature vectors. These vectors are then input into a support vector machine classifier for health status identification. The classifier outputs three labels: healthy, microscopic delamination, and severe failure. Simultaneously, it calculates the ratio of the interface layered area to the total area. When the ratio reaches 15.5% and the label is severe failure, a repair mechanism is immediately triggered. The previously generated smoothing and thickening contour data is extracted, and a grayscale lithography data generation algorithm is used to construct a gradient mask pattern on the back of the lead frame with transmittance increasing exponentially by a function T = 20% + 60% × (1 - e^(-3x)), where x is the normalized position coordinate ranging from 0 to 1. This pattern is then used to control a plasma etching machine to perform a semi-etching process. During the etching process, the material removal rate was monitored in real time. The initial thickness of 0.8 mm was reduced in size according to the parabolic decay model h(r) = 0.8 - 0.25 × (r / R)^2, where r is the radial distance from the center and R is the frame radius. After 45 seconds of etching, a smooth transition edge protrusion with a curvature radius of 0.15 mm was formed in the edge region, and the first thickness parameter retained in the center region was accurately reached to 0.55 mm. This thickness parameter was input into the finite element thermodynamic analysis model, combined with a pre-planned multi-level heat conduction path with a thermal resistance of 2.3℃ / W. This path achieves graded heat transfer from the chip to the shell by setting the thickness ratio of the copper layer, insulating layer, and solder layer, and the first position coordinates corresponding to the chip center point are 12.5 mm on the horizontal axis and 8.2 mm on the vertical axis. A multi-objective genetic algorithm was used for iterative optimization. The algorithm uses minimizing the maximum temperature rise and minimizing the peak thermal stress as dual objective functions, with constraints of pin pitch greater than 0.4mm and avoiding acute angles in routing. The population size is set to 100, and the algorithm converges after 200 iterations. It automatically adjusts the pad spacing and pin routing, and finally outputs a target package layout scheme that includes three-dimensional routing coordinates and thermal stress distribution cloud map.

[0070] Reference Figure 4 In this embodiment, a semiconductor lead frame includes a base, electronic components and chips disposed on the base, wherein the electronic components and chips are manufactured using an electronic component packaging layout processing method for optimized manufacturing.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for processing the layout of electronic component packages, characterized in that, include: Obtain the initial position coordinates of the target electronic component and the initial thickness parameters of the supporting substrate; The shear stress field along the thickness direction at the interface between the supporting substrate and the packaging material is extracted from the thermo-coupling simulation results; the target heat dissipation area is determined based on the shear stress field. A stress gradient vector field is calculated for the shear stress field within the target heat dissipation area; a pre-established stress prediction model is used to extract features from the stress gradient vector field to obtain the interface shear stress parameters at the contact interface between the target electronic component and the supporting substrate; if the interface shear stress parameters are greater than a preset stress threshold, spatial translation is performed on the initial position coordinates to obtain a first position coordinate; it is determined whether the translation amount of the first position coordinates relative to the initial position coordinates exceeds a preset bonding process window; if the translation amount exceeds the bonding process window, the same vector displacement is performed on the signal terminal group directly bonded to the target electronic component along the translation direction to obtain a displacement terminal group; a local thermally conductive extension area is extended from the connection area between the root of the displacement terminal group and the supporting substrate; power thermal coupling verification is performed on the local thermally conductive extension area based on the carrying current of the displacement terminal group; If the operating temperature rise of a certain displacement terminal exceeds the allowable value, the function of the adjacent redundant signal terminals of the displacement terminal is redefined to obtain parallel heat dissipation terminals; a thermal bridge connecting the two terminals is formed on the support substrate through thinning processing to obtain a distributed conduction path; according to the distributed conduction path and the direction of the stress gradient vector field, the extended contour of the thickened area is iteratively smoothed and approximated using a sequence of continuously curvature inscribed circular arcs to obtain a smoothed thickened contour; a pre-established interface state classification model is used to perform feature fusion processing on the smoothed thickened contour and the first position coordinates to output the first interface health status category of the contact interface between the target electronic component and the support substrate; if the first interface health status category belongs to a preset failure status category, a thinning process is performed on the back of the support substrate using a gradient mask pattern according to the smoothed thickened contour, and the initial thickness parameter is reduced in size to obtain a first thickness parameter; a target packaging layout scheme is generated based on the first thickness parameter, the distributed conduction path, and the first position coordinates.

2. The method as described in claim 1, characterized in that, The step of determining the target heat dissipation area based on the shear stress field includes: obtaining the coordinate position parameters of the target electronic component and the frame thickness of the supporting substrate; extracting thermal coupling data from a preset thermal coupling simulation model based on the coordinate position parameters and the frame thickness; extracting the interface shear stress between the supporting substrate and the packaging material using the thermal coupling data; obtaining the stress gradient distribution based on the rate of change of the interface shear stress along the thickness direction; calculating the packaging deformation displacement by spatial integration of the stress gradient distribution; obtaining the node temperature gradient by multiplying the packaging deformation displacement by a preset material thermal expansion coefficient; calculating the local heat density by multiplying the node temperature gradient by a preset material thermal conductivity; if the local heat density exceeds a preset density threshold, determining the boundary of the heat dissipation area with a risk of interface delamination; obtaining the geometric center point within the boundary of the heat dissipation area; and determining the target heat dissipation area based on the relative distance between the geometric center point and the coordinate position parameters.

3. The method as described in claim 1, characterized in that, The step of extracting features from the stress gradient vector field using a pre-established stress prediction model to obtain the interface shear stress parameters at the contact interface between the target electronic component and the supporting substrate includes: acquiring the shear stress field within the target heat dissipation area; calculating the spatial partial derivative of the shear stress field to obtain the stress gradient vector field; extracting the vector divergence and curl distribution from the stress gradient vector field; constructing a stress tensor matrix based on the vector divergence and curl distribution; performing eigenvalue decomposition on the stress tensor matrix to determine the principal stress axis direction; performing a decomposition operation on the stress gradient vector field along the principal stress axis direction to obtain the normal gradient component and the tangential gradient component; acquiring a pre-established stress prediction model; and extracting features from the normal gradient component and the tangential gradient component using the pre-established stress prediction model to obtain the interface shear stress parameters at the contact interface between the target electronic component and the supporting substrate.

4. The method as described in claim 1, characterized in that, The step of determining whether the translation amount of the first position coordinate relative to the initial position coordinate exceeds a preset bonding process window includes: obtaining the initial position coordinate of the target electronic component; if the interface shear stress parameter is greater than a preset stress threshold, performing spatial translation processing on the initial position coordinate to obtain the first position coordinate; calculating a translation variable based on the first position coordinate and the initial position coordinate; determining whether the translation variable exceeds the preset bonding process window; if the translation variable does not exceed the bonding process window, generating an offset vector based on the first position coordinate and the initial position coordinate; obtaining a pre-constructed pad boundary coordinate system; performing a vector superposition operation on the offset vector and the pre-constructed pad boundary coordinate system to obtain superimposed trajectory coordinates; determining an out-of-bounds flag in the pad boundary coordinate system based on the trajectory coordinates; and determining that the translation amount exceeds the bonding process window if the translation variable exceeds the bonding process window.

5. The method as described in claim 1, characterized in that, The step of extending a local thermally conductive expansion region from the connection area between the root of the displacement terminal group and the supporting substrate includes: obtaining an initial terminal group corresponding to the target electronic component and an offset direction corresponding to the translation amount; constructing a displacement vector value based on the offset direction and the translation amount; performing a spatial coordinate transformation on the initial terminal group using the displacement vector value to obtain the displacement terminal group; obtaining the root region coordinates of the displacement terminal group and the preset supporting substrate coordinates; calculating the spatial intersection based on the root region coordinates and the supporting substrate coordinates to determine the initial connection area; extracting peripheral contour nodes for the initial connection area; performing nonlinear fitting on the peripheral contour nodes using a support vector regression algorithm to obtain a smooth peripheral trajectory; performing normal extension processing outward based on the smooth peripheral trajectory to obtain an extended peripheral coordinate set; generating the local thermally conductive expansion region based on the extended peripheral coordinate set and the initial connection area; obtaining the area parameter of the local thermally conductive expansion region; if the area parameter is greater than a preset area threshold, performing meshing segmentation on the local thermally conductive expansion region to obtain multiple sub-thermally conductive expansion blocks.

6. The method as described in claim 1, characterized in that, The process of forming a thermally conductive bridge connecting two terminals on the support substrate through thinning to obtain a distributed conduction path includes: acquiring the carrying current of the displacement terminal group and the material thermal resistance parameters of the local thermally conductive expansion area; performing power thermal coupling verification on the local thermally conductive expansion area based on the carrying current and the material thermal resistance parameters to obtain the operating temperature rise of each displacement terminal in the displacement terminal group; if the operating temperature rise of a target displacement terminal is greater than a preset temperature rise tolerance value, extracting a redundant signal terminal adjacent to the target displacement terminal on the support substrate; redefining the function of the redundant signal terminal, modifying the signal transmission attributes of the redundant signal terminal to obtain grounding heat dissipation attributes, and obtaining the parallel heat dissipation terminal; acquiring the spacing parameters between the target displacement terminal and the parallel heat dissipation terminal; calculating the target etching depth and the target bridging width based on the spacing parameters and the operating temperature rise; generating a thinning processing trajectory on the support substrate based on the target etching depth and the target bridging width; forming the thermally conductive bridge connecting the target displacement terminal and the parallel heat dissipation terminal through the thinning processing trajectory; and determining the distributed conduction path based on the thermally conductive bridge.

7. The method as described in claim 1, characterized in that, The method of iteratively smoothing the extended contour of the thickened area using a sequence of inscribed circular arcs with continuous curvature to obtain a smoothed thickened contour includes: obtaining the distributed transmission path and the stress gradient vector field; determining the thickened area based on the distributed transmission path; extracting the boundary of the thickened area; calculating the boundary normal direction of the thickened area boundary; extracting the stress gradient direction at the boundary of the thickened area based on the stress gradient vector field; calculating the angle between the stress gradient direction and the boundary normal direction; if the angle is greater than a preset acute angle threshold, then the edge of the thickened area is smoothed. The boundary is resampled to obtain an updated boundary; the stress field tangent direction at the updated boundary is extracted based on the stress gradient vector field; the updated boundary is extended based on the stress field tangent direction to generate the thickened area extended contour; the contour curvature radius of the thickened area extended contour is calculated; the thickened area extended contour is curve-fitted using a cubic spline interpolation algorithm based on the contour curvature radius to generate the inscribed circular arc sequence; the thickened area extended contour is iteratively smoothed using the inscribed circular arc sequence to obtain the smoothed thickened contour.

8. The method as described in claim 1, characterized in that, The method of using a pre-established interface state classification model to perform feature fusion processing on the smoothed thickened contour and the first position coordinates, and outputting the first interface health state category of the contact interface between the target electronic component and the supporting substrate, includes: obtaining the smoothed thickened contour and the first position coordinates; extracting a contour node set based on the smoothed thickened contour; calculating the Euclidean distance between each contour node in the contour node set and the first position coordinates to obtain a node distance sequence; obtaining the node distance sequence; if the maximum distance value in the node distance sequence is greater than a preset distance threshold, performing a truncation operation on the contour node set to obtain a target contour node set; obtaining the target contour node set; performing a dimensionality reduction operation on the target contour node set using a principal component analysis algorithm to obtain a contour principal component vector; obtaining the contour principal component vector and the first position coordinates; performing a vector concatenation operation on the contour principal component vector and the first position coordinates to obtain a joint feature vector; obtaining the joint feature vector; and using a pre-established interface state classification model to perform feature fusion processing on the smoothed thickened contour and the first position coordinates to output the first interface health state category of the contact interface between the target electronic component and the supporting substrate. The state classification model performs a classification operation on the joint feature vector, outputting the first interface health state category of the contact interface between the target electronic component and the supporting substrate; obtains the pre-established interface state classification model; performs feature mapping processing on the joint feature vector through the pre-established interface state classification model to obtain a state classification probability distribution; determines the first interface health state category according to the state classification probability distribution; obtains the first interface health state category; if the first interface health state category is an abnormal state category, extracts the abnormal dimension index from the joint feature vector; determines the abnormal contact surface region of the target electronic component according to the abnormal dimension index; extracts local stress concentration features for the abnormal contact surface region; performs secondary translation compensation on the first position coordinates according to the local stress concentration features to obtain the second position coordinates; updates the first position coordinates according to the second position coordinates and returns to perform the feature fusion processing operation until the first interface health state category is no longer the abnormal state category.

9. The method as described in claim 1, characterized in that, The process of performing thinning processing on the back side of the support substrate using a gradient mask pattern based on the smooth thickened contour, and performing size reduction processing on the initial thickness parameter to obtain a first thickness parameter, includes: obtaining the first interface health status category; if the first interface health status category belongs to a preset failure status category, extracting the smooth thickened contour corresponding to the first interface health status category; performing pattern generation processing on the back side of the support substrate using a random forest algorithm based on the smooth thickened contour to obtain the gradient mask pattern corresponding to the pattern generation processing; performing the thinning processing based on the gradient mask pattern to obtain the initial thickness parameter corresponding to the thinning processing; performing a size reduction operation on the initial thickness parameter to obtain the size reduction amount corresponding to the size reduction operation; generating a boss with a smooth transition edge based on the size reduction amount; obtaining the first thickness parameter corresponding to the boss with a smooth transition edge; obtaining the allocated conduction path and the first position coordinates based on the first thickness parameter; and determining the target packaging layout scheme based on the allocated conduction path and the first position coordinates.

10. A semiconductor lead frame, characterized in that, It includes a base frame, electronic components and chips disposed on the base frame, wherein the electronic components and chips are manufactured by optimizing the electronic component packaging layout processing method according to any one of claims 1-9.

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