A power network fast iteration voltage drop analysis method for decoupled layout routing flow

Abstract

The application discloses a power network fast iteration voltage drop analysis method of decoupling layout wiring process, performs a round of layout wiring process on a design to be analyzed, extracts and saves intermediate data which is decoupled from the physical structure of the power network and remains unchanged in subsequent iterations; performs power consumption analysis to obtain power consumption information of each standard cell as intermediate data; under the premise of keeping the intermediate data unchanged, obtains power network information to be evaluated and replaces it into input data of voltage drop analysis; based on the replaced power network information and the intermediate data, voltage drop analysis is performed to obtain analysis results containing standard cell voltage drop values; it is judged whether the analysis results meet the preset power integrity requirements, if yes, the power network scheme is output, otherwise, the power network information is adjusted and iteration is repeated. The application reuses the layout wiring and power consumption analysis results, only iterates the power network replacement and voltage drop analysis, shortens the iteration period and saves the calculation resources.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit (IC) physical design and power integrity analysis technology, and in particular to a voltage drop (IR Drop / Voltage Drop) analysis method that decouples the power network (PDN) and place & route (P&R) processes in the early stages of a new process project, thereby supporting rapid iteration of the power network. Background Technology

[0002] As integrated circuit manufacturing processes advance to advanced nodes, supply voltage continues to decrease while cell density and current density continue to increase, making the voltage drop (IR Drop) problem on power networks increasingly severe. Excessive voltage drop can cause a decrease in the actual operating voltage of cells, leading to timing degradation, functional failure, or even chip unavailability. Therefore, power integrity analysis (including static IR Drop, dynamic IR Drop, and electromigration EM analysis) has become an indispensable and critical step in the chip signoff process.

[0003] The severity of voltage drop issues is further amplified at advanced process nodes. At these nodes, chip integration density continues to increase, supply current rises, and the reduced cross-sectional area of ​​metal interconnects leads to increased resistance, making the product effect of IR=I×R more pronounced. On the other hand, to reduce overall chip power consumption, the industry commonly employs a strategy of lowering the supply voltage, but this means that the tolerance margin for voltage drop in the power network becomes extremely limited. Therefore, rapid iteration and thorough exploration of power network solutions are crucial to ensuring chip performance.

[0004] The quality of the power distribution network (PDN) directly determines the voltage drop level. In chip design, the power network typically consists of a power / ground mesh composed of multiple layers of metal, power rings, power stripes, via arrays, and standard cell power rails. Power network design is often not a one-step process; it usually requires iterative iterations of designing the power network, performing voltage drop analysis, adjusting the power network based on the analysis results, and performing voltage drop analysis again until the voltage drop meets the design specifications.

[0005] In existing conventional design processes, the input data required for voltage drop analysis typically includes the following three types:

[0006] 1. Physical Layout File (DEF): Describes the power network information required for voltage drop analysis and the physical location of the cells after layout.

[0007] 2. Timing Window File: Used to determine the switching time and switching window of each unit in dynamic voltage drop analysis, so that the transient current superposition is closer to the real situation; this file is generated by static timing analysis (STA) based on the design and parasitic parameters after placement and routing.

[0008] 3. Parasitic RC parameters (SPEF): These include the resistance and capacitance information of the signal network, which are obtained from the layout after placement and routing through parasitic parameter extraction (RC Extraction).

[0009] In the traditional process, the above input data is tightly coupled with the placement and routing results. Whenever an engineer adjusts the power network, the industry practice is to re-execute (or partially re-execute) the entire placement and routing process, including placement, clock tree synthesis (CTS), routing, parasitic parameter extraction and timing analysis, and finally a new round of voltage drop analysis.

[0010] This approach has the following significant drawbacks:

[0011] (1) Long iteration cycle: A complete layout and routing process and subsequent extraction and timing analysis process often takes several days for large-scale designs. Power networks usually require multiple iterations, resulting in huge cumulative time consumption and severely restricting project progress.

[0012] (2) Waste of computational resources: Adjustments to the power supply network generally only change the physical structure of the power supply grid itself, without changing the location of standard cells, the wiring topology of the signal network, or the switching activities and timing behavior of the cells; however, the traditional process repeatedly performs all layout and wiring calculations that are unrelated to this local change, resulting in a large amount of repetitive and meaningless computational overhead.

[0013] (3) The problem is particularly prominent in the early stage of new processes: In the early stage of projects using new processes, the power network planning scheme has not yet been solidified, and the power network scheme needs a lot of exploration and iteration. The long cycle problem of traditional processes is further amplified at this stage, becoming a bottleneck that restricts the rapid establishment of the new process platform.

[0014] Therefore, how to decouple power network iteration from the placement and routing process so that the placement and routing process does not need to be repeated during power network iteration, thereby shortening the power network iteration cycle, is a technical problem that urgently needs to be solved in the field of integrated circuit physical design. Summary of the Invention

[0015] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for rapid iterative voltage drop analysis of power networks that decouples the placement and routing process, so as to solve the technical problems of long iteration cycles and waste of computing resources caused by the need to repeatedly execute the placement and routing process in the prior art.

[0016] The core idea of ​​this invention is that, during the power network iteration process, the standard cell location, signal network routing, cell switching activities, and timing behavior remain unchanged. Therefore, intermediate data (including cell physical location, parasitic RC parameters, and timing window files) generated by the placement and routing process and independent of the power network physical structure can be reused, as can cell power consumption information. Based on this, this invention executes only one complete placement and routing process, extracting and solidifying reusable data decoupled from the power network physical structure within this process. In subsequent power network iterations, only the power network information is replaced, and voltage drop analysis is performed again accordingly, without repeating the placement and routing and power consumption analysis processes, thereby significantly shortening the power network iteration cycle.

[0017] To achieve the above objectives, this invention provides a method for rapid iterative voltage drop analysis of power networks with decoupled placement and routing processes, comprising the following steps:

[0018] Step S1, One-time Placement and Routing and Data Extraction Stage: Perform a placement and routing process on the design to be analyzed to obtain the design data after placement and routing; and extract and save intermediate data based on the design data. The intermediate data is data that is decoupled from the physical structure of the power network and remains unchanged in subsequent power network iterations.

[0019] Preferably, the layout and routing process includes layout planning, standard cell layout, clock tree synthesis, and signal routing.

[0020] Preferably, the intermediate data includes at least one of the following: physical location of standard cells, parasitic RC parameters of the signal network, timing window file, and power consumption information of standard cells. In one specific embodiment, the intermediate data includes the physical location of standard cells, parasitic RC parameters of the signal network, and timing window file. The intermediate data is saved in the form of DEF file, SPEF file, and timing window file, respectively.

[0021] More specifically, in step S1, the parasitic RC parameters are obtained by performing parasitic parameter extraction on the design data after placement and routing. The timing window file is generated by static timing analysis based on the design data after placement and routing and the parasitic RC parameters, and is used to determine the switching time and switching window of each standard cell in dynamic voltage drop analysis.

[0022] Step S2, Power Consumption Analysis: Perform power consumption analysis to obtain the power consumption information of each standard unit as intermediate data.

[0023] Preferably, the power consumption analysis includes: obtaining the dynamic current of each standard cell based on VCD waveform back-annotation or vectorless method for dynamic voltage drop analysis; and obtaining the average current of each standard cell for static voltage drop analysis.

[0024] Step S3, Power Network Replacement Stage: While keeping the intermediate data unchanged, obtain the power network information to be evaluated and replace the power network information in the input data of voltage drop analysis.

[0025] Preferably, the power network information includes at least one of the following: power strips, power rings, via arrays, and power network metal layer assignments. In one specific embodiment, the power network information may be given in DEF format, and may include at least the position and width of the power rings and power strips, as well as the position, number, and specifications of the via array.

[0026] Preferably, the standard unit power rails remain unchanged during power network replacement.

[0027] Step S4, Voltage Drop Analysis Stage: Based on the replaced power network information and intermediate data, voltage drop analysis is performed to obtain voltage drop analysis results. The voltage drop analysis results include the difference between the actual supply voltage and the theoretical supply voltage of the standard unit, i.e., the voltage drop value. The voltage drop analysis includes at least one of static voltage drop analysis and dynamic voltage drop analysis.

[0028] Step S5, Iterative Judgment Stage: Determine whether the voltage drop analysis results meet the preset power integrity requirements. If they do, output the power network scheme. If they do not, adjust the power network information according to the voltage drop analysis results to obtain new power network information to be evaluated, and return to step S3.

[0029] Preferably, the preset power integrity requirements include at least one of dynamic voltage drop requirements, static voltage drop requirements, and electromigration requirements.

[0030] Preferably, the method of adjusting the power network information based on the voltage drop analysis results includes at least one of the following: widening the power band or power grid, increasing the density of the power band or power grid, increasing the number of vias or the via array size, and adjusting the power network metal layer distribution.

[0031] In the power network iteration loop consisting of steps S3 to S5, the placement and routing process is executed only once in step S1, and the power analysis process is executed only once in step S2.

[0032] As can be seen from the above scheme, in the entire power network iteration cycle (steps S3 to S5), the placement and routing and power analysis process is executed only once in steps S1 and S2, and is not repeated in subsequent iterations, thus achieving decoupling of the power network iteration from the placement and routing and power analysis process.

[0033] According to one embodiment of the present invention, the method is applied to power network design and voltage drop analysis scenarios at the integrated circuit chip level or module level.

[0034] The present invention, by adopting the above-described technical solution, has the following beneficial effects:

[0035] 1. Significantly shortens the iteration cycle:

[0036] This invention executes only one round of placement and routing (S1) and extracts intermediate data, and performs only one power analysis in step S2 to obtain power consumption information for each standard cell. In the subsequent iterative loop consisting of steps S3 to S5, only the power network information is replaced, and voltage drop analysis is performed again accordingly, eliminating the need to repeat the placement and routing process. For large-scale integrated circuit design, the single-round power network iteration cycle is shortened from several days in the traditional process to several hours, improving iteration efficiency by more than an order of magnitude and significantly reducing the iteration cycle. This effectively solves the technical problem of long iteration cycles caused by repeatedly executing the complete placement and routing process in existing technologies.

[0037] 2. Saves computing resources:

[0038] This invention extracts and saves intermediate data decoupled from the physical structure of the power network in step S1. In subsequent iterations, the intermediate data remains unchanged, and only the power network information is replaced. This avoids repetitive calculations of standard cell layout, clock tree synthesis, signal routing, parasitic parameter extraction, and timing analysis, significantly reducing the consumption of resources such as CPU time, memory, and EDA tool licenses. It effectively solves the technical problem of resource waste caused by repetitive calculations in the prior art.

[0039] 3. Break through the serial dependencies in the existing process:

[0040] In existing technologies, voltage drop analysis can only be performed after a power network adjustment requires a re-execution of placement and routing, resulting in a sequential, bound process. This invention identifies standard cell locations, signal network routing, cell switching activities, and timing behaviors that remain unchanged throughout power network iterations. By splitting the originally sequential, dependent process into reusable and variable parts, it decouples power network iteration from the placement and routing process, providing a new technical path for rapid power network iteration.

[0041] 4. The results of the iterations are highly comparable:

[0042] Since each iteration from step S3 to step S5 reuses the same set of intermediate data from step S1, with only the power network information changing, the voltage drop analysis results of each iteration are highly comparable. This facilitates accurate assessment of the real impact of power network modifications and avoids interference from random disturbances caused by rewiring.

[0043] 5. Adapt to new processes for rapid early exploration:

[0044] In the early stages when new process platforms are not yet solidified and power network solutions require extensive exploration, this invention decouples the placement and routing process from power network iteration, enabling engineers to quickly test multiple power network solutions in a short time, accelerating power network convergence and the establishment of new process platforms, and saving a significant amount of time in the chip design process. Attached Figure Description

[0045] The present invention will be further described below with reference to the accompanying drawings:

[0046] Figure 1 This is a flowchart illustrating the power network rapid iterative voltage drop analysis method for decoupled layout and routing processes provided in an embodiment of the present invention.

[0047] Figure 2 This is a schematic diagram comparing the power network iteration process in the prior art with the power network iteration process of this invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in further detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only for a better understanding of this invention and do not constitute a limitation on the scope of protection of this invention.

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides a method for rapid iterative voltage drop analysis of power networks that decouples the layout and routing process. This method is applied to power network design and voltage drop analysis scenarios in the early stages of new process projects, and specifically includes the following steps:

[0051] Step S1: One-time layout and routing, and extraction of reusable data.

[0052] In the early stages of a new process project, for the design to be analyzed (such as an IP module or a full chip), import the netlist, library files, timing constraints (SDC), and other files into the physical implementation tool, and then execute the following steps sequentially:

[0053] Floorplanning determines chip size, placement of I / O units, and macrocells.

[0054] Initial power network construction (Power Planning).

[0055] Standard cell placement involves arranging the synthesized standard cells within the chip area and determining the physical location of each standard cell.

[0056] Clock Tree Synthesis (CTS) constructs a clock signal distribution network and minimizes the clock delay difference from the clock source to each timing unit by inserting buffers.

[0057] Signal routing interconnects standard cells, macro cells, and I / O cells through metal layer traces according to the netlist connection relationship.

[0058] After completing the entire placement and routing process described above, the design data after placement and routing is obtained. Then, based on this design data, the following extractions are performed and saved:

[0059] (1) Parasitic RC parameter extraction: Parasitic parameters are extracted from the layout after placement and routing to obtain the parasitic RC parameters of the signal network (such as SPEF format file). The parasitic parameters of the signal network remain unchanged in subsequent power network iterations and are saved as reusable data.

[0060] (2) Timing window file generation: Static timing analysis (STA) is performed based on the design data and parasitic parameters after placement and routing to generate a timing window file. This file records the switching time and switching window information of each standard cell, which is used to determine the time distribution of transient current in subsequent dynamic voltage drop analysis.

[0061] (3) Physical layout information: Obtain the physical location of the standard cells after layout required for voltage drop analysis.

[0062] The reusable data mentioned above is saved in the form of DEF files, SPEF files, and timing window files respectively.

[0063] It should be noted that the common characteristic of the aforementioned reusable data is that they are determined by the standard cell locations, signal network routing topology, and circuit timing behavior, and are independent of the physical structure of the power network (power grid, power strips, vias, etc.). Therefore, when only the power network is adjusted subsequently, these data do not need to be regenerated.

[0064] In this embodiment, the intermediate data includes the physical location of the standard cell, the parasitic RC parameters of the signal network, and the timing window file. It is understood that in other embodiments, the intermediate data may also include standard cell power consumption information, or any one or more combinations of the above data types.

[0065] Step S2: Power consumption analysis.

[0066] Power consumption analysis is performed to obtain power consumption information for each standard cell, which serves as intermediate data. Specifically, the dynamic current of each standard cell is obtained based on VCD waveform back-annotation or vectorless method for dynamic voltage drop analysis; and the average current of each standard cell is obtained for static voltage drop analysis.

[0067] Step S3: Replace power network information.

[0068] While keeping the reusable data obtained in steps S1 and S2 unchanged, obtain the power network information to be evaluated in this round. The power network information includes at least one of the following: power strips, power rings, via arrays, and power network metal layer assignments. The standard cell power rails remain unchanged during the power network replacement process.

[0069] In a preferred embodiment, the power network information is provided in DEF format, and the power network information includes at least one of the following: power strips, power rings, via arrays, and power network metal layer assignments. For example, when the power network information includes power strips, the DEF file records parameters such as their position and width; when the power network information includes via arrays, the DEF file records parameters such as their position, quantity, and specifications.

[0070] Replace the aforementioned power network information in the input data required for voltage drop analysis, that is, replace the power network information of the previous round with the new power network information of this round, while the remaining input data (parasitic RC parameter file, timing window file, power consumption information) remain unchanged.

[0071] Step S4: Voltage drop analysis.

[0072] Based on the power network information replaced in step S3 and the reusable data from steps S1 and S2, voltage drop analysis is performed to obtain the voltage drop analysis results. Voltage drop analysis includes at least one of static voltage drop analysis and dynamic voltage drop analysis. Both analysis methods are used to obtain the voltage drop value characterizing the deviation of the actual supply voltage of the standard cell from the theoretical voltage.

[0073] The static voltage drop analysis calculates the node voltage under steady state based on the parasitic resistance parameters of the power supply network and the average current load of each unit. Its output is the voltage value of each node on the power supply network and the difference between the actual supply voltage and the theoretical supply voltage of each standard unit (i.e., the voltage drop value). The dynamic voltage drop analysis calculates the peak voltage drop value at the switching moment based on the current waveform of each unit during the switching transient.

[0074] Static analysis and dynamic analysis can be used individually or in combination, depending on the design stage and accuracy requirements.

[0075] Step S5: Iterative judgment and power network adjustment.

[0076] The voltage drop analysis results obtained in step S4 are compared with the preset power integrity requirements. In this embodiment, the static voltage drop analysis requires that the voltage drop value of each standard unit is less than 3% of the supply voltage; the dynamic voltage drop analysis requires that the peak voltage drop value of each standard unit at the switching moment is less than 12% of the supply voltage; and the electromigration analysis requires that the ratio of the average current density of each metal segment and via to the upper limit of the allowable current density is not greater than 1.0.

[0077] If the analysis results meet the preset requirements, namely, the static voltage drop is less than 3%, the dynamic voltage drop is less than 12%, and the electromigration current density ratio is not greater than 1.0, the iteration ends and the power network scheme that meets the requirements is output.

[0078] If the analysis results do not meet the preset requirements, the power network information is adjusted according to the voltage drop analysis results. The adjustment methods include, but are not limited to: widening or denser power bands and power grids in areas where the voltage drop exceeds the standard; increasing the number of vias or expanding the via array to reduce interlayer resistance; adjusting the power network metal layer allocation to allocate more power resources to high-layer low-resistance metals; after adjustment, new power network information to be evaluated is obtained, and the process returns to step S3 for the next iteration.

[0079] Steps S3 to S5 are repeated until the voltage drop analysis results meet the requirements. Throughout the entire iterative cycle, the placement and routing process is executed only once in step S1, and the power consumption analysis is executed only once in step S2; these processes are not repeated subsequently, thus decoupling the power network iteration from the placement, routing, and power consumption analysis processes.

[0080] This embodiment is applied to power network design and voltage drop analysis scenarios at the integrated circuit chip level or module level.

[0081] Example 2: Process Comparison and Numerical Examples

[0082] Based on the decoupled layout and routing process of Embodiment 1, this embodiment further illustrates the advantages of the present invention in terms of iteration efficiency by comparing it with the traditional process.

[0083] See Figure 2In existing technologies, each iteration of the power network requires sequentially performing adjustments to the power network, re-layout and routing, re-extraction of RC data, re-analysis of timing parameters, re-analysis of power consumption, and voltage drop analysis, constituting a complete iterative process. Taking a large-scale integrated circuit design as an example, assuming that a complete placement and routing process, along with subsequent parasitic parameter extraction, timing analysis, and power consumption analysis, takes approximately 8 days (T_full = 8 days), an iteration that only replaces the power network information and re-performs voltage drop analysis takes approximately 6 hours (T_pdn = 6 hours = 0.25 days).

[0084] In the traditional process, if 5 rounds of power network iteration are required, the total time is approximately 5 × 8 days = 40 days. Under the proposed solution, the initial execution of a complete placement and routing and power analysis round takes 8 days, and the subsequent 5 iterations each take 6 hours, for a total time of approximately 8 days + 5 × 0.25 days = 9.25 days. Compared to the traditional process's 40 days, this saves approximately 30.75 days, improving iteration efficiency by approximately 4.3 times. If the number of iterations is further increased to 10 rounds, the traditional process takes 10 × 8 days = 80 days, while the proposed solution takes 8 days + 10 × 0.25 days = 10.5 days, saving approximately 69.5 days and improving efficiency by approximately 7.6 times.

[0085] Comparing the time consumption of the two processes described above, the relationship between the time consumption of the traditional process and the time consumption of the process of this invention is as follows: the total time consumption of this invention in N iterations is only about 1 / N + T_pdn / T_full of the traditional process. It is evident that the more iterations, the more significant the efficiency advantage of this invention. In practical engineering applications, power network schemes typically require 5 to 15 iterations from initial planning to final convergence. This invention can shorten the design cycle from several weeks to several days, significantly improving the efficiency of chip power network design.

[0086] Example 3: Detailed Operation and Implementation

[0087] Based on the decoupled layout and routing process of Embodiment 1, this embodiment further illustrates the specific operation method of power network information replacement in step S3 and the specific implementation method of adjusting power network information in step S5.

[0088] Regarding the replacement of power network information:

[0089] The method of this invention does not depend on the implementation of any specific EDA tool vendor. In step S3, replacing the power network information into the input data for voltage drop analysis can be achieved either by directly modifying the SPECIALNETS field in the physical layout file (DEF), or by replacing the power network in the EDA tool and then exporting a new DEF file.

[0090] Since the DEF format is the standard data exchange format in the field of integrated circuit design, its SPECIALNETS field is specifically used to describe the physical structure of power networks, including parameters such as the location and size of power loops, power strips, and via arrays. By directly modifying the SPECIALNETS field in the DEF file, the dependence on specific EDA tool commands can be completely eliminated, making the method of this invention cross-platform portable.

[0091] In practice, a typical process for one iteration is as follows: Based on the voltage drop analysis results (such as IR Drop hotspot diagram), the engineer determines the area and adjustment method that needs to be adjusted, modifies the SPECIALNETS field in the DEF file, saves the modified DEF file, and inputs it along with reusable data (SPEF file, timing window file, power consumption information) into the voltage drop analysis tool to execute a new round of voltage drop analysis.

[0092] Regarding adjustments to the power network:

[0093] In this embodiment, adjustments are made manually by the designer based on the voltage drop analysis results. Specifically:

[0094] Designers use visualization reports (such as IR Drop hotspot maps and electromigration current density distribution maps) output by voltage drop analysis tools to locate areas with excessive voltage drop and areas at risk of electromigration. In the hotspot map, red or dark areas indicate that the voltage drop in that area is large, requiring additional power network resources.

[0095] Based on the area and degree of exceedance of the standard, designers will make adjustments using one or a combination of the following methods:

[0096] (1) If the static voltage drop of multiple standard units in a certain area exceeds the standard, it is determined that the power strip density in that area is insufficient. Add a new power strip in the area where the standard is exceeded or widen the existing power strip. Widening or increasing the density of the power strip can reduce the equivalent resistance of the power supply network, thereby reducing the static voltage drop.

[0097] (2) If the peak dynamic voltage drop of a standard cell in a certain region exceeds the standard, it is determined that the high-frequency response of the power network in that region is insufficient. Increasing the via array at the edge of the region exceeding the standard can reduce the interlayer parasitic resistance, or adjusting some power network resources from the lower layer metal to the lower layer metal. Increasing the number of vias or increasing the size of the via array can reduce the interlayer contact resistance, thereby improving the dynamic voltage drop response.

[0098] (3) If the current density ratio of a certain metal line segment or via is greater than 1.0, it is determined that there is a risk of electromigration at that location. The metal line segment should be widened or the number of vias should be increased to reduce the current density. Adjusting the metal layer distribution of the power network can reduce the IR product effect by utilizing high-layer low-resistance metals.

[0099] After the designers complete the adjustments, a new DEF file is generated, and the process returns to step S3 for the next round of iteration verification. Throughout the process, each iteration reuses the same set of intermediate data (standard cell physical location, parasitic RC parameters, timing window file) from step S1 and the power consumption information from step S2. Only the power network information changes. Therefore, the voltage drop analysis results of each round are highly comparable, facilitating accurate assessment of the real impact of power network modifications and avoiding interference from random disturbances caused by rewiring.

[0100] The above are merely specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications made based on the present invention to solve essentially the same technical problems and achieve essentially the same technical effects are all covered within the protection scope of the present invention.

Claims

1. A method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes, characterized in that, Includes the following steps: S1. Perform a placement and routing process on the design to be analyzed to obtain the design data after placement and routing, and extract and save intermediate data based on the design data. The intermediate data is data that is decoupled from the physical structure of the power network and remains unchanged in subsequent power network iterations. S2. Perform power consumption analysis to obtain power consumption information for each standard unit, which is used as the intermediate data; S3. While keeping the intermediate data unchanged, obtain the power network information to be evaluated, and replace the power network information in the input data of voltage drop analysis; S4. Based on the replaced power network information and the intermediate data, perform voltage drop analysis to obtain voltage drop analysis results. The voltage drop analysis results include the difference between the actual supply voltage and the theoretical supply voltage of the standard unit, i.e., the voltage drop value. The voltage drop analysis includes at least one of static voltage drop analysis and dynamic voltage drop analysis. S5. Determine whether the voltage drop analysis result meets the preset power integrity requirements. If it does, output the power network scheme. If it does not, adjust the power network information according to the voltage drop analysis result to obtain new power network information to be evaluated, and return to step S3. In the power network iterative loop consisting of steps S3 to S5, the layout and routing process is executed only once in step S1, and the power consumption analysis process is executed only once in step S2.

2. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 1, characterized in that: The intermediate data mentioned in step S1 includes at least one of the following: physical location of standard cell, parasitic RC parameters of signal network, timing window file, and power consumption information of standard cell.

3. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 2, characterized in that: The parasitic RC parameters mentioned in step S1 are obtained by performing parasitic parameter extraction on the design data after layout and routing.

4. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 2, characterized in that: The timing window file is generated by static timing analysis performed based on the design data after placement and routing and the parasitic RC parameters, and is used to determine the switching time and switching window of each standard cell in dynamic voltage drop analysis.

5. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 1, characterized in that: The layout and routing process described in step S1 includes layout planning, standard cell layout, clock tree synthesis, and signal routing.

6. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 1, characterized in that: The power network information mentioned in step S3 includes at least one of the following: power strip, power ring, via array, and power network metal layer allocation.

7. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 1, characterized in that: The standard unit power rails remain unchanged during power network replacement.

8. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing process according to claim 1, characterized in that: The power consumption analysis in step S2 includes: obtaining the dynamic current of each standard cell based on VCD waveform back-annotation or vectorless method for dynamic voltage drop analysis.

9. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing processes according to claim 1, characterized in that: The power consumption analysis in step S2 includes: obtaining the average current of each standard cell for static voltage drop analysis.

10. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing process according to claim 1, characterized in that: In step S5, adjusting the power network information based on the voltage drop analysis results includes at least one of the following: widening the power band or power grid, increasing the density of the power band or power grid, increasing the number of vias or the via array size, or adjusting the power network metal layer distribution.

11. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing process according to claim 1, characterized in that: The intermediate data mentioned in step S1 is saved in the form of DEF file, SPEF file and timing window file respectively.

12. The method for rapid iterative voltage drop analysis of power networks with decoupled layout and routing process according to claim 1, characterized in that: The method is used for integrated circuit chip-level or module-level power network design and voltage drop analysis.

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