Variable line width routing method, device and apparatus for analog integrated circuits

Abstract

The application discloses a variable line width routing method, device and equipment for analog integrated circuits, and relates to the technical field of electronic design automation. The method comprises the following steps: obtaining routing input data; constructing an obstacle avoidance generation graph according to a layout result, process parameters and port coordinates; performing multi-source shortest path search in the obstacle avoidance generation graph based on a netlist connection relationship, and performing local topology refinement to generate at least one candidate routing topology satisfying obstacle constraints; detecting a same layer conflict relationship of a line segment in the candidate routing topology and constructing a layer conflict network; distributing metal layers to each line segment in the candidate routing topology based on the layer conflict network, and outputting the candidate routing topology with metal layer information; establishing a line width optimization model based on electrical constraints and process parameters, and optimizing the line width of each line segment in the candidate routing topology with metal layer information; performing rule inspection on the candidate routing topology according to the optimized line width and performing detour repair, and outputting a target routing result.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular to a variable linewidth routing method, apparatus and device for analog integrated circuits. Background Technology

[0002] As integrated circuit process dimensions continue to shrink and integration density increases, power, ground, and high-current interconnect routing in analog integrated circuits faces severe challenges. Such routing must simultaneously meet multiple requirements, including connectivity, obstacle avoidance, metal layer orientation constraints, process spacing, and long-term reliability. Because analog circuits are extremely sensitive to power supply stability, parasitic effects, and device operating points, problems such as resistance voltage drop and excessive current density caused by routing can easily lead to circuit performance degradation and decreased reliability.

[0003] Currently, traditional automatic routing methods tend to generate redundant topologies when handling multi-port networks. Mainstream methods often treat voltage drop and electrical constraints such as electromigration separately, or adopt a fixed linewidth strategy. These methods cannot dynamically adapt to branch currents and process parameters, and the variable linewidth expansion leads to problems in meeting process rules and constraints, resulting in frequent rework and seriously affecting power supply stability.

[0004] Therefore, for analog integrated circuit power supplies and high-current network, how to overcome the defects of rigid linewidth allocation and the disconnect between optimization and rule repair in order to ensure power supply stability is an urgent problem to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a variable linewidth routing method, apparatus, and device for analog integrated circuits, aiming to solve the technical problem of how to overcome the defects of rigid linewidth allocation and the disconnect between optimization and rule repair for analog integrated circuit power supplies and high-current networks, so as to ensure power supply stability.

[0006] To achieve the above objectives, this application proposes a variable linewidth routing method for analog integrated circuits, the method comprising: Obtain cabling input data, which includes layout results, netlist connection relationships, port coordinates, obstacle areas, electrical constraints, and process parameters; An obstacle avoidance generation map is constructed based on the layout results, the process parameters, and the port coordinates; Based on the netlist connection relationship, multi-source shortest path search is performed in the obstacle avoidance generation graph, and local topology refinement is performed by introducing Steiner points to generate at least one candidate wiring topology that satisfies obstacle constraints. The same-layer conflict relationship is detected for the line segments in the candidate routing topology. A layer conflict network is constructed based on the detected same-layer conflict relationship. Metal layers are assigned to each line segment in the candidate routing topology based on the layer conflict network, and a candidate routing topology with metal layer information is output. Based on the electrical constraints and the process parameters, a linewidth optimization model is established, and the linewidth of each line segment in the candidate wiring topology with metal layer information is optimized to obtain the optimized linewidth. Based on the optimized linewidth, the candidate routing topology with metal layer information is subjected to rule verification, and local line segments with rule conflicts are repaired by detour, and the target routing result is output.

[0007] In one embodiment, the step of constructing an obstacle avoidance generation map based on the layout result, the process parameters, and the port coordinates includes: The obstacle area is determined based on the layout results; The obstacle region is expanded according to the minimum spacing in the process parameters to obtain the expanded obstacle region; Add the port node corresponding to the port coordinates and the corner point of the extended obstacle region to the candidate node set; Perform a directional scan on each candidate node in the candidate node set to find the candidate neighbor nodes of each candidate node in each scan direction and generate candidate edges; Determine whether each candidate edge crosses the extended obstacle region, and add the candidate edges that do not cross the extended obstacle region to the obstacle avoidance generation graph.

[0008] In one embodiment, the step of performing multi-source shortest path search in the obstacle avoidance generation graph based on the netlist connection relationship, and generating at least one candidate wiring topology that satisfies obstacle constraints by introducing Steiner points for local topology refinement, includes: Based on the netlist connection relationship, a multi-source shortest path search is performed in the obstacle avoidance generation graph to obtain the initial port area connection relationship. A right-angled Steiner point is introduced into the port region connection relationship to make the local connection structure right-angled and topologically refined; Determine whether the introduced Steiner point falls within the extended obstacle area and whether the connecting line segment crosses the extended obstacle area; When the Steiner point falls into the extended obstacle region or the connecting line segment crosses the extended obstacle region, a detour point is generated along the boundary of the extended obstacle region, and the illegal point or illegal line segment is replaced with the detour point to generate a candidate wiring topology.

[0009] In one embodiment, the step of detecting same-layer conflict relationships among line segments in the candidate wiring topology includes: Determine the projection relationship between any two line segments in the candidate routing topology on the same metal layer. The projection relationship includes the intersection of the planar projections of horizontal and vertical line segments, and the overlap of the projection intervals of line segments in the same direction in the routing direction. When the projection relationship exists, based on the estimated line width of the two line segments, the minimum spacing of the corresponding metal layers in the process parameters, and the centerline distance of the two line segments, it is determined whether there is a cross conflict, an overlap conflict, or a insufficient spacing conflict between any two line segments. If there are intersection conflicts, overlapping conflicts, or insufficient spacing conflicts, the two line segments will be marked as having a conflict relationship at the same level.

[0010] In one embodiment, the step of constructing a layer conflict network based on detected same-layer conflict relationships, allocating metal layers to each segment in the candidate routing topology based on the layer conflict network, and outputting a candidate routing topology with metal layer information includes: The priority of line segment layer allocation is determined based on the number of in-layer conflict relationships, conflict type, total overlap length, line segment length, and estimated line width of each line segment. According to the priority of line segment layer allocation from high to low, construct a layer conflict tree with line segments as nodes and the conflict relationship in the same layer as edges; According to the layer conflict tree, metal layers are assigned to each line segment in descending order of priority. When assigning a metal layer to the current line segment, a metal layer that does not have the same layer conflict relationship with the already assigned line segment and whose direction matches is selected. When there are line segments that cannot be assigned to a metal layer that meets the conflict constraints, the metal layer reallocation of the already assigned line segments is triggered. If all line segments are assigned to a metal layer that meets the conflict constraints after reallocation, a candidate routing topology with metal layer information is output. If no feasible metal layer redistribution scheme exists, the current candidate routing topology is marked as infeasible, and processing is switched to other candidate routing topologies.

[0011] In one embodiment, the step of establishing a linewidth optimization model based on the electrical constraints and the process parameters, and optimizing the linewidth of each segment in the candidate wiring topology with metal layer information to obtain the optimized linewidth includes: Based on the power node location, load node location, and current of each load node in the electrical constraints, the branch current of each line segment and the source-to-load path of each load node are determined in conjunction with the netlist connection relationship. Based on the metal resistance parameters, metal thickness, and maximum allowable current density in the process parameters, the resistance of the line segment is expressed as the reciprocal of the line width, the current density of the line segment is expressed as the reciprocal of the line width, and the cumulative voltage drop of the load node is expressed as the sum of the products of the resistance of each line segment and the corresponding branch current on the source-to-load path. With the goal of minimizing the total wiring area, and with the constraints that the cumulative voltage drop of each load node does not exceed the allowable voltage drop threshold in the electrical constraints, and the current density of each line segment does not exceed the maximum allowable current density in the process parameters, the line width optimization model is established. Based on the linewidth optimization model, the linewidth of each line segment in the candidate wiring topology with metal layer information is optimized to obtain the optimized linewidth.

[0012] In one embodiment, the step of optimizing the line width of each line segment in the candidate wiring topology with metal layer information based on the line width optimization model to obtain the optimized line width includes: According to the linewidth optimization model, the first lower bound and the second lower bound of the linewidth are calculated for each line segment respectively, and the maximum value among the first lower bound of the linewidth, the second lower bound of the linewidth and the minimum linewidth in the process parameters is taken as the feasible lower bound of the linewidth for each line segment. The first lower bound of the linewidth satisfies the voltage drop constraint, and the second lower bound of the linewidth satisfies the electromigration constraint. Using the lower bound of the feasible linewidth as the initial lower bound of the linewidth, the linewidth optimization model is solved analytically to obtain the analytically estimated linewidth of each line segment, and the larger value between the analytically estimated linewidth and the lower bound of the feasible linewidth is used as the initial linewidth of each line segment. Starting from the initial linewidth, the linewidth of each line segment is iteratively updated. After each iteration, the updated linewidth is projected into the feasible interval until the convergence condition is met, and the optimized linewidth is output. The feasible interval is limited based on the minimum linewidth of the process, the lower bound of the first linewidth, and the lower bound of the second linewidth.

[0013] In one embodiment, the step of performing rule checks on the candidate routing topology with metal layer information based on the optimized linewidth, repairing local line segments with rule conflicts by detour, and outputting the target routing result includes: For adjacent line segments in the same metal layer after line width optimization, rule verification is performed based on the optimized line width, the minimum spacing of the corresponding metal layer in the process parameters, and the centerline distance. When a rule conflict is detected, candidate offset directions are generated on both sides of the conflicting line segment. Priority is given to replacing the line segment with the smaller line width in the conflicting line segment with a local U-shaped winding to obtain the intermediate wiring result. The U-shaped winding consists of an offset parallel line segment and two orthogonal connecting line segments. If rule conflicts still exist in the intermediate routing results, continue to perform local offset, layer-change detour, or local rerouting; If the rule conflict is eliminated, the target wiring result is obtained; If no feasible repair solution is found, the current candidate cabling topology is marked as invalid and the process is switched to another candidate cabling topology.

[0014] Furthermore, to achieve the above objectives, this application also proposes a variable linewidth routing apparatus for analog integrated circuits, the variable linewidth routing apparatus for analog integrated circuits comprising: The data acquisition module is used to acquire cabling input data, which includes layout results, netlist connection relationships, port coordinates, obstacle areas, electrical constraints, and process parameters. An obstacle avoidance generation module is used to construct an obstacle avoidance generation map based on the layout result, the process parameters, and the port coordinates. The topology refinement module is used to perform multi-source shortest path search in the obstacle avoidance generation graph based on the netlist connection relationship, and to perform local topology refinement by introducing Steiner points to generate at least one candidate wiring topology that satisfies obstacle constraints. The topology candidate module is used to detect same-layer conflict relationships of line segments in the candidate wiring topology, construct a layer conflict network based on the detected same-layer conflict relationships, allocate metal layers to each line segment in the candidate wiring topology based on the layer conflict network, and output a candidate wiring topology with metal layer information. The linewidth optimization module is used to establish a linewidth optimization model based on the electrical constraints and the process parameters, and to optimize the linewidth of each line segment in the candidate wiring topology with metal layer information to obtain the optimized linewidth. The result output module is used to perform rule checks on the candidate routing topology with metal layer information based on the optimized line width, perform detour repair on local line segments with rule conflicts, and output the target routing result.

[0015] In addition, to achieve the above objectives, this application also proposes an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the variable linewidth routing method for analog integrated circuits as described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: (1) Obtain wiring input data; construct an obstacle avoidance generation map based on the layout results, process parameters, and port coordinates; perform multi-source shortest path search in the obstacle avoidance generation map based on the netlist connection relationship, and perform local topology refinement to generate at least one candidate wiring topology that satisfies obstacle constraints; perform same-layer conflict relationship detection on the line segments in the candidate wiring topology and construct a layer conflict network; allocate metal layers to each line segment in the candidate wiring topology based on the layer conflict network, and output the candidate wiring topology with metal layer information; establish a line width optimization model based on electrical constraints and process parameters, and optimize the line width of each line segment in the candidate wiring topology with metal layer information; perform rule verification and detour repair on the candidate wiring topology based on the optimized line width, and output the target wiring result. For analog integrated circuit power supplies and high-current nets, the full-process collaboration of obstacle avoidance topology, layer allocation, line width optimization, and rule legalization overcomes the defects of rigid line width allocation and disconnect between optimization and rule repair, ensuring power supply stability.

[0017] (2) The technical means of accurately determining the branch current of each line segment and the corresponding source-to-load path by combining electrical constraints and netlist connection relationships provides accurate electrical input for linewidth optimization. Since the line segment resistance, current density, and cumulative voltage drop of the load node are uniformly expressed as linewidth function relationships, the problem of difficulty in quantifying and modeling the coupling relationship between voltage drop, electromigration, and linewidth is solved. Discrete physical constraints are transformed into continuous and solvable mathematical expressions, laying a theoretical foundation for building a unified linewidth optimization model. Since the technical means of constructing a linewidth optimization model with the goal of minimizing the total wiring area and superimposing load node voltage drop constraints and line segment current density constraints is adopted, it is possible to take into account power supply stability, long-term reliability, and wiring resource utilization under a single optimization framework. The technical means of calculating the lower bound of the double linewidth based on voltage drop and electromigration constraints respectively, and then combining the minimum linewidth of the process to determine the lower bound of the feasible linewidth, ensures that the entire optimization process is always carried out within the feasible domain, reducing the probability of constraint violation. The initial linewidth is analytically solved based on the lower bound of the feasible linewidth. Then, the initial linewidth is used as the starting point for iterative updates, and the results are projected onto the feasible interval. This reduces the iterative computation overhead and ensures the global optimality and constraint satisfaction rate of the final result. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the first embodiment of the variable linewidth routing method for analog integrated circuits in this application. Figure 2 This is a schematic diagram illustrating the obstacle avoidance candidate wiring topology generation and local obstacle avoidance repair process of this application; Figure 3 This is a schematic diagram of the line segment conflict detection and metal layer allocation process in this application; Figure 4 This is a schematic diagram illustrating the line segment conflict relationship in this application; Figure 5 This is a schematic diagram of the variable linewidth optimization process based on voltage drop and electromigration constraints in this application; Figure 6 This is a schematic diagram of the overall process of the variable linewidth routing method for analog integrated circuits in this application. Figure 7 This is a schematic diagram showing the variable linewidth routing result and a partial enlargement of this application.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] This application provides a variable linewidth routing method for analog integrated circuits. Specifically, refer to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the variable linewidth routing method for analog integrated circuits according to this application. In this embodiment, the variable linewidth routing method for analog integrated circuits includes steps S10 to S60:

[0024] Step S10: Obtain cabling input data, which includes layout results, netlist connection relationships, port coordinates, obstacle areas, electrical constraints, and process parameters.

[0025] For example, the layout results, netlist connections, port coordinates, and obstacle regions of an analog integrated circuit can be read. The layout results are used to determine device regions, prohibited routing regions, and routable regions. The netlist connections are used to determine the nets that need to be connected, the port coordinates are used to determine the connection endpoints of each net, and obstacle regions include device-occupied areas, pre-routing areas, guard ring areas, or other non-routable areas. Simultaneously, electrical constraints and process parameters related to variable linewidth optimization are read. Electrical constraints include power node locations, load node locations, current at each load node, and allowable voltage drop thresholds. Process parameters include minimum linewidth, minimum spacing, metal thickness, metal resistance parameters, maximum allowable current density, and directional constraints for different metal layers. Using the above data, a unified input is established for subsequent obstacle avoidance routing, layer allocation, and linewidth optimization.

[0026] Step S20: Construct an obstacle avoidance generation map based on the layout results, process parameters, and port coordinates.

[0027] It should be noted that the obstacle avoidance generation graph can be understood as a graph theory model based on candidate nodes and candidate edges. Candidate nodes include port nodes and corner nodes of the extended obstacle region, and candidate edges represent feasible connections between candidate nodes that do not traverse the extended obstacle region. This obstacle avoidance generation graph can provide a foundation for subsequent multi-source shortest path search and candidate wiring topology generation.

[0028] Step S30: Based on the netlist connection relationship, perform multi-source shortest path search in the obstacle avoidance generation graph, and refine the local topology by introducing Steiner points to generate at least one candidate wiring topology that satisfies the obstacle constraints.

[0029] It should be noted that multi-source shortest path search is a graph traversal algorithm strategy that simultaneously searches for the optimal path from multiple starting points, i.e., source ports, to construct a minimum spanning tree or Steiner tree to minimize the total connection length. A Steiner point is a virtual connection point introduced outside the original port to shorten the total length of multi-port interconnections or change the routing path. Introducing Steiner points can optimize the topology, reduce line length, or avoid obstacles. Local topology refinement, based on the initially generated coarse path, fine-tunes the local connection structure by adjusting line segment directions, merging overlapping paths, or smoothing corners to remove redundancy and improve topology quality. Candidate routing topologies refer to one or more possible connection structure schemes that satisfy connectivity and obstacle avoidance requirements, providing a selection space for subsequent optimization.

[0030] Step S40: Detect same-layer conflict relationships for line segments in the candidate wiring topology, construct a layer conflict network based on the detected same-layer conflict relationships, assign metal layers to each line segment in the candidate wiring topology based on the layer conflict network, and output the candidate wiring topology with metal layer information.

[0031] It should be noted that in-layer conflict refers to a design rule violation that occurs when two or more line segments are assigned to the same metal layer and the distance between them is less than the minimum allowable spacing in the process. A layer conflict network can be used to describe the conflict relationships between line segments, where nodes represent line segments to be assigned, and edges represent in-layer conflicts between line segments. Metal layer assignment assigns a specific metal layer to each line segment in the topology, and needs to consider metal layer orientation constraints, parasitic parameters, and inter-layer conflicts.

[0032] Step S50: Based on electrical constraints and process parameters, establish a linewidth optimization model, optimize the linewidth of each segment in the candidate wiring topology with metal layer information, and obtain the optimized linewidth.

[0033] It should be noted that the linewidth optimization model can be a mathematical model that includes an objective function and constraints. The objective function may include routing area terms, voltage drop related terms, and electromigration related terms, while the constraints include voltage drop constraints and current density constraints. By solving this model, the optimal width of each line segment is determined. The optimized linewidth is the actual physical width of the line segment output after calculation by the linewidth optimization model. The optimized linewidth is dynamically adjusted based on the magnitude of the current flowing through the line segment, the properties of the metal layer it is located in, and path sensitivity.

[0034] Step S60: Perform rule checks on the candidate routing topology with metal layer information based on the optimized line width, perform detour repair on local line segments with rule conflicts, and output the target routing result.

[0035] It should be noted that the target routing result can be the final physical layout data output after topology generation, layer allocation, linewidth optimization, and rule correction. For example, the routing result can be checked against the process design rule document to see if it meets physical manufacturing requirements such as minimum width, minimum spacing, and minimum enclosure. When linewidth expansion causes overlap with existing obstacles or other line segments, or when spacing violations occur, the path of the line segment can be locally changed to restore the legality of the design rules.

[0036] In this embodiment, by constructing a generated graph containing obstacle information and performing multi-source search and Steiner point refinement, the problems of single topology and limited solution space in traditional routing methods are solved. This allows for the acquisition of multiple high-quality candidate topologies in the early stages of routing, thereby expanding the possibilities for subsequent optimization. The method of constructing a layer conflict network based on same-layer conflict relationships to guide metal layer allocation solves the problem of metal layer allocation being disconnected from topology, effectively avoiding same-layer spacing conflicts caused by linewidth changes and improving the predictability of routing results. By adopting a method of establishing a linewidth optimization model based on unified electrical constraints and process parameters, the problem of separate handling of voltage drop and electromigration constraints is solved, achieving the utilization of metal resources while meeting power supply stability and long-term reliability requirements. By adopting a method of directly performing rule checks based on optimized linewidth and implementing local detour repair, the contradiction between independent optimization and legalization is resolved, eliminating design rule violations caused by linewidth expansion, and improving the likelihood and efficiency of output results meeting layout generation requirements. This application addresses analog integrated circuit power supplies and high-current networks by overcoming the shortcomings of rigid linewidth allocation and the disconnect between optimization and rule repair through the entire process of obstacle avoidance topology, layer allocation, linewidth optimization and rule legalization, thus ensuring power supply stability.

[0037] In one implementation, step S20 includes: Step S201: Determine the obstacle area based on the layout results.

[0038] For example, all the geometric shapes in the layout result can be analyzed first, and all physical areas that are not allowed to be routed can be filtered out, including the space occupied by the device itself, pre-laid fixed traces, protective rings, design-reserved no-route strips, etc. These areas are uniformly marked as obstacle areas, and the remaining routeable areas can be deduced.

[0039] Step S202: Expand the obstacle area according to the minimum spacing in the process parameters to obtain the expanded obstacle area.

[0040] For example, the original obstacle region is expanded according to the process design rules to obtain an expanded obstacle region. The expanded obstacle region is used to reserve the minimum process spacing and to provide a safety margin for subsequent linewidth increases, avoiding candidate routing topologies from directly approaching device areas, pre-routing areas, or other prohibited routing areas.

[0041] Step S203: Add the port node corresponding to the port coordinates and the corner point of the extended obstacle area to the candidate node set.

[0042] For example, in the obstacle avoidance candidate wiring topology generation stage, net ports and extended obstacle corner points are used as candidate nodes to construct a candidate node set. Subsequently, an obstacle avoidance generation graph is constructed based on the candidate node set.

[0043] Step S204: Perform a directional scan on each candidate node in the candidate node set to find the candidate neighbor nodes of each candidate node in each scan direction and generate candidate edges.

[0044] For example, for each candidate node in the set, a "line of sight" is emitted in a specific direction to find the nearest neighbor node in that direction that can be used as a connection target. Another candidate node located in a specific direction of the current node, found through directional scanning, is a candidate neighbor node. A candidate edge is a virtual line segment connecting a candidate node and its neighbor node. It is the basic unit of the wiring topology and represents the possible connection relationship between two points.

[0045] Step S205: Determine whether each candidate edge crosses the extended obstacle region, and add the candidate edges that do not cross the extended obstacle region to the obstacle avoidance generation graph.

[0046] For example, for each candidate edge, it is determined whether the candidate edge crosses the extended obstacle region. If the candidate edge crosses the extended obstacle region, the candidate edge is discarded. If the candidate edge does not cross the extended obstacle region, the candidate edge is added to the obstacle avoidance generation graph.

[0047] In this embodiment, obstacles are precisely defined based on the layout results, and the obstacle area is expanded in conjunction with the minimum spacing of the process. This solves the problem of insufficient margin in traditional wiring leading to failure of subsequent design rule checks, ensuring that the wiring topology has a safe boundary that meets physical manufacturing requirements from the very beginning. By incorporating port nodes and obstacle corner points into the candidate node set, the problem of node redundancy or path restriction in traditional mesh graphs is solved, allowing wiring paths to flexibly utilize geometric feature points to bypass obstacles, thereby generating shorter and more efficient connection structures. By using directional scanning to generate candidate edges and performing strict obstacle crossing detection on each edge, the contradiction between connectivity and obstacle avoidance during wiring topology generation is resolved, reducing the computational complexity of subsequent path search. By constructing an obstacle avoidance generation graph, the problem of a single topology structure in multi-port net wiring is solved, providing a high-quality underlying graph theory foundation for the subsequent introduction of Steiner points and the generation of diverse candidate wiring topologies. This significantly improves the obstacle avoidance capability and space utilization of the wiring topology, laying a solid legal basis for subsequent metal layer allocation and linewidth optimization.

[0048] In one implementation, step S30 includes: Step S301: Based on the netlist connection relationship, perform multi-source shortest path search in the obstacle avoidance generation graph to obtain the initial port area connection relationship.

[0049] It should be noted that multi-source shortest path search can be understood as a graph traversal algorithm strategy. It simultaneously searches for paths using all ports of the network as starting points, thus obtaining a set of shortest connected paths covering all ports in one go. The initial port area connectivity is the original cabling topology obtained through multi-source shortest path search.

[0050] Step S302: Introduce right-angled Steiner points in the port area connection relationship to perform right-angled transformation and topology refinement of the local connection structure.

[0051] It should be noted that right-angle Steiner points are virtual connection points introduced to meet the Manhattan routing process requirements of analog integrated circuits. They are not original port or obstacle corners, but are used to optimize the connection structure of multi-port networks, shorten bus length, or simplify topology branches. Local connection structures are combinations of line segments within a local area of ​​the initial port region connection relationship, such as connection segments between two ports or intersection segments of three or more ports. Optimization is performed only on this local area, without adjusting the overall topology. Right-angle conversion is the operation of adjusting any non-horizontal or vertical straight lines in the local connection structure into right-angled line segments that meet process requirements, ensuring that the final routing paths are all horizontal or vertical, satisfying layout manufacturing rules. Topology refinement is a local optimization operation performed on the initial coarse topology, including removing redundant corners, merging duplicate line segments, and optimizing intersection point positions, making the topology more compact and the line lengths shorter without compromising connectivity and obstacle avoidance requirements.

[0052] Step S303: Determine whether the introduced Steiner point falls into the extended obstacle area and whether the connecting line segment crosses the extended obstacle area.

[0053] It should be noted that the judgment conditions are related by logical OR.

[0054] Step S304: When the Steiner point falls into the extended obstacle area or the connecting line segment crosses the extended obstacle area, a detour point is generated along the boundary of the extended obstacle area, and the illegal point or illegal line segment is replaced with the detour point to generate a candidate wiring topology.

[0055] For example, if a Steiner point falls into an extended obstacle region or a line segment crosses an extended obstacle region during the refinement process, a detour point is generated along the obstacle boundary, and this detour point replaces the illegal point or illegal line segment. Through the above steps, one or more obstacle avoidance candidate routing topologies that satisfy obstacle constraints are finally output, which are used for subsequent metal layer allocation based on layer conflict tree and linewidth optimization under voltage drop and electromigration constraints. The flowchart for obstacle avoidance candidate topology generation and local obstacle avoidance repair is as follows. Figure 2 As shown, Figure 2This process illustrates the generation of obstacle avoidance candidate wiring topology and the local obstacle avoidance repair: First, obstacles are expanded and a candidate node set is constructed. Then, candidate edges are generated through coordinate transformation and directional scanning, and it is determined whether the candidate edges avoid the expanded obstacles. Candidate edges that meet the obstacle avoidance conditions are added to the obstacle avoidance generation graph, while those that do not are discarded. After scanning, port area connection relationships are further constructed, and local topology refinement is performed. If there are points or line segments blocked by obstacles in the local topology, detour points are generated and local connections are updated. Finally, the obstacle avoidance candidate wiring topology set is output.

[0056] In this embodiment, the technique of performing multi-source shortest path search in the obstacle avoidance generation graph based on netlist connection relationships solves the problems of redundant detours and unreasonable local structures that are easily generated by traditional sequential point-to-point connections. This allows the initial port connection relationship to cover the connectivity requirements of all ports in the network at once, minimizing the bus length of the initial topology while ensuring obstacle avoidance compliance. By introducing right-angled Steiner points to right-angle the local connection structure and refine the topology, the problems of redundant initial topology line lengths, excessive corners, and non-compliance with Manhattan cabling requirements are solved. The bus length can be further shortened by optimizing the connection structure, while providing a more compact topology solution for multi-port networks. By employing techniques to determine whether Steiner points fall into extended obstacle areas and whether connecting segments cross extended obstacle areas, the problem of potentially violating early obstacle avoidance constraints when introducing new connection points is solved. This allows for the timely detection of illegal points or segments generated during topology refinement, avoiding basic compliance issues in subsequent optimizations. By employing a technique that generates detour points along the boundaries of extended obstacles to replace illegal points or illegal line segments, the problem of needing to overturn the entire structure and re-search for local topology obstacle avoidance repair is solved. Obstacle avoidance compliance can be restored by making minimal adjustments to the local illegal parts, significantly reducing the computational overhead of topology repair.

[0057] In one implementation, step S40 includes: Step S401: Determine the projection relationship between any two line segments in the candidate wiring topology on the same metal layer.

[0058] It should be noted that the projection relationship includes the intersection of the planar projections of horizontal and vertical line segments, as well as the overlap of the projection intervals of line segments in the same direction along the routing direction.

[0059] Step S402: When a projection relationship exists, determine whether there is a crossover conflict, overlap conflict, or insufficient spacing conflict between any two line segments based on the estimated line width of the two line segments, the minimum spacing of the corresponding metal layers in the process parameters, and the center line distance of the two line segments.

[0060] For example, the system traverses all horizontal and vertical segments in the candidate obstacle avoidance wiring topology and automatically determines the same-layer conflict relationship between segments based on the segment endpoint coordinates, segment direction, minimum spacing of candidate metal layers, and estimated line width. When a horizontal segment and a vertical segment intersect on the plane projection, they are determined to have an intersection conflict; when the projection intervals of two segments in the same direction overlap and their spacing does not meet the spacing requirements of the corresponding metal layers, they are determined to have an overlap conflict; when two segments do not intersect or overlap continuously, but the distance between their centerlines is less than the safe distance determined by the estimated line width of the two segments and the minimum spacing of the corresponding metal layers, they are determined to have a spacing deficiency conflict.

[0061] In step S403, if there is a cross conflict, an overlapping conflict, or a insufficient spacing conflict, the two line segments are marked as having a conflict relationship at the same level.

[0062] For example, for a pair of line segments that requires further judgment based on spacing requirements, let the estimated line widths of the two line segments be respectively... and The minimum spacing of the candidate metal layers is The distance between their centerlines is If the following conditions are met: Then determine the line segment and line segments In the There are incompatible spacing relationships on the same metal layer. For line segment pairs that intersect, overlap, or have insufficient spacing, they are marked as incompatible relationships on the same layer.

[0063] Step S404: Determine the segment layer allocation priority based on the number of in-layer conflict relationships, conflict type, total overlap length, segment length, and estimated line width for each segment; construct a layer conflict tree with segments as nodes and in-layer conflict relationships as edges, according to the segment layer allocation priority from high to low; allocate metal layers to each segment in order of priority from high to low according to the layer conflict tree, wherein when allocating a metal layer for the current segment, select a metal layer that does not have an in-layer conflict relationship with the already allocated segment and whose direction matches; when there is a segment that cannot be allocated to a metal layer that meets the conflict constraints, trigger the metal layer reallocation of the already allocated segment; if all segments are allocated to metal layers that meet the conflict constraints after reallocation, output a candidate routing topology with metal layer information; if there is no feasible metal layer reallocation scheme, mark the current candidate routing topology as infeasible and switch to other candidate routing topologies for further processing.

[0064] It should be noted that in-layer conflicts include intersection conflicts, overlap conflicts, and insufficient spacing conflicts. For example, the priority of line segment layer allocation is determined according to a hierarchical comparison rule: First, the total number of in-layer conflicts involving the line segment is compared; line segments with a larger total number of in-layer conflicts are given priority in metal layer allocation. When the total number of in-layer conflicts is the same, the conflict types involved in the line segments are compared; line segments involving intersection or overlap conflicts are given priority over line segments involving only insufficient spacing conflicts. When the total number and conflict types of in-layer conflicts are still the same, the total overlap length, line segment length, and estimated line width of the line segments are compared sequentially. Line segments with a larger total overlap length are processed first; when the total overlap lengths are the same, line segments with larger line lengths are processed first. When the line segment lengths are the same, line segments with larger estimated line widths are processed first. Through the above sorting, line segments with complex conflict relationships or those more sensitive to subsequent line width expansion are given priority in layer allocation. As shown in Table 1, when the total number of conflicts for line segments A, B, and C is the same, the system further compares the conflict types and total overlap lengths. Both line segments A and B involve overlapping conflicts, therefore they take precedence over line segment C, which only involves insufficient spacing conflicts. Between line segments A and B, line segment A has a larger total overlap length, therefore line segment A takes precedence over line segment B in metal layer allocation.

[0065] Table 1. Example of line segment conflict sorting index

[0066] Furthermore, a layer conflict tree is constructed based on the sorted line segment conflict network. Nodes in the layer conflict tree correspond to line segments in the obstacle avoidance candidate routing topology, and edges correspond to the incompatibility relationship between two line segments within the same layer. Line segments with higher sorting priority are preferentially assigned as upper-level nodes in the layer conflict tree, and line segments with conflicting relationships with them become their child nodes or associated nodes, thus transforming the geometric conflict relationships between line segments into metal layer allocation constraints. In the initial metal layer allocation stage, the system reads the recommended routing direction, minimum linewidth, minimum spacing, and available layer range for each metal layer from the process parameters. For horizontal line segments, they are preferentially allocated to available metal layers with recommended horizontal routing. For vertical line segments, they are preferentially allocated to available metal layers with recommended vertical routing. For the first... line segment and the first Candidate metal layers, orientation matching cost It can be defined as: line segment Direction and the first When the recommended orientations of all metal layers are consistent Line segment Direction and the first When the recommended orientations of the individual metal layers are inconsistent .

[0067] The system performs initial metal layer allocation according to the priority of line segment conflicts from high to low. Under the premise of satisfying the intra-layer conflict constraints of already allocated line segments, it prioritizes metal layers with matching directions and lower layer usage costs. If a line segment conflicts with an already allocated line segment, or if the current metal layer direction does not match the line segment direction and there is an alternative metal layer that satisfies the conflict constraints, then the metal layer adjustment for that line segment is triggered. After the initial allocation, the system further calculates the metal layer usage cost and, under the premise of satisfying the conflict constraints, performs reallocation optimization on some line segments. The metal layer usage cost can be expressed as:

[0068]

[0069] in, Indicates the number of available metal layers. Indicates allocation to the first Number of line segments in each metal layer Indicates the first To reduce unnecessary occupancy of high-level metal layers, the usage weight of each metal layer is set in a non-decreasing manner according to the metal layer number, meaning that the usage weight of a higher metal layer is no less than the usage weight of a lower metal layer. . This indicates the number of vias or the number of layer switches introduced by metal layer switching. This represents the through-hole cost weight. Represents line segment The currently allocated metal layer, Represents line segment The cost of orientation matching with its current metal layer. This indicates the cost weight for direction mismatch. and These are used to characterize the layer switching cost and the orientation mismatch cost, respectively, and are weighted in conjunction with the metal layer. The corresponding constraint objects are different, therefore it is not required to be the same as... A fixed size relationship is maintained. For example, when the available metal layers are M1 to M4, the weights of the metal layers can be selected sequentially as 1.0, 1.2, 1.5, and 2.0. You can select from the range of 1.0 to 3.0. The value can be selected within the range of 0.5 to 2.0. The above values ​​are used to illustrate the relative setting method of different cost items and do not limit the specific values ​​of each weight coefficient in this application.

[0070] If after a certain reassignment there are no conflicts such as intersections, overlaps, or insufficient spacing at the same level, and If the cost of using a metal layer is less than the cost before redistribution, the redistribution is accepted. Otherwise, the original allocation is retained and other alternative metal layers are evaluated. Conflict checking, layer allocation adjustment, and cost comparison are repeated until all conflicting segments meet the metal layer allocation constraints, or no feasible adjustment scheme exists that can further reduce the cost of using metal layers. The final output is an obstacle avoidance candidate routing topology with metal layer information, used for subsequent variable linewidth optimization and design rule validation. A schematic diagram of the segment conflict detection and metal layer allocation process is shown below. Figure 3 As shown, the process first identifies the intersections, overlaps, and insufficient spacing between line segments, and then constructs the line segment conflict relationships. (Reference) Figure 4 An intersection occurs when a horizontal line segment and a vertical line segment intersect on a plane projection, such as... Figure 4 In the text 'a', overlapping conflict indicates that the projection intervals of two line segments traveling in the same direction overlap, such as... Figure 4 In the context of line segment b, insufficient spacing conflict indicates that although two line segments do not intersect or overlap continuously, their spacing is less than the minimum spacing requirement of the corresponding metal layer. Figure 4 c. The three types of conflicts mentioned above collectively constitute the incompatible relationships between line segments at the same layer, serving as the basis for subsequent layer conflict tree construction and metal layer allocation. Subsequently, the line segment layer allocation priority is determined based on the total number of in-layer conflict relationships, conflict type, total overlap length, line segment length, and estimated line width. A layer conflict tree is then constructed, and initial metal layer allocation is performed. If in-layer conflicts still exist after allocation, the metal layer of the conflicting line segments is adjusted, and the conflict tree is updated until no in-layer conflicts remain. Finally, the cost of metal layer usage is further optimized, and the routing topology with metal layer information is output.

[0071] In this embodiment, a technique based on projection relationships to comprehensively detect potential conflicts between line segments solves the problem of traditional methods ignoring overlapping or non-intersecting close-range violations of line segments in the same direction, enabling conflict detection to cover three key scenarios: intersection, overlap, and insufficient spacing. By employing a quantitative judgment technique combining estimated line width, minimum process spacing, and centerline distance, it addresses the inability to predict new conflicts arising from line width expansion under a fixed line width approach, providing forward-looking rule guarantees for variable line width routing. By using a technique to determine layer allocation priority based on the number and type of conflicts, it solves the problem that simple sequential allocation can lead to unmanageable complex conflict line segments later on, ensuring that line segments with dense conflicts or sensitive to line width changes receive priority access to suitable metal layer resources. By employing a technique to construct a layer conflict tree and guide allocation and reallocation, it solves the global optimization problem under multi-segment conflict constraints, reducing the number of unnecessary vias or layer switching while improving the ability of line segments to meet same-layer spacing constraints.

[0072] In one implementation, step S50 includes: Step S501: Based on the power node location, load node location, and current of each load node in the electrical constraints, determine the branch current of each line segment and the source-to-load path of each load node in conjunction with the netlist connection relationship.

[0073] For example, for the first A line segment, let the length of the line segment be... The line width is The branch current is The metal thickness is The metal resistance parameters are Then the resistance of the line segment Represented as:

[0074] For the There are load nodes, and their source-to-load paths are denoted as . The cumulative voltage drop at the load node is then expressed as:

[0075] The summation range is from the power node to the load node. All segments on the power supply path.

[0076] Step S502: Based on the metal resistance parameters, metal thickness, and maximum allowable current density in the process parameters, the resistance of the line segment is expressed as the reciprocal of the line width, the current density of the line segment is expressed as the reciprocal of the line width, and the cumulative voltage drop of the load node is expressed as the sum of the products of the resistance of each line segment and the corresponding branch current on the source-to-load path.

[0077] For example, for the first Current density of line segment Represented as:

[0078] For any load node, when When the voltage drop constraint is met, the source-to-load path satisfies the voltage drop constraint. Conversely, the voltage drop constraint is violated. For any line segment, when... If the line segment satisfies the electromigration constraint, it does so; otherwise, it violates the electromigration constraint. For a shared backbone line segment that belongs to multiple source-to-load paths, the change in the line width of this segment will simultaneously affect the cumulative voltage drop of multiple load nodes and is limited by the current density constraint of the line segment itself. Therefore, in the variable line width optimization process, the line width update of the shared backbone line segment is jointly determined by the voltage drop constraint of its source-to-load path, the electromigration constraint of the line segment, and the wiring area constraint. Based on the above voltage drop and electromigration constraint relationship, the line width optimization process can determine the line width adjustment direction of each line segment by combining the wiring topology, branch current, line segment length, source-to-load path relationship, and process parameters.

[0079] Step S503: With the goal of minimizing the total wiring area, and with the constraints that the cumulative voltage drop of each load node does not exceed the allowable voltage drop threshold in the electrical constraints, and the current density of each line segment does not exceed the maximum allowable current density in the process parameters, a line width optimization model is established.

[0080] For example, the objective function of the variable linewidth optimization model includes a wiring area term, a voltage drop constraint term, and an electromigration constraint term, which can be expressed as:

[0081] in, Total cabling area For voltage drop related terms, For items related to electromigration, , and These are the weighting coefficients for the area, voltage drop, and electromigration terms, respectively. The area term constrains the increase in wiring area caused by increased linewidth, the voltage drop term constrains the cumulative voltage drop along the source-to-load path, and the electromigration term constrains the segment current density. By unifying these three types of objective terms into the same objective function, the linewidth optimization process can coordinate the wiring area, cumulative voltage drop, and segment current density.

[0082] It should be noted that, since the area term, voltage drop term, and electromigration term have different physical meanings and numerical scales, the linewidth initialization should be performed before... , and Adjustments are made to balance the effective contributions of the three types of objective terms to the objective function. Specifically, the initial values ​​of the three are set as follows: The three can be limited to the following range: The coefficient adjustment step size is set to... =0.1. Under analytical estimation of linewidth, the area occupancy index, path voltage drop index, and line segment current density index are calculated respectively, and the objective function coefficients are updated accordingly.

[0083] For example, suppose This represents the wiring area corresponding to the analytically estimated line width. Indicating the reference cabling area, the area occupancy index is:

[0084] in, It can be determined based on the area corresponding to the minimum linewidth in the process, the available wiring area of ​​the candidate topology, or the design area budget. When If the estimated wiring area exceeds the reference wiring area, then the area term weight is updated. : .

[0085] set up Indicates the first linewidth under analytical estimation. The cumulative voltage drop at each load node, This indicates the maximum allowable voltage drop at the load node; therefore, the path voltage drop index is:

[0086] when If at least one source-to-load path has a cumulative voltage drop exceeding its allowable voltage drop, then the voltage drop term weight is updated. : .

[0087] set up Indicates the first linewidth under analytical estimation. Current density of the line segment, This indicates the maximum allowable current density in the metal layer containing the line segment. Therefore, the line segment current density index is:

[0088] when If at least one line segment has a current density exceeding its allowable current density, then the electromigration term weights are updated. :

[0089] like If the number of coefficient adjustments reaches the preset limit, then stop adjusting the coefficients and select the current value. , and These serve as the objective function coefficients in subsequent linewidth initialization and iterative optimization. Through this method, area occupancy, cumulative voltage drop, and segment current density are transformed into calculable coefficient adjustment criteria, enabling the objective function coefficients to be updated based on the current candidate topology and the constraint satisfaction of the analytically estimated linewidth.

[0090] Step S504: Based on the linewidth optimization model, optimize the linewidth of each line segment in the candidate wiring topology with metal layer information to obtain the optimized linewidth.

[0091] Specifically, step S504 includes: calculating the first lower bound and the second lower bound of the line width for each line segment according to the line width optimization model, and taking the maximum value among the first lower bound, the second lower bound, and the minimum line width in the process parameters as the feasible lower bound of each line segment; using the feasible lower bound as the initial lower bound of the line width, performing analytical solution on the line width optimization model to obtain the analytical estimated line width of each line segment, and taking the larger value between the analytical estimated line width and the feasible lower bound as the initial line width of each line segment; starting from the initial line width, iteratively updating the line width of each line segment, and projecting the updated line width into the feasible interval after each iteration until the convergence condition is met, and outputting the optimized line width.

[0092] It should be noted that the first lower bound of the linewidth satisfies the voltage drop constraint, and the second lower bound of the linewidth satisfies the electromigration constraint. The feasible interval is limited based on the minimum process linewidth, the first lower bound of the linewidth, and the second lower bound of the linewidth. Starting from the initial linewidth, the steps for iteratively updating the linewidth of each segment include: organizing the linewidth variables of multiple nets into a linewidth matrix, where the columns of the linewidth matrix correspond to nets and the rows correspond to line segments; calculating the objective function value and its gradient under the current linewidth matrix, and updating the linewidth matrix using an adaptive moment estimation optimization method; after each update, projecting each linewidth in the linewidth matrix into the corresponding feasible interval; when both the voltage drop constraint and the electromigration constraint in the linewidth optimization model are satisfied and the change in the objective function is less than a preset threshold, the current linewidth optimization is considered to have converged.

[0093] For example, the lower bound of the feasible linewidth for each line segment is calculated based on voltage drop constraints, electromigration constraints, and the minimum process linewidth. For the... The lower bound of the line width of a line segment, obtained by voltage drop constraint, is expressed as follows:

[0094]

[0095] For a shared line segment belonging to multiple source-to-load paths, its linewidth requirement can be calculated separately based on the allowable voltage drop requirements corresponding to different source-to-load paths, and the larger value can be taken as the lower bound of the voltage drop constraint linewidth for that line segment. The first line segment obtained from the electromigration constraint... The lower bound of the line segment width is represented as follows:

[0096]

[0097] Taking into account voltage drop constraints, electromigration constraints, and minimum process linewidth, the first The lower bound of the feasible line width of a line segment is expressed as: , where This indicates the minimum linewidth of the metal layer containing the line segment. This represents the lower bound of the feasible linewidth, determined jointly by voltage drop constraints, electromigration constraints, and minimum process linewidth.

[0098] After obtaining the lower bound of the feasible linewidth, based on the joint objective function of the area term, voltage drop term, and electromigration term mentioned above, the linewidth variable is... Perform analytical estimation. Without amplifying the constraint penalty term, the objective function can be expressed as:

[0099]

[0100] right To find the first-order stationary condition, we can obtain the... The analytical estimate of the line width of a line segment is expressed as:

[0101] Subsequently, the linewidth will be analytically estimated. Lower bound of feasible linewidth Compare the two values ​​and select the larger one as the first value. The line segment is then incorporated into the initial line width before subsequent iterations of optimization. This analytical initialization method allows line width optimization to begin near the feasible region, reducing constraint violations caused by random initialization and improving the convergence stability and computational efficiency of variable line width optimization.

[0102] For multiple meshes, the linewidth variables in different meshes can be organized into a linewidth matrix. Line width matrix Each column corresponds to a mesh, and each row corresponds to the segment number within that mesh. When different meshes contain different numbers of segments, missing segments are padded with zeros in the matrix, and a corresponding mask matrix is ​​set.

[0103] In the linewidth optimization process, the resistance, current density, load node voltage drop, and total wiring area of ​​each line segment are first calculated based on the current linewidth matrix, and then the joint objective function is calculated. Subsequently, the gradient of the objective function with respect to the linewidth matrix is ​​calculated, and the linewidth matrix is ​​updated using an adaptive moment estimation optimization method. This optimization method adaptively adjusts the gradient direction and magnitude through first-order and second-order moment estimation, thereby improving the convergence stability of the linewidth optimization.

[0104] After each linewidth update, the linewidth is projected onto a feasible region jointly determined by the minimum process linewidth, voltage drop constraint, and electromigration constraint. If the voltage drop or electromigration constraint is not satisfied, the linewidth is iteratively updated again. If the constraints are satisfied and the change in the objective function is less than a preset threshold, the linewidth optimization of the current candidate routing topology is considered to have converged, and the linewidth allocation, total area, voltage drop statistics, and current density statistics of the current candidate topology are saved. If multiple candidate topologies exist, the above linewidth optimization process is executed for each, and the topology and linewidth with the optimal overall cost are selected as the final output. Figure 5 This diagram illustrates the variable linewidth optimization process based on voltage drop and electromigration constraints. Taking obstacle avoidance topology segment results and process constraints as input, it reads power node, load node, current information, and allowable voltage drop. Then, it parses the multi-line network, selects the current candidate routing topology, constructs a directed tree rooted at the power node, and calculates the branch current of each segment and the source-to-load path. It further calculates the minimum process linewidth, the lower bound of the voltage drop constraint linewidth, and the lower bound of the electromigration constraint linewidth, and initializes the linewidth variables. During linewidth iteration, it calculates the joint objective function of area, voltage drop, and electromigration, updates the linewidth using the Adam method, and performs voltage drop constraint projection and electromigration constraint projection. If the voltage drop and electromigration constraints are not satisfied or the objective function does not converge, the iteration continues. If the constraints are satisfied and convergence occurs, the optimal routing topology, linewidth, and statistical results are output.

[0105] In this embodiment, the technical means of accurately determining the branch current of each line segment and the corresponding source-to-load path by combining electrical constraints and netlist connection relationships solves the problems of not being able to distinguish the current load of different line segments and not being able to accurately calculate the voltage drop of each load node. It can truly restore the electrical transmission characteristics of the cabling topology and provide accurate electrical input for linewidth optimization. By uniformly representing the line segment resistance, current density, and cumulative voltage drop of the load node as a linewidth function relationship, the problem of difficulty in quantifying and modeling the coupling relationship between voltage drop, electromigration, and linewidth is solved. Discrete physical constraints are transformed into continuous and solvable mathematical expressions, laying a theoretical foundation for building a unified linewidth optimization model. By adopting the technical means of constructing a linewidth optimization model with the goal of minimizing the total cabling area and simultaneously superimposing load node voltage drop constraints and line segment current density constraints, it is possible to simultaneously consider power supply stability, long-term reliability, and cabling resource utilization within a single optimization framework. The technical means of calculating two linewidth lower bounds based on voltage drop and electromigration constraints respectively, and then combining them with the minimum process linewidth to determine the feasible linewidth lower bound, ensures that the entire optimization process is always carried out within the feasible domain, reducing the probability of constraint violation. The initial linewidth is analytically solved based on the lower bound of the feasible linewidth. Then, the initial linewidth is used as the starting point for iterative updates, and the results are projected onto the feasible interval. This reduces the iterative computation overhead and improves the convergence stability and constraint satisfaction rate of the linewidth optimization results.

[0106] It should be noted that since variable linewidth optimization may increase the linewidth of some line segments, adjacent line segments that originally met the spacing constraints may encounter new design rule conflicts. Based on this, in one embodiment, step S60 includes: for adjacent line segments in the same metal layer after linewidth optimization, rule checks are performed based on the optimized linewidth, the minimum spacing of the corresponding metal layer in the process parameters, and the centerline distance; when a rule conflict is detected, candidate offset directions are generated on both sides of the conflicting line segment, and the line segment with the smaller linewidth in the conflicting line segment is replaced with a local U-shaped loop to obtain the intermediate routing result; if a rule conflict still exists in the intermediate routing result, local offset, layer-changing loop, or local rerouting is continued; if the rule conflict is eliminated, the target routing result is obtained; if no feasible repair solution exists, the current candidate routing topology is marked as unvalid, and the process is switched to other candidate routing topologies for further processing.

[0107] The steps prior to the design rule check include: expanding the original obstacles according to the minimum spacing in the process parameters during the candidate routing topology generation stage; performing same-layer conflict detection according to the estimated line width of each line segment during the metal layer allocation stage; and checking the spacing between adjacent line segments in the same metal layer according to the actual line width after line width optimization during the design rule check step.

[0108] It should be noted that the U-shaped winding consists of one offset parallel line segment and two orthogonal connecting line segments. For example, for adjacent line segments within the same metal layer, the design rule check is performed using the centerline distance criterion from the metal layer allocation stage. Let the line segments... and line segments The optimized line widths are respectively and The minimum spacing between the two metal layers is The distance between their centerlines is If the following conditions are met:

[0109]

[0110] Then determine the line segment and line segments Spacing conflicts exist on the current metal layer. Unlike the metal layer allocation stage, which uses estimated linewidth to determine potential in-layer conflicts, the legalization stage uses the actual linewidth after linewidth optimization to determine final design rule conflicts. For conflicting local segments, a local U-shaped routing method can be used for repair. The U-shaped routing consists of one offset parallel segment and two orthogonal connecting segments, eliminating local spacing conflicts caused by increased linewidth while maintaining port connection and electrical connection relationships. Specifically, the system can generate candidate offset directions on both sides of the conflicting segment and prioritize U-shaped replacement of segments with smaller linewidths or lower local routing costs to reduce the additional wiring area and local congestion introduced by the routing. If new spacing conflicts still exist after U-shaped routing, local offset, layer-change routing, or local rerouting continues until the final routing result passes the design rule check. After repair, the design rule check is performed again until the final routing result meets the process rules.

[0111] The overall method flowchart of the embodiments and implementation methods of this application is as follows: Figure 6 As shown, the input includes layout results, netlists, and process technology documents. This figure illustrates the overall technical approach of this application: First, obstacle avoidance candidate routing topologies are generated to obtain candidate routing topologies that satisfy obstacle constraints. Then, layer allocation is performed based on a conflict tree to obtain routing topologies with metal layer information. Further, under different metal layer constraints, voltage drop constraints, electromigration constraints, and routing area optimization objectives, variable linewidth optimization is performed on multiple nets. Finally, design rule-driven legalization processing is used to repair local conflicts that may arise after linewidth expansion, outputting the final layout result. The final layout result is shown below. Figure 7 The diagram illustrates the layout of the final output of this application, including device regions, routing paths, and local interconnect structures. Different interconnect segments are assigned corresponding linewidths based on their branch current, source-to-load path voltage drop, and the process constraints of the metal layer they reside in. For main paths with higher current or voltage drop sensitivity, the routing linewidth is relatively increased. For branch paths with lower current, the routing linewidth is relatively decreased. The magnified local area demonstrates the actual interconnect configuration after linewidth optimization, illustrating that this application can generate variable-width routing results suitable for layout implementation while meeting voltage drop and electromigration constraints.

[0112] In this implementation, the technique of performing final rule verification based on the optimized actual linewidth rather than the estimated linewidth solves the problem of undetected implicit spacing conflicts after linewidth expansion, ensuring that the final output fully meets manufacturing requirements in terms of physical dimensions. By prioritizing local U-shaped routing replacement of the smaller linewidth among conflicting segments, the issue of unnecessary increases in routing area due to conflict repair is resolved, minimizing the area overhead introduced by routing while ensuring a high repair success rate. Furthermore, the hierarchical repair strategy of iteratively executing local offsets, layer-switching, or rerouting on intermediate results addresses the difficulty of handling complex congestion scenarios with a single repair method, effectively avoiding iterative oscillations caused by local updates in traditional methods.

[0113] Based on the same inventive concept, this application also provides a variable linewidth routing device for analog integrated circuits, the variable linewidth routing device for analog integrated circuits comprising: The data acquisition module is used to acquire cabling input data, which includes layout results, netlist connection relationships, port coordinates, obstacle areas, electrical constraints, and process parameters. An obstacle avoidance generation module is used to construct an obstacle avoidance generation map based on the layout result, the process parameters, and the port coordinates. The topology refinement module is used to perform multi-source shortest path search in the obstacle avoidance generation graph based on the netlist connection relationship, and to perform local topology refinement by introducing Steiner points to generate at least one candidate wiring topology that satisfies obstacle constraints. The topology candidate module is used to detect same-layer conflict relationships of line segments in the candidate wiring topology, construct a layer conflict network based on the detected same-layer conflict relationships, allocate metal layers to each line segment in the candidate wiring topology based on the layer conflict network, and output a candidate wiring topology with metal layer information. The linewidth optimization module is used to establish a linewidth optimization model based on the electrical constraints and the process parameters, and to optimize the linewidth of each line segment in the candidate wiring topology with metal layer information to obtain the optimized linewidth. The result output module is used to perform rule checks on the candidate routing topology with metal layer information based on the optimized line width, perform detour repair on local line segments with rule conflicts, and output the target routing result.

[0114] It should be noted that the variable linewidth routing device for analog integrated circuits provided in this application embodiment and the variable linewidth routing method for analog integrated circuits provided in this application embodiment are based on the same application concept. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned variable linewidth routing method for analog integrated circuits, and the repeated parts will not be described again.

[0115] In some embodiments, an electronic device provided in this application includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the above-described variable linewidth routing method for analog integrated circuits.

[0116] Specifically, the processor may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor may also include onboard memory for caching purposes. The processor may be a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of this application.

[0117] Memory can be any medium capable of containing, storing, transmitting, propagating, or transmitting instructions. For example, memory can include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, instruments, or propagation media. Specific examples of memory include: magnetic storage devices such as magnetic tape or hard disk drives (HDDs); optical storage devices such as optical discs (CD-ROMs); and also random access memory (RAM) or flash memory; and / or wired / wireless communication links.

[0118] This application also provides a non-transitory storage medium storing a computer program that, when executed by a processor, implements the aforementioned variable linewidth routing method for analog integrated circuits. This storage medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into that device / apparatus / system. The aforementioned non-transitory storage medium carries one or more programs, which, when executed, implement the methods described in the embodiments or implementations of this application.

[0119] According to embodiments of this application, a non-transitory storage medium can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. A computer-readable signal medium can also be any storage medium other than a computer-readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wired, optical fiber, radio frequency signals, etc., or any suitable combination thereof.

[0120] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0121] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Therefore, the scope of this application should not be limited to the above embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A variable linewidth routing method for analog integrated circuits, characterized in that, The method includes: Obtain cabling input data, which includes layout results, netlist connection relationships, port coordinates, obstacle areas, electrical constraints, and process parameters; An obstacle avoidance generation map is constructed based on the layout results, the process parameters, and the port coordinates; Based on the netlist connection relationship, multi-source shortest path search is performed in the obstacle avoidance generation graph, and local topology refinement is performed by introducing Steiner points to generate at least one candidate wiring topology that satisfies obstacle constraints. The same-layer conflict relationship is detected for the line segments in the candidate routing topology. A layer conflict network is constructed based on the detected same-layer conflict relationship. Metal layers are assigned to each line segment in the candidate routing topology based on the layer conflict network, and a candidate routing topology with metal layer information is output. Based on the electrical constraints and the process parameters, a linewidth optimization model is established, and the linewidth of each line segment in the candidate wiring topology with metal layer information is optimized to obtain the optimized linewidth. Based on the optimized linewidth, the candidate routing topology with metal layer information is subjected to rule verification, and local line segments with rule conflicts are repaired by detour, and the target routing result is output.

2. The method as described in claim 1, characterized in that, The step of constructing an obstacle avoidance generation map based on the layout result, the process parameters, and the port coordinates includes: The obstacle area is determined based on the layout results; The obstacle region is expanded according to the minimum spacing in the process parameters to obtain the expanded obstacle region; Add the port node corresponding to the port coordinates and the corner point of the extended obstacle region to the candidate node set; Perform a directional scan on each candidate node in the candidate node set to find the candidate neighbor nodes of each candidate node in each scan direction and generate candidate edges; Determine whether each candidate edge crosses the extended obstacle region, and add the candidate edges that do not cross the extended obstacle region to the obstacle avoidance generation graph.

3. The method as described in claim 2, characterized in that, The step of performing multi-source shortest path search in the obstacle avoidance generation graph based on the netlist connection relationship, and generating at least one candidate wiring topology that satisfies obstacle constraints by introducing Steiner points for local topology refinement, includes: Based on the netlist connection relationship, a multi-source shortest path search is performed in the obstacle avoidance generation graph to obtain the initial port area connection relationship. A right-angled Steiner point is introduced into the port region connection relationship to make the local connection structure right-angled and topologically refined; Determine whether the introduced Steiner point falls within the extended obstacle area and whether the connecting line segment crosses the extended obstacle area; When the Steiner point falls into the extended obstacle region or the connecting line segment crosses the extended obstacle region, a detour point is generated along the boundary of the extended obstacle region, and the illegal point or illegal line segment is replaced with the detour point to generate a candidate wiring topology.

4. The method as described in claim 1, characterized in that, The step of detecting same-layer conflict relationships among line segments in the candidate wiring topology includes: Determine the projection relationship between any two line segments in the candidate routing topology on the same metal layer. The projection relationship includes the intersection of the planar projections of horizontal and vertical line segments, and the overlap of the projection intervals of line segments in the same direction in the routing direction. When the projection relationship exists, based on the estimated line width of the two line segments, the minimum spacing of the corresponding metal layers in the process parameters, and the centerline distance of the two line segments, it is determined whether there is a cross conflict, an overlap conflict, or a insufficient spacing conflict between any two line segments. If there are intersection conflicts, overlapping conflicts, or insufficient spacing conflicts, the two line segments will be marked as having a conflict relationship at the same level.

5. The method as described in claim 4, characterized in that, The step of constructing a layer conflict network based on the detected same-layer conflict relationships, allocating metal layers to each segment in the candidate routing topology based on the layer conflict network, and outputting a candidate routing topology with metal layer information includes: The priority of line segment layer allocation is determined based on the number of in-layer conflict relationships, conflict type, total overlap length, line segment length, and estimated line width of each line segment. According to the priority of line segment layer allocation from high to low, construct a layer conflict tree with line segments as nodes and the conflict relationship in the same layer as edges; According to the layer conflict tree, metal layers are assigned to each line segment in descending order of priority. When assigning a metal layer to the current line segment, a metal layer that does not have the same layer conflict relationship with the already assigned line segment and whose direction matches is selected. When there are line segments that cannot be assigned to a metal layer that meets the conflict constraints, the metal layer reallocation of the already assigned line segments is triggered. If all line segments are assigned to a metal layer that meets the conflict constraints after reallocation, a candidate routing topology with metal layer information is output. If no feasible metal layer redistribution scheme exists, the current candidate routing topology is marked as infeasible, and processing is switched to other candidate routing topologies.

6. The method as described in claim 1, characterized in that, The step of establishing a linewidth optimization model based on the electrical constraints and the process parameters, and optimizing the linewidth of each segment in the candidate wiring topology with metal layer information to obtain the optimized linewidth includes: Based on the power node location, load node location, and current of each load node in the electrical constraints, the branch current of each line segment and the source-to-load path of each load node are determined in conjunction with the netlist connection relationship. Based on the metal resistance parameters, metal thickness, and maximum allowable current density in the process parameters, the resistance of the line segment is expressed as the reciprocal of the line width, the current density of the line segment is expressed as the reciprocal of the line width, and the cumulative voltage drop of the load node is expressed as the sum of the products of the resistance of each line segment and the corresponding branch current on the source-to-load path. With the goal of minimizing the total wiring area, and with the constraints that the cumulative voltage drop of each load node does not exceed the allowable voltage drop threshold in the electrical constraints, and the current density of each line segment does not exceed the maximum allowable current density in the process parameters, the line width optimization model is established. Based on the linewidth optimization model, the linewidth of each line segment in the candidate wiring topology with metal layer information is optimized to obtain the optimized linewidth.

7. The method as described in claim 6, characterized in that, The step of optimizing the line width of each line segment in the candidate wiring topology with metal layer information based on the line width optimization model to obtain the optimized line width includes: According to the linewidth optimization model, the first lower bound and the second lower bound of the linewidth are calculated for each line segment respectively, and the maximum value among the first lower bound of the linewidth, the second lower bound of the linewidth and the minimum linewidth in the process parameters is taken as the feasible lower bound of the linewidth for each line segment. The first lower bound of the linewidth satisfies the voltage drop constraint, and the second lower bound of the linewidth satisfies the electromigration constraint. Using the lower bound of the feasible linewidth as the initial lower bound of the linewidth, the linewidth optimization model is solved analytically to obtain the analytically estimated linewidth of each line segment, and the larger value between the analytically estimated linewidth and the lower bound of the feasible linewidth is used as the initial linewidth of each line segment. Starting from the initial linewidth, the linewidth of each line segment is iteratively updated. After each iteration, the updated linewidth is projected into the feasible interval until the convergence condition is met, and the optimized linewidth is output. The feasible interval is limited based on the minimum linewidth of the process, the lower bound of the first linewidth, and the lower bound of the second linewidth.

8. The method according to any one of claims 1 to 7, characterized in that, The steps of performing rule checks on the candidate routing topology with metal layer information based on the optimized linewidth, repairing local line segments with rule conflicts by detours, and outputting the target routing result include: For adjacent line segments in the same metal layer after line width optimization, rule verification is performed based on the optimized line width, the minimum spacing of the corresponding metal layer in the process parameters, and the centerline distance. When a rule conflict is detected, candidate offset directions are generated on both sides of the conflicting line segment. Priority is given to replacing the line segment with the smaller line width in the conflicting line segment with a local U-shaped winding to obtain the intermediate wiring result. The U-shaped winding consists of an offset parallel line segment and two orthogonal connecting line segments. If rule conflicts still exist in the intermediate routing results, continue to perform local offset, layer-change detour, or local rerouting; If the rule conflict is eliminated, the target wiring result is obtained; If no feasible repair solution is found, the current candidate cabling topology is marked as invalid and the process is switched to another candidate cabling topology.

9. A variable linewidth wiring device for analog integrated circuits, characterized in that, The variable linewidth wiring device for analog integrated circuits includes: The data acquisition module is used to acquire cabling input data, which includes layout results, netlist connection relationships, port coordinates, obstacle areas, electrical constraints, and process parameters. An obstacle avoidance generation module is used to construct an obstacle avoidance generation map based on the layout result, the process parameters, and the port coordinates. The topology refinement module is used to perform multi-source shortest path search in the obstacle avoidance generation graph based on the netlist connection relationship, and to perform local topology refinement by introducing Steiner points to generate at least one candidate wiring topology that satisfies obstacle constraints. The topology candidate module is used to detect same-layer conflict relationships of line segments in the candidate wiring topology, construct a layer conflict network based on the detected same-layer conflict relationships, allocate metal layers to each line segment in the candidate wiring topology based on the layer conflict network, and output a candidate wiring topology with metal layer information. The linewidth optimization module is used to establish a linewidth optimization model based on the electrical constraints and the process parameters, and to optimize the linewidth of each line segment in the candidate wiring topology with metal layer information to obtain the optimized linewidth. The result output module is used to perform rule checks on the candidate routing topology with metal layer information based on the optimized line width, perform detour repair on local line segments with rule conflicts, and output the target routing result.

10. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the variable linewidth routing method for analog integrated circuits as claimed in any one of claims 1 to 8.

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