Clock tree generation method and apparatus, electronic device, and storage medium

Abstract

The application provides a clock tree generation method and device, electronic equipment and storage medium, and belongs to the technical field of integrated circuit design. By modifying the cell type attribute in the library file of the custom macro cell buffer, the custom macro cell buffer is disguised as a standard cell buffer, thereby overcoming the problem that the identification error or the operation is interrupted when the custom macro cell buffer is directly input in the related technical solution. The clock tree is automatically constructed in cooperation with the placement position constraint of the virtual standard cell buffer. Through the replacement operation of the virtual standard cell buffer in the clock tree, the custom macro cell buffer is included in the clock tree, the clock tree including the custom macro cell buffer is constructed, and the application scene of adapting to the customized high-performance buffer is constructed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a method, apparatus, electronic device, and storage medium for generating a clock tree. Background Technology

[0002] In the field of integrated circuit design, Clock Tree Synthesis (CTS) is a crucial step in ensuring chip timing convergence. A clock tree refers to a network topology that distributes clock signals from the clock source point to various timing components of the chip stably, with low latency and low deviation. Commonly used clock tree implementations for high-performance chips include Flexible H-Tree, Fishbone clock tree, and Clock Mesh.

[0003] The most widely used method at present is the flexible H-tree. With the flexible H-tree, users only need to set the key parameters and use only one command to complete the automatic planning of the entire FlexH-Tree, the insertion of tap points and the routing.

[0004] However, the clock trunk unit of the flexible H-tree clock tree implementation is strictly limited to a standard unit buffer and does not support custom macro unit buffers, which limits the application scenarios of the flexible H-tree approach. Summary of the Invention

[0005] This invention provides a method, apparatus, electronic device, and storage medium for generating clock trees, which solves the problem that in the prior art, the clock backbone unit is strictly limited to a standard unit buffer and does not support custom macro unit buffers, thus limiting the application scenarios of the flexible H-tree method.

[0006] This invention provides a method for generating a clock tree, comprising the following steps.

[0007] In response to the clock tree generation instruction, modify the cell category attribute in the library file of the custom macro cell buffer to generate a virtual standard cell buffer that is consistent with the cell category attribute of the standard cell buffer. Construct placement constraints for the virtual standard cell buffer; A clock tree is generated based on the virtual standard unit buffer and the placement constraints of the virtual standard unit buffer; Replace the virtual standard cell buffer in the clock tree with the custom macro cell buffer to obtain a clock tree that supports the custom macro cell buffer.

[0008] According to a method for generating a clock tree provided by the present invention, the placement constraints include unit site constraints and / or blocking constraints. The unit site constraint is used to constrain the movement and placement of the virtual standard unit buffer on a first grid, which is the grid defined by the unit site constraint. The blocking constraint uses a blocking layer to constrain the placement position of the virtual standard unit buffer in a first direction.

[0009] According to a clock tree generation method provided by the present invention, when the placement constraints include cell site constraints, the step of constructing the placement constraints of the virtual standard cell buffer includes: Add a new cell site to the library file of the virtual standard cell buffer; Determine a first length of the preset power rail pitch in the first direction, and a second length of the preset power rail pitch in a second direction, wherein the second direction is perpendicular to the first direction; The first length is used as the dimension of the unit station in the first direction, and the second length is used as the dimension of the unit station in the second direction.

[0010] According to a clock tree generation method provided by the present invention, the output pin of the custom macrocell buffer is located on the second highest metal layer, and the preset power rail pitch is the power rail pitch between the highest metal layer and the second highest metal layer.

[0011] According to a clock tree generation method provided by the present invention, when the placement constraints include blocking constraints, the step of constructing the placement constraints of the virtual standard cell buffer includes: The plurality of blocking layers are spaced apart in the first direction, and the length of the unblocked area between two adjacent blocking layers in the first direction is greater than or equal to the size of the virtual standard unit buffer in the first direction.

[0012] According to a method for generating a clock tree provided by the present invention, generating a clock tree based on the virtual standard unit buffer and the placement constraints of the virtual standard unit buffer includes: Set a non-default routing rule and designate the clock backbone unit as the virtual standard unit buffer; The clock tree generation instructions are invoked, and electronic design automation tools are used to complete the placement of the virtual standard cell buffer and the clock winding based on timing balance.

[0013] According to a clock tree generation method provided by the present invention, before generating the clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer, the method further includes: Perform a power rail pre-routing operation, wherein no power via insertion operation is performed during the pre-routing operation; After replacing the virtual standard cell buffer in the clock tree with the custom macro cell buffer to obtain a clock tree that supports the custom macro cell buffer, the method further includes: The process involves sequentially adding a holding distance constraint to the custom macrocell buffer, performing a standard cell row cutting operation, and adding an end cap unit. Perform formal routing operations on the power rails to insert power vias and connect the power networks to the respective custom macrocell buffers.

[0014] The present invention also provides a clock tree generation apparatus, comprising the following modules: The module is modified to respond to the clock tree generation instructions, modify the cell category attribute in the library file of the custom macro cell buffer, and generate a virtual standard cell buffer with the same cell category attribute as the standard cell buffer. A construction module is used to construct the placement constraints of the virtual standard unit buffer; The generation module is used to generate a clock tree based on the virtual standard unit buffer and the placement constraints of the virtual standard unit buffer; The replacement module is used to replace the virtual standard unit buffer in the clock tree with the custom macro unit buffer to obtain a clock tree that supports the custom macro unit buffer.

[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the clock tree generation method as described above.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the clock tree generation method as described above.

[0017] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the clock tree generation method as described above.

[0018] This invention provides a method, apparatus, electronic device, and storage medium for generating clock trees. By modifying the cell category attribute in the library file of a custom macrocell buffer, it disguises the custom macrocell buffer as a standard cell buffer, overcoming the problem of recognition errors or operation aborts when directly inputting a custom macrocell buffer in related technical solutions. Combined with the placement constraints of virtual standard cell buffers, it automatically constructs a clock tree. By replacing the virtual standard cell buffers in the clock tree, the clock tree includes the custom macrocell buffer, thus constructing a clock tree containing the custom macrocell buffer, making the clock tree construction suitable for application scenarios with custom high-performance buffers. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is one of the flowcharts illustrating the clock tree generation method provided by the present invention.

[0021] Figure 2 This is a schematic diagram of the unit site provided by the present invention.

[0022] Figure 3 This is a schematic diagram showing the positions of the blocking layer, virtual standard unit buffer, and power rail provided by the present invention.

[0023] Figure 4 This is a schematic diagram of the process for constructing the placement constraints of a virtual standard cell buffer provided by the present invention.

[0024] Figure 5 This is a schematic diagram showing that the output pin of the custom macrocell buffer provided by this invention is located in the area directly below the power rail of the highest metal layer.

[0025] Figure 6 This is a schematic diagram of the process of generating a clock tree in response to a clock tree generation instruction provided by the present invention, based on a virtual standard cell buffer and the placement constraints of the virtual standard cell buffer.

[0026] Figure 7 This is a schematic block diagram of the clock tree generation device provided by the present invention.

[0027] Figure 8 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0028] Figure label: 810: Processor; 820: Communication interface; 830: Memory; 840: Communication bus. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] This application provides a method for generating a clock tree, the execution entity of which can be a computer device, a local server, a cloud server, or a system platform integrating electronic design automation tools. This execution entity has data processing and graphical interface interaction capabilities, and can read underlying integrated circuit design files and perform automated placement and routing operations.

[0031] The following is combined Figures 1 to 8 The present invention describes a method, apparatus, electronic device, and storage medium for generating a clock tree.

[0032] Figure 1 This is one of the flowcharts illustrating the clock tree generation method provided by the present invention, such as... Figure 1 As shown, the method includes the following: Step 101: In response to the clock tree generation instruction, modify the cell category attribute in the library file of the custom macro cell buffer to generate a virtual standard cell buffer that is consistent with the cell category attribute of the standard cell buffer.

[0033] A custom macro cell buffer typically refers to a macro cell buffer unit designed specifically to meet particular high-performance requirements in integrated circuit design.

[0034] In some embodiments, specific high-performance requirements may be high drive capability, specific clock skew control, or power consumption optimization.

[0035] The cell category attribute in the library file defines the cell category of the custom macro cell buffer. By default, the cell category of the custom macro cell buffer is block, while the cell category attribute of the standard cell buffer is core by default. By changing the cell category attribute of the custom macro cell buffer from block to core, the custom macro cell buffer with the modified cell category attribute can be disguised as a standard cell buffer and used as a standard cell buffer. In order to distinguish the disguised standard cell buffer from the standard cell buffer, the custom macro cell buffer with the modified cell category attribute is called a virtual standard cell buffer.

[0036] Step 102: Construct the placement constraints of the virtual standard cell buffer.

[0037] Since virtual standard cell buffers essentially correspond to large-sized custom macro cell buffers with specific power supply or wiring requirements, if tools are allowed to be placed arbitrarily according to the logic of standard cell buffers, physical conflicts such as power short circuits, wiring congestion, or out-of-bounds placement will inevitably occur.

[0038] By constructing placement constraints for virtual standard cell buffers, the placement space of virtual standard cell buffers on the layout is constrained to ensure that they are ultimately placed in the expected physical location, thereby reducing the occurrence of the aforementioned physical conflicts.

[0039] Step 103: Generate a clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer.

[0040] In some embodiments, the clock tree is a flexible H-tree structure.

[0041] In this step, the virtual standard unit buffer is retrieved as the clock backbone unit of the clock tree. At the same time, under the constraint of the placement position constraint, the placement position optimization and winding connection of the virtual standard unit buffer as the backbone unit are automatically completed to form the clock tree.

[0042] Step 104: Replace the virtual standard cell buffer in the clock tree with a custom macro cell buffer to obtain a clock tree that supports custom macro cell buffers.

[0043] In this step, the replacement operation refers to the process of unloading the virtual standard cell buffer and loading a custom macro cell buffer while keeping the original coordinate center position, pin connection relationship and rotation state unchanged.

[0044] In some embodiments, by triggering an Engineering Change Order (ECO), all virtual standard cell buffer instance names in the current clock tree are traversed, and pointer replacement is performed in the memory database based on the instance name. The reference pointer pointing to the definition of the virtual standard cell buffer is redirected to the definition address of the custom macro cell buffer, thereby completing the replacement of the instance object without interfering with the surrounding connections.

[0045] In some embodiments, the currently generated clock tree is exported as a structured netlist file. A text processor is used to perform a global search and replace operation on the device type declaration column in the netlist file, rewriting the virtual standard cell buffer as a custom macro cell buffer. Then, the netlist file is re-imported and mapped to the physical layout to realize the replacement operation.

[0046] In some embodiments, the cell replacement application interface is used to obtain the origin coordinate parameters and pin relative coordinate parameters of each virtual standard cell buffer. A custom macro cell buffer is instantiated at the origin coordinates corresponding to the layout. The clock net data originally connected to the virtual cell pins is stripped and reattached to the pins corresponding to the newly instantiated macro cell. Finally, the original virtual standard cell buffer instance is destroyed in the database to realize the replacement operation.

[0047] Traditional clock tree synthesis tools, such as flexible H-trees, can only recognize and process standard cell buffers. When a custom macro cell buffer is directly input, it will trigger an identification error or abort the operation.

[0048] In the technical solution of this application, the library file attributes of the custom macro cell buffer are modified to change it into a virtual standard cell buffer, thereby disguising it as a standard cell buffer. At this time, traditional clock tree synthesis tools such as flexible H-trees can identify the virtual standard cell buffer as a standard cell buffer, so that in response to the clock tree generation instruction, the virtual standard cell buffer is selected and the clock tree is generated.

[0049] This step disguises the custom macro cell buffer as a standard cell buffer by modifying the cell category attribute in the library file of the custom macro cell buffer. This overcomes the problem of recognition errors or operation aborts when directly inputting a custom macro cell buffer in related technical solutions. Combined with the placement constraints of the virtual standard cell buffer, a clock tree is automatically constructed.

[0050] By replacing the virtual standard cell buffers in the clock tree, a custom macrocell buffer is included in the clock tree, thus constructing a clock tree containing the custom macrocell buffer. This allows the clock tree to be adapted to application scenarios with custom high-performance buffers.

[0051] In some embodiments, placement constraints include unit site constraints and / or obstruction constraints; Among them, the cell site constraint is used to constrain the movement and placement of the virtual standard cell buffer on the first grid, which is the grid defined by the cell site constraint. The blocking constraint uses a blocking layer to constrain the placement position of the virtual standard cell buffer in the first direction.

[0052] Among them, unit site constraints refer to the data rules that regulate the coordinates of component placement by defining the template or blueprint properties of a minimum layout grid cell. Specifically, the grid cell is as follows: Figure 2 As shown, the constraint itself does not directly occupy three-dimensional physical space in the physical database. Instead, it maps a series of discrete legal coordinate points on the layout by setting specific size and type attributes, which is the so-called mesh.

[0053] When loading cell site constraints, it uses an underlying algorithm to force the origin or boundary coordinates of the virtual standard cell buffer to snap and align with the data points of that grid, thereby preventing arbitrary coordinate offsets of the device.

[0054] A blocking constraint refers to a set exclusive region rule, with the blocking layer as its core implementation. The blocking layer is a data block with specific length and width coordinate boundaries. During the exclusive algorithm's operation, coordinates within the blocking layer boundaries are marked as unusable areas. By writing blocking layer data into the database, undesirable coordinate intervals can be filtered out in the first direction, thereby squeezing or limiting the effective placement position of the virtual standard cell buffer to a specific target area in the first direction. In this embodiment, by defining a cell site constraint that matches the power rail pitch, it is ensured that the virtual standard cell buffer is aligned with the placement area defined by the cell site constraint in the second direction.

[0055] At the same time, such as Figure 3 As shown, multiple blocking layers are spaced apart, and the virtual standard unit buffer is located between the blocking layers. The blocking constraints set in the first direction limit the placement area of ​​the virtual standard unit buffer, locking it directly below the power rail.

[0056] In some embodiments, the first direction is the X-axis direction and the second direction is the Y-axis direction.

[0057] In this embodiment, under the dual constraints of cell site constraints and blocking constraints, the actual placement position of the virtual standard cell buffer is precisely determined in both the X-axis and Y-axis dimensions.

[0058] In some embodiments, where the placement constraints include unit site constraints, such as Figure 4As shown, the placement constraints for constructing the virtual standard cell buffer include: Step 401: Add a cell site to the library file of the virtual standard cell buffer.

[0059] Among them, adding a new cell site refers to injecting a data block that defines a brand-new layout grid template into the library file of the virtual standard cell buffer. This data block has an independent name identifier and geometric dimension definition.

[0060] In some embodiments, the library file may be a LEF file.

[0061] Step 402: Determine the first length of the preset power rail pitch in the first direction and the second length of the preset power rail pitch in the second direction, wherein the second direction is perpendicular to the first direction.

[0062] The preset power rail pitch refers to the physical distance between the centers of two adjacent power lines in a specific direction on the chip layout, which are used to power the entire chip. The first length and the second length are the lengths of the preset power rail pitch in the first and second directions, respectively.

[0063] In some embodiments, the first length and the second length are pixel lengths.

[0064] Step 403: Use the first length as the dimension of the unit station in the first direction, and use the second length as the dimension of the unit station in the second direction.

[0065] In some embodiments, the first direction is the X-axis direction and the second direction is the Y-axis direction.

[0066] In this embodiment, by adding a new unit station in the library file and directly assigning the first and second lengths, which represent the span of the preset power rail, as the X-axis and Y-axis dimension data of the unit station, the movement and placement of the virtual standard unit buffer can be constrained to the grid defined by the unit station.

[0067] In some embodiments, the output pin of the custom macrocell buffer is located on the second-highest metal layer, and the preset power rail pitch is the power rail pitch between the highest and second-highest metal layers.

[0068] Output pins refer to the interconnect data ports through which custom macrocell buffers drive the output clock signal. The highest and second-highest metal layers refer to the two thickest, low-impedance conductive wiring layers defined at the top along the Z-axis of the three-dimensional spatial coordinate system in the multilayer wiring technology database.

[0069] In some embodiments, such as Figure 5As shown, the output pin of the custom macrocell buffer is located directly below the power rail of the highest metal layer to shorten the power supply path and reduce impedance, thereby achieving power optimization and fast wiring.

[0070] In this embodiment, by directly coupling the power rail pitch of the highest and second-highest metal layers to the size parameters of the cell site, and combining this with the physical characteristic of pins being positioned on the second-highest metal layer, the calculated virtual standard cell boundary coordinate data can be ensured to align with the spatial topology of the main power supply network corresponding to the power rails when executing the gridded coordinate snapping algorithm. This avoids coordinate misalignment between the clock backbone cell and the power supply grid, reducing the computational overhead of subsequent routing algorithms for inserting power via data in the vertical direction.

[0071] In some embodiments, when the placement constraints include blocking constraints, constructing the placement constraints for the virtual standard cell buffer includes: Multiple blocking layers are spaced apart in the first direction, and the length of the unblocked area between two adjacent blocking layers in the first direction is greater than or equal to the size of the virtual standard cell buffer in the first direction.

[0072] In some embodiments, the first direction is the X-axis direction.

[0073] Among them, multiple blocking layers are distributed at intervals in the X-axis direction. It can be understood that in the X-axis direction, multiple blocking layers are repeatedly arranged at fixed intervals or steps.

[0074] In some embodiments, the sum of the fixed interval or step size and the length of the unblocked area between two adjacent blocking layers in the X-axis direction is equal to the first length of the power rail pitch in the X-axis direction.

[0075] The unblocked area refers to the safe coordinate gap in the layout data matrix between two adjacent exclusive blocking layer data blocks, which allows for the legal placement of devices.

[0076] In this embodiment, the virtual standard cell buffer is actually intended to replace a custom macrocell buffer, which is often physically designed to be positioned directly below the power rail to which it is adapted.

[0077] In order to enforce the placement algorithm of electronic design automation tools so that virtual standard cell buffers can only fall between the power rail pitches that they are compatible with, a comb-shaped constraint filter is constructed in the X-axis direction using the aforementioned spaced blocking layers and unblocked areas.

[0078] In some embodiments, an automated data iteration script is initiated by reading a preset power rail pitch. In each iteration, the lower left and upper right coordinate boundaries of the current barrier layer are calculated in memory using the current accumulated coordinate value and the preset barrier layer width, and the generation interface is called to write them into the layout database. At the same time, the script logic controls the spatial step size of each iteration, so that a blank coordinate interval is reserved between the boundaries of two adjacent generated barrier layers as an unblocked area. The script logic checks that the numerical difference of the unblocked area on the X-axis is strictly greater than or equal to the X-axis boundary size of the virtual standard cell buffer, thereby generating an array composed of barrier layers through iterative calculation.

[0079] In some embodiments, a basic barrier layer data model is constructed near the origin coordinates, and the template length of an unbarriered region is calculated. Then, an array copy algorithm is invoked, using the basic barrier layer data model as a seed unit and the pitch between adjacent power rails as the X-axis stepping parameter of the array. Multiple barrier layer data instances are generated at the database level by copying along the X-axis in one step. This array-based copying algorithm preserves the coordinate spacing between seed units, thus directly constructing an unbarriered region that meets the size requirements.

[0080] In this embodiment, based on the unit site, multiple blocking layers are constructed one by one according to the preset power rail pitch. The blocking layers are used to limit the placement area of ​​the virtual standard unit buffer in the X-axis direction, so that it can only be placed between the power rail pitches of the second highest metal layer, that is, directly below the highest metal layer, thereby achieving precise positioning in the X-axis direction.

[0081] Furthermore, the setting of the blocking layer can prevent the virtual standard cell buffer from being placed on the standard cell buffer.

[0082] In some embodiments, such as Figure 6 As shown, a clock tree is generated based on the virtual standard cell buffer and its placement constraints, including: Step 601: Set non-default routing rules and designate the clock backbone unit as a virtual standard unit buffer.

[0083] Non-Default Routing (NDR) refers to a dataset of special routing rules in the layout routing database that differs from the default physical parameters of regular signal lines. In clock tree synthesis, wider metal trace widths or larger line spacing are typically assigned to the clock backbone network to reduce the parasitic resistance and capacitance of clock connections.

[0084] Step 602: Call the clock tree generation instruction, use electronic design automation tools to complete the placement of virtual standard cell buffers, and clock winding based on timing balance.

[0085] The clock backbone unit is a high-level node model in a clock tree topology (such as a flexible H-tree structure) that is responsible for driving the global or large-area clock branches.

[0086] Electronic design automation tools are embodied in an algorithm engine integrated within the execution entity for automatically calculating physical coordinates and routing paths.

[0087] Timing balancing refers to an iterative calculation process at the data computation level, in which the engine automatically calculates the trace length or inserts buffers to ensure that the propagation delay time of the clock signal from the source to each end branch node meets the preset consistency requirements.

[0088] In some embodiments, a non-default routing rule (NDR) is set, and the clock backbone unit is designated as a virtual standard cell buffer. Subsequently, the FlexH tree creation command (create_flexible_htree) is invoked, and the EDA tool automatically completes the placement and routing of the virtual standard cell buffer. This step achieves automated placement of the clock backbone unit and clock routing based on timing balance.

[0089] In some specific embodiments, non-default routing rule tags are assigned to the clock backbone network layer in the internal database, and this clock topology node is instantiated as a virtual standard cell buffer model. When the clock tree generation instruction is detected, the background computing engine of the execution entity retrieves the topology model data. When calculating the physical placement, the engine establishes a layout coordinate conflict matrix, eliminates invalid coordinates based on placement constraints, and places the virtual standard cell buffer in the optimal legal position. After placement, the engine uses the RC extraction model corresponding to the non-default routing rule, with the minimization of the delay difference between each end node as the objective function, to deduce and iterate the routing topology, thereby ensuring timing balance at the geometric space level.

[0090] In some specific embodiments, a non-default routing rule parameter set is issued by the configuration system, and the synthesis rule of the clock tree backbone is specified to force the use of virtual standard cell buffers. After the generation instruction is invoked, the underlying high-level router takes over the data flow. In the placement phase, the router first performs physical coordinate matching and anchoring with the highest priority condition of satisfying the placement constraints of the virtual standard cell buffers. After entering the routing phase, the router strictly follows the line width and spacing constraints of the non-default routing rules to generate connection pattern data, and uses an internal delay relaxation evaluation algorithm to continuously fine-tune the physical direction and length data of each branch connection until the timing balance cost function of the entire network converges.

[0091] In this embodiment, by binding non-default routing rules with a disguised virtual standard cell buffer, the execution entity successfully transforms customized high-performance physical parameter requirements into standard input parameters that the automation engine can directly read and process. After invoking the generation instruction, the underlying algorithm engine can automatically call the constraint rule matrix to calculate legal coordinates within a single computation cycle to complete the placement, and introduce the RC model of the non-default routing rules to perform complex parasitic delay iterative calculations to complete timing-balanced routing. During this process, clock network data meeting customized performance requirements can be directly output using existing tool engines without interrupting the automated workflow, significantly reducing redundant consumption of computing resources.

[0092] In some embodiments, before generating the clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer, the method further includes: Perform a pre-routing operation for the power rails, wherein the insertion operation of power vias is not performed during the pre-routing operation; After replacing the virtual standard cell buffers in the clock tree with custom macrocell buffers to obtain a clock tree that supports custom macrocell buffers, the following is also included: Add holding distance constraints to the custom macrocell buffer, perform the standard cell row cutting operation, and add end cap cells in sequence; Perform formal routing operations on the power rails to insert power vias and connect the power network to the individual custom macrocell buffers.

[0093] Power rail pre-routing refers to the initial generation of power net routing path data in the layout database to meet the requirements of subsequent tools for checking the existence of the power net foundation. Power vias are three-dimensional conductive connection data models used to vertically transmit power signals between different metal layers. Power vias are intentionally not inserted during the pre-routing stage to avoid generating incorrect power connection relationships when the device type is still a virtual standard cell; that is, only fast pre-routing is performed without inserting power vias.

[0094] Maintaining distance constraints, also known as macrocells (Halo), refers to a data buffer in the database that defines a ring of spacing around a custom macrocell buffer to prevent the placement of standard cells. This buffer is used to prevent signal crosstalk and physical violations in the manufacturing process.

[0095] The standard cell row cutting operation refers to cutting and removing the standard cell row definition data that was originally laid out continuously below the macro cells at the layout data level, thereby freeing up dedicated conflict-free physical space for the macro cells.

[0096] End cap cells refer to special physical boundary cell data that is automatically instantiated at the end of a standard cell row after dicing, used to meet specific design rule checks during wafer manufacturing.

[0097] Formal routing refers to the process of calling the routing engine to complete all missing conductive layer data in the database after confirming that the device has been completely replaced with a real custom macrocell buffer, especially to accurately insert power via data in order to establish a complete power supply network.

[0098] In this embodiment, by splitting the power routing data processing into two stages, pre-routing and formal routing, the execution entity cleverly utilizes the data feature that does not contain vias in the first stage to meet the power track identification requirements of the clock tree synthesis engine when processing virtual standard cells, while avoiding unnecessary routing calculation overhead and violation errors. After the clock tree is generated and replaced with real macro cells, the entity sequentially adds holding distance constraints to the custom macro cell buffers, performs standard cell row cutting operations, and adds end cap units. Finally, it performs formal routing containing via data to completely connect the power supply to each custom macro cell buffer.

[0099] This process eliminates the need for additional power patching required for such macrocells in traditional workflows, thus simplifying the process. Finally, the final design is completed by following the standard implementation process of the backend design.

[0100] In some embodiments, the standard implementation process includes clock tree synthesis optimization, signal routing, and physical verification.

[0101] The clock tree generation apparatus provided by the present invention will be described below. The clock tree generation apparatus described below can be referred to in correspondence with the clock tree generation method described above.

[0102] In some embodiments, such as Figure 7 As shown, a clock tree generation device is proposed, comprising: Modify module 701 to respond to the clock tree generation instruction, modify the cell category attribute in the library file of the custom macro cell buffer, and generate a virtual standard cell buffer that is consistent with the cell category attribute of the standard cell buffer. Module 702 is used to construct the placement constraints of the virtual standard cell buffer; The generation module 703 is used to generate a clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer. Replacement module 704 is used to replace the virtual standard cell buffer in the clock tree with a custom macro cell buffer to obtain a clock tree that supports custom macro cell buffers.

[0103] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8 As shown, the electronic device may include a processor 810, a communication interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 can call logical instructions in the memory 830 to execute a clock tree generation method, which includes: in response to the clock tree generation instruction, modifying the cell category attribute in the library file of the custom macro cell buffer to generate a virtual standard cell buffer with the same cell category attribute as the standard cell buffer; constructing the placement constraints of the virtual standard cell buffer; generating a clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer; and replacing the virtual standard cell buffers in the clock tree with custom macro cell buffers to obtain a clock tree that supports custom macro cell buffers.

[0104] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0105] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the clock tree generation method provided by the above methods. The method includes: in response to the clock tree generation instruction, modifying the cell category attribute in the library file of the custom macro cell buffer to generate a virtual standard cell buffer that is consistent with the cell category attribute of the standard cell buffer; constructing the placement constraints of the virtual standard cell buffer; generating a clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer; and replacing the virtual standard cell buffer in the clock tree with the custom macro cell buffer to obtain a clock tree that supports the custom macro cell buffer.

[0106] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a method for generating a clock tree provided by the methods described above. This method includes: in response to a clock tree generation instruction, modifying the cell category attribute in a library file of a custom macrocell buffer to generate a virtual standard cell buffer consistent with the cell category attribute of a standard cell buffer; constructing placement constraints for the virtual standard cell buffer; generating a clock tree based on the virtual standard cell buffer and its placement constraints; and replacing the virtual standard cell buffers in the clock tree with custom macrocell buffers to obtain a clock tree supporting custom macrocell buffers.

[0107] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a clock tree, characterized in that, include: In response to the clock tree generation instruction, modify the cell category attribute in the library file of the custom macro cell buffer to generate a virtual standard cell buffer that is consistent with the cell category attribute of the standard cell buffer. Construct placement constraints for the virtual standard cell buffer; A clock tree is generated based on the virtual standard unit buffer and the placement constraints of the virtual standard unit buffer; Replace the virtual standard cell buffer in the clock tree with the custom macro cell buffer to obtain a clock tree that supports the custom macro cell buffer.

2. The method for generating a clock tree according to claim 1, characterized in that, The placement constraints include unit site constraints and / or obstruction constraints; The unit site constraint is used to constrain the movement and placement of the virtual standard unit buffer on a first grid, which is the grid defined by the unit site constraint. The blocking constraint uses a blocking layer to constrain the placement position of the virtual standard unit buffer in a first direction.

3. The method for generating a clock tree according to claim 2, characterized in that, When the placement constraints include unit site constraints, the placement constraints for constructing the virtual standard unit buffer include: Add a new cell site to the library file of the virtual standard cell buffer; Determine a first length of the preset power rail pitch in the first direction, and a second length of the preset power rail pitch in a second direction, wherein the second direction is perpendicular to the first direction; The first length is used as the dimension of the unit station in the first direction, and the second length is used as the dimension of the unit station in the second direction.

4. The method for generating a clock tree according to claim 3, characterized in that, The output pin of the custom macrocell buffer is located on the second-highest metal layer, and the preset power rail pitch is the power rail pitch between the highest metal layer and the second-highest metal layer.

5. The method for generating a clock tree according to claim 2, characterized in that, When the placement constraints include obstruction constraints, the placement constraints for constructing the virtual standard cell buffer include: The plurality of blocking layers are spaced apart in the first direction, and the length of the unblocked area between two adjacent blocking layers in the first direction is greater than or equal to the size of the virtual standard unit buffer in the first direction.

6. The method for generating a clock tree according to claim 1, characterized in that, The generation of the clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer includes: Set a non-default routing rule and designate the clock backbone unit as the virtual standard unit buffer; The clock tree generation instructions are invoked, and electronic design automation tools are used to complete the placement of the virtual standard cell buffer and the clock winding based on timing balance.

7. The method for generating a clock tree according to any one of claims 1 to 6, characterized in that, Before generating the clock tree based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer, the method further includes: Perform a power rail pre-routing operation, wherein no power via insertion operation is performed during the pre-routing operation; After replacing the virtual standard cell buffer in the clock tree with the custom macro cell buffer to obtain a clock tree that supports the custom macro cell buffer, the method further includes: The process involves sequentially adding a holding distance constraint to the custom macrocell buffer, performing a standard cell row cutting operation, and adding an end cap unit. Perform formal routing operations on the power rails to insert power vias and connect the power networks to the respective custom macrocell buffers.

8. A clock tree generation device, characterized in that, include: The module is modified to respond to the clock tree generation command, modify the cell category attribute in the library file of the custom macro cell buffer, and generate a virtual standard cell buffer with the same cell category attribute as the standard cell buffer. A construction module is used to construct the placement constraints of the virtual standard unit buffer; The generation module is used to generate a clock tree in response to the clock tree generation command, based on the virtual standard cell buffer and the placement constraints of the virtual standard cell buffer. The replacement module is used to replace the virtual standard unit buffer in the clock tree with the custom macro unit buffer to obtain a clock tree that supports the custom macro unit buffer.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the clock tree generation method as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the clock tree generation method as described in any one of claims 1 to 7.

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