A design method of carbon-based transistor integrated circuit and simulation platform

Abstract

The application discloses a kind of carbon-based transistor integrated circuit and simulation platform design method, it includes: constructing carbon-based transistor compact model, based on the intrinsic ac model of multiple physical parameters fitting of device, after superimposed contact resistance, parasitic capacitance, tunneling current parasitic effect, to classic silicon-based transistor model parameter fitting, realize carbon-based device compatible silicon-based simulation environment;Development.gte process file, carbon-based PMOS, NMOS layered information is defined in batches by.csv, with polysilicon gate as reference layer, rely on preset mathematical relationship formula linkage each layer size;With base [1], base [i], base [i-1] Array loop automatically generates any fork index layout, export tf, drf, il process file and configure CDB, Skill, Macros class IC information;Rely on the union of DRC, LVS rule and integration of uniform.gte file, build complete simulation platform.The application solves the problem that existing carbon-based PDK simulation ecology is fragmented, file is separate, multiple fork pointer layout is repeatedly drawn, and commercial EDA has poor adaptability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit electronic design automation (EDA) process library development technology, specifically involving an integrated design method for integrated circuits and simulation platforms that is adapted to carbon nanotube carbon-based transistors and compatible with commercial integrated circuit simulation environments. Background Technology

[0002] As silicon-based integrated circuit technology gradually approaches the physical miniaturization limit of 5nm and below, bottlenecks such as short-channel effect, tunneling leakage current, power consumption, and heat dissipation remain difficult to overcome. Carbon nanotube transistors (carbon-based transistors), with their advantages of ultra-high current mobility, one-dimensional dangling bond-free channel, low operating voltage, excellent thermal conductivity, low-temperature processing, and radiation resistance, have become the core device to replace silicon MOSFETs in the post-Moore's Law era. Carbon-based transistors are considered an important direction for CMOS technology below 5nm.

[0003] Currently, research on carbon-based PDKs has emerged in the industry. For example, the existing technology is the 2024 MDPI journal *Electronics* publication, "Full-Custom 90 nm CNTFET Process Design Kit: Characterization, Modeling, and Implementation" (authors: Y. Liu, X. Zhang, et al., *Electronics*, 2024, Vol. 13, No. 5, pp. 901-920). This paper discloses a basic framework for a 90nm carbon nanotube transistor PDK, including a compact carbon-based CNTFET model, a simplified transistor Pcell, basic DRC / LVS rules, and a standard cell library, enabling circuit layout and simulation verification for small-scale operational amplifiers and SRAMs. Combining the aforementioned existing technologies and industry-standard carbon-based PDK development solutions, the current field of carbon-based transistor integrated circuit design and simulation generally faces the following pain points and technical bottlenecks: First, the simulation system for carbon-based devices is severely disconnected from the mature commercial silicon-based EDA simulation ecosystem. Carbon-based transistors possess unique physical characteristics that distinguish them from silicon-based devices, such as quantum capacitance, tunneling current, and one-dimensional current-carrying transport. Existing carbon-based PDK solutions generally use independently written proprietary device models, whose model architectures are completely incompatible with the classic silicon-based transistor models built into commercial EDA platforms, making it impossible to directly reuse mature silicon-based simulation kernels and algorithms. Existing carbon-based simulation workflows suffer from poor versatility, weak simulation convergence, and time-consuming large-scale circuit simulations, making it difficult to support the design iteration of large-scale digital, analog, and mixed-signal integrated circuits.

[0004] Second, existing carbon-based PDKs generally adopt a discrete file, modular, and independent development architecture, resulting in low iteration efficiency and poor consistency. In the development of traditional carbon-based process libraries, device electrical models, parametric layout scripts, process layer definitions, DRC design rules, and LVS verification rules are stored, written, and maintained independently, with no unified relationship between the multiple sets of process files. When iterating and updating process parameters and device dimensions, manual synchronization is required across multiple files, which easily leads to problems such as mismatches between layout parameters and electrical model parameters, conflicts between layout structure and design rules, and abnormal LVS port matching. This results in long process iteration cycles and heavy reliance on the individual experience of developers.

[0005] Third, there is a lack of standardized and automated rapid development systems for multi-fingered layouts of carbon-based transistors. Carbon-based transistors often use multi-fingered structures to improve drive current and optimize device performance, but existing carbon-based Pcell development schemes only support fixed-parameter layout drawing and have not formed a mature automatic multi-fingered generation mechanism. Carbon-based transistors with different fork indices and different sizes need to be drawn repeatedly and scripts need to be written repeatedly. The layout development involves a large amount of repetitive work, poor versatility, and extremely low design efficiency.

[0006] Fourth, existing carbon-based PDKs have not formed a complete industrial-scale commercial EDA adaptation system. Most existing research solutions are lightweight academic developments that are not adapted to the complete design flow of commercial Cadence ICs. They lack complete process file compilation, layer mapping, simulation parameter configuration, callback function definition, and process verification closed-loop mechanisms. The developed carbon-based process libraries can only meet the needs of small-scale device verification and cannot be directly applied to industrial integrated circuit design and tape-out, resulting in poor practicality and engineering feasibility.

[0007] In summary, current carbon-based transistor PDK development generally suffers from technical defects such as incompatibility with simulation ecosystems, disorganized and fragmented process documentation, low degree of layout automation, and poor industrial adaptability. There is an urgent need for a new design solution for carbon-based transistor integrated circuits and simulation platforms that is compatible with mature silicon-based EDA ecosystems, integrated, automated, and industrially feasible. Summary of the Invention

[0008] A brief overview of embodiments of the invention is provided below to provide a basic understanding of certain aspects of the invention. It should be understood that this overview is not an exhaustive summary of the invention. It is not intended to identify key or essential parts of the invention, nor is it intended to limit the scope of the invention. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0009] Addressing industry pain points such as the disconnect between existing carbon-based transistor process libraries and silicon-based EDA ecosystems, low iteration efficiency due to discrete development using multiple files, cumbersome multi-fingered transistor layout drawing, and poor compatibility with commercial EDA, this invention provides a design method for carbon-based transistor integrated circuits and simulation platforms. This invention achieves compatibility and reuse between carbon-based device models and silicon-based simulation environments, completing the entire development process—from layout and modeling to verification—through a unified process file. It automates the generation of multi-fingered transistor layouts, significantly shortening the carbon-based PDK development cycle, lowering the design threshold, and constructing a carbon-based integrated circuit simulation design system that is directly compatible with commercial integrated circuit design platforms (such as Cadence) and can be industrially deployed.

[0010] Specifically, the design method of a carbon-based transistor integrated circuit and simulation platform of the present invention includes the following steps: S1. Establish device model: Construct a compact model of carbon-based transistor and perform parameter fitting on the preset classic silicon-based transistor model to obtain the device model corresponding to the carbon-based transistor. S2. Parametric Cell Development: Use the graphical editor of the automated development system of the process design kit (such as Cadence PDK) to create and edit the carbon-based transistor-specific .gte file. In the .gte file, define the layer information of the carbon-based transistor, configure detailed graphical information for each layer, build the Pcell layout and generate process-compatible files in techfile.tf, display.drf and .il formats, and configure the carbon-based transistor IC information. S3, DRC, and LVS rule development: Based on the .gte file generated by S2, design rules are developed, DRC rules are compared with the layout, and schematic LVS rules are compared. The DRC and LVS rules are then merged into the .gte file to build a complete carbon-based transistor integrated circuit and simulation platform.

[0011] Preferably, the step S1 of establishing the device model specifically includes: Based on the physical structural parameters such as mobility, drain hot electron emission current, port capacitance, quantum capacitance, channel resistance, subthreshold slope, and drain-induced barrier reduction coefficient, combined with experimental data, we carried out theoretical derivation and numerical fitting of formulas to obtain the intrinsic DC and AC signal models of carbon-based transistors. By superimposing three types of non-ideal parasitic effects—contact resistance, parasitic capacitance, and tunneling current—onto the intrinsic model, a compact model of the carbon-based transistor is obtained. This step is used to fully reproduce the true electrical characteristics of the carbon-based transistor, ensuring the accuracy of subsequent circuit simulations.

[0012] Preferably, the development of the S2 parameterization unit includes: Step S2-1: Create and save a .gte file using a graphical editor, and define the information of each layer of the carbon-based transistor by entering data in a table or importing a .csv file; The layers required to construct a carbon-based PMOS transistor include the active region, P-type source-drain contacts, P-type gate oxide, P-type gate electrode, silicon oxide via, and various metal layers. The layers required to construct a carbon-based NMOS transistor include the active region, N-type source / drain contacts, N-type gate oxide, N-type gate electrode, silicon oxide vias, and various metal layers. This process standardizes and manages the process layers of carbon-based devices, adapting to automated development toolchains for process design suites.

[0013] Step S2-2: Detailed graphical information of each layer of the carbon-based transistor includes layer name, layer information, layer label, layer target, layer graph and layer description information, among which layer name, layer information, layer target and layer graph information are required fields; The layer information bar configures layer attributes, layer number, process data, and graphic fill format information; Layer targets are used to define layer types, including normal layers, vias, and interconnects. This step is used to standardize layout display, quickly distinguish different process layers, and reduce the difficulty of layout design and verification.

[0014] Step S2-3: Define three core parameters of the carbon-based transistor: channel length, channel width, and cross exponent. The channel length and channel width are set as floating-point variables, and the cross exponent is set as an integer variable. The polysilicon gate layer GT is selected as the reference layer, and the pattern size and coordinates of the reference layer are used as the size scale of the entire Pcell. The channel length and width of each other process layer are determined by combining the channel length and width of the reference layer with a preset mathematical formula, and the center of each layer is aligned with the center of the reference layer. When the length and width of the transistors change, the entire layer layout automatically scales synchronously to adapt to the design requirements of circuits of different sizes.

[0015] Specifically, in S2-3, the cross index is set graphically using a loop variable in the base array for dynamic configuration. The specific implementation method includes: Use a programming language to define a circular array, with base[1] as the base fork in the graph; The i-th level interdigitated graph is represented by base[i]. The base[i-1] represents the previous level of interdigitated pattern, and the three-level array variable is used to automatically generate any number (any number greater than or equal to 2) of interdigitated patterns; The reference polysilicon gate is copied to obtain two sets of derived patterns. The reference coordinate association of one set of patterns is removed and set as a variable layer. The dimension annotation of the other set of patterns is removed from the reference coordinate association and set as a virtual variable layer. Set the relative coordinates between the centers of the variable layer and the virtual variable layer; The remaining process layers are created synchronously from bottom to top: the main layer, variable layer, and virtual variable layer, and the relative coordinates of the corresponding graphics for each layer are set. This step enables the automatic generation of carbon-based transistor layouts with any number of cross fingers by simply modifying the cross index parameter, eliminating the need for repeated drawing.

[0016] Steps S2-4: Store the generated .il, techfile.tf, and display.drf files in the same file path; launch the integrated circuit design software in this path, load the techfile.tf file for compilation, and generate the carbon-based transistor Pcell layout. This step seamlessly integrates with commercial integrated circuit design EDA software, directly reusing the existing silicon-based integrated circuit design environment.

[0017] Step S2-5: The configured IC information includes CDB layer information, CDF callback function information, CDF parameter definition information, simulator information, CDF definition information, CDF information summary, Pcell Skill Procedures information, Pcell Macros information, and Pcell description page information; In the CDF callback function information page, callback functions are written using a programming language to adjust the unit scale; Configure the built-in Pcell control functions of PAS (PDK Automation System) in the Pcell Macros information page to implement the calculation definition of grid point, transistor length, width, and cross index; The GEN tool is used to verify the .gte file and correct any errors generated during verification. This step completes the integrated binding of device layout, simulation parameters, and design rules, forming a complete process library that can be directly used for simulation.

[0018] Preferably, the development of S3 DRC and LVS rules specifically includes: Step S3-1: The developed DRC rules include width rules, spacing rules, extension rules, wrapping rules, overlap rules, area rules, and density rules; Additional DRC rules should be established to adapt to polysilicon and antenna structures; The generated DRC rule files are merged into a .gte file. This step enables automated design rule checking of carbon-based layouts, proactively avoiding layout violations related to process control.

[0019] Step S3-2: Establish the multilayer metal interconnect matching relationship of carbon-based transistors. The interconnect relationship includes the substrate and the first metal layer, the active region and the first metal layer, the polysilicon and the first metal layer, the first metal layer and the second metal layer, the second metal layer and the third metal layer, and the third metal layer and the fourth metal layer. In the device definition interface, define the LVS layout and extract the required device name, device port, and device graphic. The generated LVS rule files are merged into a .gte file, and single-layer-specific LVS constraints are manually added as needed. This step enables automatic comparison between the carbon-based layout and the schematic, ensuring circuit connection consistency.

[0020] This invention provides a novel integrated carbon-based PDK development architecture using the above-described solution, which offers the following advantages compared to existing technologies: 1. Existing technologies only independently build carbon-based device models, which cannot be compatible with the commercial silicon-based simulation ecosystem, resulting in poor convergence and weak versatility in large-scale circuit simulation. This invention solves the industry problem of the disconnect between carbon-based device simulation and the commercial EDA ecosystem by fitting the electrical characteristic parameters of carbon-based transistors to the mature silicon-based transistor model framework. This allows for direct reuse of commercial silicon-based simulation platforms and mature simulation algorithms without reconstructing the simulation kernel, significantly improving the simulation efficiency and stability of carbon-based integrated circuits.

[0021] 2. Existing technologies and traditional carbon-based PDKs employ a development model that stores models, layouts, and rules separately. Parameter iteration requires manual modification in multiple locations, resulting in poor consistency, high error rates, and long iteration cycles. This invention relies on automated development toolsets for process design suites (such as Cadence PAS / GTE) to unify process layer definitions, Pcell parameterization logic, simulation configurations, and the entire set of DRC / LVS process rules into a single .gte file. This enables a single modification of process parameters, resulting in synchronized updates across the entire process chain. This eliminates issues such as version inconsistencies in multiple files, parameter mismatches, and verification errors, thereby improving process iteration efficiency.

[0022] 3. In existing technologies, different cross-index devices require repeated layout drawing, resulting in a large development workload and poor versatility. This invention constructs a loop iteration mechanism through base[1], base[i], and base[i-1] array variables, combined with the scaling logic of the base layer mathematical operation, which can adaptively generate carbon-based transistor layouts of arbitrary cross indices and sizes, thereby achieving standardized and automated layout design, reducing the design threshold and repetitive workload.

[0023] 4. This invention establishes a complete closed loop from carbon-based device modeling, graphical editor process file development, parametric layout generation, CDF simulation parameter configuration, process verification to DRC / LVS integrated rule integration. The generated process files can be directly compiled and run on commercial integrated circuit design platforms, adapting to the needs of industrial integrated circuit design and tape-out. This is different from existing academic, lightweight carbon-based PDK solutions that cannot be commercially implemented.

[0024] In summary, this invention integrates silicon-based model fitting, single-file integrated development, and automatic generation of multi-interdigitation base arrays to achieve synergistic benefits. The compatibility fitting between carbon-based and silicon-based models allows device simulation to directly call mature simulator kernels. The single-file integrated architecture ensures that model parameters and layout geometry are updated synchronously during iteration. The three-level array loop mechanism enables the automatic generation of arbitrary interdigitation structures without manual intervention. The complete CDF configuration and DRC / LVS integration make the entire process library plug-and-play for commercial EDA environments, thereby significantly shortening the PDK development cycle, significantly reducing the design threshold and iteration costs, and realizing an efficient, stable, and commercially viable carbon-based integrated circuit simulation design system with excellent practicality. Attached Figure Description

[0025] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout the drawings to denote the same or similar parts. These drawings, together with the following detailed description, are incorporated in and form part of this specification, and are used to further illustrate preferred embodiments of the invention and explain the principles and advantages of the invention. In the drawings: Figure 1 This is a flowchart illustrating the design method of a carbon-based transistor integrated circuit and simulation platform according to an embodiment of the present invention. Detailed Implementation

[0026] Embodiments of the present invention will now be described with reference to the accompanying drawings. Elements and features described in one drawing or embodiment of the invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that, for clarity, representations and descriptions of components and processes unrelated to the present invention and known to those skilled in the art have been omitted from the drawings and description.

[0027] First, some terms used in this application will be explained as follows: Pcell: Parameterized Cell; CDF: Component Description Format; DRC: Design Rule Check document; LVS: Layout Versus Schematic.

[0028] This embodiment describes a design method for a carbon-based transistor integrated circuit and its simulation platform. See [link to relevant documentation]. Figure 1The process includes three main steps: establishing device models, developing parameterized units, and developing DRC and LVS rules, which are described in detail below: S1. Establish device model Electrical test data of carbon nanotube transistors were collected, and mobility, drain (thermal electron emission) current, port capacitance, quantum capacitance, channel resistance, subthreshold slope, and drain-induced barrier reduction coefficient were extracted. The formulas were derived theoretically by combining one-dimensional carbon nanotube transport theory and experimental data, and numerical fitting was performed to obtain the intrinsic DC and AC signal models of carbon-based transistors.

[0029] Based on the intrinsic model, three types of non-ideal / parasitic effects—contact resistance, parasitic capacitance, and tunneling current—are superimposed to construct a complete compact model of carbon nanotubes.

[0030] In this embodiment, the classic silicon-based transistor model BSIM series built into the Cadence simulation platform is selected as the fitting carrier. The electrical parameters of the carbon-based compact model are mapped to the parameter channels of the silicon-based model to complete parameter fitting (this can be achieved by using the least squares method or a genetic algorithm to optimize and match key parameters such as mobility, threshold voltage, and subthreshold swing, with the goal of minimizing the mean square error; alternatively, the parameters can be set according to actual conditions). This yields a carbon-based transistor device model that can be directly run on a silicon-based simulator. The classic silicon-based transistor model is stored in a pre-selected silicon-based integrated circuit simulation platform. The quantum capacitance effect unique to carbon-based transistors is equivalently mapped by adjusting the model coefficients of intrinsic capacitance-related parameters (such as Cgs, Cgd, etc.) in the BSIM model. The tunneling current component is characterized by the gate-induced drain leakage (GIDL) current parameter channel or inter-band tunneling-related parameters in the BSIM model. The specific mathematical form of the above mapping relationship can be obtained by comparing the IV and CV characteristic curves of the carbon-based compact model and the BSIM model, and by extracting and optimizing parameters with the goal of minimizing the curve fitting error.

[0031] S2, Parametric Unit Development S2-1: Define the layer information for carbon-based transistors.

[0032] Open the basic editing interface of a Pcell design tool (such as the GTE graphical editor), and generate and save the newly created .gte file.

[0033] Following the instructions of the design tool, fill in the relevant layer information in the design table in sequence. Enter the layer names of the carbon-based transistor in column A, the corresponding layer numbers in column B, and the layer name abbreviations (optional) in column C to complete the carbon-based transistor layer information table. Alternatively, you can directly read and import an edited .csv file to define the layer information (layer number, layer name, process attributes, etc.). Construct complete layer structures for carbon-based PMOS and carbon-based NMOS, including active regions, dedicated gate oxide, source / drain contacts, silicon oxide vias, and multilayer metal interconnects.

[0034] The construction of a carbon-based PMOS transistor requires an active region, P-type source / drain contacts (metal), P-type gate oxide, P-type gate electrode (metal), silicon oxide vias, and various metal layers. The construction of a carbon-based NMOS transistor requires an active region, n-type source / drain contacts (metal), n-type gate oxide, n-type gate electrode (metal), silicon oxide vias, and various metal layers.

[0035] S2-2: Add detailed graphical information for each defined layer.

[0036] Detailed graphical information for each layer of a carbon-based transistor includes layer name, layer information, layer label, layer target, layer diagram, and layer description. Among these, layer name, layer information, layer target, and layer diagram are required fields.

[0037] Enter the layer name defined in S2-1 in the layer name information field, such as AA representing the active region, and then add detailed graphic information of the layer in subsequent steps.

[0038] In the Layer Information section, add the layer attributes, layer number, process data, and graphic fill style information for the layer. This section is crucial for adding layers. Entering `input 1;0 df2order 1 packet AA fillStyle outlineStipple` indicates that the AA layer of the carbon-based transistor is the input layer, layer number 1; data type 0, DF2 layer order 1, grouping type AA; fill style is outlined as a dotted line. Specific layer information can be modified according to design requirements.

[0039] In the Layer Target field, define the target used by this layer, specifying that the layer can be a normal layer, via, interconnect, etc. Here, select "none" for the active area AA, and select "Via" for a via.

[0040] In the Layer Graphics section, select different fill graphics, colors, and outline line styles for each layer. This information can be discussed with device engineers to develop appropriate fill schemes.

[0041] After adding the detailed graphic information of each layer of the carbon-based transistor in sequence following the steps above, the pop-up information page will display the added layers and detailed graphic information. After checking that there are no errors, the addition of the carbon-based transistor layer graphic information is complete.

[0042] S2-3: Establish the P-cell layout of the carbon-based transistor.

[0043] After thorough communication with device engineers to obtain key information such as the size, spacing, and coverage of each layer of the carbon-based transistor, open the Pcell layout design page. Enter the identification information and set the carbon-based transistor library name and cell name.

[0044] Define the parameter names, parameter types, and initial values ​​of the carbon-based transistor in the parameter form table. Define the three main parameters of the carbon-based transistor in the table: channel length, channel width, and cross exponent. Set the channel length and channel width as floating-point variables, and the cross exponent as an integer variable.

[0045] In the reference layer selection interface, select the polysilicon layer GT to set the polysilicon gate as the reference layer for the carbon-based transistor, serving as the reference pattern size and scale for the entire P-cell. The pattern size and coordinates of other layers created subsequently will be extended from the pattern of this reference layer.

[0046] Draw a rectangle as the polysilicon layer of the carbon-based transistor, and label the horizontal dimension of the drawn polysilicon layer as the characteristic length L of the carbon-based transistor, and set the vertical dimension as W of the carbon-based transistor. The preset mathematical operation relationship can be: source / drain contact layer length = L + 2 × contact boundary margin; gate oxide layer width = W + 2 × gate coverage margin.

[0047] Finally, select and set a point on the polysilicon gate (usually the lower left corner) as the reference coordinate of the entire Pcell to complete the drawing of the polysilicon gate rectangle.

[0048] Following the same method used to build the polysilicon layer, other layers are drawn from bottom to top. Since the lengths (L and W) of the other layers need to vary with the L and W of the polysilicon layer, the width and length of the other layers are defined using mathematical formulas attached to the predefined L and W of the polysilicon layer. Finally, based on structural analysis, the alignment function in the design tool is used to set the relative coordinates between the centers of the other layers and the center of the polysilicon layer.

[0049] In circuit design, carbon-based transistors need to be able to be configured in a multi-fingered pattern, so the fingers of carbon-based transistors need to be graphically set.

[0050] In this process, the cross index of the carbon-based transistor is graphically set. In the new design page, the initial settings are first made according to the method in S2-2, and then the cross index is set as a loop variable parameter. Using the Pcell control function, the statement "for i 2 finger" is entered in the control bar to define the cross index as any value greater than or equal to 2. "1" is entered in the command bar to define the cross index as the first sequence control variable. Finally, "for loop" is entered to control the cross index in a loop. After setting and drawing the reference polysilicon of the carbon-based transistor, two identical reference polysilicon are obtained by copying and pasting. The reference coordinate association of one of them is canceled and it is set as a variable layer. The dimension annotation and reference coordinate association of the other reference polysilicon are canceled and it is set as a virtual variable layer. The three set reference polysilicon are set as a loop transformation graphic. The main layer is named base[1], the variable layer is named base[i], and the virtual variable layer is named base[i-1]. Finally, the relative coordinates of the distance between the center of the variable layer and the virtual variable layer are set. Other layers are drawn from bottom to top in the same way to establish the main layer, variable layer and virtual variable layer of each layer graphic. Finally, set the relative coordinates between different main layers and between different variable layers. This completes the graphical setup of the carbon-based transistor cross index.

[0051] In actual implementation, the loop array logic can be written using the SKILL language: base[1] represents the basic single-group gate pattern, base[i] is the i-th interdigitated gate, and base[i-1] is the previous stage gate pattern; the reference gate is copied to generate the variable layer and the virtual variable layer, and the relative offset coordinates of the two layers' centers are set; the active area, via, and metal layer are synchronously established to create a base three-level layer, realizing arbitrary interdigitated gate patterns. Figure 1 Key generation.

[0052] S2-4: Generate Pcells in Cadence Virtuoso software.

[0053] Open the Pcell generation tool, select the .gte file of the carbon-based transistor created in the above steps, and generate the corresponding techfile.tf and display.drf files in the target path. If there are errors, you need to go back to the above steps and modify the .gte file according to the error message. Finally, a folder containing .il files will be generated in the directory, successfully generating a Pcell file conforming to the Cadence IC software format.

[0054] Copy the .il file, techfile.tf file, and display.drf file to the same directory. Launch the Cadence IC software in that directory and select the techfile.tf file to compile. Successful compilation indicates that the carbon-based transistor P-cell layout has been successfully generated in the Cadence IC software.

[0055] S2-5: Establishment of IC information for carbon-based transistors.

[0056] IC information includes CDB layer information, CDF callback function information, CDF parameter definition information, simulator information, CDF definition information, CDF information summary, Pcell skill procedures information and macros information, and Pcell description page information.

[0057] On the CDB layer information page, complete the CDB information table according to the information of each layer of the carbon-based transistor defined in S2-1. Enter the layer name in the first column, the layer number in the second column, and the layer name abbreviation (optional) in the third column to complete the information page.

[0058] In the CDF callback function information page, use the Skill language to write callback functions and modify the unit scale to facilitate the corresponding DRC rules established in subsequent steps.

[0059] On the CDF parameter definition information page, first enter the library name and unit name that were uniformly set in S2-3. In the first column of the CDF parameter table, enter the parameter name displayed by CDF. In the second column, describe the specific value, display method, and parameter description information through a callback function.

[0060] On the simulator information page, first enter the library name and unit name that were uniformly set in S2-3. In the simulator information table, enter the simulator name, mapped port order, etc. in the first column, and enter the specific values ​​in the second column.

[0061] On the CDF definition information page, fill in the device information and specific display information.

[0062] On the CDF information summary page, you can fill out a form to associate the view of the carbon-based transistor device with the symbol in the PAS library.

[0063] On the Pcell Skill Procedures information page, enter the control functions for the device shape and parameters, as well as any warning messages.

[0064] On the Pcell Macros information page, enter the Pcell control functions that come with PAS to define grid information, width, length, cross index calculations, etc.

[0065] Finally, open the GEN tool to verify any errors that may have occurred during the creation of the carbon-based transistor's .gte file in the above steps, and return to the previous steps to make corrections based on the error messages. After the corrections are complete, you can use the PAS tool to initially build the integrated circuit and simulation platform for the carbon-based transistor.

[0066] S3: Development of DRC and LVS rules S3-1: DRC rule development.

[0067] The DRC rules mainly include width rules, spacing rules, extension rules, wrapping / enclosing rules, overlap rules, area rules, and density rules.

[0068] Configure the name, value, and description of each DRC rule. For example, you can set the minimum width of the polysilicon gate GT layer to 90nm and the minimum pitch to 100nm; the minimum width of the active region AA to 120nm and the minimum pitch to 140nm; and the minimum width of the metal layer M1 to 100nm and the minimum pitch to 110nm, etc. These specific values ​​can be adjusted according to actual process conditions. Establish width rules, pitch information, area information, wrapping information, and error information.

[0069] Establish DRC rule information for polysilicon and antenna rules.

[0070] Verify and correct any errors. Once complete, use the PAS tool to generate the corresponding DRC rules. Merge the generated DRC rule file into the .gte file generated in S2.

[0071] S3-2: LVS rule development.

[0072] The development of LVS rules mainly includes three steps: connection relationships, device definition establishment, and manual supplementation of LVS rules.

[0073] Establish the connection relationships of each metal layer of the carbon-based transistor on the design page, including the following connection relationships: substrate-first metal interconnect; active region-first metal interconnect; polysilicon-first metal interconnect; first metal-second metal interconnect; second metal-third metal interconnect; third metal-fourth metal interconnect.

[0074] On the device definition page, define the device name, device port, device parameters, and device graph to be displayed when extracting the LVS layout.

[0075] Verify and correct any errors, then use the PAS tool to generate the corresponding LVS rules. Merge the generated LVS rule file into the .gte file generated in S2. Similarly, you will need to add, edit, and generate LVS rules again in the project later.

[0076] Finally, manually add the necessary LVS rules in the separate layer's editing interface.

[0077] After the entire process is completed, the .gte file integrates device layer definitions, Pcell parameterization logic, CDF simulation configuration, and a complete set of DRC / LVS rules, directly relying on the Cadence platform to build a complete carbon-based transistor integrated circuit simulation platform that can be used for circuit design, simulation, layout verification, and tape-out.

[0078] Existing technologies generally consider carbon-based devices and silicon-based devices to have fundamental differences in carrier transport mechanisms and capacitance characteristics. Therefore, they tend to model carbon-based devices independently rather than fitting them to a silicon-based model framework. This invention, through the above-described approach, achieves an effective mapping between a compact carbon-based model and a classic silicon-based model by rationally selecting fitting parameters and optimizing algorithms. This allows for the direct reuse of a mature silicon-based simulation ecosystem without reconstructing the simulation kernel.

[0079] Although the invention has been disclosed above through the description of specific embodiments, it should be understood that all the embodiments and examples described above are exemplary and not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the invention within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the invention.

Claims

1. A design method for a carbon-based transistor integrated circuit and simulation platform, characterized in that, Includes the following steps: S1. Establish device model: Construct a compact model of carbon-based transistor and perform parameter fitting on the preset classic silicon-based transistor model to obtain the device model corresponding to the carbon-based transistor. S2. Parametric Cell Development: The graphical editor of the automated development system of the process design kit is used to create and edit the carbon-based transistor-specific .gte file. In the .gte file, the layer information of the carbon-based transistor is defined, detailed graphical information is configured for each layer, the Pcell layout is built and compatible process files in techfile.tf, display.drf and .il formats are generated, and the carbon-based transistor IC information is configured. S3, DRC, and LVS rule development: Based on the .gte file created by S2, design rules are developed, DRC rules are compared with the layout, and schematic LVS rules are compared. The DRC and LVS rules are then merged into the .gte file to build a complete carbon-based transistor integrated circuit and simulation platform.

2. The design method according to claim 1, characterized in that, S1 includes: Based on the physical structural parameters such as mobility, drain hot electron emission current, port capacitance, quantum capacitance, channel resistance, subthreshold slope, and drain-induced barrier reduction coefficient, combined with experimental data, we carried out theoretical derivation and numerical fitting of formulas to obtain the intrinsic DC and AC signal models of carbon-based transistors. By superimposing three types of non-ideal parasitic effects—contact resistance, parasitic capacitance, and tunneling current—onto the intrinsic model, a compact model of the carbon-based transistor is obtained.

3. The design method according to claim 1, characterized in that, S2 includes sub-step S2-1: Create and save a .gte file using a graphical editor, and define the information of each layer of the carbon-based transistor by entering data in a table or importing a .csv file. The layers required to construct a carbon-based PMOS transistor include the active region, P-type source-drain contacts, P-type gate oxide, P-type gate electrode, silicon oxide via, and various metal layers. The layers required to construct a carbon-based NMOS transistor include the active region, N-type source-drain contacts, N-type gate oxide, N-type gate electrode, silicon oxide via, and various metal layers.

4. The design method according to claim 1, characterized in that, S2 includes sub-step S2-2: Detailed graphical information for each layer of a carbon-based transistor includes layer name, layer information, layer label, layer target, layer graph, and layer description information. Among these, layer name, layer information, layer target, and layer graph information are required fields. The layer information bar configures layer attributes, layer number, process data, and graphic fill format information; Layer targets are used to define the layer type, which includes normal layers, vias, and interconnects.

5. The design method according to claim 1, characterized in that, S2 includes sub-steps S2-3: Define three core parameters for carbon-based transistors: channel length, channel width, and cross exponent. The channel length and channel width are set as floating-point variables, and the cross exponent is set as an integer variable. The polysilicon gate layer GT is selected as the reference layer, and the pattern size and coordinates of the reference layer are used as the size scale of the entire Pcell. The channel length and width of each of the remaining process layers are determined by combining the channel length and width of the reference layer with a preset mathematical formula, and the center of each layer is aligned with the center of the reference layer.

6. The design method according to claim 5, characterized in that, In S2-3, the cross index is graphically set using a loop variable in the base array for dynamic configuration. The specific implementation method includes: Use a programming language to define a circular array, with base[1] as the base fork in the graph; The i-th level interdigitated graph is represented by base[i]. The base[i-1] represents the previous level of interdigitated pattern, and the three-level array variable is used to automatically generate any number of interdigitated patterns. The reference polysilicon gate is copied to obtain two sets of derived patterns. The reference coordinate association of one set of patterns is removed and set as a variable layer. The dimension annotation of the other set of patterns is removed from the reference coordinate association and set as a virtual variable layer. Set the relative coordinates between the centers of the variable layer and the virtual variable layer; The remaining process layers are created synchronously from bottom to top: the main layer, the variable layer, and the virtual variable layer, and the relative coordinates of the corresponding graphics for each layer are set.

7. The design method according to claim 1, characterized in that, S2 includes sub-steps S2-4: Store the generated .il file, techfile.tf file, and display.drf file in the same file path; start the integrated circuit design software in this path, load the techfile.tf file and compile it to generate the carbon-based transistor Pcell layout.

8. The design method according to claim 1, characterized in that, S2 includes sub-steps S2-5: The configured IC information includes CDB layer information, CDF callback function information, CDF parameter definition information, simulator information, CDF definition information, CDF information summary, Pcell Skill Procedures information, Pcell Macros information, and Pcell description page information; In the CDF callback function information page, callback functions are written using a programming language to adjust the unit scale; Configure the built-in PAS Pcell control functions in the Pcell Macros information page to define the calculation of grid points, transistor length, width, and cross exponent; Use the GEN tool to verify the .gte file and correct any errors generated during verification.

9. The design method according to claim 1, characterized in that, S3 includes sub-step S3-1: The developed DRC rules include width rules, spacing rules, extension rules, wrapping rules, overlap rules, area rules, and density rules; Additional DRC rules should be established to adapt to polysilicon and antenna structures; Merge the generated DRC rule files into the .gte file.

10. The design method according to claim 1, characterized in that, S3 includes sub-step S3-2: Establish multilayer metal interconnect matching relationships for carbon-based transistors. The interconnect relationships include substrate and first metal layer, active region and first metal layer, polysilicon and first metal layer, first metal layer and second metal layer, second metal layer and third metal layer, and third metal layer and fourth metal layer. In the device definition interface, define the LVS layout and extract the required device name, device port, device parameters, and device diagram; Merge the generated LVS rule files into a .gte file, and manually add single-layer exclusive LVS constraints as needed.

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