Layout design file parsing method, device and storage medium

Abstract

The application discloses a layout design file parsing method and device and a storage medium, relates to the technical field of printed circuit board design and simulation, and comprises the following steps: parsing a layout design file to extract all geometric figures under a target network, and forming a to-be-merged figure set; using a two-color shader to alternately color and group the geometric figures according to index serial numbers, and obtaining two complementary sub-sets; recursively performing the alternately coloring and grouping until each sub-set contains no more than one figure, and constructing a binary tree merging structure; performing a bottom-up layer-by-layer traversal of the binary tree merging structure, and performing a Boolean operation layer by layer to obtain a final merged figure; and outputting the final merged figure as geometric input data for grid subdivision. According to the application, the serial Boolean operation chain is reconstructed into a parallel layered structure by constructing the binary tree merging structure, the operation depth is reduced, and the Boolean operation of the same layer can be performed in parallel, so that the calculation efficiency of the Boolean merging of the geometric figures is improved.

Description

Technical Field

[0001] This application relates to the field of PCB simulation technology, and in particular to a method, device and storage medium for parsing layout design files. Background Technology

[0002] To understand PCB performance, electromagnetic simulation of the PCB and IC is required in simulation software. Simulation software in related technologies first needs to parse the layout design file into computable geometric data using a layout parsing tool. However, scattered geometric primitives within the same net require Boolean union operations before meshing to eliminate redundant geometric nodes. Current simulation software typically merges geometric shapes pairwise sequentially when parsing layout design files. That is, it first performs a Boolean union operation on the first two shapes to obtain an intermediate result, then performs a Boolean union operation on the intermediate result with the next shape, and so on, until all shapes are merged to obtain the final merged result.

[0003] In this sequential merging method, each merging step requires traversing all the vertices of the graphics involved in the operation, and the number of merging steps increases quadratically with the number of graphics n, resulting in an overall time complexity of O(N²×V). When there are many scattered graphics in the layout, the time consumption of Boolean merging operations increases dramatically, significantly limiting processing efficiency and making it difficult to meet the requirements of large-scale electromagnetic simulation for geometric processing efficiency. Summary of the Invention

[0004] The main purpose of this application is to provide a method, device and storage medium for parsing layout design files, which aims to solve the technical problem of high time complexity caused by sequential merging.

[0005] To achieve the above objectives, this application provides a method for parsing layout design files, the method comprising: At least one target network in the layout design file is obtained by parsing, and all geometric figures under each target network are extracted to form a set of figures to be merged. The set of figures to be merged contains n geometric figures, each of which is represented by a closed polygon boundary. Two-color shaders are used to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers, resulting in two complementary subsets. The alternating coloring grouping is recursively performed on each subset until the number of geometric figures contained in each subset is no more than one, and a binary tree merging structure is constructed. The binary tree merging structure is traversed in a bottom-up hierarchical order, and Boolean operations are performed layer by layer to obtain the final merged graphic of all the geometric figures under the target network. The final merged graphic is output, and the final merged graphic is used as the geometric input data for mesh generation.

[0006] In one embodiment, the parsing process obtains at least one target network in the layout design file, and extracts all geometric figures under each target network to form a set of figures to be merged, including: The layout design file is parsed to obtain geometric data organized in units of electrical networks; Determine at least one target network from the geometric data; For each target network, extract the geometric figures belonging to the target network to form a set of figures to be merged corresponding to the target network; The geometry includes at least one of trace segments, pads, vias, and copper-clad areas, and the closed polygon boundary includes an outer ring vertex coordinate sequence and / or an inner ring vertex coordinate sequence.

[0007] In one embodiment, after parsing at least one target network in the layout design file and extracting all geometric figures under each target network to form a set of figures to be merged, the method further includes: The connectivity check and validity verification are performed on each of the geometric figures in the set of figures to be merged; wherein, the connectivity check is to determine whether there is a connection relationship between the geometric figures that needs to be merged; the validity verification includes marking degenerate geometric figures with fewer than three vertices as invalid geometric figures and removing them from the set of figures to be merged, and repairing or marking geometric figures with self-intersection or other topological errors; After completing the connectivity check and validity verification, the number of valid geometric figures in the set of figures to be merged is counted. When the number of valid geometric figures is not greater than one, the valid geometric figures are output as the final merged figures, or an empty set is output.

[0008] In one embodiment, the step of using a two-color shader to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers to obtain two complementary subsets, including: The index number corresponding to each geometric image is determined according to the arrangement order of the geometric figures in the set of figures to be merged; Each geometric figure with an odd index number in the set of figures to be merged is assigned a first color and assigned to a first subset. Each of the geometric figures with an even index number is assigned a second color and placed into a second subset.

[0009] In one embodiment, the complementary subset includes a first subset and a second subset. The alternating coloring grouping is recursively applied to each subset until the number of geometric shapes contained in each subset is no greater than one, constructing a binary tree merging structure, including: The alternating coloring grouping is performed on the first subset and the second subset respectively to obtain the next level of subsets; Repeat the alternating coloring grouping for the next level subset until the number of geometric shapes contained in each subset is no more than one. Using each of the aforementioned geometric shapes as leaf nodes and the Boolean operations performed on the geometric shapes corresponding to two child nodes as internal nodes, the binary tree merging structure is constructed; wherein, the root node of the binary tree merging structure corresponds to the Boolean operation result of all geometric shapes in the set of shapes to be merged, and the depth of the binary tree merging structure is the logarithm of base 2 n rounded up, where n is the number of geometric shapes in the set of shapes to be merged.

[0010] In one embodiment, the step of traversing the binary tree merging structure in a bottom-up hierarchical order and performing Boolean operations layer by layer to obtain the final merged graph of all geometric figures under the target network includes: Starting from the level corresponding to the leaf node of the binary tree merging structure, Boolean operations are performed on each pair of child nodes in the current level in a bottom-up order to merge the geometric figures corresponding to the two child nodes into one geometric figure, and the merging result is used as the child node of the corresponding internal node in the previous level. Perform Boolean operations layer by layer upwards until the root node completes the Boolean operations, resulting in the final merged graphic; In one embodiment, before using a two-color shader to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers to obtain two complementary subsets, the following steps are included: Calculate the bounding box center coordinates of each geometric figure in the set of figures to be merged; Sort the bounding box center coordinates of each of the geometric figures according to the space filling curve; The order of the geometric figures in the set of figures to be merged is rearranged according to the sorting results, so that spatially adjacent geometric figures have adjacent index numbers.

[0011] In one embodiment, when there exists a target subset containing a first geometric shape and no second geometric shape paired with the first geometric shape, the node corresponding to the target subset is used as the input of the upper-level node, and Boolean union operation is not performed; When the final merged graphic contains multiple unconnected sub-regions, each sub-region is output as geometric input data of independent mesh partitioning.

[0012] In addition, to achieve the above objectives, this application also provides a layout design file parsing device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the layout design file parsing method described above.

[0013] In addition, to achieve the above objectives, this application also provides a storage medium, which is a computer-readable storage medium, on which a program implementing a method for parsing layout design documents is stored. The program implementing the method for parsing layout design documents is executed by a processor to implement the steps of the method for parsing layout design documents as described above.

[0014] This application provides a method for parsing layout design files. First, it extracts all geometric figures from the target network by parsing the layout design file, forming a set of figures to be merged. Then, using a two-color shader, each geometric figure in the set is alternately colored and grouped according to its index, resulting in two complementary subsets. The coloring and grouping of these subsets are recursively performed until each subset contains no more than one geometric figure, thus constructing a binary tree merging structure. After constructing the binary tree merging structure, Boolean operations are performed layer by layer in a bottom-up hierarchical order. Multiple Boolean operations within the same layer are independent and can be executed in parallel, further shortening the actual computation time and avoiding the problem of single-core serial execution in sequential merging failing to utilize multi-core processor resources. Finally, by outputting the final merged figure as the geometric input data for mesh partitioning, the mesh partitioner can perform reasonable partitioning based on the merged real physical boundaries. This application reconstructs the serial Boolean operation chain into a binary tree structure of depth log2n by constructing a binary tree merging structure. The operation depth is reduced from n in sequential merging to log2n, and Boolean operations within the same level can be executed in parallel. This solves the technical problem that the sequential merging of a large number of geometric shapes in existing layout designs leads to high time complexity and the inability to execute in parallel. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating the method for parsing layout design documents in this application, provided in Embodiment 1. Figure 2 A flowchart illustrating the method for parsing layout design documents in this application, provided in Embodiment Seven; Figure 3 The hardware structure diagram of the device involved in the analysis of the layout design documents of this application is shown.

[0018] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not intended to limit this application.

[0020] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0021] Currently, a large number of geometric figures under the same electrical network in the layout design file need to be merged into a whole figure through Boolean union operation. However, the traditional sequential merging strategy forms a serial Boolean operation chain with a depth of N-1. The operation depth increases linearly with the number of figures, resulting in a superlinear increase in total time with the number of figures. Moreover, each operation needs to be executed serially, which cannot be accelerated by multi-core processors.

[0022] The main solution of this application is as follows: At least one target network in the layout design file is parsed, and all geometric figures under each target network are extracted to form a set of figures to be merged. The set of figures to be merged contains n geometric figures, each of which is represented by a closed polygon boundary. A two-color shader is used to alternately color and group each geometric figure in the set of figures to be merged according to its index number, resulting in two complementary subsets. The alternating coloring grouping is recursively performed on each subset until the number of geometric figures contained in each subset is no greater than one, thus constructing a binary tree merging structure. The binary tree merging structure is traversed in a bottom-up hierarchical order, and Boolean operations are performed layer by layer to obtain the final merged figure of all geometric figures under the target network. The final merged figure is output as the geometric input data for mesh partitioning.

[0023] This application extracts all geometric figures from the target network by analyzing the layout design file. It then uses a two-color shader to alternately color and group the data according to index numbers, recursively constructing a binary tree merging structure. This reduces the depth of Boolean operations from n to log₂n, and allows Boolean operations within the same layer to be executed in parallel, significantly shortening computation time and reducing error accumulation. The output merged graphic serves as the input for mesh partitioning, avoiding redundant expansion of mesh nodes. This solves the technical problem of low efficiency in sequential merging.

[0024] It should be noted that the execution subject in this embodiment can be a layout design file parsing device, or a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or any device capable of performing the above functions. This embodiment does not specifically limit it in this way. The following uses a layout design file parsing device as the execution subject as an example to describe this embodiment and the following embodiments.

[0025] Based on this, Embodiment 1 of this application proposes a method for parsing layout design files. Please refer to... Figure 1 The method for parsing the layout design file includes steps S10 to S50: Step S10: Parse at least one target network in the layout design file and extract all geometric figures under each target network to form a set of figures to be merged.

[0026] In this embodiment, a layout design file refers to a file containing physical design data for a printed circuit board or integrated circuit. A target network refers to a network with the same electrical connection in the layout design, encompassing all geometric figures within that network. A geometric figure refers to a physical graphic unit that constitutes an electrical network, and each geometric figure is represented by a closed polygon boundary. A set of figures to be merged refers to the set of all geometric figures within the same target network that need to be merged into one or more connected whole figures, and each of these geometric figures is represented by a closed polygon boundary.

[0027] As an optional implementation, the layout design file is read, and a parser corresponding to the file format is invoked to parse the layout design file. At least one target network is determined based on user input or preset rules. For each target network, all geometric figures under that network are traversed, and the closed polygon boundary data of each geometric figure is extracted to form a set of figures to be merged corresponding to that target network.

[0028] Step S20: Using a two-color shader, each geometric shape in the set of shapes to be merged is alternately colored and grouped according to its index number to obtain two complementary subsets.

[0029] In this embodiment, the two-color shader refers to a processing module used to divide a set of geometric figures into two complementary subsets according to their index numbers. Each geometric figure is considered a node in a graph, and alternating coloring is equivalent to alternating the coloring of the node sequence with two colors, ensuring that figures with adjacent indices belong to different color groups. The complementary subsets include a first subset and a second subset.

[0030] As an optional implementation, after constructing the set of graphics to be merged, the arrangement order of each geometric shape in the set is obtained. Based on the positional relationship of each geometric shape in the arrangement order, alternating coloring is used to divide the geometric shapes into two complementary subsets, so that geometric shapes in adjacent positions belong to different subsets. This alternating coloring grouping method depends only on the arrangement order of the geometric shapes in the set, and is independent of the geometric position, shape, and size of the shapes, and the grouping process does not involve any geometric calculations.

[0031] Optionally, the alternating coloring grouping method can be based on the parity of the index number, assigning odd-numbered graphics to the first subset and even-numbered graphics to the second subset; it can also be based on the position of the graphics in the set for equal-interval alternating assignment, for example, dividing the graphics into two subsets alternately with a fixed step size; or it can be based on setting an alternating flag bit according to the traversal order, flipping the assignment target once for each graphic processed during the traversal process, so that adjacent graphics are always assigned to different subsets.

[0032] It should be noted that Boolean operations satisfy the associative and commutative laws, and the order of grouping and merging does not change the geometric semantics of the final result.

[0033] Step S30: Recursively perform the alternating coloring grouping on each subset until the number of geometric figures contained in each subset is no more than one, and construct a binary tree merging structure.

[0034] In this embodiment, recursive execution refers to repeatedly performing the two-color alternating grouping operation on the two subsets obtained after grouping, further splitting each subset into two smaller subsets, forming a recursive decomposition process. The binary tree merging structure refers to a binary tree with the original geometric figures as leaf nodes and Boolean operations as internal nodes. Its root node corresponds to the final merging result of all geometric figures in the set to be merged, and each level of internal node corresponds to one Boolean operation.

[0035] As an optional implementation, the two-color alternating grouping operation is recursively performed on the obtained first and second subsets respectively. For the first subset, the current arrangement order of the graphics within it is taken, and it is divided into two smaller subsets according to the index number; for the second subset, it is similarly divided into two smaller subsets according to the parity of the index number. During the recursion, if a subset contains more than one geometric figure, the alternating coloring grouping is continued for that subset; if a subset contains one geometric figure or is empty, the recursive decomposition of that branch is stopped.

[0036] Step S40: Traverse the binary tree merging structure in a bottom-up order, perform Boolean operations layer by layer, and obtain the final merged graphic of all the geometric figures under the target network.

[0037] In this embodiment, the bottom-up hierarchical order refers to the order in which the binary tree is traversed layer by layer from the leaf nodes towards the root node, and the merge operation is performed. The leaf nodes correspond to the original geometric figures and do not require any operations. Boolean operations refer to set operations that merge, intersect, or subtract two or more geometric figures according to specific set logic rules. Common Boolean operation types include: Boolean union, Boolean intersection, and Boolean difference. The final merged figure refers to the geometric figure output by the root node after completing the Boolean operations, representing the merged result of all geometric figures in the target network.

[0038] Preferably, the Boolean operation is a Boolean union operation. After the binary tree merging structure is constructed, starting from the level corresponding to the leaf node, the Boolean union operation is performed layer by layer in a bottom-up order. For each pair of child nodes in the current level, a Boolean union operation is performed to merge the geometric figures corresponding to the two child nodes into one figure, and the merged result is used as the input of the child node of the corresponding parent node in the next higher level. Multiple Boolean union operation objects within the same level are independent of each other and can be executed in parallel. This process is performed layer by layer upwards until the root node completes the last Boolean union operation, resulting in the final merged figure of all geometric figures in the target network. If a group contains only one geometric figure, the merged result of that group is directly the figure itself, and no Boolean operation is required.

[0039] Optionally, based on the associative and commutative laws of Boolean operations, the Boolean operations in this embodiment also include Boolean intersection and Boolean difference. When applied to Boolean difference operations, a grouping strategy needs to be determined according to the order of operations, keeping the positions of the subtrahend and minuend figures in the binary tree fixed, and performing the difference operation layer by layer to obtain the correct result.

[0040] Step S50: Output the final merged graphic, and use the final merged graphic as the geometric input data for mesh generation.

[0041] In this embodiment, mesh generation refers to the process of discretizing a geometric shape into simulation mesh cells for electromagnetic field simulation calculations. Geometric input data refers to the geometric boundary data required by the mesh generator, used to determine the extent and boundary conditions of the meshed region.

[0042] As an optional implementation, after obtaining the final merged graphic of all geometries under the target network, the final merged graphic is output to a mesh generator as the geometric input data of the target network. Specifically, the closed polygon boundary data of the final merged graphic is organized according to the format required by the mesh generator and transmitted to the mesh generator through a data interface. After receiving the geometric input data, the mesh generator performs mesh generation based on the merged real physical boundaries, ensuring that mesh nodes are distributed only on the real physical boundaries, avoiding redundant expansion of mesh nodes caused by independent generation of scattered primitives. By using the merged overall graphic as the input for mesh generation in the above manner, the quality of mesh generation and the computational efficiency of subsequent electromagnetic field solutions are improved.

[0043] This embodiment compresses the originally linearly growing serial computation depth to logarithmic level by constructing a binary tree merging structure, while simultaneously achieving parallel processing of Boolean operations at the same level. This effectively adapts to the hardware architecture of current multi-core processors, significantly reducing the total computation time in scenarios involving merging large numbers of geometric figures. It addresses the pain points of traditional sequential merging strategies, which suffer from large computational depths and inability to utilize multi-core resources for acceleration. Furthermore, the grouping process in this method relies solely on the graphic index sequence, without involving additional geometric calculations. The time complexity of the grouping process is far lower than that of the geometric Boolean operations themselves, preventing the introduction of additional computational overhead into the overall parsing process and ensuring the overall execution efficiency of the method.

[0044] Based on Embodiment 1, Embodiment 2 of this application proposes a method for parsing layout design documents. Parsing yields at least one target network in the layout design document, and extracting all geometric figures under each target network to form a set of figures to be merged may include steps S11 to S13: Step S11: Parse the layout design file to obtain geometric data organized in units of electrical networks.

[0045] Step S12: Determine at least one target network from the geometric data.

[0046] Step S13: For each target network, extract the geometric figures belonging to the target network to form a set of figures to be merged corresponding to the target network.

[0047] In this embodiment, geometric data refers to the structured description information of each graphic unit extracted from the layout design file, which includes at least the graphic type identifier and the coordinates of the vertices of the closed polygon boundary.

[0048] As an optional implementation, after obtaining the layout design file, the corresponding parser is called to parse the file according to its format type. The electrical networks and their corresponding geometric information are extracted from the file. The parsing results are then categorized and organized according to the electrical networks, forming a geometric data structure indexed by the electrical networks. The geometric figures in the layout design file are categorized according to their electrical connections, with geometric figures belonging to the same electrical network grouped together. Based on user-specified or system-preset filtering rules, the electrical networks requiring geometric merging are identified as target networks. For each target network, all geometric figures corresponding to that target network are extracted from the geometric data organized by electrical network, forming a set of figures to be merged. This method organizes and extracts the geometric data in the layout design file according to electrical networks, providing the input data foundation for subsequent Boolean merging operations.

[0049] This embodiment extracts electrical networks and their corresponding geometric information from layout design files by parsing them. The parsing results are then categorized and organized according to electrical networks, forming structured data indexed by these networks. This allows for processing along the electrical network dimension without re-parsing the original file. By identifying the target network from the geometric data organized by electrical network, the processing scope is focused on the electrical networks requiring geometric merging, avoiding the processing overhead of irrelevant networks. Finally, by extracting all geometric figures corresponding to the target network to form a set of figures to be merged, scattered geometric figures within the same electrical network are organized in a set format. This embodiment solves the data organization problem of efficiently merging scattered geometric figures in layout design files using Boolean methods.

[0050] Based on Embodiment 1, Embodiment 3 of this application proposes a method for parsing layout design documents. The method parses at least one target network from the layout design document and extracts all geometric figures under each target network to form a set of figures to be merged. This may include steps S14 to S15: Step S14: Perform connectivity checks and validity verification on each geometric figure in the set of figures to be merged.

[0051] In this embodiment, connectivity checking refers to determining whether there are connectivity relationships between geometric figures that need to be merged, used to identify figures that are in contact or overlapping within the same electrical network. Validity verification refers to checking the data structure integrity and geometric validity of the geometric figures, including determining whether the number of polygon vertices meets the requirements for forming a valid closed region, and detecting whether there are self-intersections or other topological errors.

[0052] As an optional implementation, after constructing the set of graphics to be merged, each geometry in the set is traversed, and a validity check is performed: The vertex coordinate sequence of a closed polygon is checked for completeness. If the number of vertices is less than three, the geometry degenerates into a line or point, cannot form a valid closed region, and is marked as an invalid geometry and removed from the set of graphics to be merged. If the polygon has self-intersections or other topological errors, it is automatically repaired or marked as invalid based on the error type. For geometry that passes the check, a connectivity check is further performed: Bounding box intersection tests or edge intersection checks are used to determine whether there is spatial overlap or contact between the graphics, identifying the connectivity relationships that need to be merged. Through this method, invalid graphics are filtered out before the Boolean merging operation, preventing invalid data from participating in subsequent calculations.

[0053] Step S15: After completing the connectivity check and validity verification, count the number of valid geometric figures in the set of figures to be merged. When the number of valid geometric figures is not greater than one, output the valid geometric figures as the final merged figures, or output an empty set.

[0054] In this embodiment, a valid geometric figure refers to a geometric figure that has passed the validity check and can normally participate in Boolean operations.

[0055] As an optional implementation, after completing connectivity checks and validity verification, the number of valid geometric figures in the set of figures to be merged is counted. Specifically, if the number of valid geometric figures is 0, an empty set is output, indicating that there are no valid figures to be merged under the target network; if the number of valid geometric figures is 1, Boolean operations are not required, and the valid geometric figure is directly output as the final merged figure; if the number of valid geometric figures is greater than 1, the two-color grouping and binary tree merging steps are continued.

[0056] Based on Embodiment 1, Embodiment 4 of this application proposes a method for parsing layout design documents. This method uses a two-color shader to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers, obtaining two complementary subsets. This may include steps S21 to S23: Step S21: Determine the index number corresponding to each geometric image according to the arrangement order of each geometric image in the set of graphics to be merged.

[0057] Step S22: Assign a first color to each of the geometric figures with odd index numbers in the set of figures to be merged, and classify them into the first subset.

[0058] Step S23: Assign a second color to each of the geometric figures with an even index number and assign them to the second subset.

[0059] In this embodiment, the first color and the second color are logical identifiers used to distinguish different subsets. The first subset and the second subset are complementary sets, that is, the union of the two is equal to the original set, and the intersection is empty.

[0060] As an optional implementation, the set of shapes to be merged is typically stored in memory as a dynamic array, with each geometric shape's index position within the array serving as its index number. Specifically, array indices start from 0, corresponding to index number 1; index 1 corresponds to index number 2, and so on. A fixed mapping relationship exists between the index number and the array indices, eliminating the need for additional index storage; the index number can be calculated directly during array traversal using the current index. The grouping operation is completed with a single array traversal: two empty subset containers are defined. Each geometric shape in the set to be merged is traversed, its current array index value is obtained, and its index number is calculated. When the index number is odd, the geometric shape is assigned to the first subset; when the index number is even, it is assigned to the second subset. The first subset is assigned a first color identifier, and the second subset is assigned a second color identifier. The grouping operation is then completed.

[0061] This embodiment transforms the complex geometric merging problem into two independent or alternating processing logics within two subsets using the aforementioned two-color grouping strategy. It leverages the associative and commutative laws of Boolean operations to ensure that any grouping and merging order does not alter the geometric semantics of the final result, thus splitting the original problem into two independent subproblems of comparable size. Unlike complex grouping schemes based on spatial location, the grouping process in this embodiment only involves parity checks of index numbers and container assignment operations, without any geometric calculations. Therefore, regardless of whether the geometric figure is a simple triangle or a complex polygon with thousands of vertices, the time cost of the grouping operation is O(n), and it is independent of the complexity of a single figure. When the number of geometric figures reaches thousands or even tens of thousands, the time consumption of this step is typically in the millisecond range, and its impact on the overall processing flow is negligible. Furthermore, the grouping operation does not modify the original geometric data, and the original set can be safely released after grouping, effectively reducing memory usage.

[0062] Based on Embodiment 1, Embodiment 5 of this application proposes a method for parsing layout design files. The alternating coloring grouping is recursively performed on each subset until the number of geometric shapes contained in each subset is no greater than one. Constructing a binary tree merging structure may include steps S31 to S33: Step S31: Perform the alternating coloring grouping on the first subset and the second subset respectively to obtain the next level of subsets.

[0063] Step S32: Repeat the alternating coloring grouping for the next level subset until the number of geometric shapes contained in each subset is no more than one.

[0064] Step S33: Using each of the geometric shapes as leaf nodes and the Boolean operations performed on the geometric shapes corresponding to the two child nodes as internal nodes, construct the binary tree merging structure.

[0065] In this embodiment, the next level subset refers to the smaller subset generated by alternating coloring grouping of the current level subset.

[0066] As an optional implementation, after obtaining the first and second subsets, alternating coloring grouping is performed independently on each subset. For the first subset, the current arrangement order of the graphics within it is taken, and it is divided into two smaller subsets according to the parity of the index numbers; for the second subset, it is similarly divided into two smaller subsets according to the parity of the index numbers. During the recursive process, if a subset contains more than one geometric figure, alternating coloring grouping is continued on that subset; if a subset contains one geometric figure or is empty, the recursive decomposition of that branch is stopped. After the recursive decomposition is completed, a complete binary tree merging structure is constructed, with each original geometric figure as the leaf node of the binary tree and each Boolean union operation as the internal node. The leaf node corresponds to each original geometric figure, the internal node corresponds to a Boolean union operation, and its two child nodes are the two operation objects participating in that operation. The root node corresponds to the final Boolean operation merging result of all geometric figures. The depth of this binary tree merging structure is the logarithm of n to the base 2, rounded up, where n is the total number of geometric figures in the set of figures to be merged. This is an order of magnitude reduction compared to the depth of sequential merging, which is n-1.

[0067] Optionally, each level of child nodes corresponds one-to-one with a subset of the corresponding level.

[0068] This embodiment achieves independent recursive decomposition of the two branches by independently performing alternating coloring grouping on the first and second subsets. By repeatedly performing alternating coloring grouping on the next level subsets until the number of geometric figures in each subset is no greater than one, the original problem size is progressively decomposed from n to n / 2, n / 4, and finally to a single geometric figure, completing the recursive construction of the binary tree merging structure. By constructing the binary tree merging structure with each geometric figure as a leaf node and Boolean operations as internal nodes, the traditional sequential merging serial chain structure is reconstructed into a binary tree structure with a depth of 2^n rounded up, structurally eliminating the dependency of linear growth in computational depth with the number of figures. Since all Boolean union operations within the same level of the binary tree are independent, they can be distributed across multiple CPU cores for parallel execution, further shortening the actual computation time of subsequent layer-by-layer merging stages. On multi-core processors, a near-linear speedup can be achieved, fundamentally changing the execution structure of Boolean operations and improving computational efficiency.

[0069] Based on Embodiment 1, Embodiment 6 of this application proposes a method for parsing layout design files. This method involves traversing the binary tree merging structure in a bottom-up hierarchical order, performing Boolean operations layer by layer, and obtaining the final merged graphic of all geometric figures under the target network. This may include steps S41 to S42: Step S41: Starting from the level corresponding to the leaf node of the binary tree merging structure, perform Boolean operations on each pair of child nodes in the current level in a bottom-up order, merge the geometric figures corresponding to the two child nodes into one geometric figure, and use the merged result as the child node of the corresponding internal node in the previous level.

[0070] Step S42: Perform Boolean operations layer by layer upwards until the root node completes the Boolean operation, and obtain the final merged graphic.

[0071] In this embodiment, the bottom-up order refers to the sequence of traversing and performing merge operations layer by layer from the leaf node level of the binary tree towards the root node. The leaf node level corresponds to the original geometric shapes and does not require any computation.

[0072] As an optional implementation, starting from the leaf node layer, each pair of child nodes in the current level is traversed. A Boolean union operation is performed on each pair of child nodes, merging the geometric figures corresponding to the two child nodes into one figure. The merged result is then used as the input for the child node of the corresponding parent node in the next higher level. Within the same level, the operands of the Boolean operations corresponding to each internal node are independent of each other. Multiple Boolean union operations within the same level are distributed to multiple processor cores for parallel execution. The two operands participating in the same Boolean union operation both come from the paired merge results of the previous level, and their vertex size and topological complexity are comparable. This process is repeated layer by layer upwards until the root node completes its final Boolean union operation, resulting in the final merged figure of all geometric figures in the target network. If a parent node has only one child node, the merged result of that parent node is directly the figure corresponding to that child node, without needing to perform a Boolean operation.

[0073] For example, taking 8 geometric shapes as an example, the binary tree has 3 levels. The first level performs 4 Boolean union operations on the 8 leaf nodes in pairs to obtain 4 intermediate results; the second level performs 2 Boolean union operations on the 4 intermediate results in pairs to obtain 2 intermediate results; the third level performs 1 Boolean union operation on the 2 intermediate results to obtain the final merged shape.

[0074] This embodiment performs Boolean union operations layer by layer upwards from the leaf node layer, ensuring that the two graphs being merged at each layer are roughly the same size, thus avoiding the problem of continuous expansion of accumulated results in sequential merging. The independence of multiple pairs of child nodes within the same layer allows Boolean operations within the same layer to be executed in complete parallel, significantly reducing computation time on multi-core processors. By merging layer by layer upwards until the root node completes its final operation, the computation depth of the entire merging process is controlled to log₂n layers, achieving an order-of-magnitude reduction compared to the n-1 layers of sequential merging. Regarding error control, errors in this embodiment are only propagated within log₂n layers. The two operands in each layer experience approximately the same number of layers of accumulation, resulting in comparable accuracy. The accuracy asymmetry problem of "old accumulated results versus new graphs" in traditional sequential merging is eliminated, and the total accumulated error is significantly lower than in the sequential method. In terms of intermediate result control, the binary tree structure ensures that the two graphs participating in the operation at each layer are roughly equal in size, avoiding the problem of the number of vertices in the later stages of sequential merging far exceeding the number of vertices in a single graph. Combined with spatial pre-sorting optimization, graphs within the same group are physically closer, resulting in higher merging efficiency and further suppressing the expansion of intermediate results.

[0075] Based on any of the above embodiments, this seventh embodiment proposes a method for parsing layout design files. Please refer to [link / reference]. Figure 2 Before obtaining two complementary subsets by alternately coloring and grouping the geometric figures in the set of figures to be merged using a two-color shader, steps A10 to A30 may be included: Step A10: Calculate the bounding box center coordinates of each geometric figure in the set of figures to be merged.

[0076] In this embodiment, the bounding box refers to the smallest axis-aligned rectangle that can completely contain the geometry, determined by the minimum and maximum values ​​in the X direction and the Y direction. The center coordinates of the bounding box refer to the center position of the bounding box in the X and Y directions, used to approximately characterize the spatial distribution of the geometry.

[0077] As an optional implementation, after constructing the set of graphics to be merged, each geometric shape in the set is traversed to obtain the coordinate sequence of the vertices of the closed polygon boundary of each geometric shape. The minimum and maximum values ​​of the geometric shape in the X and Y directions are calculated to determine its bounding box range, and then the center coordinates of the bounding box are calculated. After the calculation is completed, the center coordinates are associated with and stored with the corresponding geometric shape.

[0078] Step A20: Sort the center coordinates of the bounding boxes of each geometric figure according to the space filling curve.

[0079] In this embodiment, the space-filling curve refers to a curve mapping method that maps points in two-dimensional space to one-dimensional space while maintaining spatial proximity. Through the space-filling curve, spatially adjacent geometric figures are also adjacent in the sorted one-dimensional sequence.

[0080] As an optional implementation, the spatial filling curve sorting can be achieved using Morton code curves. First, the bounding box center coordinates of each geometric shape in the set of shapes to be merged are calculated. The vertices of the closed polygon boundaries of each geometric shape are traversed, and the minimum and maximum values ​​in the X and Y directions are recorded respectively, and the center coordinates are calculated. Then, the center coordinates are mapped to integer coordinates with a preset grid precision, discretizing the physical extent of the entire geometric set into a uniform grid, and mapping the center coordinates of each geometric shape to the corresponding grid cell position. Next, Morton code encoding is used to map the two-dimensional grid coordinates to one-dimensional curve values. One-dimensional codes are generated by interleaving the binary bits of the integer coordinates bit by bit, ensuring that the one-dimensional code values ​​corresponding to coordinate points that are close in distance in two-dimensional space are also close. Finally, the geometric shapes are sorted from smallest to largest according to their Morton code values. After sorting, spatially adjacent geometric shapes have adjacent index numbers in the set of shapes to be merged, making them more likely to be grouped into the same subset during two-color grouping, thereby increasing the probability of spatial overlap within the same group and reducing vertex expansion in the intermediate results during the merging process.

[0081] Alternatively, the spatial filling curve sorting can also be implemented using Hilbert curves. For Hilbert curves, the curve order is generated through recursive fractal mapping. A pre-computed lookup table can be used to convert the two-dimensional coordinates into corresponding one-dimensional curve values, and then sort them according to the curve values ​​in ascending order. Compared to Morton codes, Hilbert curves have better spatial proximity preservation, meaning that adjacent points in two-dimensional space are more likely to remain adjacent in the one-dimensional sequence of Hilbert curves, but their implementation is relatively complex.

[0082] Step A30: Rearrange the order of each geometric figure in the set of figures to be merged according to the sorting result, so that spatially adjacent geometric figures have adjacent index numbers.

[0083] In this embodiment, rearrangement refers to updating the storage order of each geometric figure in the set of figures to be merged according to the sorting result, so that the sorted geometric figures are reorganized in a new order.

[0084] As an optional implementation, based on the sorting results of the space filling curve, each geometric shape is sequentially extracted and refilled into the set of shapes to be merged according to the sorting order, so that the geometric shapes in the set are changed from an unordered arrangement to an ordered arrangement according to their spatial position. Through the above rearrangement, the arrangement order of each geometric shape in the set of shapes to be merged reflects its spatial proximity relationship, and geometric shapes with adjacent serial numbers are also adjacent in physical space.

[0085] This embodiment calculates the bounding box center coordinates of each geometric shape, quantifying the position of the geometric shape in physical space into sortable center point coordinates, providing input data for spatial sorting. By sorting the center coordinates using a space-filling curve, adjacent geometric shapes in two-dimensional space are also adjacent in the sorted one-dimensional sequence, transforming the proximity relationship in physical space into a proximity relationship in a set index. By rearranging the order of the geometric shapes in the set to be merged according to the sorting results, spatially adjacent geometric shapes have adjacent index numbers, transforming the unordered arrangement into an ordered arrangement based on spatial position. Since geometric shapes with adjacent index numbers are also adjacent in physical space, geometric shapes within the same group are more likely to be spatially adjacent or even overlap, allowing for faster merging into connected regions during Boolean merge operations, reducing vertex expansion in intermediate results. Simultaneously, spatially adjacent shapes meet and merge earlier within the same group, reducing the cumulative computational load in subsequent merging stages, thereby further improving overall merging efficiency.

[0086] Based on any of the above embodiments, this embodiment eight proposes a method for parsing layout design documents, wherein the method for parsing layout design documents further includes steps B10 to B20: Step B10: When there exists a target subset containing a first geometric figure and no second geometric figure paired with the first geometric figure, the node corresponding to the target subset is used as the input of the upper-level node, and Boolean union operation is not performed.

[0087] Step B20: When the final merged graphic contains multiple unconnected sub-regions, each sub-region is output as geometric input data of independent mesh partitioning.

[0088] In this embodiment, the target subset refers to the subset containing a single geometric shape without a paired shape within a certain level during the recursive grouping process. A pair refers to two child nodes under the same parent node in a binary tree, used to perform a Boolean union operation. The parent level node refers to the parent node level of the current level in the binary tree. Disconnected sub-regions refer to multiple independent, spatially non-touching connected components contained in the final merged shape; shapes under the same electrical network may form multiple separate regions in physical space.

[0089] As an optional implementation, during the bottom-up hierarchical merging process, when traversing each group at the current level, if a group contains only one geometric shape without a paired shape, then that geometric shape is directly used as the input to the node of the next higher level, and Boolean union operation is not performed. This ensures that any number of geometric shapes can be correctly merged in the binary tree merging structure without the need to construct additional paired shapes. For the final merged shape, if the merged result contains multiple disconnected sub-regions, then the closed polygon boundary data of each sub-region is extracted, and each sub-region is output as independent meshed geometric input data. In electromagnetic simulation, multiple disconnected regions under the same electrical network can be meshed separately without affecting the correctness of subsequent electromagnetic field solutions, while avoiding the large amount of internal boundary calculation overhead generated when merging multiple disconnected regions into a single shape.

[0090] This embodiment ensures that any number of geometric shapes can be correctly merged in the binary tree merging structure by handling the case of a single shape without pairing, without the need to construct additional paired shapes. By processing the regional output when the merged result contains multiple unconnected sub-regions, multiple unconnected regions under the same electrical network can be meshed separately without affecting the correctness of the subsequent electromagnetic field solution. At the same time, it avoids the large amount of internal boundary calculation overhead generated when forcibly merging multiple unconnected regions into a single shape.

[0091] This application provides a layout design file parsing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the layout design file parsing method in Embodiment 1 above.

[0092] The following is for reference. Figure 3 The diagram illustrates a structural schematic of a layout design document parsing device suitable for implementing embodiments of this application. The layout design document parsing device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablets, and in-vehicle terminals, as well as fixed terminals such as digital TVs and desktop computers. Figure 3 The illustrated layout design document parsing device is an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0093] like Figure 3As shown, the layout design document parsing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The random access memory 1004 also stores various programs and data required for the operation of the layout design document parsing device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the layout design document parsing device to communicate wirelessly or wiredly with other devices to exchange data. Although layout design document parsing devices with various systems are shown in the figures, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems may be implemented alternatively.

[0094] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0095] The layout design file parsing device provided in this application, employing the layout design file parsing method in the above embodiments, can solve the technical problem of low efficiency in sequential merging calculations of geometric figures. Compared with the prior art, the beneficial effects of the layout design file parsing device provided in this application are the same as those of the layout design file parsing device provided in the above embodiments, and other technical features in this layout design file parsing device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0096] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0097] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0098] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the layout design file parsing method in the above embodiments.

[0099] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, radio frequency (RF), or any suitable combination thereof.

[0100] The aforementioned computer-readable storage medium may be included in a layout design document parsing device; or it may exist independently and not be assembled into a layout design document parsing device.

[0101] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by a layout design file parsing device, the layout design file parsing device performs the following actions: parses at least one target network in the layout design file, extracts all geometric figures under each target network to form a set of figures to be merged, wherein the set of figures to be merged contains n geometric figures, each represented by a closed polygon boundary; uses a two-color shader to alternately color and group each geometric figure in the set of figures to be merged according to its index number, obtaining two complementary subsets; recursively performs the alternating coloring grouping on each subset until the number of geometric figures contained in each subset is no greater than one, constructing a binary tree merging structure; traverses the binary tree merging structure in a bottom-up hierarchical order, performing Boolean operations layer by layer to obtain the final merged figure of all geometric figures under the target network; and outputs the final merged figure as the geometric input data for mesh partitioning.

[0102] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0104] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0105] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described layout design file parsing method, which can solve the technical problem of low efficiency in sequential merging calculations of geometric figures. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the layout design file parsing method provided in the above embodiments, and will not be repeated here.

[0106] This application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the layout design file parsing method described above.

[0107] The computer program product provided in this application can solve the technical problem of low efficiency in sequential merging calculations of geometric figures. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the layout design file parsing method provided in the above embodiments, and will not be repeated here.

[0108] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent scope of this application.

Claims

1. A method for parsing layout design files, characterized in that, The method for parsing the layout design file includes: At least one target network in the layout design file is obtained by parsing, and all geometric figures under each target network are extracted to form a set of figures to be merged. The set of figures to be merged contains n geometric figures, each of which is represented by a closed polygon boundary. Two-color shaders are used to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers, resulting in two complementary subsets. The alternating coloring grouping is recursively performed on each subset until the number of geometric figures contained in each subset is no more than one, and a binary tree merging structure is constructed. The binary tree merging structure is traversed in a bottom-up hierarchical order, and Boolean operations are performed layer by layer to obtain the final merged graphic of all the geometric figures under the target network. The final merged graphic is output, and the final merged graphic is used as the geometric input data for mesh generation.

2. The method for parsing layout design documents as described in claim 1, characterized in that, The analysis yields at least one target network in the layout design file, and extracts all geometric figures under each target network to form a set of figures to be merged, including: The layout design file is parsed to obtain geometric data organized in units of electrical networks; Determine at least one target network from the geometric data; For each target network, extract the geometric figures belonging to the target network to form a set of figures to be merged corresponding to the target network; The geometry includes at least one of trace segments, pads, vias, and copper-clad areas, and the closed polygon boundary includes an outer ring vertex coordinate sequence and / or an inner ring vertex coordinate sequence.

3. The method for parsing layout design documents as described in claim 1, characterized in that, After parsing to obtain at least one target network in the layout design file, and extracting all geometric figures under each target network to form a set of figures to be merged, the process further includes: The connectivity check and validity verification are performed on each of the geometric figures in the set of figures to be merged; wherein, the connectivity check is to determine whether there is a connection relationship between the geometric figures that needs to be merged; the validity verification includes marking degenerate geometric figures with fewer than three vertices as invalid geometric figures and removing them from the set of figures to be merged, and repairing or marking geometric figures with self-intersection or other topological errors; After completing the connectivity check and validity verification, the number of valid geometric figures in the set of figures to be merged is counted. When the number of valid geometric figures is not greater than one, the valid geometric figures are output as the final merged figures, or an empty set is output.

4. The method for parsing layout design documents as described in claim 1, characterized in that, The method employs a two-color shader to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers, resulting in two complementary subsets, including: The index number corresponding to each geometric image is determined according to the arrangement order of the geometric figures in the set of figures to be merged; Each geometric figure with an odd index number in the set of figures to be merged is assigned a first color and assigned to a first subset. Each of the geometric figures with an even index number is assigned a second color and placed into a second subset.

5. The method for parsing layout design documents as described in claim 1, characterized in that, The complementary subsets include a first subset and a second subset. The alternating coloring grouping is recursively applied to each subset until the number of geometric shapes contained in each subset is no greater than one, constructing a binary tree merging structure, including: The alternating coloring grouping is performed on the first subset and the second subset respectively to obtain the next level of subsets; Repeat the alternating coloring grouping for the next level subset until the number of geometric shapes contained in each subset is no more than one. Using each of the aforementioned geometric shapes as leaf nodes and the Boolean operations performed on the geometric shapes corresponding to two child nodes as internal nodes, the binary tree merging structure is constructed; wherein, the root node of the binary tree merging structure corresponds to the Boolean operation result of all geometric shapes in the set of shapes to be merged, and the depth of the binary tree merging structure is the logarithm of base 2 n rounded up, where n is the number of geometric shapes in the set of shapes to be merged.

6. The method for parsing layout design documents as described in claim 1, characterized in that, The process involves traversing the binary tree merging structure in a bottom-up, hierarchical order, performing Boolean operations layer by layer to obtain the final merged graphic of all geometric figures in the target network, including: Starting from the level corresponding to the leaf node of the binary tree merging structure, Boolean operations are performed on each pair of child nodes in the current level in a bottom-up order to merge the geometric figures corresponding to the two child nodes into one geometric figure, and the merging result is used as the child node of the corresponding internal node in the previous level. Boolean operations are performed layer by layer upwards until the root node completes the Boolean operation, resulting in the final merged graphic.

7. The method for parsing layout design documents as described in claim 1, characterized in that, Before using a two-color shader to alternately color and group the geometric figures in the set of figures to be merged according to their index numbers to obtain two complementary subsets, the process includes: Calculate the bounding box center coordinates of each geometric figure in the set of figures to be merged; Sort the bounding box center coordinates of each of the geometric figures according to the space filling curve; The order of the geometric figures in the set of figures to be merged is rearranged according to the sorting results, so that spatially adjacent geometric figures have adjacent index numbers.

8. The method for parsing layout design documents as described in claim 1, characterized in that, The method further includes: When there exists a target subset containing a first geometric figure and no second geometric figure paired with the first geometric figure, the node corresponding to the target subset is used as the input of the node of the next higher level, and Boolean union operation is not performed; When the final merged graphic contains multiple unconnected sub-regions, each sub-region is output as geometric input data of independent mesh partitioning.

9. A device for parsing layout design files, characterized in that, The layout design file parsing device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the layout design file parsing method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, it implements the steps of the layout design document parsing method as described in any one of claims 1 to 8.

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