Pulse neural network combined mapping method and system for neuromorphic hardware

Abstract

The application discloses a kind of pulse neural network combined mapping methods for neuromorphic hardware, the method includes: step S1: input analysis stage;To complete SNN model and the standardization modeling of hardware resources, output triad feature vector;The triad feature vector includes topological dynamics, parallelism and hardware reliability;Step S2: scene identification stage;To distinguish scene, output strategy combination scheme;Step S3: strategy selection stage;To schedule single strategy, the collaborative execution of multi-strategy, configure compromise hyperparameter, control multi-objective trade-off ratio;Step S4: mapping generation stage;To output compliant, performance quantifiable hardware deployment mapping scheme, generate mapping result that meets all hardware constraints, with theoretical performance guarantee.The system is implemented based on the above method.The application has the advantages of simple principle, small overhead, wide application range, good robustness, etc.

Description

Technical Field

[0001] This invention mainly relates to the fields of neuromorphic computing and spiking neural network (SNN) technology, specifically a spiking neural network combinatorial mapping method and system for neuromorphic hardware. Background Technology

[0002] Spiking neural networks (SNNs) have become the core computing model in the field of neuromorphic computing due to their event-driven computational characteristics, sparse neuron communication patterns, and ultra-low hardware power consumption. However, efficiently deploying trained SNNs onto neuromorphic hardware faces a key technical challenge—the "mapping problem."

[0003] Neuromorphic hardware typically consists of multiple neural synaptic nuclei interconnected via on-chip networks (NoCs). The mapping problem is essentially a typical constrained multi-objective optimization problem, with its main optimization objectives including: minimizing the communication cost between neurons to reduce inference latency and energy consumption; balancing the computational load of each hardware core to improve overall throughput; supporting dynamic updates of the network topology to adapt to online learning needs; supporting multi-user, multi-task concurrency to achieve performance isolation; and tolerating permanent / transient failures in nanoscale hardware to improve system reliability.

[0004] Existing traditional spiking neural network mapping methods still have some technical shortcomings: 1. Limitations of Single-Objective Optimization: Existing methods often focus on a single optimization objective. For example, communication optimization methods such as SpiNeMap focus on minimizing the transmission distance of pulse signals, but often lead to severe uneven load distribution among cores, with some cores overloaded while others are idle; while throughput optimization methods such as DFSynthesizer only focus on computational throughput, but sacrifice the spatial locality of inter-core communication and increase data exchange overhead.

[0005] 2. Lack of dynamic adaptability: In scenarios requiring online learning, the synaptic connections of spiking neural networks continuously change (e.g., synaptic plasticity based on STDP). Static mapping cannot respond to this dynamic evolution, causing the mapping scheme to fail after only a few training cycles.

[0006] 3. Does not support multi-tenancy and fault-tolerant deployment: When multiple spiking neural networks are executed concurrently, existing solutions either map each network independently and simply coexist on the same hardware, resulting in severe crosstalk between cores; or they do not detect nanoscale permanent / transient faults in the hardware at all, causing deployment failure.

[0007] 4. Lack of theoretical guarantee mechanism: Existing heuristic methods do not provide theoretical lower bounds, impossible results and combinatorial performance guarantees for simultaneous optimization of multiple objectives, and designers cannot predict the approximate optimality of the mapping scheme.

[0008] Therefore, there is an urgent need for a mapping framework that can adaptively select or combine dedicated mapping strategies according to different deployment scenarios and has theoretically provable performance guarantees. Summary of the Invention

[0009] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a simple, low-cost, widely applicable, and robust spiking neural network combinatorial mapping method and system for neuromorphic hardware.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A combinatorial mapping method for spiking neural networks for neuromorphic hardware, comprising: Step S1: Input Analysis Stage; used to complete the standardized modeling of the SNN model and hardware resources, and output a ternary feature vector; the ternary feature vector includes topological dynamics, parallelism, and hardware reliability; Step S2: Scene recognition stage; used to distinguish between five basic scenes and composite / hybrid scenes, and output strategy combination schemes; Step S3: Strategy selection phase; used to schedule the coordinated execution of single and multiple strategies, configure trade-off hyperparameters, control the multi-objective trade-off ratio, achieve low-interference combination of multiple strategies, and ensure that performance degradation after combination is controllable; Step S4: Mapping generation stage; used to output compliant and quantifiable hardware deployment mapping schemes, generating mapping results that meet all hardware constraints and have theoretical performance guarantees.

[0011] As a further improvement of the present invention: step S1 includes: The directed graph G=(V,E) of the receiving spiking neural network and its hardware topology description; Read hardware NoC parameters: k×k two-dimensional grid, maximum capacity of single-nucleus neuron / synapse, set of faulty nuclei; Extract network features: feedforward, parallel branching, dynamic evolution, number of tasks, and hardware failure rate.

[0012] As a further improvement of the present invention: step S2 includes: Decision tree traversal based on ternary feature vectors; Automatically match the current deployment scenario: static feedforward, parallel branch, dynamic evolution, multi-tenancy, faulty hardware, and composite scenarios; Output single-policy and multi-policy combination instructions.

[0013] As a further improvement of the present invention: step S3 includes: Based on the decision tree leaf nodes, load the corresponding dedicated sub-strategy; Combined scheduling rules for execution strategies in complex scenarios; Configuration strategy hyperparameters: balancing factor ε, number of redundant replicas r, performance degradation threshold δ; The complete mapping from the output neuron to the physical kernel, M: V→C, ensures that all hardware capacity constraints are met.

[0014] As a further improvement of the present invention: step S4 includes: Execute the selected sub-strategy / combination strategy to generate a neuron-to-physical kernel mapping M:V→C; Verify all hardware capacity constraints, fault core avoidance, and partition isolation constraints; Output a complete mapping table, communication cost / load balancing quantification metrics, and theoretical approximation ratio evaluation results.

[0015] As a further improvement of the present invention: the single strategy includes: LynxDAG is a communication optimization mapping for static feedforward networks. For feedforward networks with a clear hierarchical structure, a hierarchical greedy placement algorithm is adopted. The algorithm traverses the network in layer order, and consecutive layers are preferentially assigned to adjacent physical cores or the same core to minimize the Manhattan transmission distance of cross-layer communication on NoC. LynxBalance, a load balancing mapping for parallel branch networks, divides neurons into several clusters through a balance graph partitioning. The target load of each cluster is set to total_neurons / number of clusters, and the balance factor ε regulates the trade-off between communication cost and load balancing. LynxDynamic, an incremental remapping algorithm for evolutionary topology, detects topological changes in spiking neural networks during operation (including the addition / deletion of neurons, the enhancement / inhibition of synaptic connections, etc.) and performs local remapping only on the affected regions, rather than performing global remapping on the entire network. LynxMulti, a resource partitioning and performance isolation solution for multi-tenant coexistence, initially partitions the physical core set according to the resource requirements of each spiking neural network when multiple spiking neural networks share the same hardware resources. Then, it uses the Kernighan-Lin fine partitioning algorithm to minimize cross-partition communication interference. LynxFault, a fault-tolerant mapping for unreliable hardware, identifies key neurons in the network and assigns r redundant copies to each key neuron, placing them on different healthy cores; non-key neurons are assigned to a single core but avoid faulty cores.

[0016] As a further improvement of the present invention: a multi-strategy combination based on the single strategy is formed, including: a combination of the load balancing mapping LynxBalance for parallel branch networks and the fault-tolerant mapping LynxFault for unreliable hardware, which achieves fault tolerance while load balancing; firstly, the load balancing mapping LynxBalance for parallel branch networks is used for load balancing mapping, and then redundant copies are allocated to key neurons to ensure that fault tolerance does not destroy the original load balancing effect.

[0017] As a further improvement of the present invention: a multi-strategy combination based on the single strategy is formed, including: a combination of the communication optimization mapping LynxDAG for static feedforward networks and the incremental remapping LynxDynamic for evolving topologies to realize incremental updates of the communication optimization mapping; the initial mapping is generated using the communication optimization mapping LynxDAG for static feedforward networks, and then when the topology changes, the incremental remapping LynxDynamic for evolving topologies is used for local incremental updates, maintaining communication efficiency while reducing the cost of remapping.

[0018] As a further improvement of the present invention: a multi-strategy combination based on the single strategy includes: a combination of LynxMulti, a resource partitioning and performance isolation strategy for multi-tenant coexistence, and LynxDAG, a communication optimization mapping strategy for static feedforward networks, to achieve communication locality optimization under multi-tenant conditions; firstly, LynxMulti, a resource partitioning and performance isolation strategy for multi-tenant coexistence, is used for resource partitioning, and then LynxDAG, a communication optimization mapping strategy for static feedforward networks, is used within each partition to achieve communication optimization mapping, thereby achieving dual protection of isolation and communication efficiency.

[0019] The present invention further provides a spiking neural network combined mapping system for neuromorphic hardware, including a processor and a storage unit, wherein the storage unit stores a computer program for executing any of the above methods.

[0020] Compared with the prior art, the advantages of the present invention are as follows: 1. The present invention relates to a combinatorial mapping method and system for spiking neural networks on neuromorphic hardware. This method is simple in principle, has low overhead, wide applicability, and good robustness. It describes a combinatorial mapping method for deploying spiking neural network models on neuromorphic hardware (such as TrueNorth and Loihi), and its strategy implementation and combinatorial application mechanisms in various application scenarios. It also involves the hardware-software co-design of multi-objective optimization mapping in Network-on-Chip (NoC).

[0021] 2. The present invention provides a combinatorial mapping method and system for neuromorphic hardware-oriented spiking neural networks. This innovative design addresses the technical shortcomings of existing spiking neural network mapping methods, which struggle to effectively balance conflicting objectives such as minimizing communication costs, maximizing load balancing, adaptability to dynamic topology updates, multi-tenant concurrency isolation, and hardware fault tolerance robustness. The invention is a modular, scenario-adaptive combinatorial mapping framework (named Lynx), enabling designers to flexibly select or combine specific mapping strategies based on specific deployment scenarios (such as static inference, parallel computing, online learning, multi-tenant concurrency, and unreliable hardware operation). Theoretically, it guarantees near-optimality of the combinatorial mapping (providing an upper bound on the degradation of combinatorial performance) and maintains near-linear time complexity to adapt to the needs of large-scale spiking neural network deployments. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the principle of the present invention in a specific embodiment.

[0023] Figure 2 This is a schematic diagram of a decision tree structure in a specific embodiment of the present invention, which automatically selects an appropriate mapping strategy based on three features of a spiking neural network. Each leaf node corresponds to one of five dedicated strategies or a combination thereof.

[0024] Figure 3 This is a schematic diagram of the communication optimization mapping results of the static feedforward spiking neural network in a specific embodiment of the present invention; wherein (a) inter-layer communication strength matrix; (b) layer-core allocation scheme generated by LynxDAG (each core is labeled with the layer number it carries); (c) normalized NoC communication traffic distribution; (d) a bar chart comparing the average pulse transmission distance of each mapping strategy.

[0025] Figure 4 This is a schematic diagram of the load balancing performance of LynxBalance in a specific implementation of the present invention; where (a)-(c) are the heatmaps of kernel utilization of LynxBalance, DFSynthesizer and SpiNeMap respectively; (d)-(f) are the corresponding load distribution histograms and Gini coefficients.

[0026] Figure 5 This is a schematic diagram illustrating the performance of LynxDynamic in a topology change scenario in a specific example of the present invention; wherein (a) is the performance timeline under topology change; (b) the change in mapping stability over time; (c) the comparison of remapping costs; and (d) the state diagram of scalability during bottle closing as the scale of change increases.

[0027] Figure 6This invention relates to a specific example of LynxMulti's multi-tenant resource partitioning scheme; wherein (a) LynxMulti intelligent partitioning (including isolation zones); (b) uncoordinated independent mapping; (c) naive coexistence; (d) comparison of throughput, fairness index and interference; (e) communication conflict graph; and (f) comparison of resource allocation fairness.

[0028] Figure 7 This is a specific example of the fault-tolerant mapping scheme for LynxFault in this invention; wherein (a) is a distribution map of 10% fault kernels and key neuron identifiers; (b) is the fault-aware mapping of LynxFault; (c) is a failure scheme without fault-aware mapping; (d) is the fault avoidance rate and performance loss curves under different failure rates; (e) is the trade-off analysis of redundancy strategies; and (f) is a schematic diagram of critical path protection.

[0029] Figure 8 This is a schematic diagram illustrating the overall performance of the present invention in a specific instance; wherein (a) the Pareto front of communication cost and load balancing; (b) the overall performance score under each network architecture; (c) a multi-target radar chart showing the balance of the combined strategy; and (d) the time complexity growth curve as the network scale expands. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] The core innovation of this invention lies in abandoning the traditional "one-size-fits-all" single mapping strategy design paradigm and pioneering a modular, scenario-adaptive, and theoretically provable combinatorial mapping architecture—Lynx. For multiple different deployment scenarios (such as static feedforward networks, parallel branch networks, evolving topology networks, multi-tenant coexistence scenarios, and unreliable hardware scenarios), five dedicated sub-strategies are designed. Theoretical analysis and rigorous mathematical derivation prove that each sub-strategy, when combined, maintains near-optimal performance and satisfies a preset lower bound on the approximation ratio. This is fundamentally different in form from existing methods, such as SpiNeMap and DFSynthesizer, which are single-paradigm mapping schemes that cannot cover the needs of multiple scenarios and lack theoretical guarantees of combinatoriality.

[0032] like Figures 1 to 8 As shown, this invention discloses a combinatorial mapping method for spiking neural networks for neuromorphic hardware, the process of which includes: Step S1: Input Analysis Phase; It is used to complete the standardized modeling of SNN models and hardware resources, and outputs a ternary feature vector; the ternary feature vector includes topological dynamics, parallelism and hardware reliability; it provides quantitative input for subsequent automatic scene recognition and unifies the interfaces of various SNNs and neuromorphic hardware. Compared with existing traditional solutions, which only analyze the network or hardware separately and lack a standardized feature extraction module, they cannot achieve automated scene determination. In a specific application example, step S1 specifically includes: The directed graph G=(V,E) of the receiving spiking neural network and its hardware topology description; Read hardware NoC parameters: k×k two-dimensional grid, maximum capacity of single-nucleus neuron / synapse, set of faulty nuclei; Extract network features: feedforward, parallel branching, dynamic evolution, number of tasks, and hardware failure rate.

[0033] In specific application examples, the hardware model adopts a k×k two-dimensional grid (such as an 8×8 grid) NoC topology, and each core has a fixed capacity limit (for example, each core can hold a maximum of 1024 neurons and 256K synapses).

[0034] Step S2: Scene recognition stage; It is used to distinguish between five basic scenarios and composite / hybrid scenarios, and outputs strategy combination schemes, thereby eliminating the need for manual selection of mapping algorithms and achieving fully automatic scenario matching.

[0035] That is, the target scenario for the current deployment is automatically identified based on the network structure and operating environment requirements (such as high reliability / failure-prone environments). In specific application examples, the mesh structure includes one or more of the following: feedforward structure, parallel branch structure, and dynamic evolution structure.

[0036] Compared to existing traditional solutions, which lack scenario-based classification decision trees and rely entirely on a single fixed algorithm, these traditional solutions cannot adaptively switch optimization logic.

[0037] In a specific application example, step S2 specifically includes: Decision tree traversal based on ternary feature vectors; Automatically match the current deployment scenario: static feedforward, parallel branch, dynamic evolution, multi-tenancy, faulty hardware, and composite scenarios; Output single-policy and multi-policy combination instructions.

[0038] Step S3: Strategy Selection Phase; It is used to schedule the coordinated execution of single and multiple strategies, configure trade-off hyperparameters, control the proportion of multi-objective trade-offs, realize low-interference combination of multiple strategies, and ensure that the performance degradation after combination is controllable.

[0039] That is, based on a predefined decision tree (such as...) Figure 2As shown, based on three key characteristics—topology dynamics (static vs. evolution), parallelism (sequential network vs. branch network) and deployment environment (reliable vs. fault-prone)—one or more dedicated strategies are automatically selected.

[0040] Compared with existing traditional solutions, existing traditional solutions do not have a multi-strategy combination scheduling mechanism and only run a single algorithm.

[0041] In a specific application example, step S3 specifically includes: Based on the decision tree leaf nodes, load the corresponding dedicated sub-strategy; Combined scheduling rules for execution strategies in complex scenarios, such as basic mapping followed by fault tolerance / dynamic incremental optimization; Configuration strategy hyperparameters: balance factor ε, number of redundant replicas r, performance degradation threshold δ.

[0042] Step S4: Mapping generation stage; It is used to output compliant and quantifiable hardware deployment mapping schemes, along with theoretical performance evaluation reports, and generate mapping results that meet all hardware constraints and have theoretical performance guarantees. That is, the complete mapping from the output neuron to the physical kernel M: V→C, ensuring that all hardware capacity constraints are met.

[0043] Compared with existing traditional solutions, the heuristic algorithms in existing traditional solutions lack constraint verification of closed loops and have no theoretical performance evaluation output.

[0044] In a specific application example, step S4 specifically includes: Execute the selected sub-strategy / combination strategy to generate a neuron-to-physical kernel mapping M:V→C; Verify all hardware capacity constraints, fault core avoidance, and partition isolation constraints; Output a complete mapping table, communication cost / load balancing quantification metrics, and theoretical approximation ratio evaluation results.

[0045] The above-described process of this invention includes five dedicated sub-strategies: LynxDAG for communication optimization mapping of static feedforward networks, LynxBalance for load balancing mapping of parallel branch networks, LynxDynamic for incremental remapping of evolving topologies, LynxMulti for resource partitioning and performance isolation of multi-tenant coexistence, and LynxFault for fault-tolerant mapping of unreliable hardware. Specifically: 1. LynxDAG, a communication optimization mapping for static feedforward networks, employs a layered greedy placement algorithm for feedforward networks with a defined hierarchical structure (such as AlexNet and ResNet). This algorithm traverses the network layer by layer, prioritizing the allocation of consecutive layers to adjacent physical cores or the same core to minimize the Manhattan transmission distance for cross-layer communication on NoC. Its aim is to minimize the number of inter-layer pulse hops and reduce inference latency and energy consumption for static feedforward networks such as AlexNet-SNN and ResNet-SNN.

[0046] In specific application examples, the specific process includes: The neurons of the spiking neural network are divided into layers, resulting in L1, L2, …, Ln; The pulse flow matrix between each layer is statistically analyzed and used as the communication cost weight. Placement decisions are made layer by layer—for the current layer Li, the core with the smallest weighted Manhattan distance from the previous layer is selected as the placement target from the available cores; When the current kernel capacity is exhausted, the next adjacent kernel is automatically activated to continue placement. The time complexity is O(|V|+|E|), where |V| is the total number of neurons and |E| is the total number of synaptic connections.

[0047] In the above process, a hierarchical weighted greedy placement is adopted, with a near-linear time complexity of O(|V|+|E|), which is far superior to the PSO iteration complexity of SpiNeMap. The residual cross-layer traffic is incorporated into the weight calculation, adapting to deep residual SNNs, while the existing SpiNeMap uses global random particle search, lacks hierarchical local optimum greedy logic, and has an average communication overhead that is 23% higher.

[0048] 2. LynxBalance, a load balancing mapping for parallel branch networks, divides neurons into clusters using a balanced graph. The target load for each cluster is set to total_neurons / number of clusters, and a balance factor ε regulates the trade-off between communication cost and load balancing. This approach, for multi-branch parallel networks like MobileNet-SNN, can balance the computational load across hardware cores, improving overall hardware throughput.

[0049] In specific application examples, the specific process includes: The Gini coefficient is used as a quantitative indicator of load balancing (the smaller the Gini coefficient, the more balanced the load). By weighted summing of normalized communication cost and normalized load imbalance (weight coefficient β∈[0,1], the larger β is, the higher the priority of communication optimization, and the smaller β is, the higher the priority of load balancing optimization), the scheme with the smallest weighted sum is selected from all candidate mappings; The balance factor ε allows designers to make flexible trade-offs between communication and load. When ε=0, load balancing is given full priority, and when ε=1, communication optimization is given full priority. The time complexity is O((|V|+|E|)·log|C|), where |C| is the total number of hardware cores.

[0050] In the above process, by introducing a continuously adjustable balancing factor ε, a fine-grained trade-off between communication and load can be achieved; by using the Gini coefficient to quantify the load imbalance, the balancing effect can be quantitatively evaluated; DFSynthesizer only optimizes the load and has no adjustable trade-off weights, resulting in a significant increase in communication overhead.

[0051] 3. LynxDynamic, an incremental remapping approach for evolutionary topology, detects topological changes in the spiking neural network during operation (including neuron addition / deletion, synaptic connection enhancement / inhibition, etc.) and performs local remapping only on the affected regions, rather than a global remapping of the entire network. This significantly reduces the computational overhead of remapping during topology updates for online learning dynamic networks like SNN-LSTM and STDP, maintaining long-term mapping stability. The remapping time is only about 15% of that of a full remapping, while performance degradation is controlled within a δ threshold.

[0052] In specific application examples, the specific process includes: Identify the set of neurons S0 that has changed (neurons that have been added, deleted, or have had their connections altered). Centered on S0, the affected area is gradually expanded through multi-step neighborhood expansion (1 hop, 2 hops, 3 hops...) until the preset performance degradation tolerance threshold δ is met; Perform local remapping on the finally determined affected regions to maximize the mapping stability S (the similarity between the old and new mappings, i.e. the proportion of neurons not affected by the remapping). Keep the mapping of unaffected areas unchanged.

[0053] In the above process, local neighborhood incremental remapping takes only 15% of the time of global remapping; by introducing a mapping stability quantification index, the upper limit of performance degradation δ is strictly limited; existing dynamic schemes all perform global remapping, which has extremely high computational cost and poor stability.

[0054] 4. LynxMulti, a resource partitioning and performance isolation solution for multi-tenant coexistence, initially partitions the physical kernel set according to the resource requirements of each spiking neural network (SNN) when multiple SNNs (multi-tenants) share the same hardware resources. Then, it employs the Kernighan-Lin fine-tuning algorithm to minimize cross-partition communication interference. This allows for fair resource allocation, tenant performance isolation, and suppression of cross-network communication conflicts when multiple SNNs concurrently share hardware.

[0055] In specific application examples, the specific process includes: Resource requirement ratio: Determine the proportion of core resources required by each network based on the number of neurons and synapses in each network; Interference definition: The normalized value of the cost of cross-partition communication; After partitioning, other Lynx strategies (such as LynxDAG or LynxBalance) can be used for further mapping optimization within each partition; Setting up isolation zones at partition boundaries further reduces cross-partition crosstalk.

[0056] In the above process, a partition isolation band mechanism is adopted, which reduces cross-partition interference to 30% of the independent mapping scheme, and other dedicated strategies are nested within the partition, taking into account both isolation and single network optimization; in contrast, the existing multi-task scheme simply superimposes mapping without partition isolation, and there is no optimization for fairness and interference control.

[0057] 5. LynxFault, a fault-tolerant mapping for unreliable hardware, identifies key neurons in the network (ranked based on metrics such as fan-out count, synaptic connection weights, or gradient sensitivity) and assigns r redundant copies to each key neuron, placing them on different healthy kernels. Non-key neurons are assigned to a single kernel but avoid faulty kernels. This ensures robustness of network inference and controls performance loss under fault conditions, even in hardware scenarios with manufacturing defects or transient failures.

[0058] In specific application examples, the specific process includes: Obtain the set of faulty kernels F (permanent faulty kernels, such as functional failures due to nanoscale manufacturing defects) from the hardware configuration, and ensure that these kernels are avoided during mapping; Neurons are ranked based on sensitivity metrics (fan-out number, synaptic weight, gradient sensitivity), and a certain percentage of the top-ranked neurons are marked as key neurons. Each key neuron is assigned r redundant copies, ensuring that the primary copy and the copies are placed on different healthy nuclei; Non-critical neurons are assigned single nuclei, but faulty nuclei are avoided. When the network is running, if the core where the primary replica resides fails, the system will automatically switch to the core where the replica resides to continue running.

[0059] In the above process, key neurons are redundantly backed up in a hierarchical manner, and the primary and secondary neurons are differentiated for fault tolerance, which can reduce redundancy overhead. By pre-identifying faulty kernels and distributing copies across kernels, a fault avoidance rate of 98% can be achieved with a 10% fault rate. Existing fault tolerance schemes have globally unified redundancy, resulting in huge hardware resource overhead and no hierarchical mechanism for key neurons.

[0060] Furthermore, in a preferred embodiment, the present invention supports multiple combinations of the above strategies to meet complex multi-objective optimization requirements, such as: 1. LynxBalance + LynxFault: Achieve fault tolerance while maintaining load balancing; First, LynxBalance is used for load balancing mapping, and then redundant copies are allocated to key neurons to ensure that fault tolerance does not compromise the original load balancing effect.

[0061] 2. LynxDAG + LynxDynamic: Communication-optimized incremental updates of mappings; The initial mapping is generated using LynxDAG, and then LynxDynamic is used for local incremental updates when the topology changes, maintaining communication efficiency while reducing the cost of remapping. 3. LynxMulti + LynxDAG: Communication locality optimization in multi-tenancy environments; First, use LynxMulti to partition resources, and then use LynxDAG within each partition for communication optimization mapping to achieve dual protection of isolation and communication efficiency.

[0062] This invention not only provides an engineering implementation solution, but also provides rigorous theoretical performance guarantees: Theoretical lower bound (Theorem 1): It is proved that the product of communication cost and load balancing is not less than Ω(1 / √|C|), that is, it is impossible for any mapping scheme to achieve both extremely low communication cost and excellent load balancing at the same time, revealing the inherent constraints of multi-objective optimization.

[0063] Impossibility result (Theorem 2): It proves that there is no single mapping strategy that can simultaneously achieve (1+ε)-approximate optimality in both communication cost and load balancing dimensions (when ε is less than (log|C|) / 2|C|), which theoretically illustrates the necessity of scenario-specific strategies.

[0064] Pareto front closed-form solution (Theorem 3): It gives the power-law relationship between communication cost and load balancing, C_comm·I^α=constant, which allows designers to predict the inherent trade-off between the two objectives without exhaustive search.

[0065] Combinatorial performance guarantee (Theorem 4): It is proved that when multiple sub-maps are combined in a low-interference manner, the overall performance degradation does not exceed the maximum value of the approximation ratio of each sub-map and the linear combination of the interference term, thus ensuring the predictability of the combined mapping.

[0066] Specific application example of the present invention: Static reasoning scenario (LynxDAG); Taking the deployment of ResNet-18-SNN on an 8×8 grid NoC neuromorphic hardware as an example, the Lynx framework first reads the network model file (ONNX or a custom SNN format) during the input analysis phase, parsing out the neuron layer structure and synaptic connections. During the scene recognition phase, the framework detects that the network structure is feedforward and lacks online learning labels, classifying it as a "static inference scene." In the policy selection phase, LynxDAG is selected based on the decision tree.

[0067] LynxDAG algorithm execution steps: The 18 convolutional layers of ResNet-18 are arranged in topological order; Statistical analysis of the pulse flow matrix between adjacent layers (e.g., the residual connections in ResNet-18 introduce cross-layer flow). The first layer (input convolutional layer) is placed at kernel (0,0) and has a capacity of 1024 neurons. The first layer actually contains approximately 600 neurons, with some capacity remaining. When selecting the second layer (the first residual block), the weighted Manhattan distance of each available kernel relative to the placement distribution in the first layer is calculated. Since there is still remaining capacity at (0,0) and the communication traffic between (0,0) and the second layer is large, some neurons in the second layer are placed on (0,0), and the remaining ones are placed on adjacent kernels (0,1) or (1,0). Place the kernels layer by layer in this manner until all layers are placed, and finally output the kernel occupancy mapping table for each layer.

[0068] In this embodiment, the average pulse transmission distance generated by LynxDAG is 2.31 hops, while the comparison result of SpiNeMap is 3.02 hops, which verifies the communication advantages of the present invention.

[0069] Specific application example 2 of the present invention: Unreliable hardware scenario (LynxBalance + LynxFault combination) Taking the deployment of MobileNet-SNN on an 8×8 grid NoC with 10% random faulty kernels as an example, the framework first parses the branch structure of MobileNet-SNN (a multi-path parallel structure built from depthwise separable convolutions) during the input analysis phase. In the scene recognition phase, if the network is detected to have a parallel branch structure and faulty kernels are marked in the hardware configuration file, it is determined to be a combined scenario of "parallel computing + unreliable hardware". In the strategy selection phase, the LynxBalance + LynxFault combination is selected based on the decision tree.

[0070] Combinatorial mapping execution steps: Step 1: LynxBalance first divides the network into 8 clusters based on the load balancing graph (corresponding to the number of available healthy cores in an 8×8 grid), with each cluster targeting a load of approximately 1 / 8 of the total number of neurons. The load balancing quality is monitored using the Gini coefficient. Step 2: Set the balance factor ε to 0.4 (to balance load while also considering communication) to generate the initial load balancing mapping scheme; Step 3: LynxFault identifies key neurons in the network (based on the fan-out number and gradient sensitivity of each neuron, the top 15% of neurons are selected as key neurons). Step 4: Assign two redundant copies to each key neuron and place them on different healthy nuclei (avoiding faulty nuclei while also avoiding placing the nucleus on the main copy). Step 5: Non-critical neurons maintain single-nucleus allocation and adjust their placement to avoid faulty nuclei; Step 6: Verify that the number of neurons in each nucleus does not exceed the capacity limit (1024 neurons / nucleus).

[0071] This combined solution achieves a 98% failure avoidance rate and only 8% performance loss at a 10% failure rate, while LynxBalance alone cannot handle faulty cores, resulting in a 32% performance loss, and LynxFault alone increases the load balancing Gini coefficient from 0.08 to 0.15.

[0072] It is understandable that in the above application examples, the balancing factor ε of LynxBalance can take different values ​​within the range [0,1] to adapt to different scenarios when algorithm parameters change. For scenarios with high communication sensitivity, ε = 0.8 to 1.0 is chosen to favor communication optimization; for scenarios with high load balancing sensitivity, ε = 0 to 0.2 is chosen to favor load balancing; for scenarios with medium demand, ε = 0.4 to 0.6 is chosen to achieve a trade-off. All values ​​can be implemented through the framework of this invention, the only difference being the performance focus of the output mapping scheme.

[0073] It is understood that, in the above application examples, although the embodiments use an 8×8 two-dimensional mesh NoC as the hardware model for hardware topology adaptation, the method system of this invention can adapt to mesh NoCs of any size (such as 16×16, 32×32, etc.), and can even be extended to 3D mesh NoCs. Only the distance calculation function d_NoC needs to be adjusted to Manhattan distance (2D mesh) or the distance metric corresponding to the 3D topology; the core algorithm flow remains unchanged.

[0074] It is understood that, in the above application examples, for the key neuron identification method, the identification of key neurons in LynxFault can not only use fan-out number and gradient sensitivity, but also betweenness centrality—which measures the strength of the bridging effect of neurons in the network—or other graph theory importance indicators as the basis for judgment, all of which can achieve the purpose of identifying key neurons. The technical concepts of these alternative methods are all within the protection scope of this invention.

[0075] In other words, the core architecture of this invention is not limited to two-dimensional mesh NoC, and can be extended to one-dimensional / two-dimensional / three-dimensional mesh, ring, or tree topologies by adjusting the distance calculation function; the ε of LynxBalance can take any value in the range [0,1] to adapt to different communication-load trade-offs; the number of redundant replicas of LynxFault can be flexibly adjusted between 2 and 5 according to hardware reliability and redundancy overhead requirements. This invention can use fan-out quantity, gradient sensitivity, betweenness centrality, or any weighted combination as identification criteria; in addition to the three characteristics of topology dynamism, network parallelism, and deployment environment reliability, other judgment characteristics (such as energy efficiency priority, time delay sensitivity, etc.) can be extended.

[0076] The present invention further discloses a spiking neural network combinatorial mapping system for neuromorphic hardware, comprising a processor and a storage unit, wherein the storage unit stores a computer program for executing the above-described method of the present invention.

[0077] By adopting the above-described solution of the present invention, its technical effects have been verified through comparative experiments on multiple sets of standard spiking neural network benchmark tests. Specific effects include: (1) In terms of communication efficiency: On static inference networks such as AlexNet-SNN and ResNet-18-SNN, compared with the existing best method SpiNeMap, the average number of communication hops is reduced by about 23%, and the energy consumption per inference pulse is reduced by about 18%.

[0078] (2) Load balancing: On parallel computing networks such as MobileNet-SNN, Gini's load imbalance coefficient reaches 0.08, the core utilization rate reaches over 94%, and the throughput is 27% and 35% higher than DFSynthesizer and SpiNeMap, respectively.

[0079] (3) Dynamic adaptation: On the SNN-LSTM network with continuously changing topology, the mapping stability is maintained at 87%, the performance degradation is limited to within 12%, and the remapping time is only 15% of the full remapping.

[0080] (4) Multi-tenant concurrency: In the scenario of concurrent deployment of three networks, the Jain fairness index reached 0.92, and the cross-partition communication interference control was only about 30% of that of the independent mapping scheme.

[0081] (5) In terms of fault tolerance: with a 10% hardware core failure rate, the fault avoidance rate reaches 98%, and the performance loss is only 8%; while with the same failure rate, the performance loss of the mapping scheme without fault tolerance design is as high as 32%.

[0082] (6) In terms of time complexity: each strategy maintains a near-linear time growth trend, capable of handling large-scale spiking neural networks with millions of neurons, and the mapping time is controlled within 10 seconds, which is far superior to the quadratic or even higher complexity of existing methods.

[0083] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A combinatorial mapping method for spiking neural networks for neuromorphic hardware, characterized in that, include: Step S1: Input Analysis Phase; It is used to complete the standardized modeling of SNN model and hardware resources, and outputs a ternary feature vector; the ternary feature vector includes topological dynamics, parallelism and hardware reliability; Step S2: Scene recognition stage; It is used to distinguish between five basic scenarios and composite / hybrid scenarios, and output strategy combination schemes; Step S3: Strategy selection phase; used to schedule the coordinated execution of single and multiple strategies, configure trade-off hyperparameters, control the multi-objective trade-off ratio, achieve low-interference combination of multiple strategies, and ensure that performance degradation after combination is controllable; Step S4: Mapping generation stage; It is used to output compliant and quantifiable hardware deployment mapping schemes, generating mapping results that meet all hardware constraints and have theoretical performance guarantees.

2. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 1, characterized in that, Step S1 includes: The directed graph G=(V,E) of the receiving spiking neural network and its hardware topology description; Read hardware NoC parameters: k×k two-dimensional grid, maximum capacity of single-nucleus neuron / synapse, set of faulty nuclei; Extract network features: feedforward, parallel branching, dynamic evolution, number of tasks, and hardware failure rate.

3. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 1, characterized in that, Step S2 includes: Decision tree traversal based on ternary feature vectors; Automatically match the current deployment scenario: static feedforward, parallel branch, dynamic evolution, multi-tenancy, faulty hardware, and composite scenarios; Output single-policy and multi-policy combination instructions.

4. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 1, characterized in that, Step S3 includes: Based on the decision tree leaf nodes, load the corresponding dedicated sub-strategy; Combined scheduling rules for execution strategies in complex scenarios; Configuration strategy hyperparameters: balancing factor ε, number of redundant replicas r, performance degradation threshold δ; The complete mapping from the output neuron to the physical kernel, M: V→C, ensures that all hardware capacity constraints are met.

5. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 1, characterized in that, Step S4 includes: Execute the selected sub-strategy / combination strategy to generate a neuron-to-physical kernel mapping M:V→C; Verify all hardware capacity constraints, fault core avoidance, and partition isolation constraints; Output a complete mapping table, communication cost / load balancing quantification metrics, and theoretical approximation ratio evaluation results.

6. The spiking neural network combinatorial mapping method for neuromorphic hardware according to any one of claims 1-5, characterized in that, The single strategy includes: LynxDAG is a communication optimization mapping for static feedforward networks. For feedforward networks with a clear hierarchical structure, a hierarchical greedy placement algorithm is adopted. The algorithm traverses the network in layer order, and consecutive layers are preferentially assigned to adjacent physical cores or the same core to minimize the Manhattan transmission distance of cross-layer communication on NoC. LynxBalance, a load balancing mapping for parallel branch networks, divides neurons into several clusters through a balance graph partitioning. The target load of each cluster is set to total_neurons / number of clusters, and the balance factor ε regulates the trade-off between communication cost and load balancing. LynxDynamic, an incremental remapping algorithm for evolutionary topology, detects topological changes in spiking neural networks during operation (including the addition / deletion of neurons, the enhancement / inhibition of synaptic connections, etc.) and performs local remapping only on the affected regions, rather than performing global remapping on the entire network. LynxMulti, a resource partitioning and performance isolation solution for multi-tenant coexistence, initially partitions the physical core set according to the resource requirements of each spiking neural network when multiple spiking neural networks share the same hardware resources. Then, it uses the Kernighan-Lin fine partitioning algorithm to minimize cross-partition communication interference. LynxFault, a fault-tolerant mapping for unreliable hardware, identifies key neurons in the network and assigns r redundant copies to each key neuron, placing them on different healthy cores; non-key neurons are assigned to a single core but avoid faulty cores.

7. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 6, characterized in that, The multi-strategy combination based on the single strategy includes: a combination of the load balancing mapping LynxBalance for parallel branch networks and the fault-tolerant mapping LynxFault for unreliable hardware, which achieves fault tolerance while balancing the load; firstly, the load balancing mapping LynxBalance for parallel branch networks is used for load balancing mapping, and then redundant copies are allocated to key neurons to ensure that fault tolerance does not destroy the original load balancing effect.

8. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 6, characterized in that, The multi-strategy combination based on the single strategy includes: a combination of the communication optimization mapping LynxDAG for static feedforward networks and the incremental remapping LynxDynamic for evolving topologies to achieve incremental updates of the communication optimization mapping; the initial mapping is generated using the communication optimization mapping LynxDAG for static feedforward networks, and then when the topology changes, the incremental remapping LynxDynamic for evolving topologies is used for local incremental updates, maintaining communication efficiency while reducing the cost of remapping.

9. The spiking neural network combinatorial mapping method for neuromorphic hardware according to claim 6, characterized in that, The multi-strategy combination based on the single strategy includes: a combination of LynxMulti for resource partitioning and performance isolation for multi-tenant coexistence and LynxDAG for communication optimization mapping for static feedforward networks, to achieve communication locality optimization under multi-tenant conditions; firstly, LynxMulti for resource partitioning and performance isolation for multi-tenant coexistence is used for resource partitioning, and then LynxDAG for communication optimization mapping for static feedforward networks is used within each partition to achieve dual protection of isolation and communication efficiency.

10. A combinatorial mapping system for spiking neural networks for neuromorphic hardware, characterized in that, It includes a processor and a storage unit, wherein the storage unit stores a computer program for performing the method described in any one of claims 1-9.

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