Quantum computing system based on dynamic fault-tolerance layer

Abstract

The application provides a quantum computing system based on a dynamic fault-tolerant layer, comprising a software layer, a fault-tolerant layer and a hardware layer; the fault-tolerant layer specifically comprises: a synthesis layer, which is used for standardizing synthesis of a quantum algorithm according to task constraint information to obtain a logical representation; a resource allocation layer, which is used for allocating logical resources according to the logical representation and a hardware state; a translation layer, which is used for realizing logical-to-physical translation; a decoding layer, which is used for performing decoding on a measurement result according to encoding information and feeding back a decoding result and the hardware state to an adaptive scheduling layer; and the adaptive scheduling layer, which is used for sending error correction instructions to the hardware layer according to the decoding result, evaluating a current resource allocation strategy according to the hardware state, and requiring the resource allocation layer to re-allocate resources according to an evaluation result. The application changes fault-tolerant quantum computing from a "fixed implementation mode" to a "dynamic configuration mode", and significantly improves flexibility, efficiency and long-term scalability of a fault-tolerant quantum computing system.

Description

Technical Field

[0001] This invention relates to the field of quantum computing, and more particularly to a quantum computing system based on a dynamic fault-tolerant layer. Background Technology

[0002] Quantum computing, leveraging properties such as quantum superposition, entanglement, and interference, has the potential to surpass classical computing in certain problems. However, current quantum hardware is still susceptible to various non-ideal factors, including decoherence, gate operation errors, measurement errors, crosstalk, control noise, and device parameter drift, making quantum computing results vulnerable to error accumulation. For small- to medium-scale, shallow quantum circuits, these errors can sometimes be partially mitigated through repeated runs, error mitigation, or post-processing. However, for large-scale, deep, and long-running practical quantum algorithms, relying solely on bare physical qubits and simple error mitigation methods is usually insufficient to meet reliability requirements; therefore, quantum error correction and fault-tolerant computing techniques are necessary.

[0003] The basic idea of ​​fault-tolerant quantum computing is to encode logical qubits into multiple physical qubits, and maintain the correctness of the logic layer under the condition of noise in the physical device through continuous stabilizing sub-measurement, decoding, correction, and specific logic gate implementation. In fault-tolerant quantum computing systems, fault-tolerant modules are embedded separately in the compiler, specific error correction code process, or low-level control system. This results in fault-tolerant logic synthesis, resource allocation, logic-to-physical mapping, decoding feedback, and runtime adjustments being dispersed and fixed in the compilation process, error correction code implementation, or hardware control process, making it difficult to manage and dynamically optimize them in a unified manner according to algorithm requirements, resource status, and hardware drift.

[0004] Therefore, existing systems have the following problems in fault-tolerant quantum computing scenarios:

[0005] (1) Fault tolerance parameters are usually statically fixed and lack the ability to be dynamically selected according to the task.

[0006] In existing solutions, many fault-tolerance implementations rely on pre-selected error-correcting codes, fixed code distances, fixed number of logic blocks, fixed patch layouts, and fixed distillation resource configurations. Different algorithms, different precision requirements, different logic depths, and different stages of the task often can only share a set of preset fault-tolerance parameters, which cannot be dynamically adjusted according to actual needs. As a result, for tasks with lower requirements, resource over-configuration is likely; for tasks with higher requirements, insufficient fault tolerance may occur, thus affecting resource utilization and task success rate.

[0007] (2) Fault-tolerant logic is scattered and heavily coupled.

[0008] In existing systems, fault-tolerant functions are often scattered across multiple locations. For example, some are integrated into the compiler, some into a specific error-correcting code implementation, and some are embedded in the underlying hardware control flow. This often requires point-to-point adaptation between different software frameworks, fault-tolerant schemes, and hardware platforms. This deployment method results in unclear system module boundaries, severe coupling between software and hardware, and hinders the subsequent expansion to new error-correcting codes, new hardware platforms, or new scheduling strategies. It also hinders the construction of a cross-platform, universal fault-tolerant quantum computing system.

[0009] (3) Lack of runtime closed-loop feedback mechanism, unable to continuously optimize based on hardware drift.

[0010] Fault-tolerant quantum computing cannot be stably accomplished through a single static orchestration. Real-world hardware experiences error drift, calibration state changes, local resource failures, measurement noise fluctuations, and decoding latency variations during operation. Existing systems lack a channel to feed back underlying measurement results, decoding results, and hardware state changes to upper-level resource allocation and execution decisions. Therefore, once the hardware state deviates from the initial assumptions, existing solutions typically have to continue using the original configuration, making it difficult to adjust code distance, logic resource size, mapping location, or execution strategy in a timely manner, thus affecting system robustness and execution success rate.

[0011] (4) The lack of a hierarchical transition from logical abstraction to physical abstraction makes it difficult to achieve clear fault-tolerant programming.

[0012] In existing technologies, software-layer logical representations are often directly converted into underlying physical execution forms, lacking a clear logical fault-tolerant representation layer. This results in a mixture of "logic-level fault-tolerant decisions" and "physical-level execution details," hindering the formation of a unified layered architecture of logical instruction set architecture (Logical ISA) and physical instruction set architecture (Physical ISA). Due to this lack of layering, it is difficult for the system to decouple algorithm requirements, fault-tolerant resource allocation, and underlying platform adaptation, making it difficult to achieve reusable, replaceable, and scalable fault-tolerant execution chains.

[0013] Due to the aforementioned issues, existing fault-tolerant quantum systems suffer from significant limitations in resource utilization, execution success rate, module scalability, and cross-platform adaptability, typically requiring compromises on only certain local objectives. For example, some solutions are suitable for a specific hardware platform but are difficult to migrate to other platforms; some solutions are suitable for a specific fixed error correction code but struggle to support new code families; some solutions can operate statically but lack runtime optimization capabilities. Ultimately, this results in a system that struggles to simultaneously achieve high resource utilization, high task success rate, good scalability, and cross-platform adaptability. Summary of the Invention

[0014] To address the above problems, the present invention provides a quantum computing system, characterized in that it comprises:

[0015] The software layer is used to generate quantum algorithms and task constraint information;

[0016] Fault-tolerant layer;

[0017] The hardware layer is used to operate physical quantum according to the physical instruction set architecture (physical ISA) output by the fault tolerance layer, and to feed back the measurement results and hardware status to the fault tolerance layer.

[0018] The fault-tolerant layer specifically includes:

[0019] The synthesis layer is used to perform standardized synthesis of the quantum algorithm based on task constraint information to obtain the logical representation of the quantum algorithm.

[0020] The resource allocation layer is used to determine the error correction code type and allocate logical resources based on the logical representation and hardware status, and output the encoding information of the error correction code and the logical instruction set architecture (Logic ISA).

[0021] Translation layer, used to convert logical ISAs into hardware-executable physical ISAs;

[0022] The decoding layer receives measurement results and hardware status from the hardware layer, as well as encoding information from the resource allocation layer. It then decodes the measurement results based on the encoding information and feeds back the decoding results and hardware status to the adaptive scheduling layer.

[0023] The adaptive scheduling layer is used to send error correction instructions to the hardware layer based on the decoding results, evaluate the current resource allocation strategy based on the hardware status, and request the resource allocation layer to reallocate resources and / or request the translation layer to regenerate the physical ISA based on the evaluation results.

[0024] In some embodiments, the quantum algorithm includes quantum circuits and logic gate sequences; the task constraint information includes one or more of the following: accuracy requirements, success rate requirements, logic error rate constraints, latency constraints, resource budget, and task priority.

[0025] In some embodiments, the quantum algorithm is standardized and synthesized to be suitable for fault-tolerant execution based on task constraint information. Specifically, this includes: based on task constraint information, and oriented towards the fault-tolerant execution path, taking into account error correction code implementation, distillation resource pressure, logic gate organization, and scheduling complexity, the quantum algorithm is converted into a standardized logical representation suitable for fault-tolerant execution.

[0026] In some more specific embodiments, converting the quantum algorithm into a standardized logical representation suitable for fault-tolerant execution specifically includes: decomposing the logic gate sequence into Clifford + R_ z The form of (\theta).

[0027] In some embodiments, the resource allocation layer includes an optimizer for optimizing error correction code selection and resource allocation strategies.

[0028] In some embodiments, determining the error correction code type specifically includes: selecting one from a variety of error correction codes as the error correction code to be used in this fault-tolerant quantum computing based on the logical representation and hardware state, and sending the encoding information of the error correction code to the decoding layer.

[0029] In some more specific embodiments, the various error correction codes include surface codes, color codes, Steane codes, convolutional codes, Turbo codes, and Reid-Muller codes.

[0030] In some embodiments, the software layer and the fault-tolerant layer are connected through a first interface, which is used to standardize and transmit the quantum algorithm and task constraint information generated by the software layer to the fault-tolerant layer.

[0031] The fault-tolerant layer is connected to the hardware layer through a second interface, which is used to send the physical ISA to the hardware layer in a standardized manner and to feed back the hardware status and measurement results to the fault-tolerant layer.

[0032] In some embodiments, the hardware layer is any one of a superconducting quantum platform, an ion trap quantum platform, a neutral atom platform, or a photonic quantum platform.

[0033] In some embodiments, the hardware state includes the fidelity of each physical qubit; the current resource allocation strategy is evaluated based on the hardware state, and the resource allocation layer is required to reallocate resources and / or the translation layer is required to regenerate the physical ISA based on the evaluation results. Specifically, this includes: if the fidelity of a certain qubit is lower than 95%, the qubit is marked as unavailable; the unavailability information is synchronized to the resource allocation layer, requiring the resource allocation layer to reallocate resources, and unavailable qubits are avoided when reallocating resources.

[0034] The quantum computing system provided by this invention establishes an independent fault-tolerance layer between the software layer and the underlying hardware layer, freeing fault-tolerance functionality from being dispersed within the compiler or low-level control, thus enhancing the system's scalability and cross-platform adaptability. Simultaneously, a resource allocation layer dynamically determines resource allocation strategies based on task requirements and hardware status. During runtime, a decoding layer and an adaptive scheduling layer feed back the underlying measurement results and hardware status to the upper-level resource allocation and scheduling, forming a closed-loop optimization. This allows the system to allocate resources more rationally while meeting target reliability requirements and to optimize resource allocation strategies in real time based on the runtime hardware status, significantly improving resource utilization and success rate. This invention transforms fault-tolerant quantum computing from a "fixed implementation mode" to a "dynamic configuration mode," significantly improving the flexibility, efficiency, and long-term scalability of fault-tolerant quantum computing systems. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This invention illustrates a quantum computing system architecture provided by an embodiment of the present invention; Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0038] As the scale of quantum algorithms increases, the implementation of fault-tolerant quantum computing is no longer limited to "selecting an error-correcting code and running it." It has gradually expanded into a multi-layered system problem, including: how upper-layer software describes quantum algorithms, quantum circuits, and task constraints; how logic gates are synthesized into forms suitable for fault-tolerant execution; how logical quantum resources are allocated according to task requirements and hardware conditions; how logical operations are mapped to specific physical execution forms; how measurement results are decoded and fed back to subsequent execution; and how the system adjusts at runtime when the underlying hardware state changes. Therefore, fault-tolerant quantum computing is not actually a single-module problem, but a system architecture problem that spans the software, logic, and hardware layers.

[0039] Quantum computing systems typically consist of a software algorithm layer, a compilation layer, and a hardware execution layer. The software algorithm layer is responsible for expressing the problem to be solved and the quantum algorithm; the compilation layer is responsible for gate decomposition, optimization, and mapping; and the hardware execution layer is responsible for physical quantum gates, measurement, control, and readout. In some fault-tolerant systems, error-correcting code implementation, stabilizer measurement, decoder, and logic gate scheduling modules are also added. However, in most existing implementations, these fault-tolerant modules are often not organized into an independent, unified intermediate layer, but rather embedded separately in the compiler, specific error-correcting code processes, or underlying control systems, resulting in a lack of unified abstraction in the system architecture.

[0040] One type of fault-tolerant quantum computing system in related technologies focuses on upper-level compilation and mapping, concentrating on efficiently converting upper-level quantum algorithms, quantum circuits, or logic instructions into low-level executable forms from a software and compilation perspective. This type of approach typically emphasizes gate decomposition and optimization of quantum circuits, target gate set adaptation, hardware connectivity-related mapping, instruction scheduling, and execution timing. Its typical process can be summarized as: quantum algorithm / quantum circuit → compilation / synthesis / mapping → hardware execution.

[0041] In these types of schemes, if fault tolerance is considered, it often involves embedding rules related to certain error-correcting codes, transformations related to certain logic gates, or constraints related to certain resource costs into the compilation process. In other words, in these schemes, fault tolerance is more often regarded as an additional optimization problem in the compilation chain, rather than an independent system layer.

[0042] The advantage of this type of approach is its shorter overall path, making it suitable for quickly supporting certain target platforms from a software toolchain perspective, and also suitable for experiments and verifications of current small- to medium-scale quantum systems. However, its focus remains on the direct connection between upper-level compilation and lower-level execution, lacking an independent fault-tolerant intermediate layer to uniformly manage fault-tolerant logic synthesis, fault-tolerant resource allocation, logic-to-physical mapping, measurement feedback, and runtime adjustments. In this type of approach, fault-tolerant functions are scattered and embedded throughout the entire compilation process, resulting in fragmented logic and severe coupling. Changing the fault-tolerant scheme often requires modifying the entire compilation process, making it difficult to dynamically adjust the fault-tolerant execution strategy.

[0043] Another type of fault-tolerant quantum computing system in related technologies focuses on lower-level error correction. From the perspective of lower-level fault tolerance, it focuses on how to implement a certain type or class of quantum error correction and fault tolerance mechanisms. These schemes usually revolve around fixed or pre-selected quantum error correction codes or specific platforms, and specifically construct fault-tolerant execution paths for them.

[0044] This type of solution can be an implementation with a fixed error correction code and fixed resource configuration, or a dedicated optimized implementation for a specific platform, code family, or type of logic gate. Although they differ in form, they are essentially more focused on "how to do error correction and fault tolerance well," rather than building a general fault tolerance layer that starts from software task requirements, runs through hardware execution, and has a unified interface and runtime feedback capabilities. The process can be summarized as: software layer → fixed / dedicated error correction and decoding system → underlying hardware execution. The key aspects include stable sub-measurement for specific error correction codes or platforms, decoder design, logic quantum block organization, patch layout or other code block layout, lattice operation, weaving, or specific logic gate implementation methods, distillation plant configuration and scheduling, etc.

[0045] In this type of solution, the software layer typically inputs the task into a pre-defined fault-tolerant system, and the subsequent encoding, measurement, decoding, and logical operations are mainly completed within this system. The main advantage of this system lies in its ability to perform in-depth optimization for a specific type of error correction code, a specific type of hardware platform, or a specific type of logic implementation, thus resulting in good performance and mature implementation in localized scenarios.

[0046] However, these solutions focus more on "how to perform error correction" rather than "how to establish a unified middleware layer between software requirements, fault-tolerant resources, and hardware status." Therefore, while these solutions can be effectively implemented within a certain error correction system, they are often lacking in task-driven dynamic resource configuration, cross-platform adaptation, unified logical ISA / physical ISA abstraction, and runtime closed-loop feedback.

[0047] Overall, although the two types of related technologies mentioned above—one focusing more on the software compilation chain and the other on lower-level error correction implementation—share the following common problems: Fault-tolerance-related functions are often not uniformly organized but rather scattered across the compilation process, error correction code implementation, decoder, or hardware control. This necessitates point-to-point adaptation between different software frameworks, fault-tolerance schemes, and hardware platforms, resulting in fragmented and heavily coupled fault-tolerance logic. Furthermore, these technologies lack a closed-loop connection between logical resource allocation, logic-to-physical mapping, and runtime feedback, making it difficult to continuously receive hardware drift, measurement results, and resource state changes, and dynamically update resource allocation and execution strategies accordingly. Consequently, existing systems have weak adaptability to dynamic changes in real-world hardware environments. Moreover, when hardware platforms, error correction codes, task requirements, or runtime states change, the system typically requires significant modifications, making it difficult to dynamically determine the scale of logical resources, logical organization, and execution mapping methods based on task requirements.

[0048] The aforementioned problems cannot be fundamentally solved simply by adding rules to existing compilers or parameters to the underlying hardware controllers. This is because these problems stem from a fundamental deficiency at the architectural level: existing systems lack an independent, unified, fault-tolerant intermediate layer responsible for handling software task requirements, organizing fault-tolerant resources, forming logical abstractions, mapping physical execution, and receiving runtime feedback. In other words, existing technologies are either more focused on "how to compile upper-level tasks" or "how to build the lower-level error correction system," but generally lack a true intermediate layer that lies between the two, understands both software requirements and hardware states, and can uniformly handle the logic synthesis, resource allocation, translation, decoding, and scheduling issues for fault-tolerant execution. To achieve truly dynamic optimization for fault-tolerant quantum computing, a new intermediate layer—an independent fault-tolerant layer—must be introduced between the software layer and the underlying quantum hardware layer. This fault-tolerant layer should be uniformly responsible for: fault-tolerant logic synthesis; dynamic resource allocation based on hardware and resource states; translation from logical ISA to physical ISA; decoding and feedback of measurement results; and adaptive scheduling based on hardware drift. By introducing this new intermediate layer, the previously scattered, fixed, and coupled fault tolerance functions can be unified, forming a standardized interface and closed-loop optimization mechanism from software to fault tolerance and then to hardware. This will truly solve the bottleneck problems of existing systems in terms of resource utilization, success rate, scalability, and cross-platform adaptability.

[0049] Based on the above concepts, this invention proposes a dynamic fault-tolerant layer architecture for fault-tolerant quantum computing. The core idea is to introduce an independent, unified, and dynamically adjustable fault-tolerant layer between the software layer and the underlying quantum hardware layer. This eliminates the need for implementations that directly compile the software layer to the underlying hardware or pre-fix the underlying error correction system. Instead, a fault-tolerant layer is added in the middle, capable of uniformly handling software task requirements, coordinating logical fault-tolerant resources, generating physical execution representations, and receiving hardware feedback. This invention coordinates fault-tolerant functions within the quantum computing system through the fault-tolerant layer and feeds back underlying measurement results, decoding results, and hardware state changes to upper-level resource allocation and execution decisions. This allows the system to dynamically adjust its fault-tolerant execution strategy based on actual needs and resource conditions, thereby improving resource utilization efficiency and achieving a reusable, replaceable, and scalable fault-tolerant execution chain.

[0050] Figure 1This invention illustrates a quantum computing system architecture provided by an embodiment of the present invention. The system includes a software layer, a fault-tolerant layer, and a hardware layer. The software layer generates quantum algorithms and task constraint information; the fault-tolerant layer performs fault-tolerant logic synthesis, resource allocation, logic-to-physical mapping, decoding feedback, and adaptive scheduling; the hardware layer performs operations such as physical quantum gates, physical measurements, readouts, and hardware status monitoring according to the physical instruction set architecture (physical ISA) output by the fault-tolerant layer, and feeds back the measurement results and hardware status to the fault-tolerant layer.

[0051] The structure and function of each layer are described in detail below.

[0052] The software layer is used to generate quantum algorithms and task constraint information. The quantum algorithm may include quantum circuits and logic gate sequences. Task constraint information refers to the requirements of the quantum algorithm for fault-tolerant tasks, and may include one or more of the following: accuracy requirements, success rate requirements, logic error rate constraints, latency constraints, resource budget, and task priority.

[0053] The software layer and the fault-tolerant layer are connected via a first interface, which is a standardized interface used to standardize and transmit the quantum algorithm and task constraint information generated by the software layer to the fault-tolerant layer. This first interface standardizes the task requirements generated by the software layer and transmits them to the fault-tolerant layer. Thus, the upper-layer software only needs to express "what task needs to be completed" (i.e., the quantum algorithm) and "what constraints the task is subject to" (i.e., task constraint information), without directly specifying the error correction code, logical resource scale, or physical execution form to be used at the lower level. Through the first interface, the software layer can reuse the same fault-tolerant layer, and different software frameworks and different algorithm compilers can also be integrated into the system without changing the underlying fault-tolerant implementation.

[0054] like Figure 1 As shown, the fault-tolerant layer can be further divided into five functional modules: synthesis layer, resource allocation layer, translation layer, decoding layer, and adaptive scheduling layer. These modules are used to perform five main functions: fault-tolerant logic synthesis, resource allocation, logic-to-physical mapping, decoding feedback, and adaptive scheduling.

[0055] The synthesis layer is used to perform fault-tolerant logic synthesis. Specifically, the synthesis layer performs standardized synthesis of the quantum algorithm suitable for fault-tolerant execution based on task constraint information, obtaining the logical representation of the quantum algorithm. The focus of the synthesis layer is not functional equivalence gate decomposition in the ordinary sense, but rather on performing standardized representation of the input circuit suitable for fault-tolerant execution based on the specific logical execution structure of the quantum algorithm, the target accuracy requirements in the task constraint information, and the subsequent fault-tolerant resource costs.

[0056] In some embodiments, the quantum algorithm is standardized and synthesized to be suitable for fault-tolerant execution based on task constraint information. Specifically, this includes: based on the task constraint information and considering the fault-tolerant execution path, comprehensively considering error-correcting code implementation, distillation resource pressure, logic gate organization, and scheduling complexity, converting the quantum algorithm into a standardized logical representation suitable for fault-tolerant execution. The synthesis layer does not pursue the shortest gate count or lowest circuit depth in isolation during logical synthesis; instead, it considers the subsequent code implementation, distillation resource pressure, logic gate organization, and scheduling complexity to complete the standardized synthesis, taking into account the fault-tolerant execution path.

[0057] In a more specific embodiment, the quantum algorithm is converted into a standardized logical representation suitable for fault-tolerant execution. Specifically, the synthesis layer determines how to decompose the input logic gate sequence into the form of Clifford + R_z(\theta). Here, Clifford + R_z(\theta) is a universal set of quantum gates that can be used to approximate any quantum operation.

[0058] The resource allocation layer is used to determine the error correction code type and allocate logical resources based on the logical representation output by the synthesis layer and the hardware status, and outputs the encoding information of the error correction code and the logical instruction set architecture (Logic ISA).

[0059] Hardware status refers to the availability of the underlying hardware layer, including the underlying hardware capability model, resource status, calibration status, drift information, fidelity, etc. It can be obtained directly from the hardware layer or from the feedback of adaptive scheduling by the adaptive scheduling layer.

[0060] Logical resources include code distance, logical resource size, logical layout, and logical scheduling method.

[0061] Different algorithms, different precision requirements, and different logic resources and hardware conditions may require different types of error correction codes. While allocating logic resources, the resource allocation layer also needs to determine the type of error correction code used in fault-tolerant quantum computing and send the encoding information of the error correction code to the decoding layer, enabling the decoding layer to complete the decoding based on the encoding information.

[0062] In some embodiments, determining the error correction code type specifically includes: selecting one from a variety of error correction codes as the error correction code to be used in this fault-tolerant quantum computing based on the logical representation and hardware state, and sending the encoding information of the error correction code to the decoding layer. In some more specific embodiments, the variety of error correction codes may include surface codes, color codes, Steane codes, convolutional codes, Turbo codes, and Reed-Muller codes.

[0063] An ISA (Instruction Set Architecture) is the interface between quantum algorithms (software) and quantum processor architecture (hardware), used to map the semantics of high-level quantum programming languages ​​to low-level hardware control instructions. ISAs include logical ISAs and physical ISAs. A logical ISA represents a unified organization of instructions and resources at the logical level, describing logic gates, logic blocks, logic measurements, logic resource bindings, and logic scheduling, rather than specific physical gate control timing. Conversely, a physical ISA is a set of quantum operation instructions directly targeting physical qubits (qubits), which can be directly executed by the underlying hardware.

[0064] The role of the resource allocation layer is to convert the upper-layer task requirements into a unified logical execution representation logicalISA, so that the subsequent translation layer can perform platform-related physical mapping on this basis.

[0065] In some embodiments, the resource allocation layer further includes an optimizer for optimizing the selection of error correction codes and resource allocation strategies. Specifically, the optimizer can select the optimal strategy from a variety of resource allocation strategies provided by the resource allocation layer.

[0066] The translation layer is used to convert the logical ISA output by the resource allocation layer into a physical ISA that can be directly executed by the underlying hardware layer. The main responsibility of this layer is to map the logical layer abstraction into a physical execution form specific to the hardware platform. The translation layer establishes a standardized conversion relationship between the logical ISA and the physical ISA, enabling the system to adapt to different hardware platforms while preserving the fault-tolerant abstraction of the upper-layer logic.

[0067] The decoding layer receives measurement results and hardware status from the hardware layer, as well as encoding information from the resource allocation layer. It then decodes the measurement results based on the encoding information and feeds back the decoding results and hardware status to the adaptive scheduling layer.

[0068] After selecting an error correction code, the resource allocation layer synchronizes the code's encoding information to the decoding layer. Upon receiving the encoding information and the hardware layer's measurement results, the decoding layer decodes the measurement results based on the encoding information to obtain the decoding result. The decoding result includes the error type and location in the quantum hardware layer's measurement results.

[0069] In one embodiment, the error correction code selected by the resource allocation layer is a surface code. After receiving the encoded information and the underlying measurement results, the decoding layer performs decoding using the minimum weight perfect matching method to obtain the most likely type of error that occurred in the quantum hardware layer measurement, and on which physical bits(s) the error occurred.

[0070] In this system, the decoding layer not only serves the local error correction decoding stage but also acts as a crucial bridge connecting the underlying measurement behavior with the upper-level fault-tolerant decision-making. The decoding layer not only undertakes the underlying decoding function but also feeds back the underlying hardware status to the higher-level resource allocation and scheduling logic. Specifically, the decoding layer continuously receives measurement results and hardware status information returned by the hardware layer. After completing the decoding based on the measurement results, it feeds back the decoding results and hardware status information together to the adaptive scheduling layer. Hardware status refers to the available state of the underlying hardware layer, including the underlying hardware capability model, resource status, calibration status, drift information, fidelity, etc.

[0071] The adaptive scheduling layer is used to send error correction instructions to the hardware layer based on the decoding results, evaluate the current resource allocation strategy based on the hardware status, and request the resource allocation layer to reallocate resources and / or request the translation layer to regenerate the physical ISA based on the evaluation results.

[0072] The adaptive scheduling layer is responsible for sending error correction instructions to the hardware layer based on the decoding results, correcting errors, and completing the calibration.

[0073] Furthermore, the adaptive scheduling layer is also responsible for dynamically adjusting the upper-layer resource allocation and execution strategies based on the real-time state changes of the underlying hardware. Specifically, the adaptive scheduling layer can evaluate the currently enabled logical resource allocation strategy based on the hardware state feedback from the decoding layer, and based on the evaluation results, request the resource allocation layer to reallocate logical resources and / or request the translation layer to regenerate the physical ISA.

[0074] In some embodiments, the hardware state includes the fidelity of each physical qubit; the current resource allocation strategy is evaluated based on the hardware state, and the resource allocation layer is required to reallocate resources and / or the translation layer is required to regenerate the physical ISA based on the evaluation results. Specifically, this includes: if the fidelity of a certain qubit is lower than 95%, the qubit is marked as unavailable; the unavailability information is synchronized to the resource allocation layer, requiring the resource allocation layer to reallocate resources, and unavailable qubits are avoided when reallocating resources.

[0075] This layer is a key module for achieving runtime adaptability in this system. It enables the system to continuously adjust resource allocation strategies based on the actual hardware state during operation, rather than relying solely on a static configuration determined once before execution. Through this adaptive scheduling feedback, the system can adjust code distance, logical resource size, mapping location, or execution strategy according to the real-time hardware state, enhancing system robustness and execution success rate.

[0076] The hardware layer, also known as the underlying quantum hardware layer, is the foundational execution layer in this system. It operates on physical quantum gates based on the physical ISA output by the fault-tolerant layer and feeds back the measurement results and hardware status to the fault-tolerant layer. These operations can include physical quantum gates, physical measurements, readouts, and hardware status monitoring. After execution, the hardware layer feeds back the physical measurements, readout results, and monitored hardware status to the fault-tolerant layer, enabling the fault-tolerant layer to perform error correction based on the measurement results and adjust resource allocation strategies according to the hardware status.

[0077] The hardware layer and the fault-tolerant layer are connected via a second standardized interface. This interface sends the physical ISA and related control configurations to the underlying quantum hardware layer in a standardized manner, and feeds back the underlying hardware state and measurement results to the fault-tolerant layer. Different types of underlying quantum hardware platforms only need to implement execution and feedback mechanisms compatible with this unified interface to access the system, without requiring upper-layer logic to directly depend on platform details. This achieves decoupling between fault-tolerant abstraction and the underlying hardware platform.

[0078] In some embodiments, the hardware layer can correspond to different types of quantum platforms, such as superconducting quantum platforms, ion trap quantum platforms, neutral atom platforms, and optical quantum platforms. Different types of quantum platforms can all access the system through a unified interface between the fault-tolerant layer and the hardware layer under the same architecture.

[0079] The overall architecture and functions of each layer of the quantum computing system provided by this invention have been described above. Based on the above architecture, the overall workflow of the quantum computing system includes:

[0080] First, the software layer submits the quantum algorithm and corresponding task constraint information to the fault-tolerant layer through a unified interface. Then, the synthesis layer performs fault-tolerant synthesis on the quantum algorithm, representing it in a standardized form suitable for subsequent fault-tolerant execution, such as Clifford + R_z(\theta). Next, the resource allocation layer, based on the logical representation output by the synthesis layer and combined with hardware state information, determines the error correction code type, code distance, logical resource size, logical layout, and logical scheduling method, and generates a logicalISA. Then, the translation layer converts the logicalISA into a physical ISA executable by the underlying hardware layer and distributes it to the hardware layer for execution through a unified interface. During task execution, the hardware layer continuously returns measurement results and hardware state information. The decoding layer decodes the measurement results and feeds back the decoding results and hardware state to the adaptive scheduling layer. The adaptive scheduling layer corrects errors based on the decoding results and evaluates the current resource allocation and execution status based on the hardware state, requiring the resource allocation layer to reallocate resources and / or the translation layer to regenerate the physical ISA when necessary.

[0081] The quantum computing system provided by this invention not only includes a forward execution link from software to hardware, but also a reverse feedback link from hardware back to the fault-tolerant layer, and further feedback to the resource allocation and scheduling module. Thus, the entire system forms a closed-loop execution mechanism from software task input to hardware execution, and then hardware feedback drives resource reconfiguration. Through the above system architecture and workflow, the quantum computing system provided by this invention can determine the fault-tolerant implementation method based on algorithm requirements and hardware conditions before task execution, and continuously adjust resource allocation and execution strategies based on measurement results and hardware status during task execution, thereby forming a complete closed-loop control mechanism.

[0082] As can be seen from the above, the quantum computing system provided by this invention has the following advantages compared with the prior art:

[0083] 1. An independent fault tolerance layer is set up between the software layer and the underlying hardware layer to take over the task requirements of the upper layer and generate a fault tolerance implementation scheme suitable for the execution of the lower layer. This makes the fault tolerance function no longer scattered in the compiler or the underlying control, the system module boundary is clearer, and the system's scalability and cross-platform adaptability are enhanced.

[0084] 2. The resource allocation layer can dynamically determine the error correction code type, code distance, number of logic blocks, patch configuration, distillation resources, and logic mapping method based on task requirements and hardware status, and output a logical ISA. This achieves dynamic fault-tolerant configuration of logical resources, enabling the system to dynamically adjust the fault-tolerant implementation method according to algorithm requirements and hardware status, rather than using a fixed single configuration. In this way, the system can allocate resources more rationally while meeting the target reliability requirements, reducing over-configuration or under-configuration issues, and improving resource utilization and success rate.

[0085] 3. Through the layered design of logical ISA and physical ISA, the separation of logical layer abstraction and physical layer abstraction is achieved, which is more conducive to the decoupling of logical resource decision-making and underlying platform adaptation.

[0086] 4. By receiving measurement results, decoding results, and hardware status through the decoding layer and adaptive scheduling layer and feeding them back to the upper layer, the resource allocation layer and translation layer can update resource allocation and execution strategies in real time according to the hardware status. This enables the system to have runtime feedback capabilities, allowing the underlying measurement results and hardware status to be fed back to the upper layer resource allocation and scheduling, forming a closed-loop optimization, which greatly increases the reliability and flexibility of fault-tolerant quantum computing.

[0087] 5. By establishing a unified interface between the software layer and the fault-tolerant layer, and between the fault-tolerant layer and the hardware layer, the system can more easily support different software frameworks, different error correction codes, and different hardware platforms, thereby enhancing the system's scalability and cross-platform adaptability.

[0088] In the description of the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0089] In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0091] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A quantum computing system, characterized in that, include: The software layer is used to generate quantum algorithms and task constraint information; Fault-tolerant layer; The hardware layer is used to operate physical quantum according to the physical instruction set architecture (physical ISA) output by the fault tolerance layer, and to feed back the measurement results and hardware status to the fault tolerance layer. The fault-tolerant layer specifically includes: The synthesis layer is used to perform standardized synthesis of the quantum algorithm based on task constraint information to obtain the logical representation of the quantum algorithm. The resource allocation layer is used to determine the error correction code type and allocate logical resources based on the logical representation and hardware status, and output the encoding information of the error correction code and the logical instruction set architecture (Logic ISA). Translation layer, used to convert logical ISAs into hardware-executable physical ISAs; The decoding layer receives measurement results and hardware status from the hardware layer, as well as encoding information from the resource allocation layer. It then decodes the measurement results based on the encoding information and feeds back the decoding results and hardware status to the adaptive scheduling layer. The adaptive scheduling layer is used to send error correction instructions to the hardware layer based on the decoding results, evaluate the current resource allocation strategy based on the hardware status, and request the resource allocation layer to reallocate resources and / or request the translation layer to regenerate the physical ISA based on the evaluation results.

2. The system according to claim 1, characterized in that, The quantum algorithm includes quantum circuits and logic gate sequences; the task constraint information includes one or more of the following: accuracy requirements, success rate requirements, logic error rate constraints, latency constraints, resource budget, and task priority.

3. The system according to claim 1, characterized in that, Based on task constraint information, the quantum algorithm is standardized and synthesized to be suitable for fault-tolerant execution. Specifically, based on task constraint information and oriented towards fault-tolerant execution paths, the quantum algorithm is converted into a standardized logical representation suitable for fault-tolerant execution by comprehensively considering error correction code implementation, distillation resource pressure, logic gate organization, and scheduling complexity.

4. The system according to claim 3, characterized in that, Converting quantum algorithms into standardized logical representations suitable for fault-tolerant execution specifically includes decomposing the logic gate sequence into the form of Clifford + R_z(\theta).

5. The system according to any one of claims 1-4, characterized in that, The resource allocation layer includes an optimizer for optimizing error correction code selection and resource allocation strategies.

6. The system according to any one of claims 1-4, characterized in that, Determining the error correction code type specifically includes: selecting one from multiple error correction codes based on the logical representation and hardware state as the error correction code to be used in this fault-tolerant quantum computing, and sending the encoding information of the error correction code to the decoding layer.

7. The system according to claim 6, characterized in that, The various error correction codes include surface codes, color codes, Steane codes, convolutional codes, Turbo codes, and Reid-Muller codes.

8. The system according to any one of claims 1-4, characterized in that, The software layer and the fault-tolerant layer are connected through a first interface, which is used to standardize and transmit the quantum algorithm and task constraint information generated by the software layer to the fault-tolerant layer. The fault-tolerant layer is connected to the hardware layer through a second interface, which is used to send the physical ISA to the hardware layer in a standardized manner and to feed back the hardware status and measurement results to the fault-tolerant layer.

9. The system according to any one of claims 1-4, characterized in that, The hardware layer can be any one of a superconducting quantum platform, an ion trap quantum platform, a neutral atom platform, or a photonic quantum platform.

10. The system according to any one of claims 1-4, characterized in that, The hardware state includes the fidelity of each physical qubit; the current resource allocation strategy is evaluated based on the hardware state, and the resource allocation layer is required to reallocate resources and / or the translation layer is required to regenerate the physical ISA based on the evaluation results. Specifically, if the fidelity of a certain qubit is lower than 95%, the qubit is marked as unavailable; the unavailability information is synchronized to the resource allocation layer, which is required to reallocate resources, and unavailable qubits are avoided when reallocating resources.

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