A quantum circuit optimization method, device, equipment and medium

Abstract

The application discloses a quantum circuit optimization method, device, equipment and medium, and belongs to the technical field of quantum computing. The method comprises the following steps: obtaining a variational quantum circuit, wherein the variational quantum circuit comprises a plurality of target quantum logic gates, and the target quantum logic gate is a quantum rotation gate containing a variable parameter; when a target expected value is obtained by running a current variational quantum circuit, the contribution of the variable parameter of each target quantum logic gate to the target expected value is calculated under a target parameter value, wherein the target expected value is an expected value when the variational quantum circuit converges with the change of the parameter value of the variable parameter; the target quantum logic gate to be deleted is determined by using the calculated contribution; and an optimized variational quantum circuit is obtained by deleting the target quantum logic gate to be deleted from the variational quantum circuit. According to the embodiment of the application, the occupation of quantum hardware resources can be reduced.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, and in particular to a quantum circuit optimization method, device, equipment and medium. Background Technology

[0002] Variational quantum algorithms (VQA) are a class of quantum algorithms based on the variational principle. They approximate solutions to target problems by adjusting parameterized quantum states and hold an important position in the field of quantum computing. The variational principle is the core of VQA. For a quantum system, its true ground state energy is the smallest eigenvalue of the Hamiltonian. VQA constructs a trial quantum state with adjustable parameters (usually represented by a parameterized quantum circuit, which can also be called a variational quantum circuit) and calculates the expectation value of the Hamiltonian in this quantum state. This expectation value will be greater than or equal to the true ground state energy. By continuously adjusting the parameters to minimize the expectation value, an approximate solution close to the true ground state energy and the ground state quantum state can be obtained.

[0003] Variable quantum circuits require the fabrication of complex quantum states to approximate the ground state or other specific states of the target system. To express these complex quantum states, a large number of quantum logic gates are typically needed to construct sufficiently flexible and powerful circuits capable of covering a wide quantum state space. Furthermore, deeper circuits and a greater number of gates provide stronger expressive and optimization capabilities, thereby improving algorithm performance. The number of gates is directly proportional to the complexity of the quantum circuit; complex quantum circuits require significant quantum hardware resources to complete the corresponding tasks. Summary of the Invention

[0004] The purpose of this application is to provide a quantum circuit optimization method, apparatus, device, and medium, which aims to reduce the consumption of quantum hardware resources.

[0005] One embodiment of this application provides a quantum circuit optimization method, the method comprising:

[0006] A variable quantum circuit is obtained, wherein the variable quantum circuit contains multiple target quantum logic gates, and the target quantum logic gates are quantum rotation gates with variable parameters;

[0007] When running the current variable quantum circuit to obtain the target expected value, calculate the contribution of the variable parameter of each target quantum logic gate to the target expected value under the target parameter value, wherein the target expected value is the expected value of the variable quantum circuit when the parameter value of the variable parameter changes to convergence.

[0008] Using the calculated contributions, the target quantum logic gate to be deleted is determined;

[0009] The optimized variable quantum circuit is obtained by deleting the target quantum logic gate to be deleted from the variable quantum circuit.

[0010] Optionally, the method further includes:

[0011] Calculate the entanglement degree of qubit pairs in the optimized variable quantum circuit;

[0012] Using the calculated entanglement degree, a target bit pair is determined from all qubit pairs, wherein the target pair is specifically the qubit pair whose entanglement degree is to be increased;

[0013] The variable quantum circuit is updated by applying a quantum entanglement gate to the target bit pair.

[0014] Optionally, after updating the variable component quantum circuit, the method further includes:

[0015] Return to the step of calculating the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value when running the current variable quantum circuit to obtain the target expected value, until there are no target quantum logic gates and target bit pairs to be deleted.

[0016] Optionally, the degree of entanglement is the von Neumann entropy of the reduced density matrix of the qubit pair.

[0017] Optionally, after obtaining the optimized variable quantum circuit, the method further includes:

[0018] Return to the step of calculating the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value while running the current variable quantum circuit to obtain the target expected value, until there are no more target quantum logic gates to be deleted.

[0019] Optionally, the target expected value is obtained by optimizing the variable parameters using the SLSQP optimization algorithm.

[0020] Optionally, determining the target quantum logic gate to be deleted using the calculated contribution includes:

[0021] The target quantum logic gate whose calculated contribution is less than a preset threshold is selected as the target quantum logic gate to be deleted.

[0022] Another embodiment of this application provides a quantum circuit optimization device, the device comprising:

[0023] A module for obtaining a variable quantum circuit, wherein the variable quantum circuit contains multiple target quantum logic gates, and the target quantum logic gates are quantum rotation gates with variable parameters;

[0024] The calculation module is used to calculate the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value when the target expected value is obtained by running the current variable quantum circuit. The target expected value is the expected value of the variable quantum circuit when the parameter value of the variable parameters changes to convergence.

[0025] The determination module is used to determine the target quantum logic gate to be deleted using the calculated contribution;

[0026] The optimization module is used to obtain an optimized variable quantum circuit by deleting the target quantum logic gate to be deleted from the variable quantum circuit.

[0027] Another embodiment of this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the quantum circuit optimization method in any of the above embodiments.

[0028] Another embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit optimization method in any of the above embodiments.

[0029] Compared with existing technologies, this application calculates the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter values ​​when running the current variable quantum circuit to obtain the target expected value; then, using the calculated contributions, it determines the target quantum logic gates to be deleted; and finally, by deleting the target quantum logic gates to be deleted from the variable quantum circuit, it obtains the optimized variable quantum circuit. By calculating the contribution of each target quantum logic gate and using the contributions to delete some quantum logic gates, the quantum circuit can be effectively simplified, thereby reducing the occupation of quantum hardware resources. Attached Figure Description

[0030] Figure 1 Example system block diagram for a quantum circuit optimization method provided in this application embodiment;

[0031] Figure 2 A flowchart of a quantum circuit optimization method provided in this application embodiment;

[0032] Figure 3 A structural diagram of a quantum circuit optimization device provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0034] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0036] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0037] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, n quantum states can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement. The state of one qubit (whether it's 1, 0, or both) can depend on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0038] Please refer to Figure 1 This illustrates an example system block diagram for a quantum circuit optimization method according to an embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0039] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum logic gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum logic gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0040] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals instructing which quantum logic gates need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum logic gates to the qubits to manipulate the interactions between them.

[0041] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum logic gates to the qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum logic gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0042] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum logic gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum logic gates to be performed on quantum chip 113.

[0043] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0044] See Figure 2 , Figure 2 The quantum circuit optimization method provided in this application includes the following steps:

[0045] S201: Obtain a variable quantum circuit, wherein the variable quantum circuit contains multiple target quantum logic gates, and the target quantum logic gates are quantum rotating gates with variable parameters.

[0046] Variable quantum circuits are quantum computing models based on the variational principle. They represent the preparation and measurement of quantum states as a parameterized quantum circuit. By adjusting the parameters in the circuit, the objective function (such as energy and probability) is optimized. The core idea is to represent the evolution of a quantum system as a combination of quantum logic gates. The parameters of these gates can be adjusted using classical optimization algorithms to achieve specific quantum computing tasks. Variable quantum circuits offer strong flexibility and scalability, allowing for the design of different circuit structures to meet various problem requirements. Furthermore, they can utilize classical computer optimization algorithms to adjust the parameters of the quantum circuit, avoiding the need for complex analytical solutions directly to the quantum system.

[0047] Variable quantum circuits can be used to calculate the energy, structure, and chemical reactions of molecules. Specifically, by mapping the Hamiltonian of a molecule to qubits, variable quantum circuits can be used to find the ground state energy and wave function of the molecule. Variable quantum circuits can also be applied to quantum machine learning. As a form of quantum neural network, they learn the characteristics of data and map them to the quantum state space, thereby implementing quantum machine learning algorithms to perform tasks such as data classification, clustering, and feature extraction. Variable quantum circuits can also be used to solve combinatorial optimization problems. Specifically, by mapping the objective function of the combinatorial optimization problem to the energy function of the qubits, variable quantum circuits can be used to find the optimal solution.

[0048] To construct variable quantum circuits, the purpose of the construction must first be clearly defined, such as solving quantum chemistry problems or performing quantum machine learning classification. Different problems correspond to different objective functions. For example, in quantum chemistry, the objective might be to minimize the energy of molecules; in quantum machine learning, the objective might be to maximize classification accuracy. The required number of qubits is determined based on the complexity of the problem. The variable quantum circuit is then constructed based on the Hamiltonian of the problem to be solved.

[0049] In some embodiments of this application, the variable quantum circuit can be a pairwise circuit based on quantum hardware, which depends on the actual physical structure of the quantum chip. In other words, it is a quantum circuit designed with a physical connection method closely integrated with the hardware.

[0050] In quantum computing, the way qubits are connected is constrained by the physical layout of the hardware. Hardware-based pairwise circuits are a strategy proposed to adapt to this constraint. By following the actual connection topology of the chip, hardware resources can be used more efficiently, unnecessary long-distance communication between qubits can be reduced, thereby reducing the complexity and error rate of quantum circuits.

[0051] In quantum computing, entanglement is a core resource, a special correlation state between qubits. By pairwise entanglement, larger entangled structures can be gradually built, providing the foundation for the implementation of quantum algorithms. Pairwise circuits form entangled pairs by pairing qubits together. For example, in a single-layer circuit, qubit 1 and qubit 2 form an entangled pair, qubit 3 and qubit 4 form an entangled pair, and so on.

[0052] In pairwise circuits, the pairing method alternates between layers. By alternating pairings layer by layer, the entanglement range can be gradually expanded while avoiding repeated entanglement of the same qubit pairs, thus improving the efficiency and scalability of the quantum circuit. For example, in the first layer, qubits are paired according to odd and even positions (1-2, 3-4, 5-6, etc.); in the second layer, qubits may be paired in a different way (e.g., 2-3, 4-5, 6-7, etc.). Through the pairwise circuit construction strategy, an entangled structure covering the entire quantum chip can be gradually formed. This structure is both efficient (because it follows the hardware topology, reducing unnecessary operations) and scalable (it can adapt to quantum chips of different sizes).

[0053] Hardware Efficient Design (HEA) is a design framework for quantum circuits that aims to fully utilize the physical characteristics of hardware to improve the efficiency of quantum algorithms. Pairwise circuits are a fundamental building block in HEA. By combining pairwise circuits with other optimization strategies (such as parameterized quantum logic gates, adaptive tuning, etc.), HEA can design quantum circuits that are both efficient and adaptable to the hardware.

[0054] Hardware-based pairwise circuitry is a quantum circuit design method that incorporates the physical structure of quantum chips. It constructs efficient and scalable quantum entangled structures by entangled pairs of qubits and alternating pairings layer by layer, providing fundamental support for HEA (Heated Assortment).

[0055] S202: When running the current variable quantum circuit to obtain the target expected value, calculate the contribution of the variable parameter of each target quantum logic gate to the target expected value under the target parameter value, wherein the target expected value is the expected value of the variable quantum circuit when the parameter value of the variable parameter changes to convergence.

[0056] Variable quantum circuits operate iteratively. During operation, the expected value changes with the values ​​of the variable parameters. When the circuit converges, the obtained expected value is the target expected value, and the parameter values ​​of the variable parameters included in the variable quantum circuit at the time of convergence are the target parameter values. The convergence condition for variable quantum circuit operation can be set according to the actual situation. It can be set to the difference between two consecutive expected values ​​being within a preset precision range, or the number of iterations reaching a preset number.

[0057] The target expectation value is the ultimate goal of variational quantum circuit optimization. Only when the circuit converges to the target expectation value can the contribution of each quantum logic gate to the final result be accurately evaluated. Before that, the circuit parameters are constantly being adjusted, and the contribution values ​​will change accordingly, failing to accurately reflect their actual impact on the final result.

[0058] Here, "contribution" can be understood as the degree of influence of each target quantum logic gate on the expected value. For example, the contribution of each target quantum logic gate to the expected value can be determined by calculating gradients or performing sensitivity analysis. In this application, the contribution of a target quantum logic gate can be calculated by calculating the partial derivative of the target expected value with respect to the target parameter value corresponding to that target quantum logic gate. Specifically, it can be determined using the following formula:

[0059]

[0060] Where E is the target expected value, θ i Let H be the target parameter value of the target quantum logic gate, and H be the Hamiltonian.

[0061] During optimization, the parameters of the target quantum logic gates are continuously adjusted, and their contributions to the expected value also change. Only when the operation converges and the expected value stabilizes can the contribution of each target quantum logic gate be accurately evaluated. This helps determine which quantum logic gates have a greater impact on the result and which have a smaller impact. Furthermore, prematurely calculating contributions and removing quantum logic gates during optimization may lead to a decrease in circuit performance and even affect the convergence of the optimization. Waiting for convergence before calculating contributions ensures the stability and effectiveness of the optimization strategy. Computational resources are limited during optimization. Calculating contributions in every iteration increases the computational burden and reduces optimization efficiency. Calculating contributions after parameter convergence reduces unnecessary computation and improves resource utilization efficiency.

[0062] S203: Using the calculated contribution, determine the target quantum logic gate to be deleted.

[0063] When running a variable quantum circuit, the contribution of the variable parameters of each target quantum logic gate to the target expected value is calculated. This contribution can be understood as the degree of influence of the quantum logic gate on the final result (e.g., the expected value), thereby determining which target quantum logic gates can be deleted. In some implementations, if the contribution of a certain target quantum logic gate is very small (e.g., its influence on the expected value is negligible), then this logic gate may not help the optimization result and may even increase the computational complexity. By analyzing the contribution, it is possible to determine which gates are "redundant," i.e., gates that can be deleted. Specifically, target quantum logic gates whose calculated contributions are less than a first preset threshold can be selected as target quantum logic gates to be deleted.

[0064] The preset threshold is a standard used to determine whether the contribution is large enough, distinguishing which target quantum logic gates contribute significantly and which do not. If the contribution value of a target quantum logic gate is less than this preset threshold, it is considered that the quantum logic gate has a small impact on the result and can be deleted. Deleting it will not significantly affect the performance of the circuit; on the contrary, it can simplify the circuit and improve computational efficiency.

[0065] S204: By deleting the target quantum logic gate to be deleted from the variable quantum circuit, the optimized variable quantum circuit is obtained.

[0066] After removing redundant target quantum logic gates, the resulting circuit will be simpler and more efficient, while still achieving the optimization goal.

[0067] It should be noted that the process of obtaining the target expected value by running the current variable quantum circuit described above was implemented using quantum simulation and was not actually run on quantum hardware.

[0068] In quantum computing, qubits are an extremely scarce resource. Each quantum logic gate in a variable quantum circuit operates on qubits, and the more quantum logic gates used, the more qubit resources are required. By calculating the contribution of each target quantum logic gate to the target expected value, gates with smaller contributions are identified as those to be deleted and removed, significantly reducing the qubit resources required for the quantum circuit to run on quantum hardware. Each quantum logic gate operation requires corresponding physical resources and time to complete. Reducing the number of target quantum logic gates means reducing the number of quantum logic gate operations, thereby reducing the demand for quantum logic gate operation resources, such as the generation and application of control pulses and qubit coupling. The running time of a variable quantum circuit is closely related to the number of quantum logic gates it contains. The more gates there are, the greater the circuit depth, the more complex the quantum state evolution process, and the longer the computation time. By deleting the target quantum logic gates to be deleted, the depth of the quantum circuit can be effectively shortened, thereby reducing the steps of quantum state evolution, thus shortening the computation time and improving computational efficiency. Since the target quantum logic gates are quantum rotation gates with variable parameters, each gate corresponds to one or more variable parameters. Removing some gates reduces the number of variable parameters. In the variable quantum algorithm, these variable parameters need to be optimized to bring the target expected value to converge. Reducing the number of parameters means shrinking the optimization space, which reduces the complexity of the optimization algorithm and accelerates the convergence speed of the optimization process.

[0069] Quantum systems are highly susceptible to external noise, and noise is also introduced during the operation of quantum logic gates, leading to increased errors in quantum computing results. The more logic gates in a quantum circuit, the greater the likelihood of noise accumulation. By removing some target quantum logic gates, the chances of noise interference during the evolution of quantum states can be reduced, thereby mitigating the impact of noise on computational results and improving the accuracy and reliability of quantum computing.

[0070] Reducing the number of quantum logic gates also simplifies and directs the evolution of quantum states, decreasing the risk of decoherence during complex operations. Decoherence is a significant problem in quantum computing, causing quantum states to lose their quantum properties and invalidating computational results. Therefore, this optimization method helps enhance the stability of quantum states and improve the success rate of quantum computing.

[0071] When constructing large-scale quantum circuits, the complexity of the circuit increases rapidly with the number of qubits and logic gates. This optimization method can effectively reduce the complexity of quantum circuits without sacrificing too much computational accuracy, making the construction and operation of large-scale quantum circuits more feasible. This is of great significance for solving complex scientific problems and large-scale computing tasks in practical applications. This method can also be combined with other quantum circuit optimization methods to further improve the performance of quantum circuits. For example, this method can be used first for preliminary logic gate deletion optimization, and then other methods can be used for operations such as merging and rearranging quantum logic gates to achieve better optimization results.

[0072] In some possible implementations of this application, the target expected value is obtained by optimizing the variable parameters using the SLSQP optimization algorithm.

[0073] SLSQP (Sequential Least Squares Programming) is an algorithm for solving nonlinear constrained optimization problems. It combines the ideas of Sequential Quadratic Programming (SQP) with practical numerical methods, gradually determining the optimal solution by decomposing the original nonlinear optimization problem into a series of quadratic programming (QP) subproblems. In each iteration, the SLSQP optimization algorithm determines the search direction by solving a quadratic programming subproblem and uses the BFGS (quasi-Newton) method to update the approximate value of the Hessian matrix. SLSQP can directly handle complex nonlinear constraints without introducing penalty terms, reducing the complexity and uncertainty of preprocessing. Furthermore, by solving the quadratic programming subproblem in each iteration to ensure that the constraints are satisfied, it can quickly converge to the optimal solution, and its iterative process is relatively stable, ensuring high-precision optimization results within a finite time.

[0074] In some embodiments of this application, the method may further include:

[0075] Calculate the entanglement degree of qubit pairs in the optimized variable quantum circuit;

[0076] Using the calculated entanglement degree, a target bit pair is determined from all qubit pairs, wherein the target pair is specifically the qubit pair whose entanglement degree is to be increased;

[0077] An updated variable quantum circuit is obtained by applying a quantum entanglement gate to the target bit pair.

[0078] Entanglement is a measure of the degree of entanglement between pairs of qubits in a quantum system. Higher entanglement indicates stronger correlation between qubits. The entanglement degree of each pair of qubits can be calculated by analyzing the distribution of quantum states (e.g., using the density matrix and entropy of the quantum states). From all qubit pairs, those with lower entanglement degrees are selected as target pairs; specifically, qubit pairs with entanglement degrees below a threshold set for entanglement are chosen as target pairs. Increasing the entanglement degree of these qubit pairs enhances their correlation, thereby improving the overall performance of variable quantum circuits. Quantum entanglement gates (e.g., CNOT gates or SWAP gates) can be used to enhance the entanglement between these qubits. Increasing the entanglement degree of qubit pairs enhances the expressive power and optimization capabilities of quantum circuits, helping to further improve their performance while maintaining circuit simplicity.

[0079] Quantum entanglement is one of the fundamental sources of acceleration in quantum computing. Increasing entanglement enhances the correlation between qubits, thereby improving the computational power and efficiency of quantum circuits. Highly entangled quantum states typically exhibit better robustness, resisting the destructive effects of environmental noise. Increasing entanglement improves the stability and anti-interference capabilities of quantum circuits. Furthermore, increasing entanglement helps quantum circuits better adapt to different hardware architectures and quantum computing tasks. For example, by flexibly adjusting the position and type of entanglement gates, the layout and performance of the circuit can be optimized. In addition, the preparation of large-scale entangled quantum states is a crucial characterization method for the scalability of quantum computing. Increasing entanglement facilitates the realization of larger-scale qubit entanglement, thus supporting more complex quantum computing tasks.

[0080] It should be noted that, overall, the number of added quantum entanglement gates is less than the number of target quantum logic gates deleted. The placement of the quantum entanglement gates can be determined according to predetermined rules, either by placing them at the last time step of the target bit pair or by determining the position of the deleted target quantum logic gates.

[0081] In the field of quantum chemistry, variable quantum circuits can be efficiently constructed using hardware, and then the circuits can be optimized using the methods provided in the embodiments of this application. This reduces the depth of quantum logic gates while maintaining high-precision energy calculations, enabling efficient simulation of chemical molecules in hardware and promoting the development of related fields.

[0082] In some embodiments of this application, after updating the variable quantum circuit, the method may further include:

[0083] Return to the step of calculating the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value when running the current variable quantum circuit to obtain the target expected value, until there are no target quantum logic gates and target bit pairs to be deleted.

[0084] Each time redundant quantum logic gates are removed and / or entanglement is increased, the circuit structure changes, which may affect the contribution of the remaining target quantum logic gates. Recalculating the contributions ensures that the contribution of each target quantum logic gate in the new circuit structure remains significant, thus maintaining the circuit's optimality. Furthermore, quantum circuit optimization is a dynamic process; removing certain target quantum logic gates and / or increasing entanglement may change the contributions of other target quantum logic gates. By recalculating the contributions, the optimization strategy can be dynamically adjusted to ensure that each optimization improves circuit performance.

[0085] Stopping after the first optimization might miss opportunities to further improve circuit performance. By iteratively executing the optimization steps, the circuit is ensured to move towards the optimal direction in each iteration until no further optimization is possible. Recalculating the contribution after each optimization allows for a comprehensive evaluation of the new circuit structure, ensuring no areas for optimization are overlooked. This helps identify new redundant gates or bit pairs requiring increased entanglement, further simplifying and improving circuit performance. Furthermore, this iterative optimization strategy is similar to iterative training in machine learning. Through continuous evaluation and adjustment, the optimal solution is gradually approximated, ensuring the final quantum circuit is both concise and efficient. This iterative optimization strategy ensures that the variable quantum circuit maintains optimal performance after each modification until no further optimization is possible.

[0086] In some embodiments of this application, the degree of entanglement is the von Neumann entropy of the reduced density matrix of the qubit pair.

[0087] Von Neumann entropy is an important concept in quantum information theory used to quantize the uncertainty or mixing degree of quantum states. When used to calculate the degree of entanglement between qubits, it describes the degree of entanglement between qubits based on the reduced density matrix.

[0088] For a system composed of multiple qubits, the overall quantum state needs to be determined first, and represented by the density matrix ρ. If the system is in a pure state |ψ>, then the density matrix is ​​ρ=|ψ><ψ|; if the system is in a mixed state, then it is a mixture of multiple pure states with a certain probability, i.e., ρ=∑ i ρ i |ψ i ><ψ i |, where ρ i It is in pure state |ψ i The probability of >.

[0089] For a two-qubit system AB, to calculate the entanglement degree between qubits A and B, we first need to obtain the reduced density matrix ρ of the other subsystem (A) by taking the partial trace of one of the subsystems (e.g., B). A =Tr b (ρ). The partial locus operation sums all the degrees of freedom of subsystem B, retaining only the information of subsystem A. This yields the reduced density matrix ρ. A Then, through S(ρ) A )=-Tr(ρ A log2ρ A Calculate the von Neumann entropy. Here, Tr represents the trace of the matrix, i.e., the sum of the diagonal elements of the matrix. The value of the von Neumann entropy is the degree of entanglement between two qubits.

[0090] In some possible embodiments of this application, an optimized variable quantum circuit is obtained, and the method may further include:

[0091] Return to the step of calculating the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value while running the current variable quantum circuit to obtain the target expected value, until there are no more target quantum logic gates to be deleted.

[0092] Each time redundant target quantum logic gates are removed, the circuit structure changes, which may affect the contribution of the remaining quantum logic gates. Recalculating the contributions ensures that the contribution of each target quantum logic gate in the new circuit structure remains significant, thus maintaining the optimality of the circuit. Furthermore, quantum circuit optimization is a dynamic process. Removing some target quantum logic gates may change the contributions of others. By recalculating the contributions, the optimization strategy can be dynamically adjusted to ensure that no area for optimization is overlooked. This helps to discover new redundant gates, further simplifying and improving circuit performance. This iterative optimization strategy is similar to the iterative training process in machine learning. Through continuous evaluation and adjustment, the optimal solution can be gradually approximated, ensuring that the final quantum circuit is both concise and efficient. This iterative optimization strategy ensures that the variable quantum circuit maintains optimal performance after each modification until no further optimization is possible. Quantum circuit optimization requires a clear stopping condition. The algorithm stops when no more target quantum logic gates can be removed. This ensures the convergence of the optimization and avoids premature stopping.

[0093] See Figure 3 , Figure 3 A quantum circuit optimization device provided in this application embodiment may include:

[0094] The module 301 is used to obtain a variable quantum circuit, wherein the variable quantum circuit includes multiple target quantum logic gates, and the target quantum logic gates are quantum rotation gates with variable parameters;

[0095] The calculation module 302 is used to calculate the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value when the target expected value is obtained by running the current variable quantum circuit. The target expected value is the expected value of the variable quantum circuit when the parameter value of the variable parameters changes to convergence.

[0096] The determination module 303 is used to determine the target quantum logic gate to be deleted using the calculated contribution;

[0097] The optimization module 304 is used to obtain an optimized variable quantum circuit by deleting the target quantum logic gate to be deleted from the variable quantum circuit.

[0098] The specific functions and effects of the aforementioned quantum circuit optimization device can be explained by referring to other embodiments of this application, and will not be repeated here. Each sub-circuit in the quantum circuit optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. Each sub-circuit can be embedded in or independent of the processor in a computer device in hardware form, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each of the above sub-circuits.

[0099] Please see Figure 4 This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit optimization method in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 4 The computer device can be a classical computer or a quantum computer.

[0100] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit optimization method in any of the above embodiments.

[0101] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the quantum circuit optimization method in any of the above embodiments.

[0102] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0103] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0104] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0105] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software sub-circuits in the decoding processor. The software sub-circuits can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0106] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0107] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0111] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0112] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A quantum circuit optimization method, characterized in that, The method includes: A variable quantum circuit is obtained, wherein the variable quantum circuit contains multiple target quantum logic gates, and the target quantum logic gates are quantum rotation gates with variable parameters; When running the current variable quantum circuit to obtain the target expected value, calculate the contribution of the variable parameter of each target quantum logic gate to the target expected value under the target parameter value, wherein the target expected value is the expected value of the variable quantum circuit when the parameter value of the variable parameter changes to convergence. Using the calculated contributions, the target quantum logic gate to be deleted is determined; The optimized variable quantum circuit is obtained by deleting the target quantum logic gate to be deleted from the variable quantum circuit.

2. The method according to claim 1, characterized in that, The method further includes: Calculate the entanglement degree of qubit pairs in the optimized variable quantum circuit; Using the calculated entanglement degree, a target bit pair is determined from all qubit pairs, wherein the target pair is specifically the qubit pair whose entanglement degree is to be increased; The variable quantum circuit is updated by applying a quantum entanglement gate to the target bit pair.

3. The method according to claim 2, characterized in that, After updating the variable component quantum circuit, the method further includes: Return to the step of calculating the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value when running the current variable quantum circuit to obtain the target expected value, until there are no target quantum logic gates and target bit pairs to be deleted.

4. The method according to claim 2 or 3, characterized in that, The degree of entanglement is the von Neumann entropy of the reduced density matrix of the qubit pair.

5. The method according to claim 1, characterized in that, After obtaining the optimized variable quantum circuit, the method further includes: Return to the step of calculating the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value while running the current variable quantum circuit to obtain the target expected value, until there are no more target quantum logic gates to be deleted.

6. The method according to claim 1, characterized in that, The target expected value is obtained by optimizing the variable parameters using the SLSQP optimization algorithm.

7. The method according to claim 1, characterized in that, The step of determining the target quantum logic gate to be deleted using the calculated contribution includes: The target quantum logic gate whose calculated contribution is less than a preset threshold is selected as the target quantum logic gate to be deleted.

8. A quantum circuit optimization device, characterized in that, The device includes: A module for obtaining a variable quantum circuit, wherein the variable quantum circuit contains multiple target quantum logic gates, and the target quantum logic gates are quantum rotation gates with variable parameters; The calculation module is used to calculate the contribution of the variable parameters of each target quantum logic gate to the target expected value under the target parameter value when the target expected value is obtained by running the current variable quantum circuit. The target expected value is the expected value of the variable quantum circuit when the parameter value of the variable parameters changes to convergence. The determination module is used to determine the target quantum logic gate to be deleted using the calculated contribution; The optimization module is used to obtain an optimized variable quantum circuit by deleting the target quantum logic gate to be deleted from the variable quantum circuit.

9. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the quantum circuit optimization method of any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit optimization method of any one of claims 1-7.

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