Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators

Abstract

The application discloses an Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators, relates to Ising circuit technology, and aims at the low solution quality and other problems in the prior art. A serial port interface is responsible for the interaction between the chip and the user; in the initialization stage, the serial port interface receives the combination optimization problem and the annealing parameters input by the user, and after the annealing iteration is completed, the serial port interface is responsible for returning the final spin state obtained by the Ising annealing to the user as the solution of the original problem; a central controller is responsible for the control and annealing evolution scheduling of the whole circuit; a hierarchical annealing array one-to-one corresponds the structured features of the mapping model itself to the hardware levels in the physical world, and the strongly coupled spin groups are mapped to the same spin processing cluster. The application has the advantages that multiple neighborhood search operators are supported, the corresponding operator can be dynamically selected according to the constraint type of different combination optimization problems, the hardware resource utilization rate is high, and the delay and interconnection overhead caused by the flattening global communication are reduced.

Description

Technical Field

[0001] This invention relates to Ising circuit technology, and more particularly to Ising annealing processing circuits that support structured sparsity and multiple neighborhood search operators. Background Technology

[0002] The Ising annealing circuit is a specialized computational circuit for combinatorial optimization problems. It typically maps problems such as maximum cut, graph partitioning, scheduling, placement and routing, and path planning to the Ising model and searches for low-energy solutions by repeatedly updating spin states. Compared to general-purpose processors or graphics processing units (GPUs), dedicated Ising annealing circuits offer higher parallelism in steps such as spin updates, energy difference calculations, random perturbations, and neighborhood searches, and are therefore considered an important approach to solving combinatorial optimization problems.

[0003] However, existing Ising annealing circuits still have significant shortcomings when dealing with real combinatorial optimization problems. First, the Ising models mapped from many real-world problems are not uniformly dense structures, but rather exhibit structured sparse characteristics. Existing circuits often use fixed connection topologies, making it difficult to dynamically adjust the computational path according to the sparse form of different problems. This results in a large number of zero-valued coupling terms still occupying multiply-accumulate, memory access, and control resources, reducing the annealing speed. Second, existing Ising annealing circuits mainly rely on spin-flip neighborhood search operators, which have a limited variety of neighborhood search operators. For combinatorial optimization problems with complex constraints and numerous local energy traps, a single neighborhood search operator is prone to problems such as insufficient search space coverage and low constraint processing efficiency, making it difficult to achieve stable solution quality across different problem types.

[0004] Therefore, there is an urgent need for an Ising annealing circuit that can match the structured sparse characteristics of the original problem with the hardware circuit and support multiple neighborhood search operators in the annealing circuit. Summary of the Invention

[0005] The purpose of this invention is to provide an Ising annealing processing circuit that supports structured sparse and multiple neighborhood search operators, so as to solve the problems existing in the prior art.

[0006] The Ising annealing processing circuit that supports structured sparsity and multiple neighborhood search operators described in this invention includes a serial port interface, a central controller, and a hierarchical annealing array. The serial port interface is responsible for the interaction between the chip and the user; during the initialization phase, it receives the external input combinatorial optimization problem and annealing parameters, and after the annealing iteration is completed, it is responsible for returning the spin state finally obtained by Ising annealing to the user as the solution to the original problem. The central controller is responsible for the control and annealing evolution scheduling of the entire circuit; The hierarchical annealing array maps the structured features of the mapping model to the physical hardware hierarchy, and strongly coupled spin groups are mapped to the same spin processing cluster.

[0007] The Ising annealing circuit supporting structured sparsity and multiple neighborhood search operators described in this invention has at least the following advantages: (1) It supports multiple neighborhood search operators (two-spin swap in the same column, two-column spin swap, any two-spin swap and single spin flip), and can dynamically select the corresponding operator according to the constraint type of different combination optimization problems. Compared with circuits that only support single spin flip or fixed update rules, this invention can expand the effective search neighborhood, enhance the ability to escape local optima, and improve the solution quality of complex constraint problems.

[0008] (2) It has a high hardware resource utilization rate. The Neighborhood Search Unit (PNSU) can reconstruct the computation and data path according to the mapping model, so that the computational resources are concentrated on the effective coupling terms; the central controller uniformly schedules annealing parameters, spin updates, energy thresholds and array feedback through instruction storage, instruction codec and annealing process manager, which reduces the complexity of the control path and improves the circuit operation efficiency.

[0009] (3) A hierarchical annealed array structure is adopted, in which high-frequency local communication is carried out within the cluster, and necessary global communication is completed between the clusters through a tree network. This structure makes the hardware interconnection relationship correspond to the local strong coupling and cross-regional weak coupling characteristics of the mapping model, reducing the latency and interconnection overhead caused by flat global communication. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the Ising annealing circuit described in this invention.

[0011] Figure 2 This is a schematic diagram of the structure of the spin processing cluster described in this invention.

[0012] Figure 3 This is a schematic diagram of the neighborhood search unit PNSU described in this invention. Detailed Implementation

[0013] The overall hardware architecture of the Ising annealing processing circuit supporting structured sparse and multiple neighborhood search operators described in this invention is as follows: Figure 1 As shown, it consists of three key modules: a serial port interface, a central controller, and a hierarchical annealing array.

[0014] The serial port interface is responsible for the interaction between the chip and the user, and mainly consists of a register file. During the initialization phase, it receives the external input combinatorial optimization problem and annealing parameters, and after the annealing iteration is completed, it is responsible for sending the final spin state obtained from the Ising annealing back to the user as the solution to the original problem.

[0015] The central controller is responsible for the control and annealing evolution scheduling of the entire circuit. It consists of an annealing process manager, an energy and constraint threshold unit, a spin state updater, a time counter, an instruction memory, a program counter, and an instruction codec. The annealing process manager monitors the annealing stages and dynamically generates real-time annealing parameters, such as the current annealing temperature. The energy and constraint threshold unit stores and maintains the real-time model energy and constraint energy thresholds. The real-time model energy includes the quadratic component of the Hamiltonian energy. Hamiltonian energy linear term components Overall Hamiltonian Energy The spin state updater calculates the next spin state. A time counter records the clock cycles consumed during the annealing evolution process. An instruction memory stores the annealing instruction sequence. This sequence encodes all the control information required for a single iteration step; a program counter handles the ordered reading of instructions, simplifying the complexity of the hardware control path. The instruction codec combines the instructions from the instruction memory with parameters such as annealing parameters, real-time model energy, energy threshold, and the updated spin state into a complete instruction, which is then broadcast to the hierarchical annealing array. Simultaneously, it decodes feedback messages from the hierarchical annealing array into specific parameters, such as the spin address.

[0016] The hierarchical annealing array is a hierarchical network composed of multiple spin processing clusters interconnected by a tree network. Each spin processing cluster integrates seven Neighborhood Search Units (PNSUs), each supporting parallel processing of 16 arbitrarily connected spins, for a total of 112 arbitrarily connected spins per cluster. The hierarchical annealing array maps the structured features of the mapping model to physical hardware hierarchies, mapping strongly coupled spin groups to the same spin processing cluster, achieving localized computation and communication. Cross-cluster global communication is only performed via the tree network when necessary. This hierarchical interconnection provides differentiated communication guarantees for high-frequency intra-cluster communication and low-frequency inter-cluster communication, reducing annealing latency. The Neighborhood Search Unit (PNSU) achieves dynamic matching between hardware logic and problem characteristics through a two-layer reconfigurable design: 1) To address the differences in sparsity patterns across different mapping models, PNSU reconfigures its computation and data paths, reducing ineffective multiplication and addition operations on zero-value coupling coefficients and improving annealing speed and efficiency; 2) To address diverse constraint characteristics, PNSU supports neighborhood search operators for two-spin swaps in the same column, two-column spin swaps, arbitrary two-spin swaps, and single-spin flipping, dynamically switching to the most suitable search operator based on problem requirements for efficient solution of complex combinatorial optimization problems. Through this design, PNSU achieves deep collaboration between hardware and the sparse and constraint characteristics of the problem: the computation and data paths change accordingly when facing sparse characteristics; the search operators change accordingly when facing constraint characteristics.

[0017] like Figure 2 As shown, a single spin processing cluster supports parallel processing of 112 strongly coupled spins, consisting of seven Neighborhood Search Units (PNSUs) and shared auxiliary circuitry. The auxiliary circuitry mainly includes a shared register file, a data exchange readout controller, a reconfigurable comparator array, a deverification unit, a data selector, and a master-operated spin data receiver. These components are shared by all seven PNSUs within the cluster, avoiding the need to configure redundant storage and control units for each PNSU, thus reducing system hardware overhead. The shared register file is responsible for receiving and maintaining dynamic and static annealing parameters from the central controller. Before the annealing process begins, global static annealing parameters, such as the total number of rows in the 2D mesh mapping model and the energy threshold used for constraint discrimination, are extracted and stored from the broadcast command stream issued by the central controller. During the annealing process, information about the master spin object is received and stored, such as its cluster address, PNSU address, local address, and real-time row address in the two-dimensional mesh mapping model. This data is shared by all seven neighborhood search units (PNSUs) within the cluster, providing a unified parameter basis for subsequent annealing data interaction, neighborhood search, and constraint determination.

[0018] When each Neighborhood Search Unit (PNSU) executes exchange-type neighborhood search operators, such as arbitrary two-spin exchange and two-column spin exchange operators, the local spin operation object comes from the spins it maintains, while the main spin operation object comes from either a spin processing cluster outside itself or its own spin processing cluster. Specifically, in a global search, it comes from a spin processing cluster outside itself, while in a local search, it comes from its own spin processing cluster. This spin operation object is defined as the main spin operation object. This is used to calculate the energy change. Hamiltonian energy quadratic component With Hamiltonian energy linear components And update the spin local field Each Neighborhood Search Unit (PNSU) must acquire the spin state, local field value, relevant coupling coefficient, and external field value of the master-operated spin object. The exchange data readout controller, data selector, and master-operated spin data receiver are responsible for generating and acquiring the corresponding data.

[0019] The data exchange controller comprises a cluster address matching detection unit for the master-operated spin, a stage enable unit, a read address and type management unit, and a distributor. The cluster address matching detection unit for the master-operated spin compares the Cluster address of the master-operated spin object with the address of the current spin processing cluster in real time to determine whether the master-operated spin object is located within the current spin processing cluster. If the addresses are the same, the data exchange controller activates the stage enable unit and the read address and type management unit, sequentially generating relevant local fields for the master-operated spin object. Spin coupling coefficient Spin external field and spin state The read address is generated by subscripts i and j, which represent spin numbers. This address generation process masks invalid data reads and redundant memory accesses based on the structured sparse characteristics of the specific problem, reducing network traffic and thus reducing communication latency. Subsequently, the allocator sends the generated read address to the corresponding neighborhood search unit (PNSU) based on the PNSU address of the master spin object in the shared register file, and the corresponding PNSU performs the data read operation. The read data is selected and distributed by a data selector: in global search mode, the data is broadcast to all PNSUs; in local search mode, the data is only sent to the PNSUs within the current spin processing cluster. Data interaction is strictly limited to within the cluster, isolating cross-cluster communication and reducing communication latency. In this embodiment, taking two-column spin swapping as an example, when the system locks the third column of spins in PNSU #3 as the master spin object, PNSU #3 sequentially reads the corresponding local fields from its internal memory. Internal coupling coefficient External field With the current spin state This data is then sent to other neighborhood search units (PNSUs). If there is no connection between spins within a column, it will not be read. If the mapping model has no external field, then it will not be read. .

[0020] The master-operated spin data receiver consists of a shift register. After the data selector completes data distribution, the master-operated spin data receiver captures and stores the correlation coefficients of active spins in the master-operated spin object from the network during the execution of two-column spin exchange operators or two-column spin exchange operators within the same column, as shown in the example above. , and During the execution of any two spin exchange operators, the correlation coefficients of the master-operated spin objects are captured and stored. This captured data is broadcast via a shared bus to all Neighborhood Search Units (PNSUs) within the cluster, providing operands for energy calculations and local field updates for each PNSU.

[0021] The Ising annealing circuit faces a dual comparison task. First, during the constraint satisfaction judgment stage, it needs to compare the quadratic components of the Hamiltonian energy after the neighborhood search. Or Hamiltonian energy linear term components With energy threshold First, a comparison is made to determine whether candidate solutions satisfy the energy constraint. Second, in the search acceptance decision phase, when multiple neighborhood search units (PNSUs) simultaneously generate valid solutions and the system is in speed-priority mode, the neighborhood search unit with the lowest energy needs to be selected. Both tasks require comparator circuits, and the number of comparators required increases linearly with the number of PNSUs. Deploying comparator circuits independently for the two tasks would result in significant hardware overhead. Therefore, this invention designs a reconfigurable comparator array and solution verification unit circuit, which reduces hardware costs while efficiently ensuring functionality.

[0022] The reconfigurable comparator array consists of seven less-than comparators and an XOR computation array. During the constraint satisfaction determination phase, the seven less-than comparators operate independently and in parallel, each receiving the energy value from the seven neighborhood search units (PNSU) after neighborhood search and comparing it with an energy threshold. The comparison is then performed. Subsequently, the XOR calculation array inverts or directly outputs the comparison result based on the preset constraint type (greater than or equal to or less than or equal to), generating an energy violation flag signal for each neighborhood search unit (PNSU). For example, if the constraint type is a Hamiltonian energy quadratic component... The XOR calculation array will invert the output of the comparator if it is less than the value of the comparator; if the constraint type is a quadratic component of Hamiltonian energy. The XOR computation array directly outputs the result of the less-than comparator. This design allows a single hardware component to adapt to both energy constraint determination requirements. In the search acceptance decision phase, the seven less-than comparators are reconstructed into a three-level tree-like comparison network. Combined with the search validity flags output by the subsequent solution verification unit, the energy change is progressively selected from the valid candidate solutions. The minimum solution and its corresponding neighborhood search unit PNSU index.

[0023] The deverification unit mainly consists of a state XOR array, an equivalence detection unit, a selector, and a search validity flag register (REG). Based on the energy violation flag signal output by the reconfigurable comparator array, the deverification unit determines the validity of the neighborhood search of each PNSU unit in the current iteration step by combining the state and row address of the spin object operated by each neighborhood search unit (PNSU). For two spin swap operators, the state XOR array compares the current state of the local spin object with that of the master spin object. If the two states are the same, the swap operation cannot change the system energy, and the search is meaningless; when the two states are different, the search is meaningful. For two column spin swap operators, the equivalence detection unit compares the active spin row address of the local spin object operated by each PNSU unit with that of the master spin object. If the two row addresses are the same, i.e., they belong to the same row, the search is deemed invalid. For single spin-flip operators, since they do not involve paired operations, the selector directly determines that the operated spin object is valid. The inspection results are logically ANDed with the energy violation flag signal output by the reconfigurable comparator array to generate the search validity flag information for each Neighborhood Search Unit (PNSU) and store it in the search validity flag register. In speed-priority mode, the three-level tree-structured comparison network selects the optimal solution with the minimum energy and its corresponding Neighborhood Search Unit (PNSU) index from the valid candidate solutions. Then, the data selector extracts the address, state, and energy change of the operand object of the optimal solution based on the PNSU index. Hamiltonian energy quadratic component With Hamiltonian energy linear components Information such as these is injected into the communication network. In precision-priority mode, the data selector randomly selects one from the valid candidate solutions and injects the corresponding information into the communication network.

[0024] The Neighborhood Search Unit (PNSU) is the core computational carrier of the spin processing cluster, responsible for selecting the operand spin, performing neighborhood search operations, calculating energy, and updating the local field. For example... Figure 3 As shown, the Neighborhood Search Unit (PNSU) manages 16 parallel spins and mainly consists of a data memory, a local field unit, a data receiver, an energy unit, and an operand address selection and calculation unit. Its core innovation lies in supporting various neighborhood search operators and diverse structured sparse computations through programmable circuits, and achieving fast random selection and address calculation of operand objects with low hardware cost through the coordinated optimization of memory and logic circuits.

[0025] The data memory stores the external field coefficients of the 16 local spins. The coupling coefficient between the local spin and all associated spins The system also stores the row address of each spin in the two-dimensional mesh mapping model. Row addresses are only stored when the mapping model of the input problem is a two-dimensional mesh structure; otherwise, they are not stored. The row addresses and spin coefficients share a storage unit, thus avoiding additional storage overhead. The local field unit contains 16 local field registers, a right-shifted shift register, a multiply-accumulate unit (MAC), and a selector, responsible for the 16 spin local fields. Initialization and dynamic updates are performed. Before annealing begins, the 16 local field registers are reconstructed into a serial shift register chain, with initialization data from the central controller shifted into each local field register sequentially. This serial loading mechanism avoids complex global address decoders and high-fan-out multiplexers, simplifying hardware design complexity. After initialization, the serial shift register chain switches to parallel independent operating mode for local field updates. The local field update process follows structured sparse computation. The central controller reads the sparse computation instruction sequence from the instruction memory and then issues a single-instruction multiple-data (SIMD) update instruction to each spin processing cluster. Upon receiving the instruction, the local field unit extracts the selected operation spin for the current iteration step. and its updated status The corresponding coupling coefficients are read in parallel from the data memory. Then perform multiplication and accumulation operations. This completes the update of the local field. The above update process avoids ineffective coupled calculations to some extent, reduces the local field update time, and thus accelerates the entire annealing process.

[0026] The operational spin address selection and calculation unit is responsible for randomly generating corresponding operational spin objects for the execution of operators such as single spin flip, arbitrary two-spin swap, and two-column spin swap. The operational spin address selection and calculation unit mainly consists of a spin selection module, a local spin address register, and a spin address calculation unit. The spin selection module is responsible for randomly selecting any operational spin object in the random mapping model, or randomly selecting a one-hot spin in the two-dimensional mesh mapping model. The spin selection module consists of a decoder, a spin state register (REG), a linear feedback shift register (LFSR), a bidirectional priority encoder, a one-hot spin selection module, a selector, and some logic gates. The decoder is responsible for parsing the control signals related to the spin state register from the instruction stream issued by the central controller, driving the spin state register to complete the initial state loading and dynamic state update. For the one-hot spin selection in the two-dimensional mesh mapping model, the 16 spin state bits in the spin state register are first subjected to pairwise NAND operations on adjacent bits, reducing the original 16-bit state data to 8 bits. This reduces the input size of the subsequent bidirectional priority encoder, thereby reducing hardware costs. The spin state +1 / 1 is mapped to logic 1 / 0 respectively. Subsequently, the Linear Feedback Shift Register (LFSR) generates a pseudo-random 0 / 1 vector following a uniform distribution, and performs a logical AND operation between the pseudo-random 0 / 1 vector and the results of the pairwise AND and NOT operations. This operation is equivalent to randomly sampling the current active spin set using a random mask. To ensure that the probability of each spin being selected is as equal as possible, two bidirectional priority encoders perform bidirectional priority encoding on the high 4 bits and low 4 bits of the logical AND operation result, thereby locking the addresses of at most four active spins. Finally, the one-hot spin selection module performs an equal-probability random selection on the candidate addresses, outputs the final operand spin object address, and writes it into the local spin address register. For any operand spin object selection in the random mapping model, the random value of the LFSR is directly used as the operand spin object address. The Neighborhood Search Unit (PNSU) dynamically switches the corresponding address generation method through a selector when executing different neighborhood search operators.

[0027] The data receiver extracts coupling coefficients related to the master-operated spin object from the communication network or the local spin processing cluster. External field Local field With spin state The values ​​are then sequentially stored in internal shift registers to provide the correct operands for energy calculations.

[0028] The energy unit is the core component for energy calculation in the Neighborhood Search Unit (PNSU), responsible for calculating the model energy change before and after spin state flips or swaps. Hamiltonian energy quadratic component With Hamiltonian energy linear components The key design feature of this energy unit lies in its highly configurable data and control paths. Its operands can originate from three different data sources: the host spin processing cluster, data stored in the data receiver, and the data memory. Under the command of the central controller, the unit dynamically selects the computation and data paths based on the current operator type and structured sparsity characteristics, performs multiplication-accumulation operations, and temporarily stores the results in an internal register. Finally, the energy unit packages the computation results along with the address and state of the manipulated spin object and sends them to the host spin processing cluster for constraint satisfaction judgment and search acceptance decision.

[0029] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. An Ising annealing processing circuit that supports structured sparse and multiple neighborhood search operators, characterized in that, Includes serial port interface, central controller, and hierarchical annealing array; The serial port interface is responsible for the interaction between the chip and the user; during the initialization phase, it receives the combinatorial optimization problem and annealing parameters from the external input, and after the annealing iteration is completed, it is responsible for sending the spin state finally obtained by Ising annealing back to the user as the solution to the original problem. The central controller is responsible for the control and annealing evolution scheduling of the entire circuit; The hierarchical annealing array maps the structured features of the mapping model to the physical hardware hierarchy, and strongly coupled spin groups are mapped to the same spin processing cluster.

2. The Ising annealing processing circuit supporting structured sparse and multiple neighborhood search operators according to claim 1, characterized in that, The central controller consists of an annealing process manager, an energy and constraint threshold unit, a spin state updater, a time counter, an instruction memory, a program counter, and an instruction codec. The annealing process manager monitors the annealing stage and generates real-time annealing parameters; The energy and constraint threshold unit stores and maintains the real-time model energy and constraint energy threshold. The real-time model energy includes the quadratic component of the Hamiltonian energy. Hamiltonian energy linear term components Overall Hamiltonian Energy ; The spin state updater calculates the next state of the spin; The time counter records the clock cycles consumed during the annealing evolution process; The instruction memory stores the annealing instruction sequence; the annealing instruction sequence encodes all the control information required for a single iteration step. The program counter is responsible for the orderly reading of instructions; The instruction codec merges the instructions in the instruction memory with the annealing parameters, real-time model energy, energy threshold, and updated spin state into a complete instruction, and broadcasts it to the hierarchical annealing array; at the same time, it is responsible for decoding the feedback messages from the hierarchical annealing array into specific parameters.

3. The Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators according to claim 2, characterized in that, The hierarchical annealing array is a hierarchical network consisting of multiple spin processing clusters interconnected by a tree network. Each spin processing cluster integrates seven neighborhood search units (PNSUs), and each PNSU supports parallel processing of 16 arbitrarily connected spins. A single spin processing cluster supports a total of 112 arbitrarily connected spins. The Neighborhood Search Unit (PNSU) is a reconfigurable design: PNSU reconfigures its computation and data paths to address the differences in sparsity patterns of different mapping models; and supports neighborhood search operators for various constraint features, including two-spin swaps in the same column, two-column spin swaps, arbitrary two-spin swaps, and single-spin flip, dynamically switching to the most suitable search operator based on problem requirements. When each neighborhood search unit (PNSU) executes the exchange-type neighborhood search operator, the local operation spin object comes from the spin maintained by itself, while the main operation spin object comes from the spin processing cluster outside itself or the spin processing cluster to which it belongs. Specifically, the spin object comes from the spin processing cluster outside itself during global search and from the spin processing cluster to which it belongs during local search.

4. The Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators according to claim 3, characterized in that, Each spin processing cluster is equipped with auxiliary circuitry; the auxiliary circuitry includes a shared register file, an exchange data readout controller, a reconfigurable comparator array, a deverification unit, a data selector, and a master-operated spin data receiver. The shared register file is responsible for receiving and maintaining dynamic and static annealing parameters from the central controller; Before the annealing process is started, global static annealing parameters are extracted and stored from the broadcast command stream issued by the central controller; During the annealing process, relevant information about the master spin object is received and stored; The data exchange controller comprises a cluster address matching detection unit for the master-operated spin, a stage enabling unit, a read address and type management unit, and an allocator. The cluster address matching detection unit for the master-operated spin compares the Cluster address of the master-operated spin object with the address of the current spin processing cluster in real time to determine whether the master-operated spin object is located within the current spin processing cluster. If the addresses are the same, the data exchange controller activates the stage enabling unit and the read address and type management unit, sequentially generating relevant local fields for the master-operated spin object. Spin coupling coefficient Spin external field and spin state The read address is given by the subscripts i and j, which represent the spin number. The allocator sends the generated read address to the corresponding neighborhood search unit PNSU based on the PNSU address of the main operation spin object in the shared register file. The corresponding neighborhood search unit PNSU then performs the data read operation. The reconfigurable comparator array consists of seven less-than comparators and an XOR computation array. During the constraint satisfaction judgment phase, the seven less-than comparators operate independently and in parallel, each receiving the energy value from the seven neighborhood search units (PNSU) after neighborhood search and comparing it with an energy threshold. The comparison is performed; subsequently, the XOR calculation array inverts or directly outputs the comparison results according to the preset constraint type, generating the energy default flag signal of each neighborhood search unit PNSU. The deverification unit consists of a state XOR array, an equivalence detection unit, a selector, and a search validity flag register REG. Based on the energy default flag signal output by the reconfigurable comparator array, the deverification unit determines whether the neighborhood search of each neighborhood search unit PNSU in the current iteration step is valid by combining the state and row address of the spin object operated by each neighborhood search unit PNSU. The data selector is used to select and distribute the data read by the Neighborhood Search Unit (PNSU): in global search mode, the data is broadcast to all Neighborhood Search Units (PNSU); in local search mode, the data is only sent to the Neighborhood Search Units (PNSU) within the current spin processing cluster. The master-operated spin data receiver is composed of a shift register; after the data selector completes data distribution, the master-operated spin data receiver captures and stores the correlation coefficients of active spins in the master-operated spin object from the network during the execution of two columns of spin exchange operators or two spin exchange operators in the same column. During the execution of any two spin exchange operators, the correlation coefficients of the main operation spin objects are captured and stored; the captured data is broadcast to all Neighborhood Search Units (PNSUs) within the cluster via the shared bus, providing operands for energy calculation and local field updates of each PNSU.

5. The Ising annealing processing circuit supporting structured sparse and multiple neighborhood search operators according to claim 4, characterized in that, The Neighborhood Search Unit (PNSU) manages 16 parallel spins and consists of a data memory, a local field unit, a data receiver, an energy unit, and an operational spin address selection and calculation unit.

6. The Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators according to claim 5, characterized in that, The data memory stores the external field coefficients of the 16 local spins. The coupling coefficient between the local spin and all associated spins The data memory stores the row address of each spin in the two-dimensional mesh mapping model; the row address is stored only when the mapping model of the input problem is a two-dimensional mesh structure, otherwise it is not stored.

7. The Ising annealing processing circuit supporting structured sparse and multiple neighborhood search operators according to claim 6, characterized in that, The local field unit contains 16 local field registers, a right-shifted bit shift register, a multiply-accumulate unit (MAC), and a selector, responsible for the 16 spin local fields. Initialization and dynamic updates; before annealing starts, the 16 local field registers are reconstructed into a serial shift register chain, and the initialization data from the central controller is shifted into each local field register one by one. After initialization, the serial shift register chain switches to parallel independent operating mode to perform local field updates. The local field update process follows structured sparse computation. The central controller reads the sparse computation instruction sequence from the instruction memory and then issues single-instruction multiple-data (SIMD) update instructions to each spin processing cluster. After receiving the instruction, the local field unit extracts the selected operation spin for the current iteration step. and the corresponding updated status The corresponding coupling coefficients are read in parallel from the data memory. Then perform multiplication and accumulation operations. This completes the update of the local field.

8. The Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators according to claim 7, characterized in that, The data receiver extracts coupling coefficients related to the master-operated spin object from the communication network or the local spin processing cluster. External field Local field With spin state The values ​​are then sequentially stored in internal shift registers to provide the correct operands for energy calculation.

9. The Ising annealing processing circuit supporting structured sparse and multiple neighborhood search operators according to claim 8, characterized in that, The energy unit is responsible for calculating the model energy change before and after the spin state flip or exchange. Hamiltonian energy quadratic component With Hamiltonian energy linear components The operands of the energy unit come from the spin processing cluster to which it belongs, or from the data stored in the data receiver, or from the data memory. Under the instruction control of the central controller, the calculation and data paths are dynamically selected according to the current operator type and structured sparsity characteristics, the multiplication and accumulation operations are completed, and the results are temporarily stored in the internal register. Finally, the calculation results are packaged together with the address and state of the spin object being operated on and sent to the spin processing cluster to which it belongs for constraint satisfaction judgment and search acceptance decision.

10. The Ising annealing processing circuit supporting structured sparsity and multiple neighborhood search operators according to claim 9, characterized in that, The operational spin address selection and calculation unit consists of a spin selection module, a local spin address register, and a spin address calculation unit. The spin selection module is responsible for randomly selecting any operable spin object in the random mapping model, or randomly selecting a one-hot spin in the two-dimensional mesh mapping model. The spin selection module consists of a decoder, a spin state register REG, a linear feedback shift register LFSR, a bidirectional priority encoder, a one-hot spin selection module, a selector, and several logic gate circuits. The decoder is responsible for parsing the control signals related to the spin state register from the instruction stream issued by the central controller, and driving the spin state register to complete the initial state loading and dynamic state update. For the selection of one-hot spins in the two-dimensional mesh mapping model, the 16 spin state bits in the spin state register are first subjected to pairwise NAND operations on adjacent bits, reducing the original 16-bit state data to 8 bits, and then the spin state is incremented by 1 / 1 is mapped to logic 1 / 0 respectively; then, the linear feedback shift register LFSR generates a pseudo-random 0 / 1 vector that follows a uniform distribution, and performs a logical AND operation between the pseudo-random 0 / 1 vector and the result of the pairwise AND and NOT operations; Two bidirectional priority encoders encode the high 4 bits and low 4 bits of the logical AND operation result in bidirectional priority encoding, thereby locking up to four active spin addresses. Finally, the one-hot spin selection module performs a random selection with equal probability on the candidate addresses, outputs the final operand spin object address and writes it into the local spin address register. For any operation spin object selected in the random mapping model, the random value of the linear feedback shift register LFSR is directly used as the address of the operation spin object; when the neighborhood search unit PNSU executes different neighborhood search operators, it dynamically switches the corresponding address generation method through a selector.

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