A credit limit adaptive calculation method and system based on tax credit

Abstract

The application discloses a credit limit adaptive calculation method and system fusing tax credit, and relates to the technical field of data processing. The method acquires a tax credit level label, a historical tax declaration timestamp sequence and basic financial data; encodes the tax credit level label, modulates the encoded tax credit level label through a double-channel full adder in parallel, and generates two analog voltages; outputs a three-state gate signal in a release state, a fuse state or a critical state through analog domain comparison and judgment, and outputs a gray zone mark in the critical state; conditionally shunts through a three-state gate switch, and a timing attenuation engine performs interrupt mode identification and exponential time attenuation calculation according to a relaxation coefficient and the declaration timestamp sequence to generate an attenuation coefficient; maps and fuses the three-state gate signal and the attenuation coefficient to generate a limit multiplier, and multiplies the limit multiplier with a basic credit limit to obtain a final limit configuration result. The application realizes parallel processing of a credit level hardware layer, fine processing of a critical state and risk adaptive isolation.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to an adaptive calculation method and system for credit limits that integrates tax credit. Background Technology

[0002] With the deepening of the bank-tax cooperation policy, credit assessment based on tax data has become an important technical approach for financing micro and small enterprises. Tax authorities have accumulated rich corporate tax data over the long term, including tax credit rating results, historical tax declaration records, and actual tax payments. This data reflects the operating conditions and creditworthiness of enterprises from different dimensions. How to effectively apply this government data to credit limit calculation systems has become an important research direction in the field of fintech.

[0003] In existing technologies, the enterprise credit limit determination scheme based on government data typically follows these steps: collecting enterprise data from the government system; conducting initial customer screening based on enterprise access rule strategy sets; inputting enterprise characteristic information into a credit scoring model and a credit limit calculation model respectively, outputting a credit score and a basic credit limit; and then linearly adjusting the basic credit limit based on the credit score. Another technical solution uses multi-dimensional government data and corresponding access conditions to screen enterprises, determine target enterprises and their government credit limit data, and then combine this with outstanding loan data to determine the credit limit.

[0004] However, existing technical solutions have the following technical shortcomings at the data processing architecture level: First, high-risk or unqualified credit rating data entering the credit limit calculation process results in high consumption of computing resources and delayed risk response. Secondly, when a company's credit status is at a critical point, it is impossible to transmit this critical status to the subsequent credit limit calculation process for more refined processing. Third, the admission screening and credit limit calculation are two independent stages. This fragmented architecture results in the system lacking adaptive adjustment capabilities when faced with situations where the admission is strict but the credit limit is inflated or the admission is lenient but the credit limit is distorted. Fourth, existing credit scoring models are unable to quantify the credit risk reflected by discrete reporting behaviors.

[0005] In view of the above, this application is hereby submitted. Summary of the Invention

[0006] To address the aforementioned problems in existing technologies, this paper provides an adaptive calculation method and system for credit limits that integrates tax credit, aiming to solve at least one of the above problems.

[0007] The technical solution to achieve the purpose of this application is as follows: This application provides an adaptive calculation method for credit limits that integrates tax credit, which includes the following steps: Step S1: Generate a relaxation coefficient α that matches the tax credit rating label L. After the tax credit rating label L is encoded, it is superimposed with the sensitivity tuning parameter Δ1 and the threshold control parameter Δ2 for parallel modulation, and a first analog voltage V1 for sensitivity tuning and a second analog voltage V2 for threshold anchoring are generated.

[0008] Step S2, the first analog voltage V1 and the second analog voltage V2 are both related to the preset high-level threshold V. IH A voltage comparison is performed, and both the first analog voltage V1 and the second analog voltage V2 are compared to a preset low-level threshold V. IL A voltage comparison is performed to generate a three-state gating signal G, and a gray zone marker γ is output in the critical state.

[0009] Step S3: Based on the three-state gating signal G, conditional shunting is performed on the relaxation coefficient α and the gray zone marker γ, thereby controlling the calculation path of the attenuation coefficient δ.

[0010] Step S4: Generate the attenuation coefficient δ based on the relaxation coefficient α and the historical tax declaration timestamp sequence T.

[0011] Step S5: Based on the three-state gating signal G and the attenuation coefficient δ, the credit multiplier η is generated by mapping and weighted fusion.

[0012] This application also provides an adaptive credit limit calculation system that integrates tax credit, including: a first module and a second module.

[0013] The first module stores a computer program that is configured to execute the aforementioned adaptive calculation method for credit limits based on integrated tax credit when running.

[0014] The second module is configured to execute the aforementioned adaptive calculation method for credit limits based on integrated tax credit through the computer program.

[0015] The second module includes: a credit rating encoder, a parallel encoded data bus, a first full adder, a second full adder, a first storage unit, a second storage unit, a first D / A converter, a second D / A converter, an AND gate, a tri-state encoder, a relaxation coefficient storage unit, a tri-state gating switch, a timing decay engine, a first mapper, a second mapper, a multiplier generator, and a credit limit multiplier.

[0016] The output of the credit rating encoder is connected to a parallel encoding data bus. The same connection point of the parallel encoding data bus is electrically connected to the first input of a first full adder and the first input of a second full adder, respectively. The second input of the first full adder is electrically connected to a first memory unit, and the second input of the second full adder is electrically connected to a second memory unit. The output of the first full adder is electrically connected to the digital input of a first D / A converter, and the analog output of the first D / A converter is electrically connected to the first input of an AND gate, forming a first adjustment channel. The output of the second full adder is electrically connected to the digital input of a second D / A converter, and the analog output of the second D / A converter is electrically connected to the second input of an AND gate, forming a second adjustment channel. The output of the AND gate is electrically connected to the output of the three-state encoder. At the input end, the first output of the tri-state encoder is electrically connected to the control terminal of the tri-state gate switch, and the second output is electrically connected to the auxiliary input terminal of the tri-state gate switch; the data input terminal of the tri-state gate switch is electrically connected to the relaxation coefficient storage unit, and the data output terminal of the tri-state gate switch is electrically connected to the data input terminal of the timing decay engine; the first output of the tri-state encoder is also electrically connected to the input terminal of the first mapper; the output terminal of the timing decay engine is electrically connected to the input terminal of the second mapper; the output terminals of the first mapper and the second mapper are respectively electrically connected to the two input terminals of the multiplier generator, the output terminal of the multiplier generator is electrically connected to the first input terminal of the credit multiplier, the second input terminal of the credit multiplier is used to receive the basic credit limit, and the output terminal of the credit multiplier outputs the final credit limit configuration result.

[0017] Compared with the prior art, the beneficial effects of this application include: (1) In the prior art, tax credit ratings are stored in the database as text strings or enumerated values. After the system reads them through software instructions, they are converted into numerical features. This requires multiple software steps such as database access, data parsing, and type conversion, with a response time of more than milliseconds. Furthermore, the arrival times of the data at the two processing units differ. In this application, the same connection point of the parallel encoded data bus is electrically connected to the first input terminal of the first full adder and the first input terminal of the second full adder, respectively, so that the same binary digital code is transmitted in parallel to the two full adders within the same clock cycle. The modulation amplitude of the first channel is small, making the first analog voltage highly sensitive to subtle differences within the qualified rating. The modulation amplitude of the second channel is large, causing the second analog voltage to produce a step level change across the threshold range between the qualified and unqualified ratings. The two full adders share the same input signal source, but the difference in the modulation amplitude allows the two channels to perform two different functions: sensitivity tuning and threshold anchoring. The mode control signals of the two channels are independent of each other, and addition or subtraction can be selected separately, forming four modulation combinations, enabling the hardware to have reconfigurability without changing the circuit topology. Therefore, this application transforms the credit rating information processed serially at the software layer in the prior art into parallel modulation at the hardware layer, reducing the response time of the credit rating information processing stage from milliseconds to nanoseconds, and achieving an order-of-magnitude improvement in the efficiency of credit rating information processing. (2) Existing access control uses binary decision-making at the software layer, outputting either pass or reject through program execution condition judgment statements, with no intermediate state. In this application, the AND gate integrates four comparators, comparing the two analog voltages with preset high-level and low-level thresholds respectively, and outputting three decision results: release state, fuse state, and critical state. Among them, the introduction of the critical state makes the hardware decision no longer a rigid black-and-white judgment. When the credit rating is near the boundary between qualified and unqualified, the system does not simply choose to pass or reject, but outputs the critical state code, triggering the high-sensitivity recalculation of the subsequent timing decay engine. The three-state encoder synchronously outputs a gray zone mark in the critical state, quantifying the specific position of the input voltage within the critical interval into a continuous value, providing a quantitative basis for continuous parameter adjustment in the critical mode. This application realizes the leap from binary hard decision-making to three-state soft decision-making, enabling the hardware layer decision result to trigger the refined and differentiated response of the software layer; (3) In the prior art, the tax declaration timestamp sequence is not included in the credit scoring model, or it is only processed by a simple binary judgment of whether the declaration is continuous, which cannot distinguish the different causes of the interruption. In this application, the time-series decay engine compares the time interval between adjacent declaration times with the preset interruption judgment threshold one by one to identify the declaration interruption event; further, it performs periodic identification of the interruption event - the interruption that occurs repeatedly in the same relative position within two or more consecutive observation periods is classified as periodic interruption, and the rest are judged as sudden interruption. Differentiated penalty weights are assigned to periodic interruption and sudden interruption respectively, and the penalty weight of sudden interruption is higher than that of periodic interruption. At the same time, the exponential time decay factor makes the time since the most recent declaration participate in the calculation of the decay coefficient in a non-linear manner - the closer the declaration behavior is to the present, the greater the influence weight, and the further the declaration behavior is to the present, the greater the influence weight decays exponentially. This application transforms the discrete declaration timestamp sequence into a continuous decay coefficient through the three mechanisms of interruption mode classification, differentiated penalty and exponential time decay, and realizes a precise mathematical characterization of the fuzzy concept of business stability; (4) In the prior art, the tax credit rating is assigned weight along with other features as one of the model input features. There is no mathematical constraint relationship between the credit rating and the credit limit adjustment. The mapping relationship between the credit rating and the credit limit adjustment is hidden in the model's weight matrix. It is impossible to directly control the credit limit adjustment through parameters or mathematical relationships independent of the model weights. In this application, the relaxation coefficient decreases with the credit rating, with the largest for level A, the second largest for level B, and the smallest for level M. It is directly embedded in the calculation formula of the decay coefficient in the form of a multiplicative factor, and directly determines the maximum possible value of the decay coefficient as an upper limit constraint factor. For target objects with a credit rating of level A, even if there is a certain interruption in filing or a long time ago, their decay coefficient is still protected by the maximum relaxation coefficient and maintained at a high level. For target objects with a credit rating of level M, once there is an interruption in filing, their decay coefficient is significantly reduced due to the upper limit constraint of the smaller relaxation coefficient. The tax credit rating is upgraded from the feature being evaluated to the mathematical anchor point that constrains the evaluation boundary, realizing a deep mathematical coupling between qualitative credit rating and quantitative time series evaluation. (5) In the prior art, the input for credit limit adjustment is a single output value of the credit scoring model, and the adjustment method is a linear relationship between the credit score and the adjustment coefficient. In this application, the first mapper maps the three-state digital logic signal to the first potential energy base value corresponding to the release state and the second potential energy base value corresponding to the critical state; the second mapper normalizes the attenuation coefficient to the potential energy fluctuation value. After normalization and mapping, the two heterogeneous signals are in the same numerical space. The multiplier generator generates the credit limit multiplier by weighted summation and nonlinear activation function, wherein the fusion weight of the decision base value is significantly higher than the fusion weight of the fluctuation value. This weight constraint ensures that the credit limit output ranges of the release state and the critical state do not overlap, the credit limit multiplier of the release state is always higher than that of the critical state, and the final credit limit does not exceed the basic credit limit. This application nonlinearly fuses the discrete decision signal from the hardware layer and the continuous time-series evaluation signal from the software layer within the same mathematical framework, overcoming the limitations of the linear adjustment expression in the prior art; (6) In the prior art, the admission screening and quota calculation stages are independent of each other. The admission rules are responsible for screening, and the quota calculation model is responsible for output. High-risk data still needs to undergo complete software layer calculation before being rejected, which consumes a lot of computing resources and has a delayed risk response. In this application, when the three-state gating signal is in the fuse-off state, the data output terminal of the three-state gating switch is in a high-impedance state, blocking the transmission of the relaxation coefficient to the subsequent data bus; at the same time, a fuse-off interrupt command is sent to the timing decay engine through an independent interrupt control line. After receiving the fuse-off interrupt command, the timing decay engine does not start the calculation, and the quota multiplier directly outputs the preset default quota configuration result. When the three-state gating signal is in the critical state, the three-state gating switch transmits the gray zone flag and relaxation coefficient to the timing decay engine in a synchronous manner. The timing decay engine calculates the amplification coefficient according to the gray zone flag, and recalculates the attenuation coefficient after simultaneously amplifying the attenuation rate parameter and the interrupt penalty weight. Therefore, this application achieves nanosecond-level data flow blocking for unqualified credit ratings at the hardware layer and high-sensitivity parameter amplification of boundary credit ratings at the software layer, forming a dual risk isolation mechanism of rapid circuit breaking at the hardware layer and fine tightening at the software layer. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the adaptive calculation method for credit limits that integrates tax credit. Figure 2 This is a schematic diagram of the overall structure of a credit limit adaptive calculation system that integrates tax credit. Figure 3 This is a schematic diagram of the gated discrimination unit structure of an adaptive credit limit calculation system that integrates tax credit. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application.

[0021] Therefore, the following detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely illustrates some embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in this application can be combined with each other.

[0023] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0024] Regarding the technical problem addressed in this application, the inventors have discovered that, as a qualitative dimension label within authoritative government data, existing technologies use tax credit ratings along with other characteristics such as tax amount and years of operation as input features in software models, assigning weights before calculation. The system cannot proactively intercept data that does not meet security level requirements in the early stages of the data flow, nor can it use the degree of credit rating as an independent constraint to influence the subsequent quantitative assessment range.

[0025] Existing access control technologies use software-layer rule sets or access conditions for initial customer screening. Because software-layer binary decisions lack intermediate states, when a company's creditworthiness falls within the boundary between qualifying and disqualifying, the system must make an either-or choice, failing to pass this boundary state to subsequent credit limit calculation stages for refined processing.

[0026] In existing technologies, admission screening and credit limit calculation are two independent stages: admission rules are responsible for screening, and the credit limit calculation model is responsible for outputting the credit limit. The binary decision result output in the admission stage is discarded after entering the credit limit calculation stage, or is only retained as a simple prerequisite; its fragmented architecture results in the system lacking adaptive adjustment capabilities when facing situations where admission is strict but the credit limit is inflated or admission is lenient but the credit limit is distorted.

[0027] Existing credit scoring models rely primarily on tax payments and sales revenue data as input features, making it impossible to construct continuous time-series variables and thus difficult to quantify the credit risk reflected by discrete reporting behaviors.

[0028] This application constructs an adaptive credit limit calculation architecture of "hardware-based three-state judgment of credit rating - continuous decay of application time sequence - heterogeneous signal fusion", which elevates the qualitative credit rating from the features being evaluated to the mathematical anchor points that constrain the evaluation boundary, and achieves rapid risk isolation and refined boundary state processing through the synergy of hardware judgment and software calculation.

[0029] In the hardware-based three-state decision-making stage of credit rating, the tax credit rating label is encoded as a digital code that monotonically changes with the rating's quality. This code is then modulated in parallel through dual channels to generate two analog voltages. The analog domain comparison and decision output includes a three-state gating signal encompassing a release state, a circuit breaker state, and a critical state. The circuit breaker state is used to pre-intercept unqualified credit ratings early in the data stream. The critical state characterizes the credit status as being in the intermediate state between qualified and unqualified, and simultaneously outputs a gray zone indicator to quantify the degree of boundary deviation. This stage transforms the binary hard decision-making at the software layer in existing technologies into a three-state soft decision-making at the hardware layer, ensuring that boundary states are not simply discarded but are instead passed on to subsequent credit limit calculation stages.

[0030] In the continuous decay stage of the tax filing time series, based on the historical tax filing timestamp sequence, periodic interruptions and sudden interruptions are distinguished through interruption pattern recognition, and differentiated penalty weights are assigned. Combined with an exponential time decay factor, discrete filing behavior is transformed into a continuous decay coefficient. Simultaneously, a slack coefficient is determined based on the taxpayer's credit rating and embedded as an upper limit constraint factor for the decay coefficient calculation, ensuring that the credit rating directly constrains the maximum possible value of the time series assessment. This stage achieves deep mathematical coupling between qualitative credit rating and quantitative time series assessment, and accurately characterizes operational stability.

[0031] In the heterogeneous signal fusion stage, the three-state gating signal is mapped to a discrete potential energy base value, and the continuous attenuation coefficient is mapped to a potential energy fluctuation value, placing the two types of heterogeneous signals in the same numerical space. Then, a weighted nonlinear fusion is used to generate the credit multiplier, with the fusion weight of the decision base value being higher than that of the fluctuation value. This ensures that the credit multiplier in the release state is always higher than that in the critical state, and that the final credit limit does not exceed the basic credit limit. This stage fuses the discrete decision signal from the hardware layer and the continuous time-series evaluation signal from the software layer within the same mathematical framework, overcoming the limitations of linear adjustment in existing technologies.

[0032] This application implements rapid data flow blocking for unqualified credit ratings at the hardware layer and highly sensitive parameter amplification and fine-tuning of credit limits at the software layer, forming a dual risk isolation mechanism of rapid hardware circuit breaking and fine-tuning software adjustment. Simultaneously, the tax credit rating is no longer merely a model input feature participating in weight calculation, but rather an independent constraint directly determining the calculation range of subsequent quantitative assessments, thus possessing adaptive adjustment capabilities in situations where access is strict but credit limits are inflated, or access is lenient but credit limits are distorted.

[0033] Based on this, this application is hereby filed.

[0034] The present application will now be described in further detail with reference to the embodiments.

[0035] Combination Figures 1 to 3 As shown, this application also provides an adaptive calculation method for credit limits that integrates tax credit, the method comprising the following steps: Step S1: Generate a relaxation coefficient α that matches the tax credit rating label L. After the tax credit rating label L is encoded, it is superimposed with the sensitivity tuning parameter Δ1 and the threshold control parameter Δ2 for parallel modulation, and a first analog voltage V1 for sensitivity tuning and a second analog voltage V2 for threshold anchoring are generated.

[0036] Specifically, the tax credit rating label L is encoded as a binary digital code W. The binary digital code W is input in parallel to the first full adder and the second full adder. The first full adder is superimposed with the sensitivity tuning parameter Δ1 and then generates the first analog voltage V1 through the first D / A converter. The second full adder is superimposed with the threshold control parameter Δ2 and then generates the second analog voltage V2 through the second D / A converter.

[0037] Step S2, the first analog voltage V1 and the second analog voltage V2 are both related to the preset high-level threshold V. IH A voltage comparison is performed, and both the first analog voltage V1 and the second analog voltage V2 are compared to a preset low-level threshold V. IL A voltage comparison is performed to generate a three-state gating signal G, and a gray zone marker γ is output in the critical state.

[0038] The three-state gating signal G includes the release state, the circuit breaker state, and the critical state.

[0039] Step S3: Based on the three-state gating signal G, conditional shunting is performed on the relaxation coefficient α and the gray zone marker γ, thereby controlling the calculation path of the attenuation coefficient δ.

[0040] Specifically, the three-state gating signal G controls the opening and closing of the gating switch. The three-state gating switch performs conditional shunting of the relaxation coefficient α and the gray zone marker γ, controlling the start mode of the time-series decay engine. When G is in the circuit breaker state, it blocks the subsequent data flow and outputs the default quota configuration result. When G is in the release state or the critical state, it conducts the data flow and transmits the relaxation coefficient α obtained by looking up the table according to the tax credit rating label L to the time-series decay engine, thereby controlling the calculation path of the decay coefficient δ.

[0041] Step S4: Generate the attenuation coefficient δ based on the relaxation coefficient α and the historical tax declaration timestamp sequence T.

[0042] Step S5: Based on the three-state gating signal G and the attenuation coefficient δ, the credit multiplier η is generated by mapping and weighted fusion.

[0043] The credit limit multiplier η is used to multiply the basic credit limit B0 to obtain the final credit limit configuration result B. final .

[0044] It should be noted that the final quota allocation result B final As the final output of the adaptive credit limit calculation system, it is used to determine and configure the final credit limit available to the target object. With the basic credit limit B0 already determined, the credit limit multiplier η is the only factor determining how the final credit limit scales relative to the basic limit. The credit limit multiplier η represents the ratio or multiple relationship between the final credit limit configuration result and the basic credit limit B0. In other words, the credit limit multiplier η and the final credit limit configuration result B0... final All of these can serve as the basis for configuring the final credit limit that the target object can obtain.

[0045] In this embodiment, to avoid data misalignment during parallel acquisition in step S1, before data acquisition is initiated, the system generates a globally unique association identifier for the target object for this calculation. The association identifier is generated by combining the unified social credit code and the acquisition timestamp, and is injected into the acquisition instructions of the three acquisition channels. The data records returned by each channel carry this association identifier. Before the data enters their respective processing links, the association verifier performs pairing verification on the three data streams based on the association identifier. Only when the three data streams carry the same association identifier and their observation periods match are they allowed to enter the subsequent processing links. The tax credit rating label L, the historical tax declaration timestamp sequence T, and the basic financial data F are independent of each other on the acquisition channels and can be acquired in parallel. The tax credit rating label L is selected from five levels: A, B, M, C, and D. It is generated by the tax authorities based on a comprehensive assessment of tax compliance, tax registration management, and tax-related declaration information. It is a qualitative label in authoritative government data, representing the tax compliance level and creditworthiness of the target object. The order of superiority of each level is A > B > M > C > D, with A being the best and D being the worst. Historical tax return timestamp sequence T = {t1, t2, ..., t} n}. Where t i Let be the time of occurrence of the i-th tax declaration, and n be the total number of declarations within the observation period, i ∈ {1, 2, ..., n}, with the sequence arranged in ascending order of time. T originates from the timestamp record automatically generated for each declaration transaction in the tax administration system and cannot be tampered with once generated. Basic financial data F includes the target entity's total tax payment and sales revenue within the observation period, derived from the actual payment records in the tax administration system.

[0046] In this embodiment, in step S1, the tax credit rating label L is numerically input into the credit rating encoder and converted into binary digital code W according to a preset encoding rule. The binary digital code W monotonically changes with the credit rating, with a larger value for a higher rating, and the difference between adjacent rating values ​​is a constant (e.g., 1 or 5). The binary digital code is output to the parallel encoding data bus for subsequent symbol expansion and dual-channel parallel modulation. For example, taking an 8-bit binary digital code as an example, the A-level code is 00000101 (value 5), the B-level code is 00000100 (value 4), the M-level code is 00000011 (value 3), the C-level code is 00000010 (value 2), and the D-level code is 00000001 (value 1). This binary digital code satisfies monotonicity, with a larger value for a higher rating; and the difference between adjacent rating values ​​is 1, exhibiting equal spacing.

[0047] In this embodiment, in step S1, the relaxation coefficient α is obtained by looking up a table based on the tax credit rating label L. The relaxation coefficient α satisfies 1 ≥ α. A >α B >αM >0, where α A α B α M The relaxation coefficients α correspond to grades A, B, and M of the tax credit rating label L, respectively; grades C and D do not participate in the time-series decay calculation because they trigger a circuit breaker state in subsequent steps, therefore no corresponding α value needs to be defined. For example, α A It is 0.95, α B It is 0.85, α M The value is 0.70. The α obtained from the table lookup is written into the corresponding storage unit, which is then read by the gate switch in the subsequent step S4.

[0048] In this embodiment, in step S1, the basic financial data F is calculated into a basic credit limit B0 according to a preset benchmark calculation rule. The basic credit limit B0 can be obtained using an existing tax / financial credit model. The basic credit limit B0 is the base for credit limit multiplication, and in subsequent step S5, it is multiplied by the credit limit multiplier η to obtain the final credit limit configuration result B. final =B0×η. Among these, the tax credit rating label L, historical tax declaration timestamp sequence T, and basic financial data F associated with the target object are obtained based on the association identifier, avoiding data mismatch.

[0049] In this embodiment, in step S1, the binary digital code W (8 bits, for example, 00000101 for grade A) output by the credit rating encoder is sign-extended to obtain the signed two's complement W. signed For example, extending the binary code W to a 10-bit two's complement, padding the two highest bits with 0s, retains the same numerical value and still maintains a positive correlation with credit rating. signed The parallel encoded data bus outputs data that is electrically connected at the same connection point to the first input of the first full adder and the first input of the second full adder, respectively, so that the two full adders receive exactly the same W value within the same clock cycle. signed This constitutes a parallel distribution structure with one source and two feeders.

[0050] The first and second full adders incorporate controllable adders / subtractors with built-in mode control terminals. The second input terminal of the first full adder is electrically connected to a first storage unit, which stores the sensitivity tuning parameter Δ1. The second input terminal of the second full adder is electrically connected to a second storage unit, which stores the threshold control parameter Δ2. The carry input terminal of the first full adder receives the first mode control signal Mode1, and the carry input terminal of the second full adder receives the second mode control signal Mode2.

[0051] The output of the first full adder is electrically connected to the digital input of the first D / A converter, and the analog output of the first D / A converter is electrically connected to the first input of the AND gate, forming the first adjustment channel. In the first adjustment channel, when Mode1=0, the first full adder performs an addition operation, outputting W1=W signed +Δ1; When Mode1=1, the first full adder performs a subtraction operation, outputting W1=W signed -Δ1. The first D / A converter converts W1 into an analog voltage V1, which is output to the first input of the AND gate.

[0052] The output of the second full adder is electrically connected to the digital input of the second D / A converter, and the analog output of the second D / A converter is electrically connected to the second input of the AND gate, forming the second adjustment channel. In the second adjustment channel, when Mode2=0, the second full adder performs an addition operation, outputting W2=W signed +Δ2; When Mode2=1, the second full adder performs a subtraction operation, outputting W2=W signed -Δ2. The second D / A converter converts W2 into an analog voltage V2, which is output to the second input of the AND gate.

[0053] Where Δ1 and Δ2 are both positive numbers, and Δ2 > Δ1. Δ1 takes the value corresponding to 1 to 2 least significant bits (LSBs), making the modulation amplitude of the first adjustment channel smaller, used for sensitivity tuning of subtle differences within the acceptable grades (A / B / M grades, corresponding to values ​​5 / 4 / 3); Δ2 takes the value corresponding to 4 or more LSBs, making the modulation amplitude of the second adjustment channel larger, used to generate a significant voltage jump between the acceptable grades (values ​​3 / 4 / 5) and the unacceptable grades (values ​​1 / 2), achieving threshold anchoring. Since W signed It is a 10-bit two's complement, with a value range of 0 to 5, and will not overflow after adding or subtracting Δ.

[0054] The first and second adjustment channels share the same W. signed The input is different from the input, but the difference in values ​​of Δ1 and Δ2 causes the two channels to perform different functions: the first adjustment channel generates an evenly spaced voltage difference between acceptable levels, while the second adjustment channel generates a step voltage change at the acceptable / unacceptable boundary. Mode1 and Mode2 are independent of each other and can be selected to add or subtract, forming four modulation combinations, enabling the hardware to be reconfigurable without changing the circuit topology. The dual channels include the first adjustment channel and the second adjustment channel.

[0055] The output of the AND gate is connected to a tri-state encoder, together forming a gate control discrimination unit. The analog voltage V1 output from the first D / A converter and the analog voltage V2 output from the second D / A converter are respectively input to the two inputs of the AND gate. The AND gate and the tri-state encoder complete the tri-state decision in the subsequent step S2, and output a 2-bit digital logic signal G.

[0056] Optionally, in step S1, the second input terminal of the first full adder is electrically connected to the first storage unit via a first controllable two's complement inverting circuit, and the first storage unit stores the sensitivity tuning parameter Δ1; the second input terminal of the second full adder is electrically connected to the second storage unit via a second controllable two's complement inverting circuit, and the second storage unit stores the threshold control parameter Δ2. The control terminal of the first controllable two's complement inverting circuit and the carry input terminal of the first full adder both receive the first mode control signal Mode1; the control terminal of the second controllable two's complement inverting circuit and the carry input terminal of the second full adder both receive the second mode control signal Mode2.

[0057] When Mode1=0, the first controllable two's complement inverting circuit outputs Δ1 as is to the second input of the first full adder. The carry input of the first full adder is 0, and the first full adder performs an addition operation.

[0058] When Mode1=1, the first controllable two's complement inverting circuit inverts Δ1 bit by bit and outputs it to the second input of the first full adder. The carry input of the first full adder is 1, and the first full adder performs a subtraction operation. The second full adder works similarly, so it will not be described in detail.

[0059] In this embodiment, in step S2, following step S1, the analog voltage V1 output by the first D / A converter is connected to the first input terminal of the AND gate, and the analog voltage V2 output by the second D / A converter is connected to the second input terminal of the AND gate. The AND gate is a three-state analog domain decision gate, internally integrating a first high threshold comparator, a second high threshold comparator, a first low threshold comparator, and a second low threshold comparator. The positive input terminal of the first high threshold comparator is connected to V1, and the negative input terminal is connected to a preset high-level threshold V. IH The positive input of the second high threshold comparator is connected to V2, and the negative input is connected to V. IH The positive input of the first low-threshold comparator is connected to a preset low-level threshold V. IL The inverting input of the first low-threshold comparator is connected to V1; the non-inverting input of the second low-threshold comparator is connected to V1. IL The inverting input is connected to V2. Where V... IL <V IH The voltage range between the two [V] IL V IH [ ] represents the critical interval.

[0060] The decision logic for the AND gate is: when V1 < V IL Or V2 < VIL When V1 < V, it is determined to be in a circuit-breaking state, where V1 < V IL When V2 < V, the first low-threshold comparator outputs 1. IL When the circuit breaker condition is not met, but V1 ≤ V, the second low-threshold comparator outputs 1. IH Or V2≤V IH When V1 ≤ V, it is determined to be a critical state. Specifically, when the circuit breaker condition is not met, both the first low-threshold comparator and the second low-threshold comparator output 0; when V1 ≤ V IH When V2 ≤ V, the first high threshold comparator outputs 0. IH When V1 > V, the second high threshold comparator outputs 0. IH And V2 > V IH When V1 > V, it is determined to be in the release state, where V1 > V IH When V2 > V, the first high threshold comparator outputs 1. IH At that time, the second high-threshold comparator outputs 1. The above three states are generated by the analog logic core inside the AND gate based on the combination of the outputs of the four comparators, and the three states are mutually exclusive at the same time, covering all possible input combinations.

[0061] The output of the AND gate is connected to a three-state encoder. The three-state encoder encodes the circuit-breaking, critical, and release states output by the AND gate into two-bit digital logic signals: the circuit-breaking state corresponds to G=00, the critical state corresponds to G=01, and the release state corresponds to G=10. In this two-bit encoding scheme, the high-order bits of the release state are opposite to those of the circuit-breaking state, and the high-order bits of the critical state are the same as those of the circuit-breaking state, but the low-order bits are different, ensuring that the three states can be accurately distinguished in the digital domain. The three-state gating signal G includes the release state, circuit-breaking state, and critical state; among them, the release state triggers the timing decay engine to enter the normal mode, the critical state triggers the timing decay engine to enter the critical mode, and the circuit-breaking state does not start calculation.

[0062] In this embodiment, in step S2, when the three-state encoder outputs G as 01 (critical state), it synchronously outputs the gray zone quantization value D. gray D gray Generated by the critical interval quantization comparator group inside the AND gate, the critical interval [V] is... IL V IH Divide evenly into 2 N For each sub-interval (N≥2, where N is a natural number), detect the input voltage that causes the critical state to be established (either V1 or V2 falling into the critical interval; if both fall into the critical interval, take the one closer to V). IH Output the sub-interval number to which the (or) belongs as D. gray D gray =0 indicates that the input voltage is close to V. IL D gray =2 N-1 indicates that the input voltage is close to V. IH D gray Normalizable to the gray zone marker γ=D gray / (2 N -1), γ∈[0,1], used for parameter adjustment of the critical mode in subsequent step S5. When G is 00 or 10, D gray Invalid and will not be included in subsequent calculations.

[0063] The above threshold V IH V IL The parameter matching relationship is formed with the D / A converter reference voltage, sensitivity tuning parameter Δ1, and threshold control parameter Δ2 in step S1: In the default mode, the pass level (A / B / M level, corresponding to W) signed After being modulated by the second adjustment channel, V2 should be higher than V overall (values ​​5 / 4 / 3). IH For non-compliant grades (C / D level, corresponding to a value of 2 / 1), after modulation via the second adjustment channel, V2 should be lower than V overall. IL This ensures the correct execution of the three-state judgment.

[0064] In this embodiment, in step S3, following step S2, the 2-bit digital logic signal G output by the three-state encoder is connected to the control terminal of the three-state gate switch; when G=01, the gray zone flag γ (γ∈[0,1]) synchronously output by the three-state encoder is determined by D in step S2. gray (Normalized result) is connected to the auxiliary input terminal of the three-state gated switch. The data input terminal of the three-state gated switch is connected to the storage unit storing the relaxation coefficient, which has been written with the relaxation coefficient α corresponding to the tax credit rating label L in step S1.

[0065] The three-state gate switch performs conditional current shunting operations based on the value of G.

[0066] When G=00 (fuse-out state), the data output of the three-state gated switch is in a high-impedance state, blocking the transmission of the α value to the subsequent data bus. Simultaneously, a fuse-breaking interrupt command is sent to the timing decay engine via an independent interrupt control line, and a fuse-breaking notification signal is sent to the quota multiplier via a fuse-breaking notification. Upon receiving the fuse-breaking interrupt command, the timing decay engine does not initiate calculations; upon receiving the fuse-breaking notification signal, the quota multiplier directly outputs the preset default quota configuration result or terminates the current calculation process. Both the interrupt command and the fuse-breaking notification signal are transmitted through the control signal line, independent of the high-impedance state of the data output; the control path and data path are physically separated.

[0067] When G=10 (release state), the data output of the three-state gating switch switches from high impedance to on state, reads α from the storage cell containing the relaxation coefficient and drives it to the subsequent data bus, transmitting it to the data input of the timing decay engine; simultaneously, it sends a normal mode start command to the timing decay engine. The gray zone flag γ is not transmitted in the release state, and the timing decay engine performs calculations using normal decay parameters.

[0068] When G=01 (critical state), the data output of the three-state gated switch switches from high impedance to on state, reads α and drives it to the subsequent data bus; at the same time, it reads the gray zone flag γ and transmits it to the timing decay engine through the auxiliary data path; and sends a critical mode start command to the timing decay engine. In critical mode, the timing decay engine adjusts the calculation parameters according to γ ​​and performs high-sensitivity decay calculation.

[0069] The conduction state of the data output terminal of the three-state gated switch is uniquely determined by G. When G=00, the data output terminal is in a high-impedance state, electrically isolated from the subsequent data bus. When the data output terminal of the three-state gated switch is in a high-impedance state, the subsequent data bus is connected to the power supply terminal through a pull-up resistor and is maintained at an idle high level. After the timing decay engine detects this idle high level, it confirms that no valid data has arrived. After the timing decay engine detects the idle level, it confirms that no valid data has arrived; at the same time, the interrupt control line ensures that the timing decay engine does not start. The high-impedance state is not logic 0, but rather the output terminal presents extremely high impedance, achieving electrical isolation at the physical layer. When G=10 or G=01, the data output terminal switches to the conduction state, and α is driven to the data bus. The difference between the two states lies in whether γ and the start command type are transmitted simultaneously, thereby mapping the hardware layer decision result to the differentiated selection of the software layer calculation mode.

[0070] The gray zone indicator γ is transmitted synchronously with α when G=01, providing information on the degree of critical deviation for the timing decay engine: the closer γ is to 1, the closer the input voltage leading to the critical state is to V. IH (The closer it is to the qualified level); the closer γ is to 0, the closer it is to V. IL (The closer it gets to being unqualified), the more continuously the attenuation calculation in the critical mode can be adjusted according to the degree of deviation.

[0071] The relaxation coefficient α is written to the storage unit after the credit rating tag is acquired in step S1, and is not read until the conduction signal is received in step S4. The storage unit maintains the stability of α through the output holding circuit, so that the three-state gated switch can complete the reading and driving of α within the same clock cycle at the moment of conduction, without the need for additional table lookup delay. The gray zone flag γ is output synchronously with G, and the three-state gated switch completes the reading and transmission of γ within the same clock cycle, ensuring the real-time performance of critical state processing.

[0072] In this embodiment, in step S4, following step S3, the time-series decay engine starts calculating the decay coefficient δ when it receives a normal mode start command or a critical mode start command and the data input terminal receives the relaxation coefficient α; if it is a critical mode, it synchronously receives the gray zone flag γ. The time-series decay engine reads the historical tax declaration timestamp sequence T={t1, t2, ..., t...} obtained in step S1. n}, where the time-series decay engine is a software-layer computation module that performs gated-constraint time-series decay calculations.

[0073] The timing decay engine first performs interruption mode identification: it calculates the time interval ΔT between adjacent reporting times. i =t i+1 -t i Each one is compared with the preset interruption judgment threshold T threshold Comparison; when ΔT i >T threshold When an interruption occurs between the i-th and (i+1)-th applications, the start time t of this interruption is recorded. i End time t i+1 and interval length ΔT i This forms an interrupt event set E = {e1, e2, ..., e}. m}, where m is the total number of interruptions. Periodic identification is performed on the interruption event set E: using the year as the observation period, the start time of each interruption event is mapped to its relative position within the year; if within two or more consecutive observation periods, the same relative position is nearby (the deviation does not exceed the preset period tolerance T). tol If all interrupt events occur, they are classified into a periodic interrupt group; other interrupt events that do not repeat across periods are classified as sudden interrupts. A periodic penalty weight ω is assigned to each interrupt event in the periodic interrupt group. periodic Assign a sudden penalty weight ω to sudden interruption events. abrupt , satisfying ω abrupt >ω periodic >0; Each interrupt event receives a corresponding interrupt penalty weight ω. i This forms a weighted interrupt record set {(ΔT)}. i ,ω i )}.

[0074] Obtain the basic attenuation rate parameter β0, which is a preset fixed value. Determine the attenuation parameter based on the startup command type: when it is a normal mode startup command (corresponding to G=10), β=β0, ω i Keep the above classification assignments unchanged; when it is a critical mode start command (corresponding to G=01), calculate the amplification factor λ=2-γ according to the gray zone indicator γ, then β=β0×λ=β0×(2-γ), ω i '=ωi ×λ=ω i ×(2-γ;ω i ' represents the interruption penalty weight for the critical mode, and β is the decay rate parameter for the current mode.

[0075] Calculate the attenuation coefficient δ: .

[0076] Where α is the slack coefficient obtained by looking up the table based on the tax credit rating label L in step S1, satisfying 1≥α A >α B >α M >0, α A α B α M The slack coefficients α and ω correspond to the A, B, and M grades of the tax credit rating label L, respectively. i The interruption penalty weight in the current mode (ω for normal mode) i Critical mode uses ω i '); ΔT i T is the interval length of the i-th interruption; obs The total length of the observation period is defined as the time from the first report time t1 to the most recent report time t. n The time span, i.e., T obs =t n -t1, if n=1 (only one application), then Σ(ω i ×ΔT i =0, the continuity reference value is 1; when n≥2, the attenuation coefficient δ is calculated according to the above formula; when n<2, the preset attenuation coefficient is directly taken, and n is a positive integer; The positive part function, where the + sign indicates positive value operation, ensures the non-negativity of the reporting continuity benchmark value. When the value is greater than 0, its value remains unchanged; when When the value is less than or equal to 0, its value is 0; β is the decay rate parameter in the current mode; t elapsed The most recent application time t n The length of time since the current moment; This is the time decay factor. The calculated decay coefficient δ is output to step S5 for the calculation of the credit multiplier η.

[0077] In this embodiment, in step S5, following steps S2 and S4, the 2-bit digital logic signal G output by the tri-state encoder and the attenuation coefficient δ output by the timing attenuation engine are input into the multiplier generator.

[0078] When G=00 (circuit breaker state), subsequent fusion calculations are not performed, and the final quota configuration result B is directly output. finalThe result is set to 0 or the preset default limit configuration, and the calculation process is terminated.

[0079] When G=10 (release state) or G=01 (critical state), perform heterogeneous signal normalization fusion calculation: Input G into the first mapper, which is a discrete mapping circuit, and map G to the potential energy base value P. G When G=10, P G =1; when G=01, P G =0.5.

[0080] The attenuation coefficient δ is input into the second mapper, which is a linear normalization circuit that maps δ to the potential energy fluctuation value P. D The calculation formula is: P D =δ / α A .

[0081] Where, α A The relaxation coefficient corresponding to level A in step S1 is the theoretical maximum value of the decay coefficient δ (δ = α when there is no interruption and the time decay factor is 1). A When δ > α A At that time, P D Cut off to 1; when δ < 0, P D The cutoff value is 0.

[0082] P G With P D Input the multiplier generator to generate the credit limit multiplier η using the following formula: η=ReLU(w1×P G +w2×P D ).

[0083] Wherein, ReLU is a nonlinear activation function, and w1 and w2 are preset fusion weights, satisfying w1 > 2w2 > 0 and w1 + w2 ≤ 1. This constraint guarantees that: in the release state, η ∈ [w1, w1 + w2]; in the critical state, η ∈ [0.5w1, 0.5w1 + w2]; since w1 > 2w2, 0.5w1 + w2 < w1, so the credit multiplier in the release state is always higher than that in the critical state; and η ≤ 1, ensuring that the final credit limit does not exceed the basic credit limit.

[0084] Input η into the credit limit multiplier and multiply it by the basic credit limit B0 calculated in step S1 to obtain the final credit limit configuration result: B final =B0×η.

[0085] The first mapper maps the hardware decision's release state and critical state to equidistant potential base values ​​of 1 and 0.5, respectively, allowing the decision result to directly participate in the quota multiplier calculation as a benchmark anchor point; the circuit breaker state is blocked through a fast exit, eliminating the possibility of a positive quota arising from the circuit breaker state in the process. The second mapper normalizes the software layer continuous attenuation coefficient δ to P in the interval [0,1]. D A larger δ indicates better operational stability, P D The higher the normalized baseline α, the better. A Ensure P D In normal mode, the maximum value is 1. In critical mode, δ decreases due to the parameter amplification in step S4, and P... D The corresponding reduction achieves additional compression of the credit multiplier in the critical state.

[0086] The multiplier generator fuses the two signals by weighted summation followed by activation using the ReLU nonlinear activation function. Weight constraints w1 > 2w2 ensure that the decision base value dominates the credit multiplier, and the output intervals of the approval and critical states do not overlap; w1 + w2 ≤ 1 ensures that η ≤ 1, guaranteeing that the final credit limit does not exceed the basic credit limit. ReLU maintains linearity in the positive interval, facilitating hardware implementation, and outputs 0 when the input is non-positive.

[0087] Combination Figures 2 to 3 As shown, this application also provides an adaptive credit limit calculation system that integrates tax credit, including: a first module and a second module.

[0088] The first module stores a computer program that is configured to execute the aforementioned adaptive calculation method for credit limits based on integrated tax credit when running.

[0089] The second module is configured to execute the aforementioned adaptive calculation method for credit limits based on integrated tax credit through the computer program.

[0090] The second module includes: a credit rating encoder, a parallel encoded data bus, a first full adder, a second full adder, a first storage unit, a second storage unit, a first D / A converter, a second D / A converter, an AND gate, a tri-state encoder, a relaxation coefficient storage unit, a tri-state gating switch, a timing decay engine, a first mapper, a second mapper, a multiplier generator, and a credit limit multiplier.

[0091] The output of the credit rating encoder is connected to a parallel encoding data bus, which is used to encode the tax credit rating label into a binary digital code that changes monotonically with the rating. The same connection point of the parallel encoding data bus is electrically connected to the first input of the first full adder and the first input of the second full adder, so that the two full adders receive the same encoded signal.

[0092] The second input terminal of the first full adder is electrically connected to the first storage unit, which stores the sensitivity tuning parameter Δ1; the output terminal of the first full adder is electrically connected to the digital input terminal of the first D / A converter, and the analog output terminal of the first D / A converter is electrically connected to the first input terminal of the AND gate, thus forming the first adjustment channel.

[0093] The second input terminal of the second full adder is electrically connected to the second storage unit, which stores the threshold control parameter Δ2; the output terminal of the second full adder is electrically connected to the digital input terminal of the second D / A converter, and the analog output terminal of the second D / A converter is electrically connected to the second input terminal of the AND gate, forming the second adjustment channel; wherein, the first D / A converter and the second D / A converter are digital-to-analog converters, and the dual channels include the first adjustment channel and the second adjustment channel.

[0094] The output of the AND gate is connected to the input of the tri-state encoder. The tri-state encoder encodes the analog domain decision result into a 2-bit digital logic signal G and outputs a gray zone marker γ in the critical state. The AND gate and the tri-state encoder together constitute the gate control discrimination unit.

[0095] The first output terminal (G output terminal) of the tri-state encoder is connected to the control terminal of the tri-state gate switch, and the second output terminal (γ output terminal) is connected to the auxiliary input terminal of the tri-state gate switch. The data input terminal of the tri-state gate switch is connected to the relaxation coefficient storage unit, which stores the relaxation coefficient α obtained by looking up the table based on the tax credit rating label. The data output terminal of the tri-state gate switch is connected to the data input terminal of the time-series decay engine, and the tri-state gate switch is also connected to the control terminal of the time-series decay engine through an independent control line. The time-series decay engine stores the historical tax declaration timestamp sequence T, and its output terminal is connected to the input terminal of the second mapper.

[0096] The first output of the three-state encoder is also connected to the input of the first mapper, and the output of the first mapper is connected to the first input of the multiplier generator; the output of the second mapper is connected to the second input of the multiplier generator; the output of the multiplier generator is connected to the first input of the credit limit multiplier, the second input of the credit limit multiplier receives the basic credit limit, and the output of the credit limit multiplier outputs the final credit limit configuration result.

[0097] The storage unit includes a first storage unit, a second storage unit, and a relaxation coefficient storage unit, and the storage unit adopts a register.

[0098] Optionally, in some embodiments of this application, combined with Figure 3As shown, in the gated discrimination unit, a first capacitor is electrically connected between the analog output terminal of the first D / A converter and the first input terminal of the AND gate, and a second capacitor is electrically connected between the analog output terminal of the second D / A converter and the second input terminal of the AND gate; the capacitance of the second capacitor is greater than the capacitance of the first capacitor, thereby realizing low-pass filtering of the physical layer and smoothing the impact of credit abrupt changes.

[0099] The above embodiments are only used to illustrate this application and are not intended to limit the technical solutions described in this application. Although this specification has described this application in detail with reference to the above embodiments, this application is not limited to the specific implementation methods described above. Therefore, any modifications or equivalent substitutions to this application, and all technical solutions and improvements that do not depart from the spirit and scope of the invention, are covered within the scope of the claims of this application.

Claims

1. A method for adaptively calculating credit limits that integrates tax credit, characterized in that, It includes the following steps: Step S1: Generate a relaxation coefficient α that matches the tax credit rating label L. After the tax credit rating label L is encoded, it is superimposed with sensitivity tuning parameter Δ1 and threshold control parameter Δ2 for parallel modulation, and a first analog voltage V1 for sensitivity tuning and a second analog voltage V2 for threshold anchoring are generated. Step S2: Both the first analog voltage V1 and the second analog voltage V2 are at a preset high-level threshold V. IH A voltage comparison is performed, and both the first analog voltage V1 and the second analog voltage V2 are equal to a preset low-level threshold V. IL A voltage comparison is performed to generate a three-state gating signal G, and a gray zone marker γ is output in the critical state. Step S3: Based on the three-state gating signal G, conditional splitting is performed on the relaxation coefficient α and the gray zone marker γ, thereby controlling the calculation path of the attenuation coefficient δ; Step S4: Generate the attenuation coefficient δ based on the relaxation coefficient α and the historical tax declaration timestamp sequence T; Step S5: Based on the three-state gating signal G and the attenuation coefficient δ, generate the quota multiplier η through mapping and weighted fusion.

2. The adaptive calculation method for credit limits integrating tax credit as described in claim 1, characterized in that, In step S1, the relaxation coefficient α satisfies 1 ≥ α A >α B >α M >0, where α A α B α M The relaxation coefficient α corresponds to the A, B, and M grades of the tax credit rating label L, respectively.

3. The adaptive calculation method for credit limits integrating tax credit as described in claim 1, characterized in that, In step S1, both the sensitivity tuning parameter Δ1 and the threshold control parameter Δ2 are positive numbers, and the threshold control parameter Δ2 is greater than the sensitivity tuning parameter Δ1.

4. The adaptive calculation method for credit limits integrating tax credit as described in claim 1, characterized in that, In step S2, when V1 < V IL Or V2 < V IL When the circuit breaker condition is not met, but V1≤V, it is determined to be in a circuit-breaker state; when the circuit-breaker condition is not met, but V1≤V IH Or V2≤V IH When V1 > V, it is determined to be a critical state; IH And V2 > V IH When the time is right, it is determined to be in a released state.

5. The adaptive calculation method for credit limits integrating tax credit as described in claim 4, characterized in that, In step S2, when the tri-state gating signal G is 0 or 1, the gray zone quantization value D is output synchronously. gray The critical interval [V] IL V IH Divide evenly into 2 N Each sub-interval, the gray zone quantization value D gray =0 indicates that the input voltage is close to V. IL The gray zone quantization value D gray =2 N -1 indicates that the input voltage is close to V. IH The gray zone quantization value D gray Normalized to the gray zone marker γ=D gray / (2 N -1), γ∈[0,1], where N≥2, and N is a natural number.

6. The adaptive calculation method for credit limits integrating tax credit as described in claim 5, characterized in that, In step S2, the release state is encoded as 10, the fuse-breaking state as 00, and the critical state as 01; when the critical state is output, the gray zone flag γ is output, and the gray zone flag γ represents the input voltage in the critical range [V]. IL V IH The quantization position within ], the critical interval [V] IL V IH [V] is the preset low-level threshold. IL With the preset high-level threshold V IH The voltage range between.

7. The adaptive calculation method for credit limits integrating tax credit as described in claim 5, characterized in that, In step S3, when the three-state gating signal is in a critical state, the gray zone flag γ is associated with the relaxation coefficient α, and a critical mode start command is generated.

8. The adaptive calculation method for credit limits integrating tax credit as described in claim 6, characterized in that, In step S4, when the tri-state gating signal G is 10, β = β0, where β0 is the basic attenuation rate parameter and β is the attenuation rate parameter in the current mode.

9. A method for adaptively calculating credit limits based on tax credit according to claim 4 or 8, characterized in that, In step S4, when in normal mode, the three-state gating signal G is in the release state, and the attenuation coefficient δ is calculated according to the following formula: ； Where α is the slack coefficient obtained from the table based on the tax credit rating label L, satisfying 1≥α A >α B >α M >0, α A α B α M The relaxation coefficients α and ω correspond to grades A, B, and M of the tax credit rating label L, respectively. i The interruption penalty weight in the current mode; ΔT i T is the interval length of the i-th interruption; obs The total length of the observation period is defined as the time from the first report time t1 to the most recent report time t. n The time span, n≥2, where n is a positive integer; The positive part function is defined by the '+' operator, which indicates the operation of taking positive values ​​to ensure the non-negativity of the reporting continuity benchmark value; m is the total number of interruptions; β is the decay rate parameter in the current mode; t elapsed The most recent application time t n The length of time since the current moment; This is the time decay factor.

10. A credit limit adaptive calculation system integrating tax credit, characterized in that, include: Module 1 and Module 2 The first module stores a computer program, which is configured to execute, at runtime, a credit limit adaptive calculation method integrating tax credit as described in any one of claims 1-9; The second module is configured to execute, through the computer program, an adaptive calculation method for credit limits that integrates tax credit as described in any one of claims 1-9.

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