Chip edge collapse detection method, electronic device and readable storage medium

Abstract

The application relates to the technical field of semiconductor detection, and discloses a chip edge collapse detection method, an electronic device and a readable storage medium. In the application, a segmentation model that converges is used to perform region segmentation on a chip image obtained, so as to obtain a detection region image corresponding to a target detection region; then, a target edge frame in the detection region image and a polygon point set corresponding to the target edge frame are determined, the shape feature or / and the color feature of the detection region is determined through the polygon point set, and whether the current detection region meets a first requirement or / and a second requirement is determined based on the shape feature or / and the color feature; when any of the requirements is not met, it is determined that the current chip has an edge collapse anomaly. Compared with the prior art, the application combines a neural network and an image processing algorithm, thereby ensuring detection accuracy, improving detection efficiency and reducing the cost of detection scheme deployment.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, specifically a chip packaging testing method, an electronic device, and a readable storage medium. Background Technology

[0002] Chips are widely used in various high-tech devices, and their performance and quality play a crucial role in the stability and lifespan of the entire system. With the continuous miniaturization of chip manufacturing processes and the increasing complexity of packaging technologies, the physical integrity of chips is particularly important, especially the edge chipping problem that is prone to occur in the chip's edge areas. Edge chipping directly affects packaging quality, signal transmission, and the chip's inherent reliability. Therefore, how to efficiently and accurately detect chip edge chipping is one of the important issues in the current chip testing field.

[0003] With the development of machine learning technology, especially the application of convolutional neural networks (CNNs) in image recognition, some studies have attempted to apply machine learning techniques to chip edge detection. These methods extract edge features and classify them by constructing and training a large amount of edge-damped sample data. However, machine learning methods require a large amount of labeled data, which is difficult to acquire, and places high demands on computing resources. In addition, the algorithm training time is long, and the universality of the model varies among different types of chips, so practical applications still face certain challenges. Summary of the Invention

[0004] To address the technical problems in the prior art, this application provides a chip edge collapse detection method, an electronic device, and a readable storage medium. It combines convolutional neural networks with image processing methods and provides an efficient and stable edge collapse detection method based on the distribution characteristics of edge collapse features. This method improves detection efficiency while ensuring detection accuracy and reduces the cost of deploying the detection scheme.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: Firstly, a chip edge-collapse detection method is provided. The method includes: performing region segmentation on an acquired chip image to be detected based on a trained convergent segmentation model to obtain a detection region image corresponding to the target region; the segmentation model includes an encoder and a decoder, the encoder is provided with multiple feature extraction modules for acquiring feature maps of the chip image to be detected, the decoder generates a semantic segmentation mask based on the feature maps, and segments the chip image to be detected based on the semantic segmentation mask, the detection region image being a mask image; performing contour extraction on the detection region image to obtain a set of contour points corresponding to the detection region image, and filtering the contour point set based on an area threshold to determine a target contour and the corresponding target contour point set; constructing an initial bounding box and initial vertices corresponding to the initial bounding box based on the target contour point set, fitting the initial bounding box to obtain a target bounding box and a polygon point set corresponding to the target bounding box, and determining whether the angles of multiple vertices in the polygon point set meet a first requirement.

[0006] In some specific implementations, the method further includes: determining the normal vectors corresponding to the multiple target bounding boxes, determining the spatial distribution of the detection area based on the normal vectors, determining a first type of region and a second type of region, determining the real-time pixel distribution state of the first type of region and the second type of region, and determining whether the detection area satisfies a second condition based on the real-time pixel distribution state; the first type of region and the second type of region are spatially adjacent.

[0007] In some specific implementations, the method further includes determining whether the number of multiple vertices in the polygon point set meets the requirements, and when the requirements are met, determining whether the angles of the multiple vertices in the polygon point set meet the first requirement; specifically, it includes: obtaining multiple corner points in the polygon point set and the adjacent points corresponding to the corner points, and determining whether the detection area meets the first requirement based on the angle between the corner points and the adjacent points.

[0008] In some specific implementations, the contour point set is filtered based on an area threshold, including: removing contour point sets smaller than a preset area threshold and retaining only contour point sets that meet the preset area threshold.

[0009] In some specific implementations, constructing an initial bounding box and the initial vertices corresponding to the initial bounding box based on the target contour point set includes: extracting the minimum convex hull and the complete convex hull vertex sequence corresponding to the minimum convex hull based on the target contour point set; constructing the initial contour based on the minimum convex hull; and constructing the initial bounding box based on multiple convex hull vertices.

[0010] In some specific implementations, fitting the initial bounding box to obtain the target bounding box and the target vertex corresponding to the target bounding box includes: determining the updated contour point set corresponding to the initial contour, constructing a preset bounding box using the start point and end point of the updated contour point set, determining the vertical distance of any point in the updated contour point set relative to the preset bounding box, determining the relationship between the vertical distance and a preset distance threshold, and filtering the points in the updated contour point set based on this relationship to obtain the target vertex and the target bounding box.

[0011] In some specific implementations, determining whether the detection area meets the first requirement based on the angle between the corner point and its adjacent points includes: constructing a first vector and a second vector corresponding to the corner point and the two adjacent points, and determining the angle between the first vector and the second vector. When the angle between the first vector and the second vector meets a preset angle requirement, the detection area meets the first requirement.

[0012] In some specific implementations, determining whether the detection area meets the second condition based on the real-time pixel distribution state includes: determining whether the real-time pixel distribution in the first type region or the second type region of the detection area meets a preset pixel distribution condition; when either type region does not meet the preset pixel distribution condition, it is determined that the detection area does not meet the second condition; the preset pixel distribution condition includes a first condition and a second condition, the first condition being set for the first type region and the second condition being set for the second type region.

[0013] In a second aspect, a computer device is provided, the computer device including a processor and a memory coupled to the processor, the memory storing program instructions, which, when executed by the processor, cause the processor to perform the steps of the chip edge detection method as described above.

[0014] Thirdly, a computer-readable storage medium is provided, the computer-readable storage medium storing computer-executable instructions, which, when called and executed by a processor, cause the processor to implement the chip edge detection method described in any of the above claims.

[0015] The embodiments of the present invention bring the following beneficial effects: In the technical solution provided in this application embodiment, the acquired image of the chip to be detected is segmented into regions based on a trained and convergent segmentation model to obtain a detection region image corresponding to the target region. Then, the target bounding box and the polygon point set corresponding to the target bounding box in the detection region image are determined. The morphological features and / or color features of the detection region are then determined using the polygon point set. Based on the morphological features and / or color features, it is determined whether the current detection region meets the first requirement and / or the second requirement. If any of the above requirements are not met, it is determined that the current chip has an edge-collapsing anomaly. Compared with the prior art, this application embodiment combines neural networks with image processing algorithms, improving detection efficiency while ensuring detection accuracy and reducing the cost of deploying the detection scheme.

[0016] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0017] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] The methods, systems, and / or procedures shown in the accompanying drawings will be further described with reference to exemplary embodiments. These exemplary embodiments will be described in detail with reference to the drawings. These exemplary embodiments are non-limiting exemplary embodiments, wherein example figures represent similar mechanisms in the various views of the drawings.

[0020] Figure 1 This is a schematic diagram of a chip edge damage detection method.

[0021] Figure 2 This is a schematic diagram of the detection area in the chip.

[0022] Figure 3 This is a schematic diagram of the segmentation model architecture.

[0023] Figure 4 This is a schematic diagram of another chip edge damage detection method.

[0024] Figure 5 This is a schematic diagram of the detection region segmentation results.

[0025] Figure 6 This is a schematic diagram of a chip edge damage detection device.

[0026] Figure 7 This is a schematic diagram of the structure of a computer device.

[0027] Figure 8 This is a schematic diagram of a readable medium structure. Detailed Implementation

[0028] To better understand the above technical solutions, the technical solutions of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this application and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0029] In the detailed description below, numerous specific details are illustrated with examples to provide a comprehensive understanding of the relevant guidance. However, it will be apparent to those skilled in the art that this application can be practiced without these details. In other instances, well-known methods, procedures, systems, components, and / or circuits have been described at a relatively high level without detail to avoid unnecessarily obscuring aspects of this application.

[0030] This application uses flowcharts to illustrate the execution process performed by a system according to embodiments of this application. It should be clearly understood that the execution processes in the flowcharts may not be executed sequentially. Instead, these execution processes may be executed in reverse order or simultaneously. Additionally, at least one other execution process may be added to the flowchart. One or more execution processes may be deleted from the flowchart.

[0031] This application provides a detection method for chip defect detection, specifically for chip edge chipping detection. In this embodiment, the chip refers to a system-on-a-chip (SoC) packaged chip. Edge chipping refers to damage, cracks, and other irregularities at the chip's edge. These defects mainly occur on the wafer surface during the dicing process, mostly due to dicing, grinding, and other processes. These defects directly affect product quality and therefore require rigorous inspection. Because wafers are precision products, their surface defects are extremely small and difficult to detect with the human eye, making them challenging to identify.

[0032] See Figure 1 The chip edge chipping detection method provided in this application includes the following steps: Step S11. Perform region segmentation on the acquired chip image to be detected based on the trained and convergent segmentation model to obtain the detection region image corresponding to the target region.

[0033] In this embodiment, the image acquisition device can acquire the chip image corresponding to the chip to be tested, and the chip image can be found in [reference needed]. Figure 2 As shown, this chip image contains two regions: chip region 21 and cutting region 22. The chip region refers to the main area where functional devices are configured, which is the target area in this embodiment. The cutting region refers to the part that is cut off.

[0034] In this embodiment, edge chipping refers to damage and cracks at the edge of the chip area, which is determined by analyzing the distribution of edge image features in the target area.

[0035] Specifically, in this embodiment, image features include shape features and color features. Shape features refer to whether the shape of the target region is approximately a quadrilateral, and whether the four corners of the target region are close to right angles. Color features refer to whether the color ratio of the inner and outer sides corresponding to the edges of the target region meets a threshold requirement. This embodiment combines these two judgment conditions, reducing the inaccuracy of judgment results caused by a single judgment factor. By combining the characteristics of shape and color features, the two features can mutually verify each other during judgment, thereby improving overall detection accuracy.

[0036] Furthermore, in this embodiment, the acquired chip image first needs to be segmented to extract the detection area from the chip image, and then the edge of the detection area is determined based on the image corresponding to the detection area.

[0037] Specifically, in this embodiment, the segmentation of the detection region is achieved using a segmentation model that has been trained to convergence.

[0038] For the segmentation model structure in this embodiment, please refer to [reference needed]. Figure 3 As shown, SegFormer is used as the backbone network. SegFormer utilizes the Transformer architecture to capture global context information while maintaining computational efficiency. The segmentation model processes the chip image by first cutting it into multiple image blocks of the target size. Then, each image block is downsampled to the target size to reduce computational load; typically, the target size is 512×512. These downsampled image blocks are input into the trained SegFormer, and the model outputs predicted masks for the corresponding regions, resulting in multiple local predicted masks. Each local predicted mask is then upsampled and enlarged to its original size to restore the spatial resolution of the original image. Finally, the restored local predicted masks are concatenated according to their spatial positions to obtain the final segmentation result.

[0039] Specifically, the segmentation model includes an encoder and a decoder. The encoder performs feature extraction and upsampling, while the decoder completes the mapping from input to output. The encoder is responsible for performing multi-layer feature extraction and downsampling on the input downsampled image patches. The core modules include an overlapping image patch embedding module and multiple feature extraction modules. The overlapping image patch embedding module performs overlapping block embedding on multiple input downsampled image patches to generate an initial feature map. Then, the initial feature map is sequentially extracted by multiple feature extraction modules to output the final feature map.

[0040] In this invention, there are four feature extraction modules, each built based on the Transformer architecture, including an efficient self-attention unit, a hybrid feedforward network, and an overlapping block merging unit. After processing by the first feature extraction module, the resolution of the feature map is halved and the number of channels increases. After processing by the second feature extraction module, the resolution is halved again and the number of channels increases. After processing by the third feature extraction module, the resolution is halved again and the number of channels increases once more. By progressively extracting high-level features through multiple feature extraction modules and utilizing overlapping block merging to reduce the feature map size and expand the channel dimension, rich information is preserved for subsequent decoding.

[0041] Furthermore, the overlapping block merging unit connects feature maps at different resolutions to ensure local consistency between adjacent image blocks and avoid the loss of information and details from the resolution feature maps. The specific implementation of the overlapping block merging unit can be represented by the following formula: In this model, Fhigh represents the high-resolution feature map, Flow represents the low-resolution feature map, and Fmerged represents the merged feature map. The merged operation is achieved by controlling the size, padding, and stride of the convolutional kernel. First, the high-resolution feature map is downsampled to generate a low-resolution feature map. This downsampling process can be implemented using convolutional layers. During downsampling, the kernel size, padding, and stride are adjusted to create overlapping regions between adjacent image patches. Introducing these overlapping regions helps retain more detail, thus improving model performance. By introducing overlapping regions between feature maps of different resolutions, this technique effectively preserves more detail, especially at image edges and textures. These details are crucial for tasks such as image classification, object detection, and semantic segmentation because they significantly enhance the model's understanding and recognition of image content, especially when processing high-resolution images, enabling the model to more accurately capture subtle features.

[0042] The decoder consists of a multi-layer perceptron, which can efficiently utilize the multi-scale and multi-level semantic information extracted by the encoder from the input image. In the specific operation, the feature map output by the encoder is processed at different resolutions, and then merged after linear transformation and upsampling. Finally, a linear transformation and Softmax operation are performed on the channel dimension to generate a high-precision semantic segmentation mask at the end of the network, thereby achieving the segmentation of the above-mentioned detection regions in the chip image.

[0043] Step S12. Extract contours from the detection region images to obtain a set of contour points corresponding to the detection region images, and filter the contour point sets based on an area threshold to determine the target contour and the corresponding target contour point set.

[0044] In this embodiment, the contour extraction can be determined based on the OpenCV instruction function findContours(). The contours obtained through this process will include noisy contours, which need to be processed.

[0045] In terms of area, the feature distribution of noisy contours and non-noisy contours shows that non-noisy contours are generally larger than noisy contours. Therefore, in this embodiment, area is used as the filtering criterion, and contours with an area greater than a specific value are selected as target contours. Specifically, in this embodiment, only regions occupying ≥10% of the image area are retained.

[0046] Step S13. Construct an initial bounding box and the initial vertices corresponding to the initial bounding box based on the target contour point set, and fit the initial bounding box to obtain the target bounding box and the polygon point set corresponding to the target bounding box, and determine whether the angles of multiple vertices in the polygon point set meet the first requirement.

[0047] The real-time state of the detection area refers to whether the shape of the detection area is approximately quadrilateral, and whether the four corners of each detection area are close to right angles. Therefore, it is necessary to determine the border, vertices, and angles of the vertices of each detection area in the target contour.

[0048] In existing technologies, a polygon fitting method is typically used to approximate the target contour by using the set of contour points. However, it is worth noting that because the target contour point set contains a large number of contour points, directly using the target contour point set as the input data for fitting would result in high processing costs.

[0049] Therefore, to solve this technical problem, this embodiment first performs minimum convex hull processing on the target contour to obtain a complete convex hull vertex sequence for the target contour. Then, based on the convex hull vertex sequence, multiple initial bounding boxes and the corresponding polygon point sets are constructed. This process allows for polygon representation based on the convex hull, simplifying the convex hull vertices to a small number of polygon vertices, smoothing out minor bumps and depressions while preserving the overall shape, thus reducing the high cost associated with directly processing the contour point set.

[0050] In this embodiment, the extraction of the minimum convex hull is achieved by sorting all target contour points in ascending order of their x-coordinates. If all target contour points have the same x-coordinate, they are then sorted in ascending order of their y-coordinates. The process proceeds from front to back, using a stack to construct upper and lower chains. Specifically, after adding each point, if the last two edges of the stack do not satisfy the left turn condition, the stack vertex is popped until convexity is maintained. The upper and lower chains are then merged to remove duplicate starting points, resulting in a complete sequence of convex hull vertices.

[0051] The complete convex hull vertex sequence obtained through the above processing is then used to retain key vertices that can represent the overall shape features by iteratively removing points whose deviation from the initial polyline is less than a threshold, based on the Glass-Puk algorithm.

[0052] Specifically, in the complete convex hull vertex sequence, the first two points are used to construct an initial polyline segment. The maximum vertical distance from all intermediate points to this polyline segment is calculated to determine the point with the largest distance. If the maximum distance is greater than a preset threshold, the point with the largest distance is inserted into the polyline segment, and the above process is repeated on the two end subsequences. If it is less than the preset threshold, all intermediate points are discarded and only the current polyline segment is retained, thus obtaining multiple edges corresponding to the contour of this detection region, as well as the target vertex.

[0053] It's worth noting that this process also requires determining whether the number of target vertices meets the requirement of four. If the number of target vertices is four, it can be understood that the target vertices can form a standard quadrilateral, and the polygon fitting result meets the requirement. Based on this, the angles corresponding to multiple target vertices are then determined to ensure they meet the first requirement. If the number of target vertices is not four, the vertices need to be sorted, and then the angles of the sorted vertices need to be determined to ensure they meet the first requirement.

[0054] The first requirement refers to whether the shape of the detection area is approximately quadrilateral and whether the four corners of each detection area are close to right angles. It can be determined that for a chip without edge chipping, its shape should conform to the product shape characteristics requirements. Under completely standard conditions, the detection area of ​​a chip should be quadrilateral with right angles between its four vertices. Therefore, the judgment of whether the current detection area meets the requirements can be based on the degree of deviation between the included angles of the vertices and right angles. When the included angles of the vertices of the detection area are close to right angles, or the deviation from a right angle is less than a preset angle change threshold, it indicates that the shape characteristics of the current detection area are normal and there is no edge chipping abnormality. However, if the angles of the target vertices do not meet the first requirement, it indicates that the edge distribution of the detection area does not conform to normal conditions.

[0055] In this embodiment, determining the angle of a vertex first involves identifying multiple corner points within a polygon point set. Then, based on these corner points, their corresponding neighboring points are determined, and a first vector and a second vector are constructed corresponding to the corner point and its two neighboring points, respectively. The angle between the first and second vectors is then determined. If the angle between the first and second vectors meets a first requirement, the corner point is considered a right-angled corner point; otherwise, it is considered an invalid right-angled corner point. If any corner point in the corresponding detection area is detected as an invalid right-angled corner point, it indicates that the current detection area has an edge-collapse anomaly. Furthermore, in this embodiment, a range adjustment value can be set for the specific right-angled angle in the first requirement, and this range can be adjusted according to specific detection standards and requirements.

[0056] The judgment in the above process is based on the number of vertices being 4. When the number of vertices is less than 4, i.e., a quadrilateral cannot be fitted, an outer matrix is ​​constructed and regarded as the fitted quadrilateral. Based on the above processing, the angle of each vertex is determined, and then based on the above judgment rules, it is determined whether the edge of the detection area conforms to the distribution under normal conditions.

[0057] In summary, this application provides a method for edge detection based on a combination of neural networks and image processing. This method segments multiple detection regions of the chip to be detected and obtains the bounding box information corresponding to each detection region through image morphology processing. Based on the deviation between the bounding box information and the expected result, it determines whether the current chip has an edge detection anomaly.

[0058] For further details, please refer to [link / reference]. Figure 4 In this embodiment, another edge breakage detection method is also provided, which is to determine whether the color ratio of the inner and outer sides of each detection area meets the threshold requirement.

[0059] Specifically, the chip edge chipping detection method includes the following steps: Step S41. Perform region segmentation on the acquired chip image to be detected based on the trained and convergent segmentation model to obtain the detection region image corresponding to the target region.

[0060] Step S42. Extract contours from the detection region image to obtain a set of contour points corresponding to the detection region image, and filter the set of contour points based on an area threshold to determine the target contour and the corresponding set of target contour points.

[0061] Step S43. Construct an initial bounding box and the initial vertices corresponding to the initial bounding box based on the target contour point set, and fit the initial bounding box to obtain the target bounding box and the polygon point set corresponding to the target bounding box.

[0062] Step S44. Determine the normal vectors corresponding to the multiple target bounding boxes, and determine the spatial distribution of the detection area based on the normal vectors. Determine the first type of area and the second type of area, and determine the real-time pixel distribution state of the first type of area and the second type of area. Determine whether the detection area satisfies the second condition based on the real-time pixel distribution state.

[0063] The processing steps S41-S43 are the same as those in the previous embodiment, and will not be repeated here. The difference is that in this embodiment, edge collapse detection is achieved by determining the real-time pixel distribution state of the first type region and the second type region corresponding to the detection region. Compared with the morphological features of the detection region in the previous embodiment, the features in this embodiment are color features.

[0064] Specifically, in this embodiment, satisfying the second condition refers to whether the chromaticity of the inner and outer edges of the detection area meets the requirements. The process for determining the chromaticity of the inner and outer edges of the detection area involves checking whether the pixel ratio between the inner and outer sides of the target border corresponding to the detection area meets a threshold requirement.

[0065] See Figure 5 Specifically, the inner and outer sides of the approximate polygon corresponding to the detection area are determined by calculating the normal vector of each edge, and then creating multiple inner / outer quadrilaterals 51 based on the normal vectors. The directions of the "inner" and "outer" sides are determined by the quadrilaterals. Specifically, the normal vector is obtained by determining the vector corresponding to each edge, normalizing it, and then rotating it by 90°. This normal vector is used to define the inner and outer directions, thereby distinguishing between the inner and outer sides.

[0066] Then, the real-time pixel distribution state corresponding to the inner and outer sides is determined. The real-time pixels collected for different regions are different. For the outer side, since it is expected to be a background image, the high white distribution meets expectations, so the real-time pixel distribution state for the outer side refers to the proportion of white distribution within the region. For the inner side, since it is expected to be an object, the high black distribution meets expectations, so the real-time pixel distribution state for the inner side refers to the proportion of black distribution within the region.

[0067] The threshold values ​​differ for the inner and outer sides. For the inner side, the threshold is 80% black within the region, while for the outer side, the threshold is 70% white within the region. This can be understood as follows: if the real-time pixel distribution in the inner side is determined to be 75% black, then the target region does not meet the requirements of the second condition.

[0068] In this embodiment, the processing methods in steps S11-S14 and S41-S44 detect edge collapse from two feature perspectives. In actual detection tasks, either method can be selected for configuration, or both methods can be configured simultaneously. However, for determining the detection result, if either method detects an edge collapse, the overall detection result is considered an edge collapse. It is preferable to configure both methods simultaneously, as the processing of two targeted features can improve detection accuracy.

[0069] See Figure 6 , Figure 6 A chip edge chipping detection device 60 provided in this embodiment of the invention includes: The segmentation module 61 is used to perform region segmentation on the acquired image of the chip to be detected based on a trained and convergent segmentation model, so as to obtain the detection region image corresponding to the target region. The contour extraction module 62 is used to extract contours from the detection area image to obtain a set of contour points corresponding to the detection area image, and to filter the set of contour points based on an area threshold to determine the target contour and the corresponding set of target contour points. The morphological feature module 63 is used to construct an initial bounding box and the initial vertices corresponding to the initial bounding box based on the target contour point set, and to fit the initial bounding box to obtain the target bounding box and the polygon point set corresponding to the target bounding box. Detection module 64 is used to determine whether the detection area meets the first requirement and / or the second requirement based on the polygon point set.

[0070] In this embodiment, the first requirement is whether the corners of the polygon are close to right angles, and the second requirement is whether the color ratio of the outer and inner sides of the four sides of the polygon meets the threshold requirement.

[0071] See Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Figure 7 As shown, the computer device 70 includes a processor 71 and a memory 72 coupled to the processor 71. The memory 72 stores program instructions. When the program instructions are executed by the processor 71, the processor 71 performs the chip edge detection method steps described in any of the above embodiments.

[0072] The processor 71 can also be referred to as a Central Processing Unit (CPU). The processor 71 may be an integrated circuit chip with signal processing capabilities. The processor 71 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0073] See Figure 8 The present invention also provides a readable medium 80, which stores computer-readable instructions 801, including instructions for performing the aforementioned chip failure detection method.

[0074] The functions and technical effects of the readable medium 80 provided in the embodiments of the present invention can be referred to the technical effects of the calibration method in the foregoing embodiments, and will not be repeated here.

[0075] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and / or methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units / modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0076] The units / modules described as separate components may or may not be physically separate. The components shown as units / modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units / modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0077] Furthermore, in the various embodiments of the present invention, the functional units / modules can be integrated into one processing unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated into one unit / module. The integrated unit / module described above can be implemented in hardware or in the form of hardware plus software functional units / modules.

[0078] The integrated unit / module implemented as a software functional unit / module described above can be stored in a computer-readable storage medium. The software functional unit, stored in a storage medium, includes several instructions to cause one or more processors of a computer device (which may be a personal computer, server, or network device, etc.) to execute some steps of the methods described in the various embodiments of the present invention.

[0079] The integrated unit / module implemented as a software functional unit / module described above can be stored in a computer-readable storage medium. The software functional unit, stored in a storage medium, includes several instructions to cause one or more processors of a computer device (which may be a personal computer, server, or network device, etc.) to execute some steps of the methods described in the various embodiments of the present invention.

[0080] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip edge chipping detection method, characterized in that, The method includes: The acquired image of the chip to be detected is segmented into regions based on a training-converging segmentation model to obtain the detection region image corresponding to the target region. The segmentation model includes an encoder and a decoder. The encoder is equipped with multiple feature extraction modules to obtain feature maps of the image of the chip to be detected. The decoder generates a semantic segmentation mask based on the feature maps and segments the image of the chip to be detected based on the semantic segmentation mask. The detection region image is a mask image. Contour extraction is performed on the detection area image to obtain a set of contour points corresponding to the detection area image. The set of contour points is then filtered based on an area threshold to determine the target contour and the corresponding set of target contour points. An initial bounding box and its corresponding initial vertices are constructed based on the target contour point set. The initial bounding box is then fitted to obtain the target bounding box and its corresponding polygon point set. It is then determined whether the angles of multiple vertices in the polygon point set meet the first requirement.

2. The chip edge chipping detection method according to claim 1, characterized in that, The method further includes: determining the normal vectors corresponding to the multiple target bounding boxes, determining the spatial distribution of the detection area based on the normal vectors, determining a first type of region and a second type of region, determining the real-time pixel distribution state of the first type of region and the second type of region, and determining whether the detection area satisfies a second condition based on the real-time pixel distribution state; the first type of region and the second type of region are adjacent in spatial relationship.

3. The chip edge chipping detection method according to claim 1, characterized in that, The method further includes determining whether the number of multiple vertices in the polygon point set meets the requirements, and when the requirements are met, determining whether the angles of the multiple vertices in the polygon point set meet the first requirement; specifically, it includes: obtaining multiple corner points in the polygon point set and the adjacent points corresponding to the corner points, and determining whether the detection area meets the first requirement based on the angle between the corner points and the adjacent points.

4. The chip edge chipping detection method according to claim 1, characterized in that, The contour point set is then filtered based on an area threshold, including: removing contour point sets smaller than a preset area threshold and retaining only contour point sets that meet the preset area threshold.

5. The chip edge chipping detection method according to claim 1, characterized in that, Constructing an initial bounding box and its corresponding initial vertices based on the target contour point set includes: extracting the minimum convex hull and the complete convex hull vertex sequence corresponding to the minimum convex hull based on the target contour point set; constructing the initial contour based on the minimum convex hull; and constructing the initial bounding box based on multiple convex hull vertices.

6. The chip edge chipping detection method according to claim 5, characterized in that, The process involves fitting the initial bounding box to obtain the target bounding box and the target vertices corresponding to the target bounding box, including: determining the updated contour point set corresponding to the initial contour, constructing a preset bounding box using the start and end points of the updated contour point set, determining the vertical distance of any point in the updated contour point set relative to the preset bounding box, determining the relationship between the vertical distance and a preset distance threshold, and filtering the points in the updated contour point set based on this relationship to obtain the target vertices and the target bounding box.

7. The chip edge chipping detection method according to claim 1, characterized in that, Determining whether the detection area meets the first requirement based on the angle between the corner point and its adjacent points includes: constructing a first vector and a second vector corresponding to the corner point and two adjacent points, and determining the angle between the first vector and the second vector. When the angle between the first vector and the second vector meets a preset angle requirement, the detection area meets the first requirement.

8. The chip edge chipping detection method according to claim 2, characterized in that, Determining whether the detection area meets the second condition based on the real-time pixel distribution status includes: determining whether the real-time pixel distribution in the first type region or the second type region of the detection area meets the preset pixel distribution conditions; when either type region does not meet the preset pixel distribution conditions, it is determined that the detection area does not meet the second condition; the preset pixel distribution conditions include a first condition and a second condition, the first condition is set for the first type region, and the second condition is set for the second type region.

9. A computer device, characterized in that, The computer device includes a processor and a memory coupled to the processor, the memory storing program instructions that, when executed by the processor, cause the processor to perform the steps of the chip edge-damping detection method as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the chip edge detection method according to any one of claims 1-8.

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