Semiconductor wafer defect recognition method and system based on visual detection

Abstract

The application discloses a semiconductor wafer defect recognition method and system based on visual detection, relates to the technical field of visual detection, and comprises the following steps: collecting and processing wafer visual data to generate a wafer visual detection set; registering die regions and constructing a die corresponding grid; collecting the same local regions to generate a wafer defect analysis sample; generating a wafer defect visual feature package through improved PP-LiteSeg processing; determining an abnormal core and expansion to generate a wafer defect candidate region; analyzing the contour and merging the candidate regions to generate a wafer defect recognition record; determining a defect position range and a category to generate a wafer defect recognition result. The application constructs a die corresponding grid and introduces an improved PP-LiteSeg model, and realizes high-precision recognition, positioning and classification of semiconductor wafer micro defects, slender defects and cross-die continuous defects.

Description

Technical Field

[0001] This invention relates to the field of visual inspection technology, and in particular to a method and system for identifying semiconductor wafer defects based on visual inspection. Background Technology

[0002] As integrated circuit manufacturing processes advance towards higher integration and refinement, the size of defects on semiconductor wafer surfaces is gradually decreasing, while their morphologies are becoming more complex. Wafer visual inspection has become a crucial inspection method in wafer manufacturing and quality control. Existing technologies typically utilize industrial cameras, microscopic imaging equipment, or automated optical inspection equipment to acquire images of the wafer surface, followed by image correction, grain segmentation, feature extraction, and defect identification. Because the wafer surface has a large number of structurally similar grains regularly distributed, some methods employ template matching, comparison of adjacent grains, or image difference analysis at the same location to identify grayscale anomalies, texture anomalies, edge damage, scratches, and local structural defects. Convolutional neural networks and semantic segmentation networks are also increasingly being used for wafer defect detection, extracting defect features through encoding and decoding to obtain defect regions and their corresponding categories.

[0003] Existing vision-based methods for semiconductor wafer defect identification still have certain shortcomings. Traditional template comparison or adjacent grain difference methods often use a single grain or local region as a reference, failing to adequately utilize the co-position, adjacency, and boundary correspondence of multiple grains. Grain position offsets and normal texture fluctuations can easily interfere with defect identification. After continuous downsampling, lightweight semantic segmentation networks are prone to attenuation of the feature responses of small defects, and information on point defects, fine cracks, and narrow scratches may be lost. For continuous defects spanning multiple grains, existing methods mostly identify them independently within each grain region, lacking processing of the defect extension direction and the continuity of adjacent grain boundary positions, easily segmenting the same defect into multiple independent regions. Existing region merging methods also rely heavily on area, overlap, or simple distance for judgment, failing to adequately utilize the defect contour extension relationship and structural morphology differences, easily leading to problems such as duplicate defect recording, inaccurate range determination, and unstable category identification.

[0004] Therefore, how to provide a method and system for identifying semiconductor wafer defects based on visual inspection is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] One objective of this invention is to propose a semiconductor wafer defect identification method and system based on visual inspection. This invention utilizes wafer visual image correction and grain correspondence lattice construction, isotopic grain structure distance analysis, an improved PP-LiteSeg model, abnormal core expansion, and defect region merging techniques. It details the implementation process of wafer visual inspection, grain correspondence construction, defect feature extraction, micro-defect preservation, defect extension discrimination, cross-grain continuity recovery, and defect identification result generation. This achieves the identification, location, and classification of micro-defects, elongated defects, and cross-grain continuous defects on the semiconductor wafer surface. Compared to traditional wafer defect detection methods based on single-grain template comparison or independent region segmentation, this invention offers advantages such as stable characterization of isotopic grain structure differences, complete preservation of micro-defect features, accurate recovery of cross-grain defect continuity, reasonable defect region merging, and high accuracy in wafer defect location and category determination.

[0006] A semiconductor wafer defect identification method based on visual inspection according to an embodiment of the present invention includes: Collect wafer visual images and die position data, correct the wafer visual images and perform wafer coordinate mapping, divide the die regions according to the die position data, and generate a wafer visual inspection set; Register the grain region according to the wafer visual inspection set, establish corresponding nodes according to the corresponding positions of the grain region, connect adjacent nodes according to the row and column relationship of the grain and establish corresponding boundary edges to form a corresponding grain grid; Local visual regions of corresponding nodes along the corresponding lattice of the grain are collected, structural distances are calculated and arranged according to node connection relationships to generate wafer defect analysis samples; The wafer defect analysis samples are input into the improved PP-LiteSeg model, and processed by the grain difference verification unit, micro-defect retention unit, defect extension discrimination unit and cross-grain recovery unit to generate a wafer defect visual feature package. Based on the visual feature package of wafer defects, the abnormal core is determined, and it is expanded along the direction of abnormal feature attenuation. Intersecting regions are merged to generate wafer defect candidate regions. Extract the outline of candidate regions for wafer defects, calculate the principal axis direction and structural deviation, merge candidate regions for wafer defects according to the principal axis extension relationship and structural deviation, and generate wafer defect identification records; Based on the wafer defect identification records, the defective grain, wafer coordinates, defect range, and defect category are determined, and semiconductor wafer defect identification results are generated.

[0007] Optionally, the wafer visual image specifically includes a wafer surface grayscale image, a grain edge image, and a grain local texture image; the grain position data specifically includes the grain number, grain row and column coordinates, grain center coordinates, grain boundary coordinates, and grain region size.

[0008] Optionally, the generation of the wafer visual inspection set includes: The wafer edge is fitted based on the wafer visual image to determine the wafer center and effective radius. The rotation and scale deviations of the wafer surface grayscale image, grain edge image and grain local texture image are corrected to generate a corrected wafer visual image. Using the center of the wafer as the origin of the coordinate system, the pixel positions in the corrected wafer visual image are converted into wafer coordinates according to the effective radius, establishing the mapping relationship between pixel positions and wafer coordinates, and generating a wafer coordinate image; Based on the grain number, grain row and column coordinates, grain center coordinates, grain boundary coordinates, and grain region size, the grain boundary is located and the grain region is divided in the wafer coordinate image to generate a grain region set. Collect wafer surface grayscale images, grain edge images, and local grain texture images from the grain region set according to the grain number, retain the corresponding wafer coordinates and grain row and column coordinates, and generate a wafer visual inspection set.

[0009] Optionally, the lattice corresponding to the grains includes: The grain region is translated to a unified local coordinate system according to the coordinates of the grain center, and the scale of the grain region is corrected according to the grain boundary to obtain the registered grain region; The corresponding positions are determined by the same local coordinates within the registered grain region, and the local visual regions of the corresponding positions of different grains are established as co-position nodes. Based on the row and column coordinates of the grains, adjacent grains are determined, and the corresponding nodes of the adjacent grains are identified as adjacent nodes and connected. Align the boundary positions of adjacent grains, pair the boundary positions according to local coordinates, and establish corresponding boundary edges between the corresponding co-located nodes of the paired boundary positions; Organize corresponding nodes, adjacent nodes, and boundary edges according to the grain row and column relationship to form a grain correspondence lattice.

[0010] Optionally, generating wafer defect analysis samples includes: Local visual regions are aggregated along the corresponding lattice of the grain according to the same node; Calculate the grayscale difference, edge position difference, and texture feature difference between the local visual regions of the same node, and summarize the grayscale difference, edge position difference, and texture feature difference to obtain the structural distance; The structural distance is mapped to the corresponding node combination involved in the calculation, and the arrangement order of the local visual regions is determined according to the node connection relationship; By combining local visual regions and corresponding structural distances in an ordered manner, wafer defect analysis samples are generated.

[0011] Optionally, the generation of the wafer defect visual feature package includes: An improved PP-LiteSeg model is constructed, which includes a grain difference verification unit, a micro-defect retention unit, a defect extension discrimination unit, and a cross-grain recovery unit. The grain difference verification unit receives wafer defect analysis samples, converts the local visual regions of co-located nodes into local visual features using the PP-LiteSeg encoder, arranges the structural distances between co-located nodes into a structural distance matrix, performs a negative exponential transformation on the structural distances and normalizes them by row to obtain consistency weights, aggregates the local visual features according to the consistency weights to form a consistency benchmark, and calculates the difference between the local visual features and the consistency benchmark position by position to generate grain difference features. The micro-defect retention unit receives grain difference features, divides local windows according to the coding position, sums the absolute values ​​of the grain difference features within the local window to obtain the anomalous energy before downsampling, maps the local window to the next coding layer according to the downsampling ratio and converts it to the anomalous energy after downsampling, calculates the difference between the anomalous energy before downsampling and the anomalous energy after downsampling and truncates the non-negative part, and allocates the non-negative part to the corresponding coding position according to the local response ratio to generate micro-defect retention features; The defect extension discrimination unit receives micro-defect retention features, calculates the local window response centroid using the micro-defect retention feature response value as weight, calculates the transverse gradient and longitudinal gradient within the local window respectively, arranges the sum of squared transverse gradients, the sum of the product of transverse and longitudinal gradients, and the sum of squared longitudinal gradients into a 2×2 structure tensor, takes the eigenvector corresponding to the smallest eigenvalue of the structure tensor as the extension vector, and obtains the boundary exit by intersecting the extension vector with the grain boundary from the response centroid, thus generating the defect extension feature; The cross-grain recovery unit receives defect extension features, determines adjacent grains according to the order of the defect extension features, takes the same-order endpoints of the corresponding boundaries of adjacent grains as the boundary start points, calculates the boundary distances from the boundary start points to the boundary exits, uses the ratio of the boundary distance to the corresponding grain boundary length as the boundary parameter, calculates the boundary parameter difference between the corresponding boundaries of adjacent grains and performs a negative exponential transformation to obtain the connection weights, fuses the defect extension features on both sides of the boundary exit according to the connection weights to generate cross-grain recovery features, and generates wafer defect visual feature packets by PP-LiteSeg decoding step by step; The improved PP-LiteSeg model was trained using wafer defect region annotations as supervision information. The defect segmentation error, co-location node consistency error, micro-defect energy preservation error, defect propagation direction error, and cross-grain boundary continuity error were combined as a joint loss function to constrain wafer defect segmentation, grain difference features, adjacent coding layer anomalous energy, defect propagation vector, and cross-grain recovery features, respectively. The parameters of the improved PP-LiteSeg model were updated by backpropagation based on the joint loss function. The training of the improved PP-LiteSeg model was completed when the relative change rate of the joint loss value in 6 consecutive training rounds was no greater than 0.002.

[0012] Optionally, generating candidate regions for wafer defects includes: The absolute values ​​of the channel responses at each feature location in the visual feature package of wafer defects are summed to obtain the abnormal response value. The feature location with the largest abnormal response value in the local neighborhood is determined as the abnormal core. Centered on the anomaly core, calculate the anomaly response difference between adjacent feature locations and the anomaly core. Weight the directions corresponding to adjacent feature locations with decreasing anomaly response values ​​according to the anomaly response difference to determine the attenuation direction of the anomaly features. Along the direction of abnormal feature decay, select feature positions that are adjacent to the current feature position and whose abnormal response values ​​decrease step by step. Connect the selected feature positions continuously with the abnormal core until there are no adjacent positions that meet the condition of decreasing abnormal response values, thus forming an abnormal expansion region. By comparing the coverage positions of different anomalous expansion regions, anomalous expansion regions with intersecting positions are merged, while non-intersecting anomalous expansion regions are retained to generate wafer defect candidate regions.

[0013] Optionally, the generation of the wafer defect identification record includes: Extract the outer contour of each wafer defect candidate region, calculate the region centroid according to the contour coordinates, and transform the contour coordinates with the region centroid as the origin. Based on the transformed contour coordinates, a coordinate covariance matrix is ​​constructed. The eigenvector corresponding to the largest eigenvalue is determined as the principal axis direction of the wafer defect candidate region, and the projection endpoints at both ends of the contour are determined along the principal axis direction. Calculate the vertical distance from each contour coordinate to the principal axis, determine the structural deviation by the ratio of the average vertical distance to the maximum vertical distance, and extend the principal axis outward from the projection endpoint to determine the principal axis extension relationship intersecting with the contours of other wafer defect candidate regions. Based on the principal axis extension relationship, candidate regions of wafer defects to be merged are determined. The absolute difference between the corresponding structural deviations is calculated. For each candidate region of wafer defects, the region with the smallest absolute difference is selected. Wafer defect candidate regions with the smallest absolute difference and principal axis extension relationship are merged to form a merged region. Unmerged wafer defect candidate regions are treated as independent merged regions. The region coordinates and corresponding grains of the merged regions are recorded to generate a wafer defect identification record.

[0014] Optionally, the generation of semiconductor wafer defect identification results includes: Determine the defective grains according to the corresponding grains in the merged regions of the wafer defect identification record; The region coordinates of the merged regions are transformed to the wafer coordinate system according to the mapping relationship between pixel position and wafer coordinates, and the wafer coordinates of each merged region are determined. Extract the extreme values ​​of the horizontal and vertical coordinates of each merged region in the wafer coordinate system, and determine the defect range based on the horizontal and vertical coordinate spans. The morphological characteristics of the merged region are calculated based on its area, horizontal coordinate span, vertical coordinate span, and cross-grain coverage. The defect category is determined according to the morphological characteristics of the region. The defect grain, wafer coordinates, defect range, and defect category are then aggregated to generate semiconductor wafer defect identification results.

[0015] A semiconductor wafer defect identification system based on visual inspection according to an embodiment of the present invention includes the following modules: The wafer vision processing module is used to acquire and process wafer vision images and die position data to generate a wafer vision inspection set. The grain structure construction module is used to register grain regions and construct corresponding lattices for grains; The defect sample generation module is used to organize the local visual regions of co-located nodes and calculate the structural distance to generate wafer defect analysis samples. The defect feature extraction module is used to process wafer defect analysis samples by improving the PP-LiteSeg model and generate a wafer defect visual feature package. The candidate region generation module is used to identify and expand the anomaly core, merge intersecting regions, and generate wafer defect candidate regions. The defect region merging module is used to merge wafer defect candidate regions based on contour, main axis direction and structural deviation, and generate wafer defect identification records. The identification result generation module is used to determine the defective grain, wafer coordinates, defect range, and defect category, and generate semiconductor wafer defect identification results.

[0016] The beneficial effects of this invention are: This invention proposes a visual inspection-based semiconductor wafer defect identification method. Through wafer visual image correction, grain-to-grain lattice construction, wafer defect analysis sample generation, and wafer defect visual feature extraction, a defect identification process for repetitive wafer structures is formed. By organizing the co-positions of different grains into co-position nodes and combining adjacent nodes and boundary edges to establish a grain-to-grain lattice, the method can uniformly represent the co-positional relationships, adjacency relationships, and boundary correspondences between grains. This reduces the interference of grain position offset and normal texture fluctuations on defect judgment and improves the stability of abnormal region identification under repetitive wafer structure conditions.

[0017] This invention improves the grain difference verification unit, micro-defect retention unit, defect extension discrimination unit, and cross-grain recovery unit in the PP-LiteSeg model to perform layered processing of wafer defect features. The grain difference verification unit uses the structural distance of co-located nodes to form a consistent benchmark and extract grain difference features. The micro-defect retention unit compensates for abnormal energy loss between adjacent coding layers, reducing feature attenuation of small defects during continuous downsampling. The defect extension discrimination unit determines the defect extension vector and boundary exit. The cross-grain recovery unit fuses defect extension features based on the positional relationship of adjacent grain boundaries, enabling fine cracks, scratches, and continuous contamination areas crossing grain boundaries to maintain continuous feature representation, thereby improving the identification integrity of micro-defects and continuous cross-grain defects.

[0018] This invention identifies anomaly cores based on the visual feature package of wafer defects and forms candidate regions for wafer defects along the attenuation direction of the anomaly features. It then combines the candidate region contour, principal axis direction, and structural deviation to complete defect region merging, reducing the problem of repeated segmentation and recording of the same continuous defect. By uniformly determining the defect grain, wafer coordinates, defect range, and defect category, a complete closed loop is achieved from feature extraction, region formation, continuity relationship restoration to final identification result output for wafer defects. This improves the accuracy of semiconductor wafer defect localization, range determination, and category classification, and enhances the ability to identify minute defects, elongated defects, and cross-grain continuous defects. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the semiconductor wafer defect identification method based on visual inspection proposed in this invention; Figure 2 This is a schematic diagram of the improved PP-LiteSeg model of the semiconductor wafer defect identification method based on visual detection proposed in this invention. Figure 3 This is a schematic diagram of the semiconductor wafer defect identification system based on visual inspection proposed in this invention. Detailed Implementation

[0020] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0021] refer to Figure 1 and Figure 2 A visual inspection-based method for identifying semiconductor wafer defects includes: Collect wafer visual images and die position data, correct the wafer visual images and perform wafer coordinate mapping, divide the die regions according to the die position data, and generate a wafer visual inspection set; Register the grain region according to the wafer visual inspection set, establish corresponding nodes according to the corresponding positions of the grain region, connect adjacent nodes according to the row and column relationship of the grain and establish corresponding boundary edges to form a corresponding grain grid; Local visual regions of corresponding nodes along the corresponding lattice of the grain are collected, structural distances are calculated and arranged according to node connection relationships to generate wafer defect analysis samples; The wafer defect analysis samples are input into the improved PP-LiteSeg model, and processed by the grain difference verification unit, micro-defect retention unit, defect extension discrimination unit and cross-grain recovery unit to generate a wafer defect visual feature package. Based on the visual feature package of wafer defects, the abnormal core is determined, and it is expanded along the direction of abnormal feature attenuation. Intersecting regions are merged to generate wafer defect candidate regions. Extract the outline of candidate regions for wafer defects, calculate the principal axis direction and structural deviation, merge candidate regions for wafer defects according to the principal axis extension relationship and structural deviation, and generate wafer defect identification records; Based on the wafer defect identification records, the defective grain, wafer coordinates, defect range, and defect category are determined, and semiconductor wafer defect identification results are generated.

[0022] In this embodiment, the wafer visual image specifically includes a wafer surface grayscale image, a grain edge image, and a grain local texture image; the grain position data specifically includes the grain number, grain row and column coordinates, grain center coordinates, grain boundary coordinates, and grain region size.

[0023] In this embodiment, generating the wafer visual inspection set includes: The wafer edge is fitted based on the wafer visual image to determine the wafer center and effective radius. Rotational and scale deviations in the wafer surface grayscale image, grain edge image, and local grain texture image are corrected to generate a corrected wafer visual image, where: Generate a corrected wafer visual image, specifically: The horizontal and vertical gray-level gradients of adjacent pixels are calculated from the gray-level image of the wafer surface. The square root of the sum of the squares of the two gradients is used to obtain the gradient magnitude. Pixels whose gradient magnitude is greater than the sum of the average gradient magnitude of the entire image and 1.5 times the standard deviation are retained as candidate points on the outer edge of the wafer. Using the image center as the pole, the candidate points on the outer edge of the wafer are divided into 1° polar angle intervals. Within each polar angle interval, the candidate point with the largest radial distance is retained. The median of the radial distances of the retained candidate points is calculated. Discrete points whose radial distance difference from adjacent candidate points exceeds 5% of the median are removed to obtain the set of wafer edge points. The wafer edge point set is fitted with least squares circle. The wafer center is determined by the coordinates where the sum of the squared residuals between the distance from each edge point to the center of the desired circle and the radius of the desired circle is the smallest. The effective radius is determined by the average distance from each edge point to the wafer center. Edge points whose absolute deviation from the effective radius exceeds 2% of the effective radius are removed, and the fit is repeated until the effective radius change rate of two consecutive fits is no greater than 0.1%. Extract straight edges from the grain edge image with a length of more than 30% of the grain region width, calculate the angle between each straight edge and the horizontal coordinate axis of the image, convert the angle to -45° to 45° and take the median as the rotation deviation angle, and perform inverse rotation coordinate transformation on the wafer surface grayscale image, grain edge image and grain local texture image with the wafer center as the rotation center. The reference effective radius is determined based on the imaging calibration parameters of the wafer vision image acquisition equipment. The scale correction coefficient is obtained by dividing the reference effective radius by the effective radius after rotation correction. The horizontal and vertical distances of each pixel in the three types of images relative to the wafer center are multiplied by the scale correction coefficient, and bilinear interpolation is used to determine the gray value, edge value, and texture value at non-integer coordinate positions. The effective radius after scale correction is determined as the reference effective radius, and the corrected wafer vision image is generated. Using the wafer center as the origin, the pixel positions in the calibrated wafer visual image are converted into wafer coordinates according to the effective radius, establishing a mapping relationship between pixel positions and wafer coordinates, and generating a wafer coordinate image, where: Generate a wafer coordinate image, specifically as follows: Using the pixel coordinates of the wafer center as the origin, the horizontal coordinates of each pixel in the corrected wafer visual image are subtracted from the horizontal coordinates of the wafer center to obtain the horizontal pixel offset. The vertical coordinates of each pixel are subtracted from the vertical coordinates of the wafer center to obtain the vertical pixel offset. Calculate the square root of the sum of the squares of the horizontal and vertical pixel offsets of each pixel, and determine the effective area of ​​the wafer as the pixel whose calculation result is not greater than the effective radius. Divide the horizontal and vertical pixel offsets within the effective area of ​​the wafer by the effective radius to obtain normalized horizontal and vertical coordinates with values ​​ranging from -1 to 1. Multiply the normalized horizontal coordinate and the normalized vertical coordinate by the actual effective radius of the wafer to obtain the corresponding horizontal wafer coordinate and vertical wafer coordinate, where the actual effective radius of the wafer is 1 / 2 of the actual diameter of the wafer. A one-to-one mapping is established between the pixel positions within the effective area of ​​the wafer and the corresponding horizontal and vertical wafer coordinates. The wafer coordinates are mapped to the corrected wafer visual image according to the pixel arrangement, and the corresponding grayscale values, edge values ​​and texture values ​​are retained to generate a wafer coordinate image. Based on the grain number, grain row and column coordinates, grain center coordinates, grain boundary coordinates, and grain region size, the grain boundary is located and the grain region is divided in the wafer coordinate image to generate a grain region set. Collect wafer surface grayscale images, grain edge images, and local grain texture images from the grain region set according to the grain number, retain the corresponding wafer coordinates and grain row and column coordinates, and generate a wafer visual inspection set.

[0024] In this embodiment, the formation of the corresponding lattice of grains includes: The grain region is translated to a unified local coordinate system according to the grain center coordinates, and the grain region scale is corrected according to the grain boundary to obtain the registered grain region, where: The registered grain region is obtained as follows: Based on the coordinates of the grain center, determine the pixel position corresponding to each grain center in the wafer coordinate image. Using the pixel position corresponding to the grain center as the local coordinate origin, subtract the horizontal and vertical coordinates of the corresponding pixel position from the horizontal and vertical coordinates of each pixel in the grain region to obtain the local horizontal and vertical coordinates. The corresponding boundary pixel position is determined based on the grain boundary coordinates. The lateral boundary spacing and longitudinal boundary spacing of each grain region are calculated respectively. The median of the lateral boundary spacing of all grain regions is used as the reference width, and the median of the longitudinal boundary spacing is used as the reference height. The lateral scale factor is obtained by dividing the reference width by the lateral boundary spacing of the current grain region, and the longitudinal scale factor is obtained by dividing the reference height by the longitudinal boundary spacing of the current grain region. The local lateral coordinates and local longitudinal coordinates are multiplied by the corresponding scale factors to obtain the scale-corrected local coordinates. Bilinear interpolation is performed on the wafer surface grayscale image, grain edge image, and grain local texture image according to the scale-corrected local coordinates to unify each grain region to the reference width and reference height, and keep the grain center located at the unified local coordinate origin to obtain the registered grain region; The corresponding positions are determined by the same local coordinates within the registered grain region, and the local visual regions at corresponding positions of different grains are established as co-position nodes, where: Establishing a peer node is specifically as follows: Each registered grain region is matched position by position according to a unified local coordinate system, and the center of the local visual region is determined at the same local horizontal coordinate and local vertical coordinate. Extend 4 pixels horizontally and vertically from the center of the local visual region, and extract the wafer surface grayscale image, grain edge image and grain local texture image within a 9×9 pixel range to form the local visual region at the corresponding position. Local visual regions with the same local coordinates in each grain are established as corresponding nodes, and the corresponding grain number, grain row and column coordinates and local coordinates are recorded. For local visual regions located at the grain boundary and whose cropping range exceeds the grain area, the boundary copying method is used to fill in the excess position, so that the local visual regions contained in each co-position node remain 9×9 pixels. Based on the row and column coordinates of the grains, adjacent grains are determined, and the corresponding nodes of the adjacent grains are identified as adjacent nodes and connected. Align the boundary positions of adjacent grains, pair the boundary positions according to local coordinates, and establish corresponding boundary edges between the corresponding co-located nodes of the paired boundary positions, wherein: Establish the corresponding edges at the boundaries, specifically as follows: The relative orientation of adjacent grains is determined based on the grain row and column coordinates. For adjacent grains in the same row, the right grain boundary and the left grain boundary are selected, and for adjacent grains in the same column, the lower grain boundary and the upper grain boundary are selected to form relative boundaries. In a unified local coordinate system, the relative boundaries of adjacent grains in the same row are arranged in the direction of increasing local vertical coordinates, and the relative boundaries of adjacent grains in the same column are arranged in the direction of increasing local horizontal coordinates. The starting ends of the two relative boundary arrangement directions are respectively determined as the same sequence endpoints. Calculate the local coordinate difference of the corresponding position pixel by pixel along the relative boundary, calculate the local vertical coordinate difference for adjacent grains in the same row, calculate the local horizontal coordinate difference for adjacent grains in the same column, and pair up the positions with an absolute value of coordinate difference of no more than 1 pixel. When a boundary position corresponds to multiple positions that meet the conditions, retain the position with the smallest absolute value of coordinate difference; Determine the corresponding co-located nodes based on the local coordinates of the pairing boundary position, connect the co-located nodes belonging to two adjacent grains, and record the connected grain number, co-located node and boundary position to establish the corresponding boundary edge; Organize corresponding nodes, adjacent nodes, and boundary edges according to the grain row and column relationship to form a grain correspondence lattice.

[0025] In this embodiment, generating wafer defect analysis samples includes: Local visual regions are aggregated along the corresponding lattice of the grain according to the same node; Calculate the grayscale difference, edge position difference, and texture feature difference between the local visual regions of co-located nodes, and summarize these differences to obtain the structural distance, where: The structural distance is obtained as follows: Pair up the same local horizontal and vertical coordinates of the same local nodes, align the 9×9 pixel local visual regions corresponding to each pair of the two local nodes pixel by pixel, normalize the gray values ​​of the grayscale image on the wafer surface to the range of 0-1, calculate the absolute difference of the gray values ​​of the corresponding pixels and calculate the average of 81 pixels to obtain the grayscale difference. Extract the edge pixels of two local visual regions in the grain edge image. When neither local visual region has edge pixels, the edge position difference is recorded as 0. When only one local visual region has edge pixels, the edge position difference is recorded as 1. When both local visual regions have edge pixels, calculate the Euclidean distance from each edge pixel in the first local visual region to the nearest edge pixel in the second local visual region and calculate the average value. Then, calculate the distance from the second local visual region to the nearest edge pixel in the first local visual region and calculate the average value. Divide the arithmetic mean of the two average values ​​by the diagonal length of the 9×9 pixel region to obtain the edge position difference. The texture values ​​of the local texture images of the grains corresponding to the two local visual regions are normalized to the range of 0-1 and divided into 9 3×3 pixel texture sub-regions. The mean and standard deviation of the texture values ​​in each texture sub-region are calculated. The absolute difference of the mean and the absolute difference of the standard deviation of the corresponding texture sub-regions are added together and divided by 2. The average value of the calculation results of the 9 texture sub-regions is taken to obtain the texture feature difference. Multiply the grayscale difference, edge position difference, and texture feature difference by 0.35, 0.35, and 0.30 respectively, and then sum them to obtain the structural distance of the corresponding co-located node combination; The structural distance is mapped to the corresponding node combination involved in the calculation, and the arrangement order of the local visual regions is determined according to the node connection relationship, where: The order of local visual regions is determined as follows: Based on the local coordinates recorded by the corresponding nodes, the corresponding positions are first arranged in the order of increasing local vertical coordinates and increasing local horizontal coordinates. Then, the corresponding nodes with the same corresponding position are arranged in the order of increasing grain row coordinates and increasing grain column coordinates within the same row to form the initial node order. Select corresponding nodes one by one according to the initial node order and write them into the permutation sequence. For the current corresponding node, determine the adjacent nodes that have not yet been written into the permutation sequence along the connection relationship of adjacent nodes, and write them after the current corresponding node according to the grain row and column coordinate order. When the current sibling node has a boundary edge, after connecting the sibling nodes that have not yet been written into the permutation sequence with the boundary edge, write the sibling nodes that have been written into the permutation sequence into the current sibling node, mark the sibling nodes that have been written into the permutation sequence and skip duplicate nodes. After traversing all the corresponding nodes, the corresponding nodes that were not written into the arrangement sequence are added in the order of increasing local vertical coordinate, local horizontal coordinate, grain row coordinate and grain column coordinate to obtain the arrangement order of the local visual region. By combining local visual regions and corresponding structural distances in an ordered manner, wafer defect analysis samples are generated.

[0026] In this embodiment, the generation of the wafer defect visual feature package includes: An improved PP-LiteSeg model is constructed, comprising a grain difference verification unit, a micro-defect retention unit, a defect extension discrimination unit, and a cross-grain recovery unit, wherein: The improved PP-LiteSeg model is constructed as follows: The original backbone network is retained based on the encoder, simple pyramid pooling module and lightweight decoder structure of the traditional PP-LiteSeg model; A new grain difference verification unit is added to the encoder feature output path to perform feature difference verification on the same node and generate grain difference features. Add micro-defect retention units to the feature transfer path of adjacent coding layers to preserve abnormal energy of grain difference features and generate micro-defect retention features. A defect extension discrimination unit is added between the micro-defect retention unit and the simple pyramid pooling module to determine the extension direction of the micro-defect retention features and generate defect extension features. A cross-grain recovery unit is added between the defect extension discrimination unit and the simple pyramid pooling module. The defect extension features of adjacent grains are fused across the boundary to generate cross-grain recovery features. The cross-grain recovery features are then input into the simple pyramid pooling module and the lightweight decoder in sequence to obtain the improved PP-LiteSeg model. The grain difference verification unit receives wafer defect analysis samples, converts the local visual regions of co-located nodes into local visual features using a PP-LiteSeg encoder, arranges the structural distances between co-located nodes into a structural distance matrix, performs a negative exponential transformation on the structural distances and normalizes them by row to obtain consistency weights, aggregates the local visual features according to the consistency weights to form a consistency benchmark, and calculates the difference between the local visual features and the consistency benchmark position by position to generate grain difference features, where: The grain difference verification unit includes: Local feature buffer: stores the local visual features of peer nodes; Distance matrix register: stores the distance matrix. Negative exponent lookup table: Completes the negative exponent mapping of structural distances; Row normalization calculator: generates consistency weights; Consistent baseline accumulator: Weighted aggregation of local visual features to form a consistent baseline; Difference Calculator: Calculates the positional difference between local visual features and a consistent reference, generating grain difference features; The processing procedure of the grain difference verification unit is as follows: The die difference verification unit receives wafer defect analysis samples and sequentially inputs the local visual regions of N co-located nodes corresponding to the same local coordinates into the PP-LiteSeg encoder to obtain encoded features of size H×W×C. The local feature buffer stores the encoded features according to the order of the co-located nodes and stacks them into a local visual feature tensor of size N×H×W×C, where N is the number of co-located nodes, and H, W and C are the height, width and number of channels of the encoded feature, respectively. The distance matrix register receives the structural distances from the wafer defect analysis samples. According to the order of the co-location nodes, the structural distances corresponding to the combination of the i-th co-location node and the j-th co-location node are written into the i-th row and j-th column and the j-th row and i-th column, respectively, forming a structural distance matrix of size N×N. 0 is written to the main diagonal position, and a masking mark is set for the main diagonal position. The negative exponent lookup table receives the off-diagonal structural distances from the structural distance matrix, quantizes the structural distances in the range of 0-1 into lookup indices at intervals of 0.001, and pre-stores the negative exponent values ​​corresponding to each index in the lookup table. The negative exponent values ​​are determined by dividing the structural distance by the attenuation coefficient 0.15, taking the negative value, and then performing exponentiation. The consistent response values ​​are obtained based on the lookup indices, and the consistent response values ​​at the main diagonal positions are kept as 0, forming a consistent response matrix of size N×N. The row normalization calculator accumulates the off-diagonal consistent response values ​​in the consistent response matrix row by row, divides each consistent response value by the sum of the consistent response values ​​in its row to obtain the consistency weight, and writes it into a consistency weight matrix of size N×N according to the original matrix position, with the sum of the off-diagonal consistency weights in each row being 1. The consensus benchmark accumulator sequentially selects the consensus weight of the i-th row, multiplies the H×W×C local visual feature corresponding to the j-th co-node by the consensus weight of the i-th row and j-th column position by position, and then accumulates the N-1 weighted local visual features other than the i-th co-node position by position to obtain the H×W×C consensus benchmark corresponding to the i-th co-node. After N calculations, an N×H×W×C consensus benchmark tensor is formed. The difference calculator subtracts the local visual feature tensor from the uniform reference tensor element by element according to the co-location node number, spatial position and channel position, retains the positive or negative sign of the difference, and writes it into the N×H×W×C difference tensor according to the original co-location node arrangement order to generate grain difference features. The parameters of the grain difference verification unit include the number of co-location nodes N, the coding feature height H, the coding feature width W, the number of coding channels C, and the attenuation coefficient. The attenuation coefficient is set to 0.15. The number of co-location nodes N is determined based on the actual number of co-location nodes participating in the calculation under the same local coordinates and is not less than 2. The coding feature height H, the coding feature width W, and the number of coding channels C are determined based on the output size of the PP-LiteSeg coding layer connected to the grain difference verification unit. The micro-defect retention unit receives grain difference features, divides local windows according to encoding positions, sums the absolute values ​​of grain difference features within each local window to obtain the pre-downsampling anomalous energy, maps the local window to the next encoding layer according to the downsampling ratio, and calculates the post-downsampling anomalous energy. The difference between the pre-downsampling and post-downsampling anomalous energy is calculated, and the non-negative portion is truncated. This non-negative portion is then allocated to the corresponding encoding positions according to the proportion of the local response, generating the micro-defect retention feature, where: The micro-defect retention unit includes: Local window index table: records the local windows and corresponding coding positions of grain difference characteristics; Pre-stage energy accumulator: calculates the anomalous energy before downsampling of the local window; Inter-layer mapping table: records the positional mapping relationship from a local window to the next coding layer; Post-stage energy accumulator: calculates the downsampled anomalous energy at the mapped location; Energy Residual Register: Stores the non-negative difference between the abnormal energy before downsampling and the abnormal energy after downsampling; Response Ratio Calculator: Calculates the proportion of local response at each encoding position within a local window; Energy distributor: Distributes energy residuals according to the proportion of local response, generating micro-defect retention features; The processing procedure for micro-defect retention cells is as follows: The local window index table receives the grain difference features with a size of N×H×W×C. According to the H×W encoding position corresponding to each co-location node, a 3×3 encoding position is used as the local window, and it moves along the horizontal and vertical directions with a step size of 2. Adjacent windows overlap by 1 row or 1 column of encoding positions along the moving direction. When the local window formed by the regular movement does not cover the horizontal or vertical end coding position, a boundary local window is constructed with the three end coding positions in the corresponding direction. The uncovered end coding positions are included in the boundary local window, and the corresponding co-node number and coding position of each local window are recorded. The pre-stage energy accumulator takes the absolute value of each channel feature value of the grain difference feature in each local window, and accumulates 3×3×C absolute values ​​to obtain the anomalous energy before downsampling of the corresponding local window; The inter-layer mapping table determines the corresponding position in the next coding layer by dividing the horizontal and vertical indices of the coding position within the local window by r and rounding down according to the downsampling ratio r from the current coding layer to the next coding layer. Duplicate mapping positions are merged to form a mapping window. The coding feature size of the next coding layer is P×Q×D, where P and Q are determined by reducing H and W according to the downsampling ratio r, and D is determined according to the number of output channels of the next coding layer. The subsequent energy accumulator extracts the coding features within the mapping window of the next coding layer, takes the absolute value of the feature values ​​of each coding position and channel and accumulates them to obtain the original energy after downsampling. The original energy after downsampling is multiplied by the ratio of the number of local window elements before downsampling to the number of mapping window elements to obtain the downsampling abnormal energy. The number of local window elements before downsampling is determined by the product of the number of coding positions and C, and the number of mapping window elements is determined by the product of the number of coding positions and D. The energy residual register subtracts the abnormal energy after downsampling from the abnormal energy before downsampling. When the calculation result is greater than 0, the calculation result is recorded; when the calculation result is not greater than 0, 0 is recorded, thus obtaining the abnormal energy residual of the corresponding local window. The response ratio calculator sums the absolute values ​​of the C channel features at each encoding position in the local window to obtain the local response value of the corresponding encoding position. The local response value is then divided by the sum of the local response values ​​of all encoding positions in the local window to obtain the local response ratio. When the sum of all local response values ​​in the local window is 0, the local response ratio of each encoding position is set to 1 / 9. The energy distributor allocates the abnormal energy residual to each encoding position of the local window according to the proportion of the local response. Then, it allocates it to each channel according to the proportion of the absolute value of the grain difference feature of each channel to the sum of the absolute values ​​of the corresponding encoding position channels. When the sum of the absolute values ​​of the corresponding encoding position channels is 0, the allocation ratio of each channel is set to 0. The positive and negative signs of the original channel feature values ​​are written to the corresponding positions. For encoding positions that belong to multiple local windows at the same time, the average value of the allocation results of each window is taken and added element by element with the corresponding grain difference feature to generate a micro-defect retention feature with size N×H×W×C. The parameters of the micro-defect retention unit include local window size, window movement step size, downsampling ratio r, number of co-location nodes N, coding feature height H, coding feature width W, and number of coding channels C. The local window size is set to 3×3, the window movement step size is set to 2, and the downsampling ratio r is determined according to the spatial size of the adjacent coding layers. The defect extension discrimination unit receives micro-defect retention features, calculates the local window response centroid using the micro-defect retention feature response values ​​as weights, calculates the lateral and longitudinal gradients within the local window, and arranges the sum of squared lateral gradients, the sum of the products of lateral and longitudinal gradients, and the sum of squared longitudinal gradients into a 2×2 structure tensor. The eigenvector corresponding to the smallest eigenvalue of the structure tensor is taken as the extension vector. The boundary exit is obtained by intersecting the extension vector with the grain boundary, starting from the response centroid, thus generating the defect extension feature. Where: The defect extension discrimination unit includes: Response coordinate buffer: Stores the local window response value and its corresponding encoded position; Response Centroid Calculator: Calculates the response centroid of a local window; Gradient calculator: calculates the lateral and longitudinal gradients; Structure Tensor Register: Stores 2×2 structure tensors; Eigenvector solver: calculates the eigenvalues ​​and eigenvectors of the structure tensor; Extended Vector Selector: Selects the eigenvector corresponding to the smallest eigenvalue as the extended vector; Grain boundary index table: records the location of the corresponding grain boundary; Boundary Intersection Calculator: Calculates the intersection points of the extended vector and the grain boundary; Extended Feature Writer: Generates defect extended features; The processing procedure of the defect extension discrimination unit is as follows: The response coordinate buffer receives micro-defect retention features of size N×H×W×C, takes the absolute value of the C channel feature values ​​at each encoding position and sums them to obtain the response value at the corresponding encoding position. The response map of size N×H×W is formed by arranging the corresponding node numbers and encoding positions. The 5×5 encoding positions are used as local windows and moved along the horizontal and vertical directions with a step size of 2. When the local window formed by the normal movement does not cover the horizontal or vertical end encoding positions, the boundary local window is constructed with the 5 encoding positions at the end of the corresponding direction. The response centroid calculator multiplies the horizontal and vertical coordinates of each encoded position within the local window by the corresponding response value and sums them up. Then, it divides each of the sums by the sum of all response values ​​within the local window to obtain the horizontal and vertical coordinates of the response centroid. When the sum of all response values ​​within the local window is 0, the local window is marked as a zero response window, and the structure tensor and boundary intersection calculations are not performed on the zero response window. The gradient operator uses the response map as the calculation object. It calculates the difference between the horizontal and vertical adjacent response values ​​for non-boundary encoding positions within the local window, and divides them by 2 to obtain the horizontal and vertical gradients. For the edge encoding positions of the local window, it calculates the corresponding gradient using the unilateral response difference of adjacent encoding positions. The structure tensor register accumulates the squared horizontal gradient, the product of the horizontal and vertical gradients, and the squared vertical gradient within the local window, respectively. The sum of the squared horizontal gradients is written to the first row and first column of the matrix, the sum of the products of the horizontal and vertical gradients is written to the first row and second column and the second row and first column, respectively, and the sum of the squared vertical gradients is written to the second row and second column, forming a 2×2 structure tensor. The eigenvector solver calculates the two eigenvalues ​​of the 2×2 structure tensor and obtains the two-dimensional unit eigenvectors corresponding to each eigenvalue; The stretch vector selector compares the magnitudes of two eigenvalues ​​and selects the unit eigenvector corresponding to the smallest eigenvalue as the stretch vector; The grain boundary index table obtains the grain boundary position based on the grain number corresponding to the co-located node. The horizontal local coordinates of the grain boundary position are scaled according to the ratio of the coded feature width W to the grain region width, and the vertical local coordinates are scaled according to the ratio of the coded feature height H to the grain region height. The grain boundary positions within the range of H×W coded coordinates are obtained, and a set of grain boundary line segments is formed according to the order of connecting the boundary points. The boundary intersection calculator starts from the response centroid and establishes parametric rays along the positive and negative directions of the extension vector. It calculates the intersection points of the parametric rays with the grain boundary line segments, retains the intersection points within the grain boundary line segments, and determines the intersection point with the smallest Euclidean distance to the response centroid as the boundary exit. The extension feature writer skips the zero response window and, according to the co-location node number and local window position, combines the micro-defect retention features, response centroid coordinates, extension vectors and boundary exit coordinates corresponding to the remaining local windows to generate defect extension features; The parameters of the defect extension discrimination unit include the number of co-location nodes N, the height of the encoded feature H, the width of the encoded feature W, the number of encoded channels C, the local window size and the window movement step size. The local window size is set to 5×5, the window movement step size is set to 2, and N, H, W and C are consistent with the size of the input micro-defect retention feature. The cross-grain recovery unit receives defect extension features, determines adjacent grains according to the order of the defect extension features, uses the same-order endpoints of the corresponding boundaries of adjacent grains as boundary start points, calculates the boundary distances from the boundary start points to the boundary exits, uses the ratio of the boundary distance to the corresponding grain boundary length as the boundary parameter, calculates the boundary parameter difference between the corresponding boundaries of adjacent grains and performs a negative exponential transformation to obtain the connection weights, fuses the defect extension features on both sides of the boundary exit according to the connection weights to generate cross-grain recovery features, and generates a wafer defect visual feature package through PP-LiteSeg step-by-step decoding, in which: The transgrain recovery unit includes: Adjacent Grain Index Table: Records adjacent grains corresponding to defect propagation characteristics; Boundary endpoint register: stores the corresponding endpoints of the boundaries of adjacent grains; Boundary Distance Calculator: Calculates the boundary distance from the starting point of the boundary to the exit point of the boundary. Boundary parameter calculator: Calculates the ratio of boundary distance to the corresponding grain boundary length; Parameter difference register: stores the boundary parameter difference between corresponding boundaries of adjacent grains; Connection weight lookup table: Performs negative exponential mapping on the boundary parameter differences to generate connection weights; Boundary Feature Fuder: Fuses micro-defect retention features from the defect extension features on both sides of the boundary exit according to the connection weight; Recovery Feature Writer: Generates cross-grain recovery features; The process of processing trans-grain recovery units is as follows: The adjacent grain index table receives the defect extension characteristics, determines the adjacent grains according to the co-location node number and the local window arrangement order, selects the corresponding boundary between adjacent grains according to the grain row and column coordinates, and writes the corresponding boundary and the two side boundary exits into the adjacent grain index record. The boundary endpoint register obtains the corresponding endpoints of the adjacent grains according to the connection order of the boundary points of the corresponding boundary, determines the corresponding endpoints as the boundary start point, and records the boundary start point, boundary exit and corresponding grain number. The boundary distance calculator connects the boundary points within the H×W coded coordinate range in sequence, starting from the boundary start point and successively accumulating the Euclidean distances of each boundary segment before the boundary segment where the boundary exit is located. Then, it accumulates the Euclidean distance from the starting boundary point of the boundary segment where the boundary exit is located to the boundary exit to obtain the boundary distance. The Euclidean distance of all boundary segments of the corresponding boundary is accumulated along the same boundary point connection sequence to obtain the corresponding grain boundary length. The boundary parameter calculator divides the boundary distance by the corresponding grain boundary length to obtain the boundary parameter with a value range of 0-1, and records the boundary parameter according to the adjacent grains. The parameter difference register pairs the boundary exits on both sides of the corresponding boundary of adjacent grains, calculates the absolute value of the difference between the two boundary parameters in each combination and arranges them in ascending order. When the boundary parameter differences are the same, they are arranged according to the local window arrangement order. The combination that has not been selected on both sides is selected as the boundary exit combination, and the corresponding boundary parameter difference is recorded. The connection weight lookup table quantizes the boundary parameter difference in the range of 0-1 into lookup indices at intervals of 0.001. The lookup table pre-stores the negative exponent values ​​corresponding to each index. The negative exponent values ​​are determined by dividing the boundary parameter difference by the connection attenuation coefficient of 0.10, taking the negative value, and then performing exponential calculation. The connection weight is obtained based on the lookup index. The boundary feature fusion unit determines the corresponding encoding positions on both sides of the adjacent grains based on the boundary exit coordinates. It extracts the C-dimensional micro-defect retention feature vectors corresponding to the encoding positions from the defect extension features on both sides. The micro-defect retention feature vector of the second side is multiplied by the connection weight and added to the micro-defect retention feature vector of the first side. Then, it is divided by 1 and the sum of the connection weights to obtain the first side recovery feature. The micro-defect retention feature vector of the first side is multiplied by the connection weight and added to the micro-defect retention feature vector of the second side. Then, it is divided by 1 and the sum of the connection weights to obtain the second side recovery feature. The first side recovery feature and the second side recovery feature are written into the corresponding boundary exit encoding positions respectively. When the same encoding position corresponds to multiple recovery features, the channel-wise average value of each recovery feature is taken. The recovery feature writer arranges the first-side recovery features and the second-side recovery features according to the co-location node number and the encoding position. For the encoding positions that do not participate in the boundary fusion, the corresponding micro-defect retention features are retained to form cross-grain recovery features with a size of N×H×W×C. The cross-grain recovery features are input into the simple pyramid pooling module of PP-LiteSeg and decoded step by step by the lightweight decoder to generate a wafer defect visual feature package. The parameters of the cross-grain recovery unit include the number of co-location nodes N, the coding feature height H, the coding feature width W, the number of coding channels C, the boundary parameter quantization interval, and the connection attenuation coefficient. The boundary parameter quantization interval is set to 0.001, and the connection attenuation coefficient is set to 0.10. N, H, W, and C are consistent with the coding feature size in the input defect extension feature. The improved PP-LiteSeg model was trained using wafer defect region annotations as supervision information. A joint loss function was used, combining defect segmentation error, co-location node consistency error, micro-defect energy preservation error, defect propagation direction error, and cross-grain boundary continuity error. This function constrained wafer defect segmentation, grain difference features, anomalous energy of adjacent coding layers, defect propagation vector, and cross-grain recovery features, respectively. The parameters of the improved PP-LiteSeg model were updated via backpropagation based on the joint loss function. Training of the improved PP-LiteSeg model was considered complete when the relative change rate of the joint loss value over six consecutive training rounds was no greater than 0.002. The improved PP-LiteSeg model was trained as follows: Wafer defect analysis samples with wafer defect region annotations were divided into training set and validation set in an 8:2 ratio. The training set was input into the improved PP-LiteSeg model in batches of 8 samples each, and the following results were obtained in sequence: grain difference features, anomalous energy before downsampling, anomalous energy after downsampling, defect extension vector, cross-grain recovery features and wafer defect segmentation results. Defect pixels and non-defect pixels are determined based on the marking of the wafer defect region. Corresponding nodes that belong to the same local coordinates and do not fall into the wafer defect region are identified as consistent node combinations. Marked defect regions with a width of no more than 6 pixels are identified as micro-defect regions. Marked defect regions that cross the corresponding boundaries of adjacent grains are recorded. The defect segmentation error is obtained by calculating the binary cross-entropy of the wafer defect segmentation result and the wafer defect region label pixel by pixel and taking the average value. The squared value of the grain difference feature corresponding to the consistent node combination is calculated position by position and the average value is taken to obtain the consistency error of the co-position node. The absolute value of the difference between the abnormal energy before and after downsampling of the local window corresponding to the micro-defect region is calculated and divided by the sum of the abnormal energy before downsampling and 0.000001. The average value of the calculation results of all micro-defect windows is taken to obtain the micro-defect energy preservation error. Based on the pixel coordinates of each defect region in the wafer defect region annotation, the defect region is mapped to the encoded coordinate range corresponding to the defect extension vector. The coordinate covariance matrix of the mapped defect region is calculated, the maximum eigenvalue and the minimum eigenvalue are calculated, the maximum eigenvalue is divided by the sum of the minimum eigenvalue and 0.000001, and defect regions with a calculation result not less than 2 are retained. The unit eigenvector corresponding to the maximum eigenvalue is taken as the annotation extension direction. The absolute value of the inner product of the defect extension vector and the annotation extension direction is calculated. The absolute value is subtracted from 1 and the average value is taken to obtain the defect extension direction error. For the marked defect region that crosses the corresponding boundary of adjacent grains, the cross-grain recovery features of the encoded positions on both sides are extracted according to the corresponding boundary exit combination. The square of the feature difference is calculated for each channel and the average value is taken to obtain the cross-grain boundary continuous error. When there is no consistent node combination, micro-defect region, defect region that meets the calculation conditions of the annotation extension direction, or annotation defect region that crosses the corresponding boundary of adjacent grains in the current training batch, the corresponding co-position node consistency error, micro-defect energy retention error, defect extension direction error, or cross grain boundary continuity error is recorded as 0. The combined loss value is obtained by multiplying the defect segmentation error, co-location node consistency error, micro-defect energy retention error, defect propagation direction error, and cross-grain boundary continuity error by 0.35, 0.20, 0.15, 0.15, and 0.15, respectively. The gradient of the joint loss value relative to the trainable parameters of the improved PP-LiteSeg model is calculated using an initial learning rate of 0.001. The model parameters are updated according to the gradient backpropagation direction. After each training round, the joint loss value is calculated on the validation set. The absolute value of the difference between the current round's joint loss value and the previous round's joint loss value is divided by the sum of the previous round's joint loss value and 0.000001 to obtain the relative change rate of the joint loss value. When the relative change rate of the joint loss value for 6 consecutive training rounds is no greater than 0.002, the training of the improved PP-LiteSeg model is completed. This invention structurally optimizes the traditional PP-LiteSeg model and proposes a method for recognizing visual features of semiconductor wafer defects. While retaining the original encoder, simple pyramid pooling module and lightweight decoder, it introduces a grain difference verification unit, a micro-defect retention unit, a defect extension discrimination unit and a cross-grain recovery unit to form a feature processing structure suitable for wafer micro-defects, slender defects and cross-grain continuous defects. To address the issue that differences in normal texture and local structure between different grains can easily interfere with defect judgment, a grain difference verification unit is introduced. By comparing the consistency between co-located grains, difference features are formed, so that recurring normal structures are uniformly referenced, while local responses that deviate from normal structures are highlighted, thereby improving the ability to distinguish abnormal areas of the wafer. To address the issue of easily attenuated responses to minute defects during downsampling in the coding layer, a minute defect preservation unit is introduced to compensate for abnormal energy changes before and after downsampling, enabling the weak defect responses to be retained in the encoded features and reducing feature loss caused by scale compression of minute defects. To address the issue that scratches and cracks have a clear directionality and are easily interrupted at grain boundaries, a defect extension discrimination unit is introduced. Based on local response changes, the defect extension direction and boundary exit are determined, so that the spatial extension relationship of the defect can be preserved along with the feature, thus improving the continuity of the directional characterization of slender defects. To address the issue that the same defect can easily form separated features when it crosses adjacent grains, a cross-grain recovery unit is introduced. The connection weight is established based on the relative position of the boundary exit of adjacent grains, and the features on both sides of the boundary are fused together, so that the cross-grain defect features corresponding to the position can be re-formed into a continuous expression, thereby improving the overall characterization ability of cross-grain continuous defects. The improved PP-LiteSeg model not only retains the original lightweight encoding and step-by-step decoding capabilities, but also achieves joint modeling of grain structure differences, micro-defect responses, defect extension directions, and cross-grain continuity relationships, which greatly improves the completeness and accuracy of feature extraction and identification of micro-defects, elongated defects, and cross-grain continuity defects in the semiconductor wafer defect identification process.

[0027] In this embodiment, generating wafer defect candidate regions includes: The absolute values ​​of the channel responses at each feature location within the visual feature package of wafer defects are summed to obtain the anomaly response value. The feature location with the largest anomaly response value in its local neighborhood is determined as the anomaly core, where: The core of the anomaly was identified, specifically: The response values ​​of each channel are extracted one by one according to the feature positions in the wafer defect visual feature package. The absolute values ​​of each channel response value are taken and then summed to obtain the abnormal response values ​​of the corresponding feature positions. The abnormal response map is then formed by arranging the values ​​according to the original feature positions. For each feature location, a 3×3 neighborhood is selected. The abnormal response values ​​of the center location are compared with those of the other feature locations in the neighborhood. The center location whose abnormal response value is not less than that of the other locations in the neighborhood is determined as the local maximum location. When multiple local maxima with the same abnormal response value exist within the same 3×3 neighborhood, the first local maximum is retained in the order of increasing vertical coordinate and increasing horizontal coordinate of the feature location. The feature coordinates and abnormal response value of the retained location are recorded and identified as the anomaly core. Centered on the anomaly core, calculate the anomaly response difference between adjacent feature locations relative to the anomaly core. Then, weight the directions corresponding to adjacent feature locations with decreasing anomaly response values ​​according to the anomaly response difference to determine the anomaly feature attenuation direction, where: The direction of anomalous feature attenuation is determined as follows: A 3×3 neighborhood is selected centered on the feature location corresponding to the anomaly core. The eight feature locations other than the anomaly core are taken as adjacent feature locations. The anomaly response value of each adjacent feature location is subtracted from the anomaly response value of the anomaly core to obtain the anomaly response difference. Adjacent feature locations with an anomaly response difference greater than 0 are retained. The corresponding direction vector is determined based on the coordinate difference between the anomaly core and each retained adjacent feature position. The direction vector is divided by the vector length to obtain the unit direction vector, and each unit direction vector is multiplied by the corresponding anomaly response difference. The weighted unit direction vector is accumulated component by component, and then divided by the sum of all abnormal response differences to obtain the attenuation composite vector; Calculate the magnitude of the attenuation synthesis vector. When the magnitude is greater than 0, divide the attenuation synthesis vector by the magnitude to obtain the attenuation direction of the abnormal feature. When the magnitude of the attenuation synthesis vector is 0 and there are adjacent feature positions with an abnormal response difference greater than 0, the unit direction vector corresponding to the adjacent feature position with the largest abnormal response difference is selected as the attenuation direction of the abnormal feature. When the abnormal response differences are the same, they are selected in ascending order of the vertical and horizontal coordinates of the adjacent feature positions. When there are no adjacent feature locations with an abnormal response difference greater than 0, directional expansion is not performed and the corresponding abnormal core is preserved; Along the direction of anomaly feature decay, select feature positions adjacent to the current feature position that have decreasing anomaly response values. Connect the selected feature positions continuously to the anomaly core until there are no more adjacent positions that satisfy the condition of decreasing anomaly response values, forming an anomaly expansion region, where: The abnormal expansion region is formed, specifically: The anomaly core is determined as the initial current feature position. A 3×3 neighborhood is selected around the current feature position. The eight adjacent feature positions other than the current feature position are selected as candidate positions. The anomaly response values ​​of each candidate position are compared with those of the current feature position. Candidate positions with anomaly response values ​​less than those of the current feature position are retained. Calculate the unit direction vector based on the coordinate difference between the current feature position and each retained candidate position. Calculate the inner product of the unit direction vector and the attenuation direction of the abnormal feature. Retain candidate positions with an inner product greater than 0 and select the candidate position with the largest inner product as the next feature position. When the inner products are the same, the candidate position with the largest difference from the current feature position is selected. If the difference in abnormal response is still the same, the candidate position is selected in ascending order of vertical and horizontal coordinates. Connect the next feature position to the current feature position and write it into the extended position sequence. Update the next feature position to the current feature position. Repeat the adjacent position filtering, abnormal response comparison and directional inner product calculation until there are no adjacent feature positions that satisfy the condition of decreasing abnormal response value and directional inner product greater than 0. The abnormal core and each selected feature location are connected sequentially according to the expansion location sequence, and the abnormal core, expansion location sequence and corresponding connection locations are combined to form the abnormal expansion region. When the abnormal core does not form an abnormal feature decay direction, or when there is no adjacent feature position that meets the conditions when the abnormal core is used as the current feature position, the feature position corresponding to the abnormal core is determined as the abnormal expansion region. By comparing the coverage positions of different anomalous expansion regions, anomalous expansion regions with intersecting positions are merged, while non-intersecting anomalous expansion regions are retained to generate wafer defect candidate regions.

[0028] In this embodiment, the generation of wafer defect identification records includes: Extract the outer contour of each wafer defect candidate region, calculate the region centroid according to the contour coordinates, and transform the contour coordinates with the region centroid as the origin. Based on the transformed contour coordinates, a coordinate covariance matrix is ​​constructed. The eigenvector corresponding to the largest eigenvalue is determined as the principal axis direction of the wafer defect candidate region, and the projection endpoints at both ends of the contour are determined along the principal axis direction, where: Determine the projected endpoints at both ends of the contour, specifically as follows: The transformed contour coordinates are arranged according to the horizontal and vertical coordinates respectively. The sum of squares of the horizontal components, the sum of the products of the horizontal and vertical components, and the sum of squares of the vertical components of each contour coordinate are calculated and divided by the number of contour coordinates to form a 2×2 coordinate covariance matrix. Calculate the two eigenvalues ​​of the coordinate covariance matrix and the corresponding two-dimensional unit eigenvectors. Compare the magnitudes of the two eigenvalues ​​and determine the unit eigenvector corresponding to the largest eigenvalue as the principal axis direction of the wafer defect candidate region. When the two eigenvalues ​​are the same, determine the lateral unit vector as the principal axis direction. Calculate the inner product of each contour coordinate with the principal axis direction to obtain the projection value of each contour coordinate in the principal axis direction. Determine the principal axis positions corresponding to the minimum and maximum projection values ​​as the projection positions at both ends. Multiply the minimum and maximum projection values ​​by the horizontal and vertical components of the principal axis direction, respectively, to obtain the horizontal and vertical coordinates of the corresponding projection positions relative to the centroid of the region. Then add the horizontal and vertical coordinates of the centroid of the region to form the projection endpoints at both ends of the contour. When multiple contour coordinates have the same minimum or maximum projection value, the corresponding projection position is retained as the same projection endpoint. Calculate the vertical distance from each contour coordinate to the principal axis, and determine the structural deviation by the ratio of the average vertical distance to the maximum vertical distance. Extend the principal axis outward from the projection endpoint to determine the principal axis extension relationship intersecting with other candidate wafer defect regions, where: The principal axis extension relationship intersecting with the contours of other wafer defect candidate regions is determined as follows: Calculate the vertical distance from each transformed contour coordinate to the principal axis, average all vertical distances to obtain the mean vertical distance, and take the maximum value as the maximum vertical distance. Divide the mean vertical distance by the maximum vertical distance to obtain the structural deviation. When the maximum vertical distance is 0, the structural deviation is recorded as 0. Using the projection endpoints at both ends of the contour as the starting points of the main axis extension, the first extension ray is established along the main axis direction at the projection endpoint corresponding to the maximum projection value, and the second extension ray is established along the opposite direction of the main axis at the projection endpoint corresponding to the minimum projection value. Connect the outer contours of other wafer defect candidate regions according to the coordinates of adjacent contours to form contour segments. Calculate the intersection points of the first and second extended rays with each contour segment, and retain the intersection points that are located in the positive direction of the extended ray and within the range of the corresponding contour segment. Calculate the Euclidean distance from each retained intersection point to the corresponding projection endpoint. When the same extended ray intersects with the outlines of multiple wafer defect candidate regions, select the intersection point with the smallest Euclidean distance to correspond to the wafer defect candidate region. The current wafer defect candidate region and the wafer defect candidate region selected by the first or second extension ray are recorded as a region combination with a principal axis extension relationship. When neither of the two extension rays intersects with the outline of other wafer defect candidate regions, no principal axis extension relationship is established. Candidate wafer defect regions to be merged are determined based on the principal axis extension relationship. The absolute difference between corresponding structural deviations is calculated. For each candidate wafer defect region, the region with the smallest absolute difference is selected. Wafer defect candidate regions with the smallest absolute difference and a principal axis extension relationship are merged to form a merged region. Unmerged wafer defect candidate regions are treated as independent merged regions. The region coordinates and corresponding grains of the merged regions are recorded to generate a wafer defect identification record, wherein: Generate wafer defect identification records, specifically: Based on the principal axis extension relationship, other wafer defect candidate regions that have a principal axis extension relationship with each wafer defect candidate region are gathered to form a set of regions to be merged. Calculate the absolute difference of structural deviation between the candidate regions of wafer defects and each region in the set of regions to be merged. Arrange them in ascending order of absolute difference and select the region with the smallest absolute difference as the corresponding region. When the smallest absolute difference is the same, select the region in ascending order of the vertical and horizontal coordinates of the centroid of the corresponding region. Compare the selection results of each wafer defect candidate region with the corresponding region. When two wafer defect candidate regions have a principal axis extension relationship and are selected as corresponding regions, they are determined to be merged and a merge mark is set. The coverage positions of each wafer defect candidate region in the merged combination are collected and duplicate positions are removed. The region coordinates are arranged according to the outer boundary of the merged region to form the merged region. Wafer defect candidate regions without merge markers retain their original coverage positions and region coordinates, forming independent merge regions; Based on the grain numbers corresponding to the locations covered by the merged and independent merged regions, the corresponding grains are aggregated, duplicate grain numbers are removed, and the grains are arranged according to their row and column coordinates. The region coordinates and corresponding grains of each merged and independent merged region are written into the record entries to generate a wafer defect identification record.

[0029] In this embodiment, generating semiconductor wafer defect identification results includes: Determine the defective grains according to the corresponding grains in the merged regions of the wafer defect identification record; The region coordinates of the merged regions are transformed to the wafer coordinate system according to the mapping relationship between pixel position and wafer coordinates, and the wafer coordinates of each merged region are determined. Extract the extreme values ​​of the horizontal and vertical coordinates of each merged region in the wafer coordinate system, and determine the defect range based on the horizontal and vertical coordinate spans. The morphological characteristics of the merged regions are calculated based on their area, horizontal coordinate span, vertical coordinate span, and cross-grain coverage. Defect categories are determined according to these morphological characteristics. Finally, the defect grains, wafer coordinates, defect ranges, and defect categories are aggregated to generate semiconductor wafer defect identification results, including: The semiconductor wafer defect identification results are generated as follows: The number of wafer coordinate positions covered by each merged region and the independent merged region is counted separately. The number of wafer coordinate positions is multiplied by the wafer coordinate area corresponding to a single mapped position to obtain the region area. The larger of the horizontal and vertical coordinate spans is divided by the sum of the smaller value and 0.000001 to obtain the aspect ratio. The region area is divided by the product of the sum of the horizontal coordinate span and the horizontal dimension of a single mapping position, and the sum of the vertical coordinate span and the vertical dimension of a single mapping position to obtain the region filling ratio. The number of different grain numbers corresponding to this is counted to obtain the number of cross-grain coverages. The region area, aspect ratio, region filling ratio, and number of cross-grain coverages are combined as the region morphological features. When both the horizontal and vertical coordinate spans are 0, the defect category is determined as a point defect. When the number of cross-grain coverages is not less than 2, the defect category is determined as a cross-grain continuous defect; When the cross-grain coverage is 1 and the aspect ratio of the shape is not less than 3, the defect category is determined as a linear defect; When the cross-grain coverage is 1, the aspect ratio of the shape is less than 3, and the region filling ratio is not less than 0.60, the defect category is determined as a block defect. When the cross-grain coverage is 1, the aspect ratio of the shape is less than 3, and the area fill ratio is less than 0.60, the defect category is determined as point defect; According to the recording order of each merged region and independent merged region, the defect grain, wafer coordinates, defect range and defect category are written into the corresponding identification entries, and the identification entries are arranged according to the wafer coordinates to generate semiconductor wafer defect identification results.

[0030] refer to Figure 3 A semiconductor wafer defect identification system based on visual inspection includes the following modules: The wafer vision processing module is used to acquire and process wafer vision images and die position data to generate a wafer vision inspection set. The grain structure construction module is used to register grain regions and construct corresponding lattices for grains; The defect sample generation module is used to organize the local visual regions of co-located nodes and calculate the structural distance to generate wafer defect analysis samples. The defect feature extraction module is used to process wafer defect analysis samples by improving the PP-LiteSeg model and generate a wafer defect visual feature package. The candidate region generation module is used to identify and expand the anomaly core, merge intersecting regions, and generate wafer defect candidate regions. The defect region merging module is used to merge wafer defect candidate regions based on contour, main axis direction and structural deviation, and generate wafer defect identification records. The identification result generation module is used to determine the defective grain, wafer coordinates, defect range, and defect category, and generate semiconductor wafer defect identification results.

[0031] Example 1: To verify the feasibility of this invention in practice, it was applied to a batch of semiconductor wafer visual inspection. The system received visual data from 96 300mm wafers, generating a total of 59,520 grain region images. The original wafer visual images had a resolution of 8192×8192 pixels, with 4,387 manually marked defects, including 1,246 particle defects, 782 local pits, 916 fine cracks, 1,035 scratches, and 408 grain edge breaks. 612 defects crossed adjacent grain boundaries. The effective defect width was mainly distributed between 3 and 18 pixels, with 864 micro-defects having a width not exceeding 6 pixels. The original images exhibited a rotational deviation of −0.42° to 0.38° and a scale deviation of −0.31% to 0.27%.

[0032] The system performs visual correction on one wafer. After edge fitting, the center pixel coordinates are obtained as (4094.6, 4097.2), with an effective radius of 3981.5 pixels. After correction, the rotation residual is reduced from 0.34° to 0.03°, and the scale residual is reduced from 0.26% to 0.04%. A wafer coordinate system is established with the wafer center, and the pixel positions are converted to actual wafer coordinates. This wafer is divided into 621 effective grain regions. The center of grain number 286 is converted from image coordinates (5326, 4018) to wafer coordinates (46.38, −3.01) mm, and the center of grain number 287 is (55.71, −3.04) mm, forming a wafer visual inspection set.

[0033] The system translates the center of each grain to a unified local coordinate origin and corrects the grain region to 512×512 pixels based on the grain boundaries. Taking the local coordinates (184, 227) as an example, six co-located nodes are established among six grains with the same structural position. Grains No. 286 and No. 287 are determined to be adjacent grains according to their row and column relationships, and 512 sets of boundary correspondence relationships are established at the corresponding boundaries of the two grains to form a grain correspondence grid.

[0034] The system aggregates local visual regions from six corresponding nodes along the grain lattice. The average grayscale values ​​of the six local regions in a set of fine scratch samples are 126.8, 127.1, 126.4, 126.9, 118.6, and 127.0, respectively. The edge position difference in normal regions is 0.018–0.023, while that in abnormal regions is 0.164. The texture feature difference in normal regions is 0.028–0.034, while that in abnormal regions is 0.207. The structural distance between five normal corresponding nodes is 0.038–0.061, and the structural distance between abnormal and normal nodes is 0.276–0.308. The system maps these structural distances to corresponding node combinations and arranges the local visual regions according to node connectivity, forming a wafer defect analysis sample.

[0035] After the wafer defect analysis samples are fed into the improved PP-LiteSeg model, the encoder transforms the 512×512 local visual region into a 128×128×64 local visual feature. The grain difference verification unit arranges the structural distances between the six co-located nodes into a 6×6 structural distance matrix. After negative exponential transformation and row-wise normalization, the consistency weights of normal co-located nodes are concentrated between 0.17 and 0.23, while the weight of abnormal nodes is 0.06. After establishing a consistency benchmark and subtracting at each position, the average difference response in the scratch area increases from 0.41 to 0.72, while the normal texture area decreases from 0.19 to 0.08.

[0036] After grain difference features are incorporated into the micro-defect retention unit, the system divides local windows into 8×8 encoding positions. Taking a grain defect with a width of 6 pixels as an example, the anomalous energy before downsampling is 11.84, which decreases to 6.93 after mapping to the next encoding layer, resulting in an energy loss of 4.91. The system allocates the non-negative energy difference to the corresponding encoding position according to the proportion of local response. After compensation, the anomalous energy recovers to 11.21, and the energy retention rate increases from 58.5% to 94.7%.

[0037] Micro-defect retention features are entered into the defect extension discrimination unit. The centroid of the response in the scratch region within grain 286 is (486.2, 301.7), the sum of squared transverse gradients is 3.76, the sum of the products of transverse and longitudinal gradients is 2.04, and the sum of squared longitudinal gradients is 1.69, forming a 2×2 structure tensor. The system takes the eigenvector corresponding to the smallest eigenvalue as the extension vector, obtaining an extension direction of 31.4°. The intersection of the extension direction from the response centroid with the right grain boundary is obtained, yielding the boundary exit (512, 316.9).

[0038] The boundary exit corresponding to the left side of grain 287 is (0, 320.1). The cross-grain recovery unit uses the same-order endpoints of the corresponding boundaries of adjacent grains as the boundary starting points and calculates the boundary distances respectively. The boundary parameters of grains 286 and 287 are 0.619 and 0.625 respectively, with a parameter difference of 0.006. After negative exponential transformation, the connection weight is 0.994. The system fuses the defect extension features on both sides according to the connection weight. After step-by-step decoding by PP-LiteSeg, the scratch that was originally interrupted by 4 pixels at the grain boundary is restored to a continuous abnormal region. The average response on both sides of the boundary is improved from 0.52 and 0.49 to 0.81 and 0.79.

[0039] The system sums the absolute values ​​of the channel responses at each feature location in the wafer defect visual feature package. The maximum abnormal response value of the scratch region is 18.42, and the corresponding location is identified as the core of the abnormality. As the abnormality extends along the decay direction of the abnormal feature, the response at adjacent locations gradually decreases from 16.73 to 2.46, stopping when no adjacent locations satisfy the decreasing condition, forming two abnormal expansion regions. The two abnormal expansion regions have an overlap of 27 pixels, which, after merging, form a single wafer defect candidate region with an area of ​​638 pixels.

[0040] The system extracts the outer contour of candidate defect regions on the wafer, obtaining a total of 146 contour coordinate points, with the centroid of the region at (521.8, 318.6). A coordinate covariance matrix is ​​constructed based on the transformed contour coordinates, with the principal axis corresponding to the largest eigenvalue at 32.0°. The average vertical distance from the contour coordinates to the principal axis is 3.68 pixels, the maximum vertical distance is 16.94 pixels, and the structural deviation is 0.217. The structural deviation between adjacent candidate regions is 0.224, and the absolute difference is 0.007. When the principal axes of two regions extend, they intersect each other's contours. The system merges the two regions into one merged region and records grains numbered 286 and 287 as the corresponding grains.

[0041] After the merged region is transformed to the wafer coordinate system, the defect center coordinates are obtained as (46.52, −3.18) mm, with a lateral coordinate span of 0.151 mm and a longitudinal coordinate span of 0.029 mm, covering two grains. Based on the merged region area, lateral coordinate span, longitudinal coordinate span, and the number of grains covered, the region morphology characteristics are formed, the defect type is determined to be a scratch, and a semiconductor wafer defect identification result containing the defect grain, wafer coordinates, defect range, and defect type is generated.

[0042] The improved PP-LiteSeg model was trained using 14,880 training samples and 3,180 validation samples. The initial joint loss was 1.284, which decreased to 0.462 in round 20, 0.218 in round 40, and 0.119 in round 60. The joint loss values ​​for rounds 82 to 87 were 0.0865, 0.0864, ​​0.0863, 0.0862, 0.0862, and 0.0861, respectively. The relative change rate was no greater than 0.002 for six consecutive rounds, indicating that the model had completed training.

[0043] On the same batch of 3180 test samples, the method of the present invention was compared with the traditional method of using the original PP-LiteSeg to process the grains independently.

[0044] The defect identification accuracy rate of traditional methods is 86.9%, while that of this invention is 94.3%. The traditional method has a defect recall rate of 82.7%, while the present invention has a recall rate of 92.8%. The recall rate for minor defects using traditional methods is 73.8%, while that of this invention is 91.6%. The traditional method achieves a cross-grain continuous defect integrity identification rate of 69.4%, while this invention achieves 94.1%. The traditional method has a repeat defect recording rate of 15.2%, while the present invention has a rate of 3.6%. The average positioning error of wafer coordinates using traditional methods is 18.9 μm, while that of this invention is 7.6 μm.

[0045] Statistical analysis of 864 micro-defects with a width not exceeding 6 pixels showed that traditional methods correctly identified 596 defects, while the present invention correctly identified 783. Statistical analysis of 612 trans-grain continuous defects showed that traditional methods resulted in 181 defects being split into two or more defect records, while the present invention only showed splitting in 34 cases. Furthermore, traditional methods resulted in 96 missed defects at grain boundaries, while the present invention reduced this to 28.

[0046] As can be seen from Example 1, the present invention can generate clear data change results in the analysis of differences in isotopic structure of grains, preservation of abnormal energy of micro-defects, discrimination of defect extension direction, and recovery of continuous features across grains. It can reduce misjudgments caused by normal grain texture differences, reduce the loss of micro-defect features and the splitting of continuous defects across grains, and improve the accuracy of semiconductor wafer defect identification, location and classification.

[0047] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A semiconductor wafer defect identification method based on visual inspection, characterized in that, include: Collect wafer visual images and die position data, correct the wafer visual images and perform wafer coordinate mapping, divide the die regions according to the die position data, and generate a wafer visual inspection set; Register the grain region according to the wafer visual inspection set, establish corresponding nodes according to the corresponding positions of the grain region, connect adjacent nodes according to the row and column relationship of the grain and establish corresponding boundary edges to form a corresponding grain grid; Local visual regions of corresponding nodes along the corresponding lattice of the grain are collected, structural distances are calculated and arranged according to node connection relationships to generate wafer defect analysis samples; The wafer defect analysis samples are input into the improved PP-LiteSeg model, and processed by the grain difference verification unit, micro-defect retention unit, defect extension discrimination unit and cross-grain recovery unit to generate a wafer defect visual feature package. Based on the visual feature package of wafer defects, the abnormal core is determined, and it is expanded along the direction of abnormal feature attenuation. Intersecting regions are merged to generate wafer defect candidate regions. Extract the outline of candidate regions for wafer defects, calculate the principal axis direction and structural deviation, merge candidate regions for wafer defects according to the principal axis extension relationship and structural deviation, and generate wafer defect identification records; Based on the wafer defect identification records, the defective grain, wafer coordinates, defect range, and defect category are determined, and semiconductor wafer defect identification results are generated.

2. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The wafer visual images specifically include wafer surface grayscale images, grain edge images, and grain local texture images; the grain position data specifically includes grain number, grain row and column coordinates, grain center coordinates, grain boundary coordinates, and grain region size.

3. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The generated wafer visual inspection set includes: The wafer edge is fitted based on the wafer visual image to determine the wafer center and effective radius. The rotation and scale deviations of the wafer surface grayscale image, grain edge image and grain local texture image are corrected to generate a corrected wafer visual image. Using the center of the wafer as the origin of the coordinate system, the pixel positions in the corrected wafer visual image are converted into wafer coordinates according to the effective radius, establishing the mapping relationship between pixel positions and wafer coordinates, and generating a wafer coordinate image; Based on the grain number, grain row and column coordinates, grain center coordinates, grain boundary coordinates, and grain region size, the grain boundary is located and the grain region is divided in the wafer coordinate image to generate a grain region set. Collect wafer surface grayscale images, grain edge images, and local grain texture images from the grain region set according to the grain number, retain the corresponding wafer coordinates and grain row and column coordinates, and generate a wafer visual inspection set.

4. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The lattice constituting the grain includes: The grain region is translated to a unified local coordinate system according to the coordinates of the grain center, and the scale of the grain region is corrected according to the grain boundary to obtain the registered grain region; The corresponding positions are determined by the same local coordinates within the registered grain region, and the local visual regions of the corresponding positions of different grains are established as co-position nodes. Based on the row and column coordinates of the grains, adjacent grains are determined, and the corresponding nodes of the adjacent grains are identified as adjacent nodes and connected. Align the boundary positions of adjacent grains, pair the boundary positions according to local coordinates, and establish corresponding boundary edges between the corresponding co-located nodes of the paired boundary positions; Organize corresponding nodes, adjacent nodes, and boundary edges according to the grain row and column relationship to form a grain correspondence lattice.

5. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The generated wafer defect analysis sample includes: Local visual regions are aggregated along the corresponding lattice of the grain according to the same node; Calculate the grayscale difference, edge position difference, and texture feature difference between the local visual regions of the same node, and summarize the grayscale difference, edge position difference, and texture feature difference to obtain the structural distance; The structural distance is mapped to the corresponding node combination involved in the calculation, and the arrangement order of the local visual regions is determined according to the node connection relationship; By combining local visual regions and corresponding structural distances in an ordered manner, wafer defect analysis samples are generated.

6. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The generated wafer defect visual feature package includes: An improved PP-LiteSeg model is constructed, which includes a grain difference verification unit, a micro-defect retention unit, a defect extension discrimination unit, and a cross-grain recovery unit. The grain difference verification unit receives wafer defect analysis samples, converts the local visual regions of co-located nodes into local visual features using the PP-LiteSeg encoder, arranges the structural distances between co-located nodes into a structural distance matrix, performs a negative exponential transformation on the structural distances and normalizes them by row to obtain consistency weights, aggregates the local visual features according to the consistency weights to form a consistency benchmark, and calculates the difference between the local visual features and the consistency benchmark position by position to generate grain difference features. The micro-defect retention unit receives grain difference features, divides local windows according to the coding position, sums the absolute values ​​of the grain difference features within the local window to obtain the anomalous energy before downsampling, maps the local window to the next coding layer according to the downsampling ratio and converts it to the anomalous energy after downsampling, calculates the difference between the anomalous energy before downsampling and the anomalous energy after downsampling and truncates the non-negative part, and allocates the non-negative part to the corresponding coding position according to the local response ratio to generate micro-defect retention features; The defect extension discrimination unit receives micro-defect retention features, calculates the local window response centroid using the micro-defect retention feature response value as weight, calculates the transverse gradient and longitudinal gradient within the local window respectively, arranges the sum of squared transverse gradients, the sum of the product of transverse and longitudinal gradients, and the sum of squared longitudinal gradients into a 2×2 structure tensor, takes the eigenvector corresponding to the smallest eigenvalue of the structure tensor as the extension vector, and obtains the boundary exit by intersecting the extension vector with the grain boundary from the response centroid, thus generating the defect extension feature; The cross-grain recovery unit receives defect extension features, determines adjacent grains according to the order of the defect extension features, takes the same-order endpoints of the corresponding boundaries of adjacent grains as the boundary start points, calculates the boundary distances from the boundary start points to the boundary exits, uses the ratio of the boundary distance to the corresponding grain boundary length as the boundary parameter, calculates the boundary parameter difference between the corresponding boundaries of adjacent grains and performs a negative exponential transformation to obtain the connection weights, fuses the defect extension features on both sides of the boundary exit according to the connection weights to generate cross-grain recovery features, and generates wafer defect visual feature packets by PP-LiteSeg decoding step by step; The improved PP-LiteSeg model was trained using wafer defect region annotations as supervision information. The defect segmentation error, co-location node consistency error, micro-defect energy preservation error, defect propagation direction error, and cross-grain boundary continuity error were combined as a joint loss function to constrain wafer defect segmentation, grain difference features, adjacent coding layer anomalous energy, defect propagation vector, and cross-grain recovery features, respectively. The parameters of the improved PP-LiteSeg model were updated by backpropagation based on the joint loss function. The training of the improved PP-LiteSeg model was completed when the relative change rate of the joint loss value in 6 consecutive training rounds was no greater than 0.

002.

7. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The generated wafer defect candidate region includes: The absolute values ​​of the channel responses at each feature location in the visual feature package of wafer defects are summed to obtain the abnormal response value. The feature location with the largest abnormal response value in the local neighborhood is determined as the abnormal core. Centered on the anomaly core, calculate the anomaly response difference between adjacent feature locations and the anomaly core. Weight the directions corresponding to adjacent feature locations with decreasing anomaly response values ​​according to the anomaly response difference to determine the attenuation direction of the anomaly features. Along the direction of abnormal feature decay, select feature positions that are adjacent to the current feature position and whose abnormal response values ​​decrease step by step. Connect the selected feature positions continuously with the abnormal core until there are no adjacent positions that meet the condition of decreasing abnormal response values, thus forming an abnormal expansion region. By comparing the coverage positions of different anomalous expansion regions, anomalous expansion regions with intersecting positions are merged, while non-intersecting anomalous expansion regions are retained to generate wafer defect candidate regions.

8. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The generated wafer defect identification record includes: Extract the outer contour of each wafer defect candidate region, calculate the region centroid according to the contour coordinates, and transform the contour coordinates with the region centroid as the origin. Based on the transformed contour coordinates, a coordinate covariance matrix is ​​constructed. The eigenvector corresponding to the largest eigenvalue is determined as the principal axis direction of the wafer defect candidate region, and the projection endpoints at both ends of the contour are determined along the principal axis direction. Calculate the vertical distance from each contour coordinate to the principal axis, determine the structural deviation by the ratio of the average vertical distance to the maximum vertical distance, and extend the principal axis outward from the projection endpoint to determine the principal axis extension relationship intersecting with the contours of other wafer defect candidate regions. Based on the principal axis extension relationship, candidate regions of wafer defects to be merged are determined. The absolute difference between the corresponding structural deviations is calculated. For each candidate region of wafer defects, the region with the smallest absolute difference is selected. Wafer defect candidate regions with the smallest absolute difference and principal axis extension relationship are merged to form a merged region. Unmerged wafer defect candidate regions are treated as independent merged regions. The region coordinates and corresponding grains of the merged regions are recorded to generate a wafer defect identification record.

9. The semiconductor wafer defect identification method based on visual inspection according to claim 1, characterized in that, The generated semiconductor wafer defect identification results include: Determine the defective grains according to the corresponding grains in the merged regions of the wafer defect identification record; The region coordinates of the merged regions are transformed to the wafer coordinate system according to the mapping relationship between pixel position and wafer coordinates, and the wafer coordinates of each merged region are determined. Extract the extreme values ​​of the horizontal and vertical coordinates of each merged region in the wafer coordinate system, and determine the defect range based on the horizontal and vertical coordinate spans. The morphological characteristics of the merged region are calculated based on its area, horizontal coordinate span, vertical coordinate span, and cross-grain coverage. The defect category is determined according to the morphological characteristics of the region. The defect grain, wafer coordinates, defect range, and defect category are then aggregated to generate semiconductor wafer defect identification results.

10. A semiconductor wafer defect identification system based on visual inspection, comprising the semiconductor wafer defect identification method based on visual inspection as described in any one of claims 1 to 9, characterized in that, include: The wafer vision processing module is used to acquire and process wafer vision images and die position data to generate a wafer vision inspection set. The grain structure construction module is used to register grain regions and construct corresponding lattices for grains; The defect sample generation module is used to organize the local visual regions of co-located nodes and calculate the structural distance to generate wafer defect analysis samples. The defect feature extraction module is used to process wafer defect analysis samples by improving the PP-LiteSeg model and generate a wafer defect visual feature package. The candidate region generation module is used to identify and expand the anomaly core, merge intersecting regions, and generate wafer defect candidate regions. The defect region merging module is used to merge wafer defect candidate regions based on contour, main axis direction and structural deviation, and generate wafer defect identification records. The identification result generation module is used to determine the defective grain, wafer coordinates, defect range, and defect category, and generate semiconductor wafer defect identification results.

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