A LCD maximum refresh rate detection method and device based on clock pin load voltage polarity flip

Abstract

The application provides an LCD maximum refresh rate detection method and detection device based on clock pin load voltage polarity inversion, a sampling resistor is connected in series between a driving end and an LCD clock pin, a first voltage on the driving end side of the sampling resistor and a second voltage on the LCD clock pin side are synchronously collected by a voltage collection unit, and then a voltage difference between the two ends of the sampling resistor is calculated; a clock signal frequency output from the driving end to the LCD clock pin is gradually increased, a polarity change of the voltage difference is monitored in real time, when the voltage difference is inverted from a positive polarity to a negative polarity, it is determined that the current clock frequency reaches a load bearing limit of an internal clock circuit of the LCD, a clock frequency corresponding to the polarity inversion point is determined as a maximum reliable clock frequency of the LCD, and then a maximum refresh rate of the LCD is calculated according to an LCD resolution parameter. The application takes the voltage polarity inversion feature of the clock pin load response as a judgment basis, and can realize high-precision, automatic and non-invasive LCD maximum refresh rate detection without LCD display pictures.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display testing technology, and in particular to a method and device for detecting the highest refresh rate of an LCD based on the polarity reversal of the load voltage of the clock pin. Background Technology

[0002] Liquid crystal displays (LCDs) are core display devices widely used in consumer electronics, industrial control, automotive displays, medical equipment, and other fields. Their refresh rate is a key indicator of display performance, directly determining the smoothness of the displayed image, the clarity of moving images, and the user's visual experience. Accurately determining the highest refresh rate at which the LCD can operate stably is a crucial prerequisite for ensuring product quality, optimizing driver solutions, and matching application scenarios during the LCD manufacturing, incoming material inspection, quality control, and application solution selection processes.

[0003] Currently, existing methods for detecting the maximum refresh rate of LCDs mainly fall into three categories: The first is the visual observation method, which involves observing the display effect of the LCD at different refresh rates to determine whether there are abnormal phenomena such as flickering, ghosting, or screen tearing, thereby determining the maximum refresh rate. This method has low detection accuracy, high subjectivity, and is greatly affected by the experience and condition of the inspector. It cannot achieve automation or batch testing, and the test results have poor reliability, making it difficult to meet the accuracy requirements of industrial mass production. The second is the parameter manual lookup method, which relies on theoretical parameter manuals provided by LCD chip or panel suppliers to obtain refresh rate indicators. However, the theoretical values ​​often differ significantly from the actual operating limits of the LCD, making it impossible to accurately reflect the refresh rate. The first method reflects the LCD's working ability under real load conditions, and the performance differences between different batches and individuals cannot be reflected by the manual parameters. The second method is the high-frequency instrument testing method, which uses high-speed testing equipment such as oscilloscopes, frequency counters, and logic analyzers to collect the signal waveform of the LCD clock pin. By analyzing the integrity, rising edge, falling edge and other parameters of the waveform, the upper limit of the refresh rate is determined. Although this method has high accuracy, the equipment is expensive and the operation is complicated. It requires professional technicians to debug and interpret the data. Moreover, it can only detect the external waveform characteristics of the clock signal and cannot directly determine whether the internal clock circuit of the LCD is actually latching and working normally. Therefore, it is not suitable for large-scale mass production testing scenarios.

[0004] Furthermore, most existing testing methods rely on the LCD's display function, requiring the LCD to be lit up normally and display a specific test image for testing. This makes them unsuitable for unassembled LCD semi-finished products, returned products with malfunctioning display functions, and modules with backlight failures, significantly limiting the scope of testing application. Simultaneously, existing technologies lack a solution that can reuse a hardware platform with other testing processes such as LCD pin identification and driver testing, leading to the need to deploy multiple different testing devices on the production line, increasing testing costs and space requirements. Therefore, achieving high-precision, automated, and non-invasive testing of LCDs at their highest refresh rates without relying on display functions or using high-speed, expensive instruments has become a key technical challenge for the industry. Summary of the Invention

[0005] Based on this, the present invention provides a method and device for detecting the maximum refresh rate of an LCD based on the polarity reversal of the load voltage of the clock pin. The method uses the voltage polarity reversal characteristics of the load response of the clock pin as the criterion, and can achieve high-precision, automated and non-invasive detection of the maximum refresh rate of an LCD without the need for an LCD display screen or high-speed detection instruments.

[0006] In a first aspect, the present invention provides a method for detecting the highest refresh rate of an LCD based on the polarity reversal of the load voltage on a clock pin, comprising the following steps: A sampling resistor is connected in series between the driving end and the LCD clock pin. The first voltage on the driving end side of the sampling resistor and the second voltage on the LCD clock pin side are synchronously acquired by the voltage acquisition unit, and then the voltage difference across the sampling resistor is calculated. Gradually increase the frequency of the clock signal output from the driving terminal to the LCD clock pin, and monitor the polarity change of the voltage difference in real time; When the voltage difference flips from positive to negative polarity, it is determined that the current clock frequency has reached the load tolerance limit of the internal clock circuit of the LCD, and the clock frequency corresponding to the polarity reversal point is determined as the highest reliable clock frequency of the LCD. The maximum refresh rate of the LCD is calculated based on the LCD resolution parameters and the highest reliable clock frequency.

[0007] In some embodiments, synchronously acquiring the first voltage on the sampling resistor drive side and the second voltage on the LCD clock pin side through the voltage acquisition unit specifically includes: An analog-to-digital converter with a synchronous sampling channel is used, which is connected to the driving end node of the sampling resistor and the LCD clock pin side node, respectively. At each clock frequency test point, the analog-to-digital converter simultaneously samples the voltage of two nodes to obtain the first voltage and the second voltage at the same moment, and converts the sampling result into a digital quantity and outputs it to the driver terminal.

[0008] In some embodiments, real-time monitoring of the polarity change of the voltage difference, and determining that the current clock frequency has reached the load-bearing limit when the voltage difference flips from positive to negative polarity, specifically includes: The voltage difference is calculated by subtracting the driving terminal voltage from the LCD clock pin side voltage. Under low-frequency clock excitation, the voltage difference is positive, indicating that the LCD internal clock circuit is normally latching the clock signal. As the clock frequency is gradually increased, the voltage difference value corresponding to each frequency point is continuously calculated and recorded. When the sign of the voltage difference between two adjacent frequency points changes from positive to negative, it is determined that a voltage difference polarity reversal has occurred, and the frequency boundary corresponding to the reversal interval is determined as the highest reliable clock frequency of the LCD.

[0009] In some embodiments, the physical causes of the positive and negative polarities of the voltage difference are based on a dynamic load model of the LCD clock pin, specifically including: In the low-frequency operating range, the charging and discharging effect of the equivalent input capacitance of the LCD clock pin is dominant, and the dynamic average current satisfies the linear relationship of I=CVccf, where I is the dynamic average current, C is the equivalent input capacitance, Vcc is the driving power supply voltage, and f is the clock frequency. The dynamic average current flows through the sampling resistor to generate a positive voltage difference, and the amplitude of the positive voltage difference increases linearly with the frequency. In the high-frequency limit range, parasitic inductance of PCB traces, signal reflection, and impedance mismatch dominate, the linear growth law of dynamic average current is broken, the reverse voltage drop generated by parasitic inductance cancels out and exceeds the forward voltage drop of the sampling resistor, causing the voltage difference polarity to reverse, indicating that the internal clock circuit of the LCD can no longer latch the clock signal normally.

[0010] In some embodiments, gradually increasing the frequency of the clock signal output from the driver to the LCD clock pin specifically includes: A frequency scanning strategy combining graded coarse scanning and interval fine scanning is adopted. First, a larger frequency step size is used to gradually increase from low frequency to high frequency to quickly locate the frequency interval where polarity reversal occurs. Within the identified polarity reversal frequency range, a fine scan is performed with a small frequency step size to gradually approach and determine the precise polarity reversal point. Both the frequency step size and the scanning direction can be configured via the driver to adapt to the detection requirements of different LCD models.

[0011] In some embodiments, calculating the maximum refresh rate of the LCD based on the LCD resolution parameters and the highest reliable clock frequency specifically includes: Obtain the number of pixels per row and the total number of rows of the LCD under test, and calculate the total number of clock cycles required for a single frame display of the LCD; Dividing the highest reliable clock frequency by the total number of clocks yields the maximum number of frames that the LCD can refresh per second, which is the LCD's highest refresh rate.

[0012] In some embodiments, the method further includes an automated detection process, specifically comprising: The driver automatically configures the sampling parameters and range of the voltage acquisition unit; The driving end automatically outputs clock signals of different frequencies according to a preset frequency sequence, and automatically triggers voltage acquisition at each frequency point; The driver automatically calculates the voltage difference corresponding to each frequency point, automatically determines the polarity reversal point, and automatically calculates the maximum refresh rate. The entire detection process requires no manual intervention.

[0013] In some embodiments, the resistance value of the sampling resistor is in the range of 10 to 100 to ensure that the voltage drop of the sampling resistor is sufficient to be distinguished by the voltage acquisition unit, while not affecting the normal transmission of the LCD clock signal; the voltage acquisition unit adopts an analog-to-digital converter with a precision of 16 bits or higher and a range covering 5V to ensure the sensitivity and accuracy of voltage difference polarity reversal detection.

[0014] In some embodiments, the detection process does not require the LCD to display any image. The maximum refresh rate can be detected solely by the load voltage response characteristics of the clock pin. This is suitable for LCD modules that are not fully assembled, have abnormal display functions, or have their backlight turned off. The sampling resistor is connected in series between the driver and the LCD clock pin, without damaging the original circuit structure of the LCD. After the detection is completed, removing the sampling resistor will restore the LCD to normal operation.

[0015] Secondly, the present invention provides an LCD maximum refresh rate detection device based on clock pin load voltage polarity reversal, comprising: The sampling resistor module is connected in series between the driver terminal and the LCD clock pin to convert the dynamic load current of the LCD clock pin into a detectable voltage signal. The voltage acquisition module is used to synchronously acquire the first voltage on the driving end of the sampling resistor and the second voltage on the LCD clock pin side, and output digital voltage data. The frequency control module is used to gradually increase the frequency of the clock signal output to the LCD clock pin and control the trigger timing of voltage acquisition. The polarity reversal determination module is used to calculate the voltage difference across the sampling resistor and monitor the polarity change of the voltage difference in real time. When the voltage difference reverses from positive to negative polarity, it determines that the current clock frequency has reached the load limit of the internal clock circuit of the LCD and determines the highest reliable clock frequency. The refresh rate calculation module is used to calculate the maximum refresh rate of the LCD based on the LCD resolution parameters and the highest reliable clock frequency.

[0016] Compared with the prior art, the present invention has the following advantages: The present invention provides a method and device for detecting the maximum refresh rate of an LCD based on the polarity reversal of the load voltage of the clock pin. First, a sampling resistor is connected in series between the driving end and the LCD clock pin. The voltage acquisition unit synchronously acquires the first voltage on the driving end side of the sampling resistor and the second voltage on the LCD clock pin side, and then calculates the voltage difference across the sampling resistor. This step, through a simple series sampling resistor and dual-channel synchronous voltage acquisition architecture, converts the dynamic load current change inside the LCD clock pin, which is difficult to observe directly, into a voltage difference signal that can be accurately measured. This provides a quantifiable and acquireable physical quantity basis for subsequent limit determination. Moreover, the entire hardware architecture can be implemented with only a small-value sampling resistor and an ordinary analog-to-digital converter, without the need for high-speed and expensive detection equipment such as oscilloscopes and frequency meters, thus greatly reducing the detection cost.

[0017] Secondly, the frequency of the clock signal output from the driver to the LCD clock pin is gradually increased, and the polarity change of the voltage difference is monitored in real time. When the voltage difference flips from positive to negative polarity, it is determined that the current clock frequency has reached the load tolerance limit of the LCD's internal clock circuit. The clock frequency corresponding to the polarity reversal point is determined as the LCD's highest reliable clock frequency. This step innovatively utilizes the physical transformation law of the load characteristics of the LCD clock pin at different frequencies. In the low-frequency range, the equivalent input capacitance is mainly charged and discharged, the dynamic average current increases linearly with the frequency, and the voltage difference increases positively. In the high-frequency limit range, the parasitic inductance effect and impedance mismatch are mainly present, and the voltage difference polarity reverses. Using the clear physical characteristic of voltage difference polarity reversal as the judgment mark of the load tolerance limit of the LCD's internal clock circuit, it directly reflects the true working state of whether the LCD's internal clock circuit can properly latch the clock signal. This avoids the defect of only detecting the external waveform and being unable to determine whether the internal circuit is working properly. The detection result directly corresponds to the true working limit of the LCD, and the detection accuracy and reliability are significantly improved.

[0018] Then, the maximum refresh rate of the LCD is calculated based on the LCD resolution parameters and the highest reliable clock frequency. This step converts the measured highest reliable clock frequency into an intuitive refresh rate indicator through a fixed quantization relationship between clock frequency and refresh rate, which is convenient for direct use in product specification determination and driver solution selection.

[0019] Furthermore, the detection process of this invention does not require the LCD to display any image. The highest refresh rate detection can be completed solely through the load voltage response characteristics of the clock pin. It is not only applicable to the detection of normal finished LCDs, but also to the detection of LCD modules that are not fully assembled, have abnormal display functions, or have backlight failures, greatly expanding the scope of application of the detection. At the same time, the sampling resistor is connected in series between the driver end and the LCD clock pin, which does not damage the original circuit structure of the LCD. It is a non-invasive detection method. After the detection is completed, the sampling resistor can be removed to restore the normal operation of the LCD. The detection process is safe and non-damaging.

[0020] In summary, the solution of this invention uses the voltage polarity reversal characteristic of the clock pin load response as the core judgment criterion. It can achieve high-precision, automated, and non-invasive detection of the highest refresh rate of LCD without the need for an LCD display screen or high-speed testing instruments. It can be widely used in LCD production testing and quality control in consumer electronics, industrial control, automotive displays and other fields. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is an exemplary flowchart of an LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal, according to some embodiments of the present invention. Figure 2 This is a schematic diagram of the hardware connection structure for detecting the maximum refresh rate of an LCD according to some embodiments of the present invention; Figure 3 This is a schematic diagram illustrating the hardware connection principle for detecting the maximum refresh rate of an LCD according to some embodiments of the present invention; Figure 4 This is a schematic diagram of an LCD maximum refresh rate detection device based on clock pin load voltage polarity reversal, according to some embodiments of the present invention. Figure 5 This is a schematic diagram of a computer device that implements an LCD maximum refresh rate detection method based on the polarity reversal of the clock pin load voltage, according to some embodiments of the present invention. Detailed Implementation

[0022] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings.

[0024] refer to Figure 1 The figure is an exemplary flowchart of an LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal according to some embodiments of the present invention. This LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal mainly includes the following steps: In step 101, a sampling resistor is connected in series between the driving end and the LCD clock pin. The first voltage on the driving end side of the sampling resistor and the second voltage on the LCD clock pin side are synchronously acquired by the voltage acquisition unit, and then the voltage difference across the sampling resistor is calculated.

[0025] In practical implementation, the series sampling resistor between the driver and the LCD clock pin can be implemented in the following way: First, a small-value precision sampling resistor is selected. In this embodiment, a 33µF metal film resistor with a precision of 1% is used. This resistance value balances the requirements of sampling sensitivity and signal integrity. On the one hand, the 33µF resistance can generate a voltage drop sufficient to be distinguished by the analog-to-digital converter under the dynamic load current of the LCD clock pin, ensuring the sensitivity of voltage difference detection. On the other hand, this resistance value is small enough relative to the input impedance of the LCD clock pin to not significantly affect the amplitude and waveform of the clock signal, ensuring... The normal transmission of the LCD clock signal is then performed. The sampling resistor is connected in series between the clock output pin of the driver (in this embodiment, the FPGA is used as the driver) and the clock input pin (SCLK) of the LCD under test. One end of the sampling resistor is connected to the clock output of the FPGA, and the other end is connected to the SCLK pin of the LCD, thus forming a complete clock signal transmission path. In other embodiments, other sampling resistor values ​​can also be used, such as any value in the range of 10 to 100. The specific value can be selected according to the LCD driving voltage, the expected dynamic current range, and the sensitivity of the analog-to-digital converter. No limitation is made here.

[0026] It should be noted that the sampling resistor in this invention refers to a precision resistor element connected in series between the driving terminal and the LCD clock pin, used to convert the dynamic load current of the LCD clock pin into a detectable voltage signal. Its core function is to convert the dynamic current signal, which is difficult to measure directly, into a voltage difference signal that is easy to acquire through Ohm's law, thereby realizing the indirect observation of the load characteristics of the LCD clock pin.

[0027] In some embodiments, reference Figure 2As shown in the figure, this figure is a schematic diagram of the hardware connection structure for detecting the highest refresh rate of an LCD according to some embodiments of the present invention. The figure mainly includes four core components: a driver (FPGA / MCU), a sampling resistor, a voltage acquisition unit (ADC), and the LCD under test. The sampling resistor is connected in series between the clock output terminal of the driver and the SCLK pin of the LCD. The two sampling channels of the voltage acquisition unit are respectively connected to the two ends of the sampling resistor, namely the driver-side node and the LCD-side node. The data output terminal of the voltage acquisition unit is connected to the driver, and the driver controls the sampling and reads the sampling results.

[0028] In some embodiments, the synchronous acquisition of the first voltage on the driving side of the sampling resistor and the second voltage on the LCD clock pin side by the voltage acquisition unit can be achieved by the following steps: An analog-to-digital converter with a synchronous sampling channel is used, which is connected to the driving end node of the sampling resistor and the LCD clock pin side node, respectively. At each clock frequency test point, the analog-to-digital converter simultaneously samples the voltage of two nodes to obtain the first voltage and the second voltage at the same moment, and converts the sampling result into a digital quantity and outputs it to the driver terminal.

[0029] In specific implementation, an analog-to-digital converter (ADC) with a synchronous sampling channel can be used in the following way: An ADC with dual-channel synchronous sampling function is selected. In this embodiment, the AD7606 16-bit synchronous sampling ADC is used. This chip has eight built-in synchronous sampling channels. In this embodiment, two of these channels are connected to the two ends of the sampling resistor. The first channel (CH1) is connected to the node near the driver end of the sampling resistor to acquire the first voltage V1, and the second channel (CH2) is connected to the node near the LCD clock pin of the sampling resistor to acquire the second voltage V2. The AD7606's range is configured to 5V to cover the voltage swing of the clock signal, while ensuring that both positive and negative voltage differences can be accurately acquired. The ADC's digital interface is connected to the driver FPGA via an SPI bus, with the FPGA providing the sampling clock and control signals. In other embodiments, other models of ADCs can also be used, as long as they have synchronous sampling capability and meet the accuracy and range requirements. This is not limited here.

[0030] In specific implementation, the analog-to-digital converter can simultaneously sample the voltages of two nodes at each clock frequency test point in the following way: After the driver adjusts the clock signal frequency to a certain test frequency and stabilizes it, the driver sends a sampling trigger command to the ADC via the SPI bus. After receiving the trigger command, the ADC starts sampling on both channels simultaneously, and synchronously collects the voltages of the two nodes at the same sampling time to ensure that the first voltage V1 and the second voltage V2 are voltage values ​​at exactly the same time, avoiding errors in voltage difference calculation due to sampling time deviation. After sampling is completed, the ADC sends the 16-bit sampling results of the two channels back to the driver via the SPI bus. The driver converts the two digital values ​​into actual voltage values, i.e., the first voltage V1 and the second voltage V2. In other embodiments, other synchronous triggering methods can also be used, such as synchronous sampling with external trigger signals, etc., which are not limited here.

[0031] In specific implementation, the voltage difference across the sampling resistor can be calculated as follows: after the driving end obtains the values ​​of the first voltage V1 and the second voltage V2, the voltage difference V across the sampling resistor is calculated according to the formula V=V2-V1, where V2 is the voltage on the LCD clock pin side and V1 is the voltage on the driving end side. The sign of this voltage difference directly reflects the direction of the voltage drop across the sampling resistor, that is, the flow characteristic of the dynamic current. In the low-frequency normal operating range, since the charging and discharging current of the equivalent input capacitor of the LCD clock pin flows from the driving end through the sampling resistor to the LCD side, the average voltage on the LCD side is slightly lower than that on the driving end side. However, due to the AC characteristics of the clock signal and the charging and discharging effect of the load capacitor, under a specific measurement method, a positive voltage difference characteristic of V2>V1, i.e., V>0, will be presented. This characteristic is a sign that the internal clock circuit of the LCD is working normally. In other embodiments, other voltage difference calculation methods can also be used, as long as the polarity reversal characteristic can be reflected. There is no limitation here.

[0032] It should be noted that the above steps, through a simple series sampling resistor and dual-channel synchronous voltage acquisition architecture, transform the dynamic load current changes inside the LCD clock pin, which are difficult to observe directly, into a voltage difference signal that can be accurately measured. This provides a quantifiable and acquireable physical quantity basis for subsequent limit determination. Moreover, the entire hardware architecture can be implemented with only small-value sampling resistors and ordinary analog-to-digital converters, eliminating the need for high-speed and expensive detection equipment such as oscilloscopes and frequency counters, thus significantly reducing detection costs.

[0033] In step 102, the frequency of the clock signal output from the driving terminal to the LCD clock pin is gradually increased, and the polarity change of the voltage difference is monitored in real time.

[0034] In some embodiments, gradually increasing the frequency of the clock signal output from the driver to the LCD clock pin can be achieved by the following steps: A frequency scanning strategy combining graded coarse scanning and interval fine scanning is adopted. First, a larger frequency step size is used to gradually increase from low frequency to high frequency to quickly locate the frequency interval where polarity reversal occurs. Within the identified polarity reversal frequency range, a fine scan is performed with a small frequency step size to gradually approach and determine the precise polarity reversal point. Both the frequency step size and the scanning direction can be configured via the driver to adapt to the detection requirements of different LCD models.

[0035] In practical implementation, the frequency scanning strategy combining graded coarse scanning and interval fine scanning can be implemented as follows: First, a coarse scanning stage is performed. The driver starts from a low initial frequency, which is set to 5MHz in this embodiment. The frequency is gradually increased with a larger frequency step size, with the coarse scanning step size set to 10MHz. Clock signals at frequencies of 5MHz, 15MHz, 25MHz, and 35MHz are output sequentially. At each frequency point, after the driver stabilizes the output clock signal, it triggers the ADC to perform voltage acquisition and calculate the voltage difference V, while recording the voltage difference value corresponding to that frequency point. The coarse scanning process continues until the voltage difference V at a certain frequency point is detected to become negative, indicating that the polarity reversal occurred in the interval between that frequency point and the previous frequency point. At this point, the coarse scanning stage ends, and the frequency interval in which the polarity reversal occurred is recorded, for example, the previous frequency point is 45MHz. When V is positive and V is negative at the current frequency point of 55MHz, the polarity reversal range is 45MHz to 55MHz. Then, the fine scan stage begins. Within the frequency range located by the coarse scan, a fine scan is performed with a small frequency step size. The fine scan step size is set to 1MHz and gradually increases from the lower limit frequency of the range. Voltage acquisition and voltage difference calculation are performed at each frequency point until the voltage difference changes from positive to negative again. At this point, the precise polarity reversal frequency point can be determined. In this embodiment, the fine scan accuracy can reach the 1MHz level. In other embodiments, the coarse scan step size and the fine scan step size can be flexibly configured according to the actual detection accuracy requirements. For example, the fine scan step size can be further reduced to 0.5MHz or 0.1MHz to obtain higher detection accuracy. The scanning direction can also be configured to scan from high frequency to low frequency, or a more efficient search strategy such as the binary search method can be used. There are no limitations here.

[0036] It should be noted that the frequency scanning strategy in this invention is not limited to the hierarchical scanning method described above. It can also employ various scanning methods such as linear scanning, logarithmic scanning, binary search, and adaptive step size, as long as the clock frequency can be gradually changed and the polarity reversal point can be found. The specific scanning method can be selected according to the balance requirements of detection efficiency and accuracy.

[0037] In some embodiments, real-time monitoring of voltage difference polarity changes can be achieved in the following way: after the driver completes voltage acquisition and voltage difference calculation at each frequency point, it immediately determines the positive or negative polarity of the current voltage difference and stores the frequency value, voltage difference value, and polarity information corresponding to the current frequency point together in the detection data buffer; the driver maintains a historical record of voltage difference polarity, and after each new voltage difference is calculated, it compares it with the voltage difference polarity of the previous frequency point. If a change in polarity from positive to negative is found, the polarity reversal judgment logic is immediately triggered. In other embodiments, other polarity monitoring methods can also be used, such as setting a polarity flag and triggering the reversal judgment through an interrupt, etc., which are not limited here.

[0038] In step 103, when the voltage difference flips from positive to negative polarity, it is determined that the current clock frequency has reached the load tolerance limit of the internal clock circuit of the LCD, and the clock frequency corresponding to the polarity reversal point is determined as the highest reliable clock frequency of the LCD.

[0039] In some embodiments, determining that the current clock frequency has reached the load tolerance limit when the voltage difference flips from positive to negative polarity can be achieved using the following steps: The voltage difference is calculated by subtracting the driving terminal voltage from the LCD clock pin side voltage. Under low-frequency clock excitation, the voltage difference is positive, indicating that the LCD internal clock circuit is normally latching the clock signal. As the clock frequency is gradually increased, the voltage difference value corresponding to each frequency point is continuously calculated and recorded. When the sign of the voltage difference between two adjacent frequency points changes from positive to negative, it is determined that a voltage difference polarity reversal has occurred, and the frequency boundary corresponding to the reversal interval is determined as the highest reliable clock frequency of the LCD.

[0040] In specific implementation, the determination of voltage difference polarity reversal and the determination of the highest reliable clock frequency can be achieved in the following way: First, clarify the definition and polarity meaning of voltage difference. In this embodiment, V = V2 - V1 is used as the voltage difference, where V2 is the voltage on the LCD clock pin side and V1 is the voltage on the drive side. When V > 0, it is positive polarity, and when V < 0, it is negative polarity. Under low-frequency clock excitation, the internal clock circuit of the LCD can latch the clock signal normally. The load characteristic of the clock pin is mainly the charging and discharging of the equivalent input capacitor. At this time, a positive voltage difference is presented across the sampling resistor, that is, V > 0. This positive polarity is the sign of normal operation of the LCD. As the clock frequency gradually increases, the amplitude of the positive voltage difference first increases linearly with the frequency. When the frequency approaches the load limit of the internal clock circuit of the LCD, the growth rate of the voltage difference begins to slow down and fluctuates. Finally, when the frequency exceeds the limit, the voltage difference increases. When the voltage difference exceeds the limit, the polarity of the voltage difference reverses, changing from positive to negative. When the driving terminal detects that the sign of the voltage difference between two adjacent frequency points changes from positive to negative, for example, V1>0 at frequency f1, V2<0 at frequency f2, and f2>f1, it is determined that a voltage difference polarity reversal has occurred within the frequency range of f1 to f2. For determining the highest reliable clock frequency, this embodiment adopts a conservative value selection strategy, determining the frequency corresponding to the last positive polarity before the polarity reversal, i.e., f1, as the highest reliable clock frequency of the LCD, to ensure that the LCD can work stably at this frequency. In other embodiments, an interpolation method can also be used to calculate a more accurate reversal point frequency based on the voltage difference values ​​at both ends of the reversal interval through linear interpolation, or the midpoint of the interval can be taken as the highest reliable clock frequency. The specific value selection method can be selected according to the requirements of detection accuracy and safety margin, and is not limited here.

[0041] In some embodiments, the physical causes of the positive and negative polarities of the voltage difference are based on a dynamic load model of the LCD clock pin, specifically including: In the low-frequency operating range, the charging and discharging effect of the equivalent input capacitance of the LCD clock pin is dominant, and the dynamic average current satisfies the linear relationship of I=CVccf, where I is the dynamic average current, C is the equivalent input capacitance, Vcc is the driving power supply voltage, and f is the clock frequency. The dynamic average current flows through the sampling resistor to generate a positive voltage difference, and the amplitude of the positive voltage difference increases linearly with the frequency. In the high-frequency limit range, parasitic inductance of PCB traces, signal reflection, and impedance mismatch dominate, the linear growth law of dynamic average current is broken, the reverse voltage drop generated by parasitic inductance cancels out and exceeds the forward voltage drop of the sampling resistor, causing the voltage difference polarity to reverse, indicating that the internal clock circuit of the LCD can no longer latch the clock signal normally.

[0042] In practical implementation, the dynamic load model in the low-frequency range can be understood as follows: An input buffer stage circuit exists inside the LCD clock pin, and its input is equivalent to a capacitive load, i.e., an equivalent input capacitor C. In this embodiment, the driving power supply voltage Vcc is 3.3V. When the clock signal frequency is low, the rising and falling edges of the signal are sufficiently short relative to the signal period. The internal clock circuit of the LCD can complete the charging and discharging of the equivalent input capacitor within each clock cycle and properly latch the clock signal. At this time, the dynamic average current I satisfies the formula I=CVccf, where I is the dynamic average current, C is the equivalent input capacitor of the LCD clock pin, Vcc is the driving power supply voltage, and f is the clock frequency. From this formula, it can be seen that when C and Vcc are fixed, the dynamic average current I is positively correlated with the clock frequency f. The ratio, i.e., I increases linearly with f; this dynamic average current flows out from the driving end, through the sampling resistor to the LCD clock pin. According to Ohm's law, a voltage drop corresponding to the current will be generated on the sampling resistor. Since the current direction is from the driving end to the LCD side, under a specific average voltage measurement method, a positive voltage difference of V2>V1, i.e., V>0, will be presented, and the amplitude of the positive voltage difference increases linearly with the frequency. This characteristic indicates that the internal clock circuit of the LCD can flip and latch the clock signal normally, and the LCD can work stably. In this state, the clock signal transmission is smooth and there is no obvious signal reflection interference, which belongs to the stable working range. In other embodiments, the specific value of the equivalent input capacitance C will vary depending on the LCD model, but the linear relationship of I=CVccf generally holds in the low frequency range, and is not limited here.

[0043] In practical implementation, the polarity reversal in the high-frequency limit range can be understood as follows: When the clock signal frequency is gradually increased to the load limit of the LCD's internal clock circuit, the situation changes fundamentally. First, as the frequency increases, the clock signal period shortens, and the proportion of the rising and falling edges in the entire period increases. The parasitic inductance effect of the PCB traces begins to appear, and the impedance of the parasitic inductance to the high-frequency signal increases with the frequency, i.e., XL = 2fL, where XL is the inductive reactance, L is the parasitic inductance, and f is the frequency. Second, when the frequency is high enough, the LCD's internal clock circuit can no longer complete the full charging and discharging of the input capacitor in each cycle, i.e., it cannot properly latch the clock signal. At this time, the load impedance characteristics of the clock pin change, and it is no longer a simple capacitive load, but exhibits complex impedance characteristics. At the same time, the impedance mismatch of the high-frequency signal on the transmission path exacerbates the signal reflection phenomenon, and the reflected wave superimposes with the incident wave. This will result in an abnormal voltage distribution across the sampling resistor. As a result of the combined effects of the above factors, the linear growth law of the dynamic average current I=CVccf is broken. The average current no longer increases linearly with frequency, but instead fluctuates abnormally due to impedance mismatch. More importantly, the reverse voltage drop generated by parasitic inductance and the voltage redistribution caused by signal reflection cancel out or even exceed the forward voltage drop across the sampling resistor, ultimately causing the polarity of the voltage difference across the sampling resistor to reverse, i.e., V=V2-V1<0, or V1>V2. The clock frequency corresponding to this polarity reversal point is the highest reliable clock frequency at which the LCD can operate stably. At this point, the internal clock circuit of the LCD can no longer latch the clock signal normally, and the dynamic average current is also in an unstable state. In other embodiments, the specific frequency point of polarity reversal may vary depending on factors such as LCD model, PCB layout, and driving capability, but the physical characteristic of polarity reversal is universal and is not limited here.

[0044] It should be noted that the above steps innovatively utilize the physical transformation law of the load characteristics of the LCD clock pin at different frequencies, and use the clear physical characteristic of voltage difference polarity reversal as the judgment mark of the load bearing limit of the LCD internal clock circuit. This directly reflects the true working state of whether the LCD internal clock circuit can properly latch the clock signal, avoiding the defect of only detecting the external waveform and being unable to determine whether the internal circuit is working properly. The detection result directly corresponds to the true working limit of the LCD, and the detection accuracy and reliability are significantly improved.

[0045] In step 104, the maximum refresh rate of the LCD is calculated based on the LCD resolution parameters and the highest reliable clock frequency.

[0046] In some embodiments, the maximum refresh rate of the LCD can be calculated based on the LCD resolution parameters and the highest reliable clock frequency using the following steps: Obtain the number of pixels per row and the total number of rows of the LCD under test, and calculate the total number of clock cycles required for a single frame display of the LCD; Dividing the highest reliable clock frequency by the total number of clocks yields the maximum number of frames that the LCD can refresh per second, which is the LCD's highest refresh rate.

[0047] In specific implementation, obtaining the LCD resolution parameters and calculating the total number of clock cycles can be achieved in the following way: First, obtain the resolution parameters of the LCD under test, including the number of pixels per row (horizontal pixels H) and the total number of rows (vertical pixels V). These parameters can be obtained from the LCD's specifications, or by pre-reading the configuration register of the LCD driver chip, or by the operator inputting the configuration parameters into the driver before testing. In this embodiment, an LCD with a resolution of 480272 is used as an example, i.e., the number of pixels per row H=480 and the total number of rows V=272. Then, calculate the total number of clock cycles required for a single frame display. For a typical RGB interface LCD, each pixel corresponds to one clock cycle, so the total number of clock cycles per frame N=HV. In this embodiment, N=480272=130560 clock cycles. In other embodiments, for LCD interface standards that include blanking intervals, the clock cycles corresponding to horizontal blanking and vertical blanking also need to be included in the total number of clock cycles. The specific calculation method is determined according to the LCD's interface type and timing specifications, and is not limited here.

[0048] In practice, the maximum refresh rate can be calculated in the following way: the highest reliable clock frequency f determined in step 103 is used as the reference. max Divide by the total number of clock cycles per frame N to obtain the maximum number of frames that the LCD can refresh per second, i.e., the maximum refresh rate FR. max =f max / N; In this embodiment, it is assumed that the highest reliable clock frequency f is measured. max If the clock speed is 50MHz and the total number of clock cycles per frame is N=130560, then the maximum refresh rate FR is... max =5010 6 / 130560383Hz, which means that the LCD can support a maximum refresh rate of about 383Hz. In other embodiments, the refresh rate calculation formula can be adjusted according to the specific LCD interface type and timing requirements, as long as the correct quantization relationship between clock frequency and refresh rate is established. There is no limitation here.

[0049] It should be noted that the above steps convert the measured highest reliable clock frequency into an intuitive refresh rate indicator through a fixed quantization relationship between clock frequency and refresh rate, which is convenient for direct use in product specification determination and driver solution selection.

[0050] In some embodiments, the method further includes an automated detection process, specifically comprising: The driver automatically configures the sampling parameters and range of the voltage acquisition unit; The driving end automatically outputs clock signals of different frequencies according to a preset frequency sequence, and automatically triggers voltage acquisition at each frequency point; The driver automatically calculates the voltage difference corresponding to each frequency point, automatically determines the polarity reversal point, and automatically calculates the maximum refresh rate. The entire detection process requires no manual intervention.

[0051] In practice, the automated testing process can be implemented as follows: Before testing begins, the operator correctly connects the LCD to be tested to the testing device, and then starts the automatic testing program through the human-machine interface or host computer software on the driver side. After the testing program starts, the driver side first automatically configures the sampling rate, range, channel enable, and other parameters of the ADC via the SPI bus to ensure that the ADC works in the preset optimal state. Then, the driver side turns off the backlight of the LCD (to reduce power consumption and avoid unnecessary display operations), and then, according to the preset frequency scanning strategy, gradually increases the clock frequency from the starting frequency. At each frequency point, the driver side outputs a stable clock signal for a certain period of time (the stabilization time is set to 10ms in this embodiment) to ensure that the clock signal and the internal circuit of the LCD reach a stable state. Then, the ADC is automatically triggered to acquire voltage and read the sampling results. The driver side automatically calculates the voltage of each frequency. The driver calculates the voltage difference V corresponding to each frequency point and stores the frequency value and voltage difference value in the detection data buffer. Simultaneously, it checks for polarity reversal in real time. When a polarity reversal is detected, the driver automatically determines the highest reliable clock frequency according to a preset value selection strategy, then automatically calls the refresh rate calculation formula and calculates the highest refresh rate based on the LCD resolution parameters. Finally, the driver outputs the detection results (including the highest reliable clock frequency, highest refresh rate, and voltage difference data at each frequency point) to the host computer or display interface and generates a detection report. The entire detection process, from startup to result output, is fully automated without manual intervention. The detection time for a single LCD can be controlled within seconds, making it ideal for batch detection scenarios in industrial mass production. In other embodiments, the specific steps and parameters of the automated process can be adjusted according to actual needs, such as adding temperature compensation or averaging multiple measurements. This is not limited here.

[0052] It should be noted that the detection process of this invention does not require the LCD to display any image. The highest refresh rate can be detected solely through the load voltage response characteristics of the clock pin. This method is not only applicable to the detection of normal finished LCDs, but also to the detection of LCD modules that are not fully assembled, have abnormal display functions, or have backlight failures, greatly expanding the scope of application. At the same time, the sampling resistor is connected in series between the driver and the LCD clock pin, which does not damage the original circuit structure of the LCD. This is a non-invasive detection method. After the detection is completed, removing the sampling resistor will restore the LCD to normal operation. The detection process is safe and non-damaging.

[0053] Furthermore, in another aspect of the present invention, in some embodiments, the present invention provides an LCD maximum refresh rate detection device based on the polarity reversal of the clock pin load voltage, referencing... Figure 4 The figure is a schematic diagram of an LCD maximum refresh rate detection device based on clock pin load voltage polarity reversal according to some embodiments of the present invention. This LCD maximum refresh rate detection device includes: a sampling resistor module 401, a voltage acquisition module 402, a frequency control module 403, a polarity reversal determination module 404, and a refresh rate calculation module 405, which are described below: The sampling resistor module 401 is mainly used in series between the driving terminal and the LCD clock pin to convert the dynamic load current of the LCD clock pin into a detectable voltage signal. Voltage acquisition module 402, in this invention, is mainly used to synchronously acquire the first voltage on the driving end of the sampling resistor and the second voltage on the LCD clock pin side, and output digital voltage data; Frequency control module 403: In this invention, frequency control module 403 is mainly used to gradually increase the frequency of the clock signal output to the LCD clock pin and control the triggering timing of voltage acquisition. The polarity reversal determination module 404 in this invention is mainly used to calculate the voltage difference across the sampling resistor, monitor the polarity change of the voltage difference in real time, and determine the current clock frequency reaches the load limit of the internal clock circuit of the LCD when the voltage difference reverses from positive to negative polarity, and determine the highest reliable clock frequency. The refresh rate calculation module 405 in this invention is mainly used to calculate the maximum refresh rate of the LCD based on the LCD resolution parameters and the highest reliable clock frequency.

[0054] Each module in the aforementioned LCD maximum refresh rate detection device based on clock pin load voltage polarity reversal can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the detection device in hardware form or independent of it, or stored in the memory of the detection device in software form, so that the processor can call and execute the corresponding operations of each module.

[0055] In another embodiment, the present invention provides a computer device, which may be an embedded processor or an industrial control computer, and its internal structure diagram may be as follows. Figure 5As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores historical data and configuration parameters for LCD detection. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a method for detecting the highest refresh rate of an LCD based on the polarity reversal of the clock pin load voltage.

[0056] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0057] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above embodiment of the LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal.

[0058] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above embodiment of the LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal.

[0059] In one embodiment, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the computer device to perform the steps in the above embodiment of the LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal.

[0060] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0061] Working principle of the invention: The working principle of this invention is based on the load characteristics of the LCD clock pin and the physical laws of high-frequency signal transmission. The core is to determine the stable operating limit of the LCD's internal clock circuit by detecting the voltage difference (V) change characteristics across the sampling resistor under clock signal excitation, and then calculate the maximum refresh rate that the LCD can support. Figure 3 The specific working principle is as follows: 1. Hardware connection principle: A small-value sampling resistor (33 in this embodiment) is connected in series between the driver end (such as FPGA / MCU) and the LCD clock pin (SCLK). This resistor is used to collect the voltage drop corresponding to the dynamic load current of the LCD clock pin. A common ADC (such as AD7606, 16-bit, 5V range) is used to synchronously collect the voltage across the sampling resistor, which is recorded as V1 (voltage on the driver side) and V2 (voltage on the LCD clock pin side). The ADC converts the analog voltage signal into a digital signal and transmits it to the driver end for data processing.

[0062] 2. Load Response Characteristics Principle: The LCD clock pin contains an input capacitor and a driving circuit, forming a specific load model. Its dynamic load current can be quantified and described by the following formula: Where I is the dynamic average current of the LCD clock pin, C is the equivalent input capacitance of the LCD clock pin, Vcc is the drive power supply voltage, and f is the clock signal frequency. Under low-frequency clock signal excitation (e.g., 5MHz~20MHz), the load model is mainly based on capacitor charging and discharging, and the dynamic average current I output by the drive terminal increases linearly with the increase of clock frequency f (from the formula). It can be seen that, with C (equivalent capacitance of the LCD clock pin) and Vcc (drive power supply voltage 3.3V) fixed, the dynamic average current I is directly proportional to the clock frequency f, i.e., I increases linearly with f. This dynamic average current flows to the LCD clock pin through the sampling resistor, according to Ohm's law... A positive voltage difference (V=V2-V1>0) corresponding to the average current will be generated across the sampling resistor. As the clock frequency increases and the average current increases, this positive voltage difference will also increase. This characteristic indicates that the internal clock circuit of the LCD can flip and latch the clock signal normally, and the LCD can work stably. In this state, the clock signal transmission is smooth and there is no signal reflection interference, which is within the stable operating range.

[0063] 3. Limit Determination Principle: When the clock signal frequency is gradually increased to the load limit of the LCD's internal clock circuit, the parasitic inductance of the PCB traces, signal reflection, and impedance mismatch effects begin to dominate. At this point, the equivalent input capacitance C of the LCD clock pin changes, and the dynamic average current... The changing pattern is broken; the average current no longer increases linearly with frequency, but instead fluctuates abnormally due to impedance mismatch. Simultaneously, the reverse voltage drop generated by the parasitic inductance cancels out or even exceeds the forward voltage drop across the sampling resistor, causing the polarity of the voltage difference across the sampling resistor to reverse (V=V2-V1<0), i.e., V1>V2. The clock frequency corresponding to this polarity reversal point is the highest reliable clock frequency at which the LCD can operate stably. At this point, the internal clock circuit of the LCD can no longer properly latch the clock signal, and the dynamic average current is also in an unstable state, as shown in the table below: 4. Refresh Rate Calculation Principle: The refresh rate of an LCD has a fixed quantization relationship with the clock frequency. The refresh rate is equal to the highest reliable clock frequency divided by the LCD resolution (number of pixels per row and total number of rows). After determining the highest reliable clock frequency through the above steps, the highest refresh rate that the LCD can support can be accurately calculated by substituting it into this quantization relationship.

[0064] Detailed automated testing process: 1. Correctly connect the FPGA, ADC acquisition board, LCD, and power supply. 2. Configure the FPGA ADC, turn off the LCD backlight, start the automatic test program and send clock signals of different lengths and levels such as 5MHz, 10MHz, 20MHz, 50MHz, 75MHz, and 100MHz respectively. At the same time, sample V1 and V2 at different frequencies. The frequency value corresponding to the abrupt change (from positive to negative) of V=V2-V1 is used as the final highest driving clock frequency.

[0065] 3. The frequency step and the direction of frequency increase / decrease are configurable, thereby achieving the effect of automatically sending test waveforms and automatically judging test results.

[0066] The entire process does not require the LCD to display any image or rely on high-speed testing instruments. Through simple hardware connection and voltage difference characteristic judgment, it can achieve automated and accurate detection of the LCD's highest refresh rate. Furthermore, it can reuse hardware with LCD pin recognition solutions, balancing detection accuracy and cost control.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The technical solutions provided by the embodiments disclosed in this invention have the following beneficial effects: The present invention provides a method and device for detecting the maximum refresh rate of an LCD based on the polarity reversal of the load voltage of the clock pin. First, a sampling resistor is connected in series between the driving end and the LCD clock pin. The voltage acquisition unit synchronously acquires the first voltage on the driving end side of the sampling resistor and the second voltage on the LCD clock pin side, and then calculates the voltage difference across the sampling resistor. This step, through a simple series sampling resistor and dual-channel synchronous voltage acquisition architecture, converts the dynamic load current change inside the LCD clock pin, which is difficult to observe directly, into a voltage difference signal that can be accurately measured. This provides a quantifiable and acquireable physical quantity basis for subsequent limit determination. Moreover, the entire hardware architecture can be implemented with only a small-value sampling resistor and an ordinary analog-to-digital converter, without the need for high-speed and expensive detection equipment such as oscilloscopes and frequency meters, thus greatly reducing the detection cost.

[0069] Secondly, the frequency of the clock signal output from the driver to the LCD clock pin is gradually increased, and the polarity change of the voltage difference is monitored in real time. When the voltage difference flips from positive to negative polarity, it is determined that the current clock frequency has reached the load tolerance limit of the LCD's internal clock circuit. The clock frequency corresponding to the polarity reversal point is determined as the LCD's highest reliable clock frequency. This step innovatively utilizes the physical transformation law of the load characteristics of the LCD clock pin at different frequencies. In the low-frequency range, the equivalent input capacitance is mainly charged and discharged, the dynamic average current increases linearly with the frequency, and the voltage difference increases positively. In the high-frequency limit range, the parasitic inductance effect and impedance mismatch are mainly present, and the voltage difference polarity reverses. Using the clear physical characteristic of voltage difference polarity reversal as the judgment mark of the load tolerance limit of the LCD's internal clock circuit, it directly reflects the true working state of whether the LCD's internal clock circuit can properly latch the clock signal. This avoids the defect of only detecting the external waveform and being unable to determine whether the internal circuit is working properly. The detection result directly corresponds to the true working limit of the LCD, and the detection accuracy and reliability are significantly improved.

[0070] Then, the maximum refresh rate of the LCD is calculated based on the LCD resolution parameters and the highest reliable clock frequency. This step converts the measured highest reliable clock frequency into an intuitive refresh rate indicator through a fixed quantization relationship between clock frequency and refresh rate, which is convenient for direct use in product specification determination and driver solution selection.

[0071] Furthermore, the detection process of this invention does not require the LCD to display any image. The highest refresh rate detection can be completed solely through the load voltage response characteristics of the clock pin. It is not only applicable to the detection of normal finished LCDs, but also to the detection of LCD modules that are not fully assembled, have abnormal display functions, or have backlight failures, greatly expanding the scope of application of the detection. At the same time, the sampling resistor is connected in series between the driver end and the LCD clock pin, which does not damage the original circuit structure of the LCD. It is a non-invasive detection method. After the detection is completed, the sampling resistor can be removed to restore the normal operation of the LCD. The detection process is safe and non-damaging.

[0072] In summary, the solution of this invention uses the voltage polarity reversal characteristic of the clock pin load response as the core judgment criterion. It can achieve high-precision, automated, and non-invasive detection of the highest refresh rate of LCD without the need for an LCD display screen or high-speed testing instruments. It can be widely used in LCD production testing and quality control in consumer electronics, industrial control, automotive displays and other fields.

[0073] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for detecting the highest refresh rate of an LCD based on the polarity reversal of the load voltage on a clock pin, characterized in that, Includes the following steps: A sampling resistor is connected in series between the driving end and the LCD clock pin. The first voltage on the driving end side of the sampling resistor and the second voltage on the LCD clock pin side are synchronously acquired by the voltage acquisition unit, and then the voltage difference across the sampling resistor is calculated. Gradually increase the frequency of the clock signal output from the driving terminal to the LCD clock pin, and monitor the polarity change of the voltage difference in real time; When the voltage difference flips from positive to negative polarity, it is determined that the current clock frequency has reached the load tolerance limit of the internal clock circuit of the LCD, and the clock frequency corresponding to the polarity reversal point is determined as the highest reliable clock frequency of the LCD. The maximum refresh rate of the LCD is calculated based on the LCD resolution parameters and the highest reliable clock frequency.

2. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that, The synchronous acquisition of the first voltage on the sampling resistor drive side and the second voltage on the LCD clock pin side by the voltage acquisition unit specifically includes: An analog-to-digital converter with a synchronous sampling channel is used, which is connected to the driving end node of the sampling resistor and the LCD clock pin side node, respectively. At each clock frequency test point, the analog-to-digital converter simultaneously samples the voltage of two nodes to obtain the first voltage and the second voltage at the same moment, and converts the sampling result into a digital quantity and outputs it to the driver terminal.

3. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that, Real-time monitoring of the polarity change of the voltage difference, determining that the current clock frequency has reached the load-bearing limit when the voltage difference flips from positive to negative polarity specifically includes: The voltage difference is calculated by subtracting the driving terminal voltage from the LCD clock pin side voltage. Under low-frequency clock excitation, the voltage difference is positive, indicating that the LCD internal clock circuit is normally latching the clock signal. As the clock frequency is gradually increased, the voltage difference value corresponding to each frequency point is continuously calculated and recorded. When the sign of the voltage difference between two adjacent frequency points changes from positive to negative, it is determined that a voltage difference polarity reversal has occurred, and the frequency boundary corresponding to the reversal interval is determined as the highest reliable clock frequency of the LCD.

4. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that, The physical cause of the positive and negative polarities of the voltage difference is based on the dynamic load model of the LCD clock pin, specifically including: In the low-frequency operating range, the charging and discharging effect of the equivalent input capacitance of the LCD clock pin is dominant, and the dynamic average current satisfies the linear relationship of I=CVccf, where I is the dynamic average current, C is the equivalent input capacitance, Vcc is the driving power supply voltage, and f is the clock frequency. The dynamic average current flows through the sampling resistor to generate a positive voltage difference, and the amplitude of the positive voltage difference increases linearly with the frequency. In the high-frequency limit range, parasitic inductance of PCB traces, signal reflection, and impedance mismatch dominate, the linear growth law of dynamic average current is broken, the reverse voltage drop generated by parasitic inductance cancels out and exceeds the forward voltage drop of the sampling resistor, causing the voltage difference polarity to reverse, indicating that the internal clock circuit of the LCD can no longer latch the clock signal normally.

5. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that, Gradually increasing the frequency of the clock signal output from the driver to the LCD clock pin specifically includes: A frequency scanning strategy combining graded coarse scanning and interval fine scanning is adopted. First, a larger frequency step size is used to gradually increase from low frequency to high frequency to quickly locate the frequency interval where polarity reversal occurs. Within the identified polarity reversal frequency range, a fine scan is performed with a small frequency step size to gradually approach and determine the precise polarity reversal point. Both the frequency step size and the scanning direction can be configured via the driver to adapt to the detection requirements of different LCD models.

6. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that, The maximum refresh rate of the LCD is calculated based on the LCD resolution parameters and the highest reliable clock frequency, specifically including: Obtain the number of pixels per row and the total number of rows of the LCD under test, and calculate the total number of clock cycles required for a single frame display of the LCD; Dividing the highest reliable clock frequency by the total number of clocks yields the maximum number of frames that the LCD can refresh per second, which is the LCD's highest refresh rate.

7. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that, The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal also includes an automated detection process, specifically including: The driver automatically configures the sampling parameters and range of the voltage acquisition unit; The driving end automatically outputs clock signals of different frequencies according to a preset frequency sequence, and automatically triggers voltage acquisition at each frequency point; The driver automatically calculates the voltage difference corresponding to each frequency point, automatically determines the polarity reversal point, and automatically calculates the maximum refresh rate. The entire detection process requires no manual intervention.

8. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that: The resistance value of the sampling resistor is in the range of 10 to 100 to ensure that the voltage drop of the sampling resistor is sufficient to be distinguished by the voltage acquisition unit, while not affecting the normal transmission of the LCD clock signal. The voltage acquisition unit uses an analog-to-digital converter with a precision of 16 bits or higher and a range covering 5V to ensure the sensitivity and accuracy of voltage difference polarity reversal detection.

9. The LCD maximum refresh rate detection method based on clock pin load voltage polarity reversal as described in claim 1, characterized in that: The detection process does not require the LCD to display any image. The highest refresh rate can be detected only by the load voltage response characteristics of the clock pin. It is suitable for LCD modules that are not fully assembled, have abnormal display functions, or have the backlight off. The sampling resistor is connected in series between the driver and the LCD clock pin, without damaging the original circuit structure of the LCD. After the test is completed, removing the sampling resistor will restore the LCD to normal operation.

10. A device for detecting the highest refresh rate of an LCD based on the polarity reversal of the load voltage on a clock pin, characterized in that, include: The sampling resistor module is connected in series between the driver terminal and the LCD clock pin to convert the dynamic load current of the LCD clock pin into a detectable voltage signal. The voltage acquisition module is used to synchronously acquire the first voltage on the driving end of the sampling resistor and the second voltage on the LCD clock pin side, and output digital voltage data. The frequency control module is used to gradually increase the frequency of the clock signal output to the LCD clock pin and control the trigger timing of voltage acquisition. The polarity reversal determination module is used to calculate the voltage difference across the sampling resistor and monitor the polarity change of the voltage difference in real time. When the voltage difference reverses from positive to negative polarity, it determines that the current clock frequency has reached the load limit of the internal clock circuit of the LCD and determines the highest reliable clock frequency. The refresh rate calculation module is used to calculate the maximum refresh rate of the LCD based on the LCD resolution parameters and the highest reliable clock frequency.

Images