Gate driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving modules. Each gate driving module comprises a first abnormality detection unit configured to transmit a signal state on a driving control node to at least one detection line in a scanning phase of a current stage; and a second abnormality detection unit configured to transmit a signal state on a noise reduction control node to at least one detection line in a non-scanning phase of the current stage, so that a subsequent stage load determines whether an abnormality exists in the gate driving module of the current stage according to output signals of the at least one detection line in the scanning phase and the non-scanning phase. Therefore, the application guides the signal states of key nodes in the gate driving modules of all stages to the detection lines by arranging the first abnormality detection unit and the second abnormality detection unit in each gate driving module, and thus realizes accurate positioning of a fault position of a GOA unit without damaging the panel.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In the display panel, the Gate Driver on Array (GOA) circuit implements line-by-line scanning drive through multiple cascaded GOA units, with each GOA unit outputting a corresponding line scan signal (Gn). When a display malfunction occurs, it is necessary to locate the faulty GOA unit for fault analysis.

[0003] Currently, the common method is to break the glass of the color filter substrate to expose the GOA region, and then use an oscilloscope probe to probe the corresponding position. However, this method is cumbersome, and the GOA region is easily damaged during the breaking process. Inaccurate measurement signals may occur because the ITO traces in the GOA region are short-circuited with the ITO layer on the color filter substrate. Furthermore, the destructive nature of the experiment renders the sample unusable, resulting in wasted costs.

[0004] Therefore, how to accurately locate the fault position of the GOA unit without damaging the panel is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a gate driving circuit and a display panel. By setting a first abnormality detection unit and a second abnormality detection unit in each stage of the gate driving module, the signal status of key nodes in each stage of the gate driving module is guided to the detection line, thereby achieving accurate location of GOA unit faults without damaging the panel.

[0006] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules and at least one detection line; the nth-stage gate driving module includes: a pre-charge unit, connected to the stage transmission output terminal of the nith-stage gate driving module and the drive control node of the current stage, configured to: pre-charge the drive control node of the current stage in response to the stage transmission signal output by the nith-stage gate driving module; an output unit, connected to the drive control node and the clock signal line corresponding to the current stage, configured to: output the stage transmission signal and the gate driving signal of the current stage in response to the clock signal output by the clock signal line and the voltage on the drive control node; and a noise reduction unit, connected to the drive output terminal of the drive control node and the output unit. The system is configured to: perform noise reduction on the drive control node and the drive output during the non-scanning phase of the current stage; a first anomaly detection unit, connected to the at least one detection line and the drive control node, is configured to: transmit the signal state on the drive control node to the at least one detection line during the scanning phase of the current stage; a second anomaly detection unit, connected to the at least one detection line and the noise reduction control node in the noise reduction unit, is configured to: transmit the signal state on the noise reduction control node to the at least one detection line during the non-scanning phase of the current stage, so that the subsequent load can determine whether there is an anomaly in the current stage gate drive module based on the output signals of the at least one detection line during the scanning phase and the non-scanning phase.

[0007] Secondly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the drive output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0008] The technical solutions provided in this application have at least the following beneficial effects: This application sets up a first anomaly detection unit and a second anomaly detection unit in each stage of the gate drive module. The first anomaly detection unit transmits the signal status of the drive control node to at least one detection line during the scanning phase, and the second anomaly detection unit transmits the signal status of the noise reduction control node to at least one detection line during the non-scanning phase. This allows the subsequent load to determine the working status of the drive control node and the noise reduction control node based on the output signals of at least one detection line at different times, thereby determining whether there is an anomaly in the current stage gate drive module. This achieves accurate location of the gate drive unit fault without damaging the panel, reduces detection costs, and improves the efficiency and accuracy of fault analysis. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0010] Figure 1 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0011] Figure 2 The diagram shown is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0012] Figure 3 The diagram shown is a circuit diagram of the first type of gate driving module provided in an embodiment of this application.

[0013] Figure 4 The diagram shown is a first timing diagram provided in an embodiment of this application.

[0014] Figure 5 The diagram shown is a second timing diagram provided in an embodiment of this application.

[0015] Figure 6 The diagram shown is a circuit diagram of a second type of gate driving module provided in an embodiment of this application.

[0016] Figure 7 The diagram shown is a circuit diagram of a third type of gate driving module provided in an embodiment of this application.

[0017] Figure 8 The diagram shown is a circuit diagram of the fourth gate driving module provided in the embodiment of this application.

[0018] Figure 9 The diagram shown is a third timing diagram provided in the embodiments of this application.

[0019] Figure 10 The diagram shown is a fourth timing diagram provided in the embodiments of this application.

[0020] Figure 11 The diagram shown is a fifth timing diagram provided in the embodiments of this application.

[0021] Figure 12 The diagram shown is a circuit diagram of the fifth gate driving module provided in the embodiment of this application.

[0022] Figure 13 The diagram shown is a circuit diagram of the sixth gate driving module provided in the embodiment of this application.

[0023] Figure 14The diagram shown is a sixth timing diagram provided in the embodiments of this application.

[0024] Figure 15 The diagram shown is a circuit diagram of the seventh gate driving module provided in the embodiments of this application.

[0025] Figure 16 The diagram shown is a seventh timing diagram provided in the embodiments of this application.

[0026] Figure 17 The diagram shown is a circuit diagram of the eighth gate driving module provided in the embodiment of this application.

[0027] Figure 18 The figure shown is an eighth timing diagram provided in the embodiments of this application.

[0028] Explanation of reference numerals in the attached figures: 10. Gate drive circuit; 100, Gate driving module; 110, Precharge unit; 120, Output unit; 130, Noise reduction unit; 140, First anomaly detection unit; 150, Second anomaly detection unit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; C1, storage capacitor; Qn, drive control node; Gn, drive output terminal; Pn, noise reduction control node; Fn, stage transmission output terminal; An, first node; Bn, second node; Cn, third node; SW1, first detection control terminal; SW2, second detection control terminal; SW3, third detection control terminal; CF1, first detection line; CF2, second detection line; CF3, third detection line; LC, noise reduction control terminal; VSS, low level terminal. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0030] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0031] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0032] Figure 1 The diagram shows a schematic of a gate driving circuit 10 according to an embodiment of this application. The gate driving circuit 10 of this embodiment includes N cascaded gate driving modules 100 and at least one detection line. The detection line is used to transmit the status signal inside the gate driving module 100 to the subsequent load, so that the subsequent load can determine the operating state of the gate driving module 100. Figure 1 As shown, in this embodiment, each gate driving module 100 includes a pre-charge unit 110, an output unit 120, a noise reduction unit 130, a first anomaly detection unit 140, and a second anomaly detection unit 150.

[0033] Specifically, for the nth-stage gate drive module 100, the pre-charge unit 110 is connected to the stage transmission output terminal of the nith-stage gate drive module and the current-stage drive control node Qn, respectively. It is used to pre-charge the current-stage drive control node Qn in response to the stage transmission signal output by the nith-stage gate drive module; that is, when the stage transmission signal from the previous stage or multiple stages arrives, the current-stage drive control node Qn is pre-charged, allowing the voltage of this node to be established in advance, preparing for the subsequent output stage. It should be noted that in this embodiment, n is a variable, and N and i are constants. The value range of n is [1, 2, ..., N], and the value of i can be 2, 3, or 4. Figure 1 In this context, Fn-i represents the stage output terminal of the ni-th stage gate drive module.

[0034] In some embodiments, the output unit 120 is connected to the drive control node Qn and the clock signal line corresponding to the current stage, respectively, and is used to output the stage transmission signal and the gate drive signal of the current stage in response to the clock signal output from the clock signal line and the voltage on the drive control node Qn; that is, after the voltage of the drive control node Qn is established, in response to the clock signal provided by the clock signal line, the clock signal is output as the gate drive signal of the current stage to the pixel array of the display panel to drive the pixels of the corresponding row to turn on, and at the same time, the clock signal is also output as the stage transmission signal to the gate drive module 100 of the next stage or multiple stages below, as the input trigger signal of the precharge unit 110.

[0035] In this embodiment, the noise reduction unit 130 is connected to both the drive control node Qn and the drive output terminal Gn of the output unit 120, and is used to reduce noise in the drive control node Qn and the drive output terminal Gn during the non-scanning phase of the current stage. The noise reduction in this embodiment maintains the drive control node Qn and the drive output terminal Gn at a stable low level to prevent transistors from being mistakenly turned on due to coupling interference or charge leakage. The noise reduction unit 130 internally has a noise reduction control node Pn, whose voltage is opposite to that of the drive control node Qn. That is, when the drive control node Qn is high, the noise reduction control node Pn is low; when the drive control node Qn is low, the noise reduction control node Pn is high. This complementary voltage relationship ensures that the noise reduction unit 130 can intervene and operate at appropriate times.

[0036] In this embodiment, the first anomaly detection unit 140 is connected to the detection line and the drive control node Qn, and is used to transmit the signal state of the drive control node Qn to the detection line during the scanning phase of the current stage. That is, when the stage is in the selected scanning period, the drive control node Qn is at a high level, and the first anomaly detection unit 140 reflects this high-level state to the detection line. The second anomaly detection unit 150 is connected to the detection line and the noise reduction control node Pn, and is used to transmit the signal state of the noise reduction control node Pn to the detection line during the non-scanning phase of the current stage. That is, when the stage is in the unselected non-scanning period, the noise reduction control node Pn is at a high level, and the second anomaly detection unit 150 reflects this high-level state to the detection line.

[0037] Therefore, the detection line exhibits signal states corresponding to the drive control node Qn and the noise reduction control node Pn during the scanning and non-scanning phases, respectively. Under normal operation, the drive control node Qn and the noise reduction control node Pn are strictly alternately turned on; they cannot both be high or low simultaneously. Thus, the output signal of the detection line during the scanning and non-scanning phases follows a definite and predictable pattern. The downstream load continuously monitors the output signal of the detection line throughout the scanning phase. If the signal state on the detection line deviates from expectations at a certain time, it indicates an anomaly in the drive control node Qn or the noise reduction control node Pn of that stage of the gate drive module 100. The downstream load can then deduce and accurately locate the faulty stage based on the corresponding scanning timing.

[0038] It should be noted that at least one detection line can be a single detection line or multiple detection lines. For example... Figure 1 As shown, the first anomaly detection unit 140 and the second anomaly detection unit 150 transmit the signal states of the drive control node Qn and the noise reduction control node Pn to the first detection line CF1 in a time-division manner. Specifically, during the scanning phase of the current stage, the first anomaly detection unit 140 transmits the signal state of the drive control node Qn to the first detection line CF1; during the non-scanning phase of the current stage, the second anomaly detection unit 150 transmits the signal state of the noise reduction control node Pn to the first detection line CF1. Since the scanning phase and the non-scanning phase are staggered in timing, the two detection paths can reuse the same detection line without signal conflict. The subsequent load can comprehensively determine the working state of the stage by detecting the output signals of the first detection line CF1 at different times. The advantage of this implementation is that it only requires one detection line, which reduces the space occupied on the panel.

[0039] In another specific implementation, the first anomaly detection unit 140 and the second anomaly detection unit 150 can also be connected to different detection lines respectively. The signal states of the drive control node Qn and the noise reduction control node Pn are simultaneously transmitted to two independent first detection lines CF1 and second detection lines CF2. The subsequent load can acquire the signal states of the two nodes at the same time, thereby further improving the detection efficiency.

[0040] In summary, this application provides a first anomaly detection unit 140 and a second anomaly detection unit 150 in each stage of the gate drive module 100. The first anomaly detection unit 140 transmits the signal state of the drive control node Qn to at least one detection line during the scanning phase, and the second anomaly detection unit 150 transmits the signal state of the noise reduction control node Pn to at least one detection line during the non-scanning phase. This allows the subsequent load to determine the working state of the drive control node Qn and the noise reduction control node Pn based on the output signals of at least one detection line at different times, thereby determining whether there is an anomaly in the current stage gate drive module 100. This achieves accurate location of the gate drive unit fault without damaging the panel, reduces detection costs, and improves the efficiency and accuracy of fault analysis.

[0041] Figure 3 The diagram shown is a circuit schematic of a first type of gate driving module provided in an embodiment of this application; as shown Figure 3 As shown, at least one detection line in this embodiment includes a first detection line CF1; the first anomaly detection unit 140 includes a first transistor T1 and a second transistor T2; specifically, the control terminal of the first transistor T1 is connected to the first detection control terminal SW1, and the first terminal of the first transistor T1 is connected to the noise reduction control node Pn; the control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2 is connected to the drive control node Qn, and the second terminal of the second transistor T2 is connected to the first detection line CF1.

[0042] Optionally, the second anomaly detection unit 150 in this embodiment includes: a third transistor T3 and a fourth transistor T4; the control terminal of the third transistor T3 is connected to the second detection control terminal SW2, and the first terminal of the third transistor T3 is connected to the noise reduction control node Pn; the control terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3, the first terminal of the fourth transistor T4 is connected to the drive output terminal Gn, and the second terminal of the fourth transistor T4 is connected to the first detection line CF1.

[0043] like Figure 3 As shown, the precharge unit 110 in this embodiment includes a fifth transistor T5. The control terminal and the first terminal of the fifth transistor T5 are both connected to the stage transmission output terminal of the ni-th stage gate drive module, and the second terminal of the fifth transistor T5 is connected to the drive control node Qn.

[0044] The output unit 120 of this embodiment includes a sixth transistor T6, a seventh transistor T7, and a storage capacitor C1. The control terminals of both the sixth transistor T6 and the seventh transistor T7 are connected to the drive control node Qn. The first terminals of both the sixth transistor T6 and the seventh transistor T7 are connected to their respective clock signal lines. The second terminal of the sixth transistor T6 serves as the stage transmission output terminal Fn of the output unit 120, and the second terminal of the seventh transistor T7 serves as the drive output terminal Gn of the output unit 120. The first terminal of the storage capacitor C1 is connected to the drive control node Qn, and the second terminal of the storage capacitor C1 is connected to the second terminal of the seventh transistor T7.

[0045] like Figure 3 As shown, the noise reduction unit 130 in this embodiment includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The control terminal and the first terminal of the eighth transistor T8 are both connected to the noise reduction control terminal LC, and the second terminal of the eighth transistor T8 serves as the noise reduction control node Pn. The control terminal of the ninth transistor T9 is connected to the drive control node Qn, the first terminal of the ninth transistor T9 is connected to the noise reduction control node Pn, and the second terminal of the ninth transistor T9 is connected to the low-level terminal VSS. The control terminals of the tenth transistor T10 and the eleventh transistor T11 are both connected to the noise reduction control node Pn. The first terminal of the tenth transistor T10 is connected to the drive control node Qn, the first terminal of the eleventh transistor T11 is connected to the drive output terminal Gn, and the second terminals of both the tenth transistor T10 and the eleventh transistor T11 are connected to the low-level terminal VSS.

[0046] In addition, the gate driving module 100 in this embodiment also includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is connected to the stage output terminal of the (n+j)th stage gate driving module. The first terminal of the twelfth transistor T12 is connected to the drive output terminal Gn, and the second terminal of the twelfth transistor T12 is connected to the low-level terminal VSS.

[0047] It should be noted that the connection point between the second transistor T2 and the first detection line CF1 is denoted as the first node An, and the connection point between the fourth transistor T4 and the first detection line CF1 is denoted as the second node Bn. Taking i=2 as an example, combined with... Figure 4 and Figure 5 The working principle of the gate driving module 100 in this embodiment is explained below using the corresponding timing diagram: (1) During the scanning phase of the current frame, when the stage transmission signal output by the (n-2)th stage gate drive module arrives, the fifth transistor T5 is turned on to precharge the drive control node Qn, causing the potential of the drive control node Qn to rise. When the voltage of the drive control node Qn rises to a level sufficient to turn on the sixth transistor T6 and the seventh transistor T7, the sixth transistor T6 and the seventh transistor T7 are turned on. The clock signal is output to the next stage as the stage transmission signal through the sixth transistor T6, and simultaneously output to the pixel array as the gate drive signal through the seventh transistor T7. At this time, the drive control node Qn is at a high level, the gate drive signal is at a high level, and the noise reduction control node Pn is at a low level.

[0048] (2) The anomaly detection in this embodiment is divided into two detection modes, which are controlled by the first detection control terminal SW1 and the second detection control terminal SW2, respectively. For example... Figure 4 As shown, when the first detection control terminal SW1 is high, the first abnormal detection unit 140 is controlled to enter the working state. At this time, the first transistor T1 is turned on, transmitting the low level of the noise reduction control node Pn to the control terminal of the second transistor T2, and the second transistor T2 is turned off. Therefore, during the scanning phase and when the current stage is in the scanning state, the first transistor T1 is turned on, the second transistor T2 is turned off, there is no signal output on the first detection line CF1, and the first node An is in a floating state. When entering the non-scanning phase, the drive control node Qn becomes low, the noise reduction control node Pn becomes high, the first transistor T1 is still turned on under the control of the first detection control terminal SW1, transmitting the high level of the noise reduction control node Pn to the control terminal of the second transistor T2, the second transistor T2 is turned on, transmitting the low level of the drive control node Qn to the first detection line CF1, at this time the first detection line CF1 is pulled down to a low level, and the first node An outputs a low-level signal. In other words, when the first anomaly detection unit 140 is enabled, the first detection line CF1 has no signal output during the scanning phase and outputs a low-level signal during the non-scanning phase. If the first detection line CF1 outputs a low-level signal during the scanning phase or has no signal output during the non-scanning phase, it indicates that there is a timing anomaly in the drive control node Qn or noise reduction control node Pn of this stage.

[0049] (3) such as Figure 5As shown, when the second detection control terminal SW2 is high, controlling the second abnormal detection unit 150 to enter the working state, the third transistor T3 is turned on, transmitting the low level of the noise reduction control node Pn to the control terminal of the fourth transistor T4, and the fourth transistor T4 is turned off. Therefore, during the scanning phase and when the current stage is in the scanning state, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the second node Bn is in a floating state, and there is no signal output on the first detection line CF1. When entering the non-scanning phase, the drive control node Qn becomes low, and the noise reduction control node Pn becomes high. The third transistor T3 is still turned on under the control of the second detection control terminal SW2, transmitting the high level of the noise reduction control node Pn to the control terminal of the fourth transistor T4, the fourth transistor T4 is turned on, transmitting the low-level gate drive signal of the drive output terminal Gn to the first detection line CF1, at which time the second node Bn outputs a low-level signal. In other words, when the second anomaly detection unit 150 is enabled, the first detection line CF1 has no signal output during the scanning phase and outputs a low-level signal during the non-scanning phase. If the first detection line CF1 outputs a low-level signal during the scanning phase or has no signal output during the non-scanning phase, it indicates that there is an anomaly in the drive output terminal Gn or the noise reduction control node Pn of this stage.

[0050] It should be noted that the control signals of the first detection control terminal SW1 and the second detection control terminal SW2 are staggered in timing, meaning that only one anomaly detection unit is activated at any given time. Therefore, the first detection line CF1 carries the output signals of the first anomaly detection unit 140 or the second anomaly detection unit 150 at different times, and there will be no signal conflict between the two. The downstream load continuously monitors the voltage of the first detection line CF1 during the scanning phase: if the first detection line CF1 exhibits an unexpected signal state at a certain time, the downstream load can deduce and accurately locate the fault level based on the scanning sequence corresponding to the current time period.

[0051] Figure 6 The diagram shown is a circuit schematic of a second type of gate driving module provided in an embodiment of this application; Figure 6 The circuit shown is Figure 3 The difference in the circuit structure shown lies in the different structure of the second anomaly detection unit 150; specifically, the second anomaly detection unit 150 in this embodiment includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the noise reduction control node Pn, the first terminal of the third transistor T3 is connected to the drive output terminal Gn, and the second terminal of the third transistor T3 is connected to the first detection line CF1.

[0052] It should be noted that the working principle of the second anomaly detection unit 150 in this embodiment is as follows: (1) During the scanning phase and when the current stage is in the scanning state, the drive control node Qn is at a high level, the gate drive signal is at a high level, the noise reduction control node Pn is at a low level, and the third transistor T3 is turned off. Therefore, the second node Bn on the first detection line CF1 has no signal output.

[0053] (2) When entering the non-scanning stage, the drive control node Qn becomes low level, the gate drive signal becomes low level, and the noise reduction control node Pn becomes high level. At this time, the third transistor T3 is turned on, and the low-level gate drive signal of the drive output terminal Gn is transmitted to the second node Bn, so that the first detection line CF1 outputs a low level.

[0054] In other words, in this embodiment, the second anomaly detection unit 150 has no signal output on the first detection line CF1 during the scanning phase, and outputs a low-level signal on the first detection line CF1 during the non-scanning phase. The subsequent load can determine whether there is an anomaly in the noise reduction control node Pn and the drive output terminal Gn of this stage by monitoring whether the first detection line CF1 normally outputs a low level during the non-scanning phase. Compared to... Figure 3 In this embodiment, the second detection control terminal SW2 and the fourth transistor T4 are omitted, making the circuit structure simpler. However, it can still achieve the abnormal detection function in the non-scanning stage. Moreover, the detection logic is directly determined by the level state of the noise reduction control node Pn itself, without the need for additional control signals.

[0055] Figure 7 The diagram shown is a circuit schematic of a third type of gate driving module provided in an embodiment of this application; Figure 7 The circuit shown is Figure 3 The difference in the circuit structure shown lies in the different structure of the first anomaly detection unit 140; specifically, the first anomaly detection unit 140 in this embodiment includes: a first transistor T1, the control terminal of the first transistor T1 is connected to the noise reduction control node Pn, the first terminal of the first transistor T1 is connected to the drive control node Qn, and the second terminal of the first transistor T1 is connected to the first detection line CF1.

[0056] It should be noted that the working principle of the first anomaly detection unit 140 in this embodiment is as follows: (1) During the scanning phase and when the current stage is in the scanning state, the drive control node Qn is at a high level, the noise reduction control node Pn is at a low level, the first transistor T1 is turned off, so there is no signal output on the first node An.

[0057] (2) When entering the non-scanning stage, the drive control node Qn becomes low level, the noise reduction control node Pn becomes high level, the first transistor T1 is turned on, and the low level of the drive control node Qn is transmitted to the first node An, so that the first detection line CF1 is pulled down to low level.

[0058] In other words, in this embodiment, the first anomaly detection unit 140 has no signal output on the first detection line CF1 during the scanning phase, and outputs a low-level signal on the first detection line CF1 during the non-scanning phase. The subsequent load can determine whether there are any anomalies in the drive control node Qn and noise reduction control node Pn of this stage by monitoring whether the first detection line CF1 normally outputs a low level during the non-scanning phase. Compared to... Figure 3 In this embodiment, the first detection control terminal SW1 and the second transistor T2 are omitted, making the circuit structure simpler. However, it can still achieve the abnormal detection function during the scanning stage. Moreover, the detection logic is directly determined by the level state of the noise reduction control node Pn itself, without the need for additional control signals.

[0059] Figure 8 The diagram shown is a circuit schematic of a fourth gate driving module provided in an embodiment of this application; as follows: Figure 8 As shown, the first anomaly detection unit 140 in this embodiment includes a first transistor T1 and a second transistor T2; the control terminal of the first transistor T1 is connected to the first detection control terminal SW1, the first terminal of the first transistor T1 is connected to the drive control node Qn, and the second terminal of the first transistor T1 is connected to the first detection line CF1; the control terminal of the second transistor T2 is connected to the second detection control terminal SW2, the first terminal of the second transistor T2 is connected to the drive output terminal Gn, and the second terminal of the second transistor T2 is connected to the first detection line CF1.

[0060] like Figure 8 As shown, the second anomaly detection unit 150 in this embodiment includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the third detection control terminal SW3, the first terminal of the third transistor T3 is connected to the noise reduction control node Pn, and the second terminal of the third transistor T3 is connected to the first detection line CF1.

[0061] It should be noted that in this embodiment, the connection point between the first transistor T1 and the first detection line CF1 is designated as the first node An, the connection point between the second transistor T2 and the first detection line CF1 is designated as the second node Bn, and the connection point between the third transistor T3 and the first detection line CF1 is designated as the third node Cn. Anomaly detection in this embodiment is controlled by the first detection control terminal SW1, the second detection control terminal SW2, and the third detection control terminal SW3. The first detection control terminal SW1 controls the first transistor T1 to transmit the signal driving the control node Qn to the first detection line CF1; the second detection control terminal SW2 controls the second transistor T2 to transmit the signal driving the output terminal Gn to the first detection line CF1; and the third detection control terminal SW3 controls the third transistor T3 to transmit the signal of the noise reduction control node Pn to the first detection line CF1. In actual detection, one of the detection control terminals can be selected to be active as needed to obtain the signal status of the corresponding node; this is combined with... Figure 9 , Figure 10 and Figure 11 The timing diagram illustrates the working principle of the first anomaly detection unit 140 and the second anomaly detection unit 150 in this embodiment. (1) such as Figure 9 As shown, when the first detection control terminal SW1 is high, the first transistor T1 is turned on, transmitting the signal of the drive control node Qn to the first detection line CF1. During the scanning phase and when the current stage is in scanning mode, the drive control node Qn is high, and the first node An on the first detection line CF1 is high. When entering the non-scanning phase, the drive control node Qn becomes low, and the first node An is also low. That is, the first abnormality detection unit 140 directly transmits the voltage change of the drive control node Qn to the first detection line CF1, and the subsequent load can determine whether the drive control node Qn is normal by monitoring the signal of the first detection line CF1.

[0062] (2) such as Figure 10 As shown, when the second detection control terminal SW2 is high, the second transistor T2 is turned on, transmitting the signal from the drive output terminal Gn to the first detection line CF1. During the scanning phase and when the current stage is in scanning mode, the drive output terminal Gn outputs a high-level gate drive signal, the first detection line CF1 outputs a high-level signal, and the second node Bn is high. When entering the non-scanning phase, the gate drive signal becomes low, and the first detection line CF1 outputs a low-level signal. That is, the first abnormal detection unit 140 can also directly transmit the voltage change of the gate drive signal to the first detection line CF1, and the subsequent load can determine whether the drive output terminal Gn is normal by monitoring the signal of the first detection line CF1.

[0063] (3) such as Figure 11 As shown, when the third detection control terminal SW3 is high, the third transistor T3 is turned on, transmitting the signal of the noise reduction control node Pn to the first detection line CF1. During the scanning phase and when the current stage is in scanning mode, the noise reduction control node Pn is low, the first detection line CF1 outputs a low-level signal, and the third node Cn is low. When entering the non-scanning phase, the noise reduction control node Pn becomes high, and the first detection line CF1 outputs a high-level signal. That is, the second anomaly detection unit 150 directly transmits the voltage change of the noise reduction control node Pn to the first detection line CF1, and the subsequent load can determine whether the noise reduction control node Pn is normal by monitoring the signal of the first detection line CF1.

[0064] It should be noted that the control signals of the first detection control terminal SW1, the second detection control terminal SW2, and the third detection control terminal SW3 are staggered in timing, meaning that only one abnormal detection unit is activated at any given time. Therefore, the first detection line CF1 carries the output signals of the first node An, the second node Bn, and the third node Cn respectively at different time periods, and there will be no signal conflict among the three. The downstream load can determine whether the drive control node Qn, the drive output terminal Gn, and the noise reduction control node Pn are all in normal condition by monitoring the level state of the first detection line CF1 at different time periods and comparing it with the expected signal corresponding to the current time period. If the signal state on the first detection line CF1 at a certain time period does not match the expectation, it indicates that there is an abnormality in the corresponding node of that stage. The downstream load can then reverse the process and accurately locate the stage where the fault occurred based on the scan timing corresponding to the current time period.

[0065] Figure 12 The diagram shown is a circuit diagram of the fifth type of gate driving module provided in an embodiment of this application; Figure 12 The circuit shown is Figure 8 The difference lies in the specific circuit structure of the second anomaly detection unit 150; specifically, the second anomaly detection unit 150 includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the noise reduction control node Pn, the first terminal of the third transistor T3 is connected to the drive output terminal Gn, and the second terminal of the third transistor T3 is connected to the first detection line CF1.

[0066] In this embodiment, the second anomaly detection unit 150 no longer requires the third detection control terminal SW3. Instead, the noise reduction control node Pn directly controls the conduction and cutoff of the third transistor T3. The specific working principle is as follows: (1) During the scanning phase and when the current stage is in the scanning state, the drive control node Qn is at a high level, the gate drive signal is at a high level, the noise reduction control node Pn is at a low level, and the third transistor T3 is turned off. Therefore, the third node Cn on the first detection line CF1 has no signal output.

[0067] (2) When entering the non-scanning stage, the drive control node Qn becomes low level, the gate drive signal becomes low level, the noise reduction control node Pn becomes high level, the third transistor T3 is turned on, and the low-level gate drive signal of the drive output terminal Gn is transmitted to the third node Cn, so that the first detection line CF1 is pulled down to low level.

[0068] In other words, in this embodiment, the second anomaly detection unit 150 has no signal output on the first detection line CF1 during the scanning phase, and outputs a low-level signal on the first detection line CF1 during the non-scanning phase. The subsequent load can determine whether there is an anomaly in the noise reduction control node Pn and the drive output terminal Gn of this stage by monitoring whether the first detection line CF1 outputs a low level normally during the non-scanning phase.

[0069] Figure 13 The diagram shown is a circuit schematic of the sixth gate driving module provided in an embodiment of this application; as follows: Figure 13 As shown, at least one detection line in this embodiment includes a first detection line CF1 and a second detection line CF2. The first anomaly detection unit 140 includes a first transistor T1, the control terminal of the first transistor T1 is connected to the drive control node Qn, the first terminal of the first transistor T1 is connected to the drive output terminal Gn, and the second terminal of the first transistor T1 is connected to the first detection line CF1.

[0070] like Figure 13 As shown, the second anomaly detection unit 150 in this embodiment includes: a second transistor T2, the control terminal of the second transistor T2 is connected to the noise reduction control node Pn, the first terminal of the second transistor T2 is connected to the drive output terminal Gn, and the second terminal of the second transistor T2 is connected to the second detection line CF2.

[0071] It should be noted that in this embodiment, the connection point between the first transistor T1 and the first detection line CF1 is taken as the first node An, and the connection point between the second transistor T2 and the second detection line CF2 is taken as the second node Bn; in conjunction with this... Figure 14 The timing diagram shown below illustrates the working principle of the first anomaly detection unit 140 and the second anomaly detection unit 150 in this embodiment: (1) such as Figure 14 As shown, during the scanning phase and when the current stage is in scanning state, the drive control node Qn is at a high level, the gate drive signal is at a high level, and the noise reduction control node Pn is at a low level. At this time, the first transistor T1 is turned on, transmitting the high-level gate drive signal from the drive output terminal Gn to the first detection line CF1, and the first node An outputs a high-level signal. Simultaneously, the control terminal of the second transistor T2 receives the low level of the noise reduction control node Pn and is turned off, and there is no signal output on the second node Bn.

[0072] (2) When entering the non-scanning stage, the drive control node Qn becomes low, the gate drive signal becomes low, and the noise reduction control node Pn becomes high. At this time, the first transistor T1 is turned off, and there is no signal output on the first node An. At the same time, the second transistor T2 turns on in response to the high level of the noise reduction control node Pn, and transmits the low-level gate drive signal of the drive output terminal Gn to the second detection line CF2, and the second node Bn outputs a low-level signal.

[0073] In other words, in this embodiment, the first detection line CF1 outputs a high-level gate drive signal during the scanning phase and has no signal output during the non-scanning phase; the second detection line CF2 has no signal output during the scanning phase and outputs a low-level signal during the non-scanning phase. The two detection lines carry signals from different phases respectively. By simultaneously monitoring the signals of both detection lines, the subsequent load can synchronously obtain the operating status of the drive control node Qn and the noise reduction control node Pn, thereby more quickly and comprehensively determining whether there is an anomaly in the current stage. Compared to a time-division multiplexing scheme with a single detection line, this embodiment uses two detection lines outputting in parallel, resulting in higher detection efficiency. Furthermore, the two detection paths are independent and do not interfere with each other, which helps improve the reliability of the detection.

[0074] Figure 15 The diagram shown is a circuit diagram of the seventh gate driving module provided in an embodiment of this application; Figure 15 The circuit structure shown is similar to Figure 13 The difference lies in the structure of the second anomaly detection unit 150; specifically, the second anomaly detection unit 150 in this embodiment includes: a second transistor T2, the control terminal of the second transistor T2 is connected to the drive control node Qn, the first terminal of the second transistor T2 is connected to the noise reduction control node Pn, and the second terminal of the second transistor T2 is connected to the second detection line CF2.

[0075] Here, combined with Figure 16 The working principle of the second anomaly detection unit 150 in this embodiment is explained as follows: (1) such as Figure 16 As shown, during the scanning phase and when the current stage is in the scanning state, the drive control node Qn is at a high level, the noise reduction control node Pn is at a low level, the second transistor T2 is turned on, and the low level of the noise reduction control node Pn is transmitted to the second node Bn, so that the second detection line CF2 outputs a low level signal.

[0076] (2) For example Figure 16 As shown, when entering the non-scanning stage, the drive control node Qn becomes low, the noise reduction control node Pn becomes high, the second transistor T2 is turned off, and the second detection line CF2 has no signal output.

[0077] In other words, the second anomaly detection unit 150 in this embodiment outputs a low-level signal during the scanning phase and no signal output during the non-scanning phase. The subsequent load can determine whether the timing of the drive control node Qn and the noise reduction control node Pn is normal by monitoring whether the second detection line CF2 outputs a low level normally during the scanning phase.

[0078] Figure 17 The diagram shown is a circuit diagram of the eighth gate driving module provided in an embodiment of this application; Figure 17 The circuit shown is in Figure 15Based on the above, a third transistor T3 and a detection line are added. Specifically, at least one detection line also includes a third detection line CF3. The first anomaly detection unit 140 includes: a first transistor T1 and a third transistor T3. The control terminal of the first transistor T1 is connected to the drive control node Qn, the first terminal of the first transistor T1 is connected to the drive output terminal Gn, and the second terminal of the first transistor T1 is connected to the first detection line CF1. The control terminal of the third transistor T3 is connected to the drive control node Qn, the first terminal of the third transistor T3 is connected to the stage transmission output terminal, and the second terminal of the third transistor T3 is connected to the third detection line CF3.

[0079] It should be noted that the connection point between the third transistor T3 and the third detection line CF3 is taken as the third node Cn, and this is combined with... Figure 18 The timing diagram illustrates the working principle of the first anomaly detection unit 140 in this embodiment as follows: (1) such as Figure 18 As shown, during the scanning phase and when the current stage is in scanning state, the drive control node Qn is high, the gate drive signal is high, the stage transmission signal is high, and the noise reduction control node Pn is low. At this time: the first transistor T1 is turned on, transmitting the high-level gate drive signal from the drive output terminal Gn to the first detection line CF1, and the first node An outputs a high-level signal; the third transistor T3 is turned on, transmitting the high-level stage transmission signal from the stage transmission output terminal to the third detection line CF3, and the third node Cn outputs a high-level signal. Simultaneously, the second transistor T2 is turned on, transmitting the low-level signal from the noise reduction control node Pn to the second detection line CF2, and the second node Bn outputs a low-level signal.

[0080] (2) For example Figure 18 As shown, when entering the non-scanning phase, the drive control node Qn goes low, the gate drive signal goes low, the stage transmission signal goes low, and the noise reduction control node Pn goes high. The first transistor T1, the second transistor T2, and the third transistor T3 all turn off in response to the low level of the drive control node Qn, and there is no signal output on the three detection lines.

[0081] In other words, in this embodiment, the first detection line CF1 and the third detection line CF3 output high-level gate drive signals and stage transmission signals respectively during the scanning phase, and have no signal output during the non-scanning phase; the second detection line CF2 outputs a low-level signal during the scanning phase, and has no signal output during the non-scanning phase. By simultaneously monitoring the signals of the three detection lines, the subsequent load can synchronously acquire the signal states of three key nodes under the control of the drive control node Qn: the drive output terminal Gn, the stage transmission output terminal, and the noise reduction control node Pn, thereby performing more comprehensive anomaly detection on the current stage.

[0082] In summary, this application provides a first abnormality detection unit 140 and a second abnormality detection unit 150 in each stage of the gate driving module 100. Through the cooperation of the first abnormality detection unit 140 and the second abnormality detection unit 150 in the scanning phase and the non-scanning phase respectively, the effective monitoring and abnormality location of the working state of the gate driving module 100 is achieved without damaging the panel.

[0083] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes a gate driving circuit of any of the above embodiments, and the drive output terminal of the gate driving module in the gate driving circuit is electrically connected to at least one scan line.

[0084] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0085] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, It includes N cascaded gate drive modules and at least one detection line; the nth stage gate drive module includes: The pre-charge unit is connected to the stage transmission output terminal of the ni-th stage gate drive module and the drive control node of the current stage, respectively, and is configured to: pre-charge the drive control node of the current stage in response to the stage transmission signal output by the ni-th stage gate drive module. The output unit, which is connected to the drive control node and the clock signal line corresponding to the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage in response to the clock signal output by the clock signal line and the voltage on the drive control node. The noise reduction unit, which is connected to the drive output terminal of the drive control node and the output unit respectively, is configured to: reduce noise for the drive control node and the drive output terminal during the non-scanning phase of the current level; The first anomaly detection unit, connected to the at least one detection line and the drive control node, is configured to: during the current scanning phase, transmit the signal status on the drive control node to the at least one detection line; The second anomaly detection unit, connected to the at least one detection line and the noise reduction control node in the noise reduction unit, is configured to: during the non-scanning phase of the current stage, transmit the signal status on the noise reduction control node to the at least one detection line, so that the subsequent load can determine whether there is an anomaly in the current stage gate drive module based on the output signals of the at least one detection line during the scanning phase and the non-scanning phase.

2. The gate driving circuit according to claim 1, characterized in that, The at least one detection line includes a first detection line, and the first anomaly detection unit includes: A first transistor, wherein the control terminal of the first transistor is connected to a first detection control terminal, and the first terminal of the first transistor is connected to the noise reduction control node; The second transistor has a control terminal connected to the second terminal of the first transistor, a first terminal connected to the drive control node, and a second terminal connected to the first detection line.

3. The gate driving circuit according to claim 2, characterized in that, The second anomaly detection unit includes a third transistor and a fourth transistor; the control terminal of the third transistor is connected to the second detection control terminal, and the first terminal of the third transistor is connected to the noise reduction control node; the control terminal of the fourth transistor is connected to the second terminal of the third transistor, the first terminal of the fourth transistor is connected to the drive output terminal, and the second terminal of the fourth transistor is connected to the first detection line. Alternatively, the second anomaly detection unit includes: a third transistor, the control terminal of which is connected to the noise reduction control node, the first terminal of which is connected to the drive output terminal, and the second terminal of which is connected to the first detection line.

4. The gate driving circuit according to claim 1, characterized in that, The at least one detection line includes a first detection line, and the first anomaly detection unit includes: A first transistor, wherein the control terminal of the first transistor is connected to a first detection control terminal, the first terminal of the first transistor is connected to the drive control node, and the second terminal of the first transistor is connected to the first detection line; The second transistor has a control terminal connected to a second detection control terminal, a first terminal connected to the drive output terminal, and a second terminal connected to the first detection line.

5. The gate driving circuit according to claim 4, characterized in that, The second anomaly detection unit includes: a third transistor, wherein the control terminal of the third transistor is connected to a third detection control terminal, the first terminal of the third transistor is connected to the noise reduction control node, and the second terminal of the third transistor is connected to the first detection line; Alternatively, the second anomaly detection unit includes: a third transistor, the control terminal of which is connected to the noise reduction control node, the first terminal of which is connected to the drive output terminal, and the second terminal of which is connected to the first detection line.

6. The gate driving circuit according to claim 1, characterized in that, The at least one detection line includes a first detection line, and the first anomaly detection unit includes: a first transistor, the control terminal of the first transistor is connected to the noise reduction control node, the first terminal of the first transistor is connected to the drive control node, and the second terminal of the first transistor is connected to the first detection line; The second anomaly detection unit includes a third transistor and a fourth transistor; the control terminal of the third transistor is connected to the second detection control terminal, and the first terminal of the third transistor is connected to the noise reduction control node; the control terminal of the fourth transistor is connected to the second terminal of the third transistor, the first terminal of the fourth transistor is connected to the drive output terminal, and the second terminal of the fourth transistor is connected to the first detection line.

7. The gate driving circuit according to claim 1, characterized in that, The at least one detection line includes a first detection line and a second detection line. The first anomaly detection unit includes: a first transistor, the control terminal of the first transistor is connected to the drive control node, the first terminal of the first transistor is connected to the drive output terminal, and the second terminal of the first transistor is connected to the first detection line. The second anomaly detection unit includes: a second transistor, the control terminal of the second transistor being connected to the noise reduction control node, the first terminal of the second transistor being connected to the drive output terminal, and the second terminal of the second transistor being connected to the second detection line.

8. The gate driving circuit according to claim 1, characterized in that, The at least one detection line includes a first detection line and a second detection line. The first anomaly detection unit includes: a first transistor, the control terminal of the first transistor is connected to the drive control node, the first terminal of the first transistor is connected to the drive output terminal, and the second terminal of the first transistor is connected to the first detection line. The second anomaly detection unit includes: a second transistor, the control terminal of the second transistor being connected to the drive control node, the first terminal of the second transistor being connected to the noise reduction control node, and the second terminal of the second transistor being connected to the second detection line.

9. The gate driving circuit according to claim 8, characterized in that, The at least one detection line further includes a third detection line, and the first anomaly detection unit further includes: The third transistor has its control terminal connected to the drive control node, its first terminal connected to the stage output terminal, and its second terminal connected to the third detection line.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output terminal of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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