Driving method of display panel, timing controller and display device

Abstract

The present disclosure provides a display panel driving method, a timing controller and a display device. The display panel driving method is applied to the timing controller, and includes: in response to a first signal, controlling the display panel to switch from a first display mode to display in a second display mode; wherein the first display mode includes: controlling a refresh frequency of the display panel to be a first refresh frequency, and controlling shift registers in a gate drive circuit to output valid working levels one by one; the second display mode includes: controlling the refresh frequency of the display panel to be a second refresh frequency, and controlling at least part of the shift registers in the gate drive circuit to output valid working levels at the same time, and the second refresh frequency is less than the first refresh frequency.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, and specifically relates to a driving method for a display panel, a timing controller, and a display device. Background Technology

[0002] As people's living standards and technological levels improve, their requirements for displays are also gradually increasing, especially in the application of high resolution and high refresh rate. The improved experience brought by high resolution and high refresh rate is accompanied by an increase in the power consumption of display modules. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a driving method for a display panel, a timing controller, and a display device.

[0004] This disclosure provides a driving method for a display panel, applied to a timing controller, the driving method for the display panel including:

[0005] In response to the first signal, the display panel is controlled to switch from the first display mode to the second display mode;

[0006] The first display mode includes: controlling the refresh frequency of the display panel to a first refresh frequency, and controlling the shift registers in the gate drive circuit to output valid working levels one by one;

[0007] The second display mode includes: controlling the refresh frequency of the display panel to a second refresh frequency, and controlling at least some shift registers in the gate drive circuit to simultaneously output valid operating levels, wherein the second refresh frequency is less than the first refresh frequency.

[0008] The second display mode includes: controlling the refresh frequency of the display panel to a second refresh frequency, and controlling the shift register in the gate drive circuit connected to the two adjacent rows of gate lines to simultaneously output a valid working level.

[0009] The first display mode further includes: providing a PWM signal to the backlight driving circuit with a first duty cycle; the second display mode further includes: providing a PWM signal to the backlight driving circuit with a second duty cycle, wherein the second duty cycle is less than the first duty cycle.

[0010] The first display mode further includes: providing a first grayscale signal to each sub-pixel of the display panel; the second display mode further includes: providing a second grayscale signal to each sub-pixel of the display panel; for a sub-pixel, the grayscale corresponding to the second grayscale signal is higher than the grayscale corresponding to the first grayscale signal.

[0011] In this context, for a sub-pixel, in the first display mode, the sum of its grayscale brightness and backlight brightness is the first brightness; when the grayscale signal provided to the sub-pixel is the second grayscale signal, and the duty cycle of the PWM signal provided to the backlight driving circuit is the third duty cycle, the sum of the grayscale brightness of the sub-pixel and the backlight brightness is the second brightness; thus, the second brightness is the same as the first brightness, establishing a one-to-one correspondence between the second grayscale signal and the third duty cycle;

[0012] The second display mode further includes: based on the one-to-one correspondence between the second grayscale signal for each sub-pixel and the third duty cycle, determining the second duty cycle of the PWM signal provided to the backlight driving circuit according to the number of different sub-pixels of the second grayscale signal and the third duty cycle corresponding to each different second grayscale signal.

[0013] The second duty cycle of the PWM signal provided to the backlight driving circuit in the second display mode is determined according to the following formula:

[0014]

[0015] Where P represents the second duty cycle of the PWM signal provided to the backlight driving circuit, A1, A2, ..., An represent the number of each sub-pixel of the second grayscale signal, n represents the number of different second grayscale signals, P1, P2, ..., Pn represent the third duty cycle corresponding to each different second grayscale signal, a represents the number of columns of sub-pixels on the array substrate, b represents the number of rows of sub-pixels on the array substrate, a×b represents the number of sub-pixels on the array substrate, and K represents the compensation coefficient.

[0016] This also includes:

[0017] In response to the first signal, record the handshake parameters between the controller chip and the main control chip;

[0018] In response to the second signal, the main link communication with the main control chip is restored according to the handshake parameters, and the display panel is controlled to switch from the second display mode to the third display mode. The third display mode includes: controlling the refresh frequency of the display panel to the third refresh frequency, and controlling the shift registers in the gate drive circuit to output valid working levels one by one. The third refresh frequency is greater than the second refresh frequency.

[0019] The first signal includes any one of a command signal, a hard-wired signal, and a conditional trigger signal.

[0020] This disclosure provides a driving method for a display panel, applied to a main control chip, comprising:

[0021] After the timing controller controls the display panel to run in the first display mode for a first preset time, a first signal is sent to disconnect the main link communication with the timing controller.

[0022] Send a second signal to restore main link communication with the timing controller.

[0023] This disclosure provides a timing controller, which includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the display panel driving method described in any of the preceding claims.

[0024] This disclosure provides a display device that includes the timing controller described above. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a display device disclosed herein;

[0026] Figure 2 This is a topology diagram of a pixel driving circuit disclosed herein;

[0027] Figure 3 This is a timing diagram of scanning four adjacent rows of grid lines on the display panel in the first display mode of this disclosure;

[0028] Figure 4 This is a timing diagram of scanning four adjacent rows of grid lines on the display panel in the second display mode of this disclosure;

[0029] Figure 5 This is a schematic diagram of the structure of a backlight module disclosed herein;

[0030] Figure 6 This is a schematic diagram of another backlight module disclosed herein;

[0031] Figure 7 This is a schematic diagram of the structure of a timing controller disclosed herein. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] like Figure 1 As shown, the display device includes a system board 10, a timing controller TCON 20, a display panel 30, a gate drive circuit 40, and a source drive circuit 50.

[0035] The GPU110 (Graphics Processing Unit) on the system board 10 can be connected to the timing controller 20 through display interfaces such as LVDS / VBO (Low-Voltage Differential Signaling / V-by-One) to transmit frame image data to the timing controller 20. The timing controller 20 has a static random-access memory (SRAM) inside that can be used as a frame buffer to store frame image data.

[0036] The display panel 30 includes multiple data lines D1 to D2. a and multiple grid lines G1~G b Multiple data lines D1 to D a and multiple grid lines G1~G b Multiple sub-pixels 330 are defined in the array arrangement. Sub-pixels 330 located in the same row are provided with gate scan signals by the same gate line, and sub-pixels 330 located in the same column are provided with data signals by the same data line. The source drive circuit 50 is used to drive the data lines D1 to D2 of the display panel 30. a The gate drive circuit 40 is used to drive the gate lines G1 to G2 of the display panel 30. b The timing controller 20 is used to drive and control the source drive circuit 50 and the gate drive circuit 40.

[0037] The timing controller 20 is connected to the gate driving circuit 40 via a flexible circuit board. The timing controller 20 outputs a frame start signal, a clock signal, and an output enable signal to the gate driving circuit 40. The gate driving circuit 40 includes multiple cascaded shift registers 410, each connected to a clock signal line. Each shift register 410 generates a scan signal based on the frame start signal and the clock signal, and loads the scan signal onto the gate line under the control of the output enable signal, thereby scanning multiple rows of sub-pixels 330 line by line. The timing controller 20 is also connected to the source driving circuit 50 via a flexible circuit board. The timing controller 20 transmits frame image data to the source driving circuit 50 line by line in grayscale format. The source driving circuit 50 converts the grayscale into voltage. When the gate driving circuit 40 scans multiple rows of sub-pixels 330 line by line, the source driving circuit 50 converts the grayscale of the corresponding row into voltage and loads it onto the data line to charge the sub-pixels 330 for display.

[0038] In related technologies, one way to reduce power consumption is Panel Self Refresh (PSR). Its principle is as follows: Timing controller 20 stores the frame image data from GPU 110 in its internal frame buffer. However, when timing controller 20 detects that the current frame's image data is consistent with the previous frame, it suspends the data transmission circuit with GPU 110 and maps the stored data onto the screen, relieving the computational pressure on the system GPU 110 and thus effectively reducing power consumption. When the screen changes, timing controller 20 receives new image data, at which point PSR is released. PSR includes PSR1 and PSR2. The biggest difference between PSR1 and PSR2 is the full refresh versus partial refresh of the panel screen. With PSR1, when entering a static screen, any update anywhere on the screen (a change in the polarity of the written data voltage) requires GPU 110 to update the entire frame's data to timing controller 20. With PSR2, when entering a non-static screen, only the GPU 110 needs to update the changed data to timing controller 20.

[0039] When TCON puts the display panel 30 into PSR self-refresh state, the refresh rate of the display panel 30 can be reduced, and the data transmission circuit between the display panel 30 and the GPU 110 can be shut down, thus reducing power consumption. However, this method only reduces the logic power consumption of the display panel 30, and the overall power consumption reduction is relatively small, generally not exceeding 20%, and the overall power consumption is still relatively high.

[0040] In view of this, this disclosure provides a driving method for a display panel 30, which reduces the refresh rate and logical resolution of the display panel 30 without affecting the display effect. For display systems with self-refresh function, power consumption can be further reduced.

[0041] This disclosure provides a driving method for a display panel 30, applied to a timing controller 20. The method includes: in response to a first signal, controlling the display panel 30 to switch from a first display mode to a second display mode for display; wherein the first display mode includes: controlling the refresh frequency of the display panel 30 to a first refresh frequency, and controlling the shift registers 410 in the gate driving circuit 40 to output valid operating levels one by one; the second display mode includes: controlling the refresh frequency of the display panel 30 to a second refresh frequency, and controlling at least some of the shift registers 410 in the gate driving circuit 40 to output valid operating levels simultaneously, and the second refresh frequency is less than the first refresh frequency.

[0042] In some examples, the GPU 110 on system board 10 sends a first signal to timing controller 20. When timing controller 20 receives the first signal, it controls display panel 30 to switch from a first display mode to a second display mode. The first signal can be any of an instruction signal, a hardwired signal, or a conditional trigger signal, without specific limitations.

[0043] In some examples, in response to the first signal, the timing controller 20 controls the display panel 30 to switch from a first display mode to a second display mode. This can be understood as the timing controller 20, upon receiving the first signal, controlling the display panel 30 to display according to new timing control data. This timing control data can be stored in the timing controller 20's own memory or in other locations accessible to the timing controller 20; no specific limitation is made here. The first display mode can be the normal display mode of the display panel 30 or other power-saving modes, such as the PSR mode. The second display mode can be a more power-saving mode than the first display mode, which can be referred to as a deep power-saving mode, thereby reducing power consumption when the display panel 30 switches from the first display mode to the second display mode.

[0044] In some examples, the timing controller 20 controls the display panel 30 to have a first refresh rate in a first display mode and a second refresh rate in a second display mode, wherein the second refresh rate is lower than the first refresh rate. For example, the first refresh rate could be 240Hz, and the second refresh rate could be 20Hz. By controlling the display panel 30 to switch from the first display mode to the second display mode, the timing controller 20 reduces the refresh rate of the display panel 30, which in turn reduces the number of times the shift register 410 in the gate drive circuit 40 outputs signals per unit time, thereby reducing the power consumption of the display panel 30.

[0045] In some examples, in the first display mode, the timing controller 20 controls the shift registers 410 in the gate drive circuit 40 to output valid operating levels one by one. In the second display mode, the timing controller 20 controls at least some of the shift registers 410 in the gate drive circuit 40 to output valid operating levels simultaneously. The timing controller 20 controls the display panel 30 to switch from the first display mode to the second display mode, increasing the number of shift registers 410 in the gate drive circuit 40 that simultaneously output valid operating levels, i.e., increasing the number of gate lines scanned per scan, and reducing the number of times the gate drive circuit 40 switches between shift registers 410 per unit time, thereby reducing the power consumption of the display panel 30. By scanning multiple rows of gate lines simultaneously, the logic resolution of the display panel 30 is reduced, but the size of the image displayed on the display panel 30 is not affected.

[0046] In some examples, sub-pixel 330 includes a light-emitting device and a pixel driving circuit, which drives the light-emitting device to emit light. The pixel driving circuit can have a 7T1C (seven transistors and one capacitor) structure, a 7T12C structure, a 6T1C structure, a 6T12C structure, or a 9T12C structure, etc. For example... Figure 2 As shown, the effective operating level is illustrated using the 7T1C structure as an example, but this does not constitute a limitation of this disclosure.

[0047] like Figure 2As shown, the pixel driving circuit includes: a first reset sub-circuit 2, a threshold compensation sub-circuit 8, a driving sub-circuit 1, a data writing sub-circuit 7, a first light emission control sub-circuit 51, a second light emission control sub-circuit 52, a second reset sub-circuit 4, and a storage sub-circuit 6. The first reset sub-circuit 2 is connected to the control terminal of the driving sub-circuit 1 and is configured to reset the control terminal of the driving sub-circuit 1 under the control of a first reset signal. The threshold compensation sub-circuit 8 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 1, and is configured to perform threshold compensation on the driving sub-circuit 1. The data writing sub-circuit 7 is electrically connected to the first terminal of the driving sub-circuit 1 and is configured to write data signals into the storage sub-circuit 6 under the control of a scan signal. The storage sub-circuit 6 is electrically connected to the control terminal and the first power supply terminal VDD of the driving sub-circuit 1, and is configured to store data signals. The first light-emitting control sub-circuit 51 is connected to the first power supply terminal VDD and the first terminal of the driving sub-circuit 1, and is configured to enable or disable the connection between the driving sub-circuit 1 and the first power supply terminal VDD. The second light-emitting control sub-circuit 52 is electrically connected to the second terminal of the driving sub-circuit 1 and the first electrode of the light-emitting device OLED (Organic Light-Emitting Diode) (taking OLED as an example), and is configured to enable or disable the connection between the driving sub-circuit 1 and the light-emitting device OLED. The second reset sub-circuit 4 is electrically connected to the first electrode of the light-emitting device OLED, and is configured to reset the control terminal of the driving sub-circuit 1 and the first electrode of the light-emitting device OLED under the control of the second reset control signal.

[0048] like Figure 2 As shown, the first reset sub-circuit 2 includes a first transistor T1, the threshold compensation sub-circuit 8 includes a second transistor T2, the driving sub-circuit 1 includes a third transistor T3, the control terminal of the driving sub-circuit 1 includes the control electrode of the third transistor T3, the first terminal of the driving sub-circuit 1 includes the first electrode of the third transistor T3, and the second terminal of the driving sub-circuit 1 includes the second electrode of the third transistor T3. The data writing sub-circuit 7 includes a fourth transistor T4, the storage sub-circuit 6 includes a storage capacitor C, the first light-emitting control sub-circuit 51 includes a fifth transistor T5, the second light-emitting control sub-circuit 52 includes a sixth transistor T6, and the second reset sub-circuit 4 includes a seventh transistor T7. Figure 2 The transistors in the pixel driving circuit are all P-type transistors (e.g., P-type MOS transistors), but in other examples, they may also be N-type transistors.

[0049] Figure 2The pixel driving circuit shown operates through an initialization phase, a data writing and threshold compensation phase, and a light-emitting phase. Initialization phase: A high-level signal is written to the first reset signal terminal Re1, and a high-level signal is written to the second reset signal terminal Re2. At this time, the first transistor T1 and the seventh transistor T7 are turned on, resetting the control electrode of the third transistor T3 and the anode of the light-emitting diode, respectively. Data writing and threshold compensation phase: The gate driving circuit 40 writes a high-level signal to the first scan line Gate1 and a high-level signal to the second scan line Gate2. Light-emitting phase: A high-level signal is written to the enable signal terminal EM, turning on both the fifth transistor T5 and the sixth transistor T6. The source of the third transistor T3 is connected to the first power supply terminal VDD, and the source voltage of the third transistor T3 instantaneously changes from Vdata in the previous phase to VDD.

[0050] like Figure 2 As shown, the effective operating level is the first scan signal written to the first scan line Gate1, which turns on the fourth transistor T4 and writes the voltage on the data line to the first terminal of the third transistor T3. When the third transistor T3 is turned on, the voltage on the data line is written to the anode of the light-emitting device OLED.

[0051] In some examples, when the timing controller 20 receives a first signal from the GPU 110 on the system board 10, it also records the handshake parameters with the GPU 110 on the system board 10. When it receives a second signal from the GPU 110 on the system board 10, it restores the main link communication with the GPU 110 on the system board 10 according to the handshake parameters, continues to receive frame image data from the GPU 110 on the system board 10, and controls the display panel 30 to switch from the second display mode to a third display mode. The third display mode includes: controlling the refresh frequency of the display panel 30 to a third refresh frequency, and controlling the shift register 410 in the gate drive circuit 40 to output valid working levels one by one. The third refresh frequency is greater than the second refresh frequency.

[0052] When the timing controller 20 receives the first signal from the GPU 110 on the system board 10, it records the handshake parameters with the GPU 110 on the system board 10. When it receives the second signal from the GPU 110 on the system board 10, it can achieve handshake without training the communication link with the GPU 110 on the system board 10. This saves the time for the timing controller 20 and the GPU 110 on the system board 10 to resume the main link communication, and can control the display panel 30 to switch from the second display mode to the third display mode more quickly.

[0053] In some examples, the second signal can take various forms, such as a command signal, a hard-wired signal, a conditional trigger signal, etc., and no specific limitation is made here. The form of the second signal can be the same as or different from that of the first signal, and no specific limitation is made here.

[0054] In some examples, the third display mode differs from the second display mode. The timing controller 20 controls the display panel 30 to have a third refresh rate in the third display mode, which is higher than the second refresh rate. That is, the timing controller 20 controls the display panel 30 to switch from the second display mode to the third display mode, increasing the refresh rate of the display panel 30. In the third display mode, the timing controller 20 controls the shift registers 410 in the gate drive circuit 40 to output valid operating levels one by one. This reduces the number of shift registers 410 in the gate drive circuit 40 that simultaneously output valid operating levels; at any given time, only one shift register 410 outputs a valid operating level. The timing controller 20 controlling the display panel 30 to switch from the second display mode to the third display mode can be understood as the timing controller 20 controlling the display panel 30 to exit the second display mode, i.e., exit the deep power-saving mode. The third display mode can be the same as or different from the first display mode; no specific limitation is made here.

[0055] The following describes the driving method of the display panel 30 of this disclosure with reference to several specific examples, but this should not be construed as limiting the disclosure.

[0056] The first example provides a driving method for a display panel 30, applied to a timing controller 20. The method includes: in response to an AUX (Auxiliary) signal, controlling the display panel 30 to switch from a first display mode to a second display mode; wherein the first display mode includes: controlling the refresh frequency of the display panel 30 to a first refresh frequency, and controlling the shift register 410 in the gate driving circuit 40 to output valid operating levels one by one; the second display mode includes: controlling the refresh frequency of the display panel 30 to a second refresh frequency, the second refresh frequency being less than the first refresh frequency, and controlling the shift register 410 in the gate driving circuit 40 connected to two adjacent rows of gate lines to simultaneously output valid operating levels.

[0057] In this example, the system board 10 is connected to the timing controller 20 via an AUX communication terminal, and the GPU 110 on the system board 10 sends an AUX signal to the timing controller 20. When the timing controller 20 receives the AUX signal from the GPU 110 of the system board 10, it controls the display panel 30 to switch from the first display mode to the second display mode.

[0058] like Figure 1 As shown, the display panel 30 includes multiple gate lines, each corresponding to a different shift register 410 in the gate drive circuit 40. In the second display mode, the timing controller 20 controls the shift registers 410 in the gate drive circuit 40 connected to adjacent rows of gate lines to simultaneously output valid operating levels. Figure 3 and Figure 4 As shown, four adjacent rows of grid lines are selected for illustration, but this does not constitute a limitation of this disclosure.

[0059] like Figure 3 As shown, in the first display mode, the timing controller 20 controls the shift register 410 in the gate drive circuit 40, which is connected to the four adjacent gate lines, to output valid operating levels one by one, thereby scanning the four adjacent gate lines line by line. Figure 3 As shown, the voltage polarities of the data lines corresponding to any two adjacent rows of gate lines are opposite. That is, the voltage polarities of the data lines corresponding to the m-th row of gate lines are opposite to those of the (m+1)-th row of gate lines, the voltage polarities of the data lines corresponding to the (m+1)-th row of gate lines are opposite to those of the (m+2)-th row of gate lines, and the voltage polarities of the data lines corresponding to the (m+2)-th row of gate lines are opposite to those of the (m+3)-th row of gate lines.

[0060] like Figure 4 As shown, in the second display mode, the timing controller 20 controls the shift register 410 in the gate drive circuit 40, which is connected to the two adjacent rows of gate lines, to simultaneously output a valid operating level, thereby simultaneously scanning the two adjacent rows of gate lines. That is, the shift register 410 in the gate drive circuit 40, which is connected to the two adjacent rows of gate lines, simultaneously outputs a valid operating level. m and G m+1 The connected shift register 410 simultaneously outputs a valid operating level, along with the two adjacent rows of gate lines G. m+2 and G m+3 The connected shift register 410 simultaneously outputs a valid operating level. For example... Figure 4 As shown, two adjacent rows of gate lines G m and G m+1 The corresponding data line voltage, and the adjacent two rows of gate lines G m+2 and G m+3 The corresponding data line voltages have opposite polarities.

[0061] In this example, the timing controller 20 controls the display panel 30 to switch from the first display mode to the second display mode, reducing the refresh rate of the display panel 30. This reduces the number of times the shift register 410 in the gate drive circuit 40 outputs signals per unit time, thereby reducing the power consumption of the display panel 30. Increasing the number of shift registers 410 in the gate drive circuit 40 that simultaneously output valid operating levels to two further halves the pixel clock signal rate inside the timing controller 20 per unit time, thus reducing the power consumption of the timing controller 20 and further reducing the power consumption of the display panel 30. By scanning two rows of gate lines simultaneously, the logic resolution of the display panel 30 is reduced, for example, from 3840*2400 to 3840*1200, without affecting the size of the image displayed on the display panel 30.

[0062] like Figure 5 and Figure 6 As shown, the display panel 30 includes an array substrate 310 and a backlight module 320. The backlight module 320 includes a frame structure, an optical film 323, a light guide plate 324, and a backlight source 325. The frame structure includes a back plate 321 and a middle frame 322. The back plate 321 and the middle frame 322 are assembled and fixed. The back plate 321 includes a bottom plate 3211 and a sidewall 3212 formed by bending the edge of the bottom plate 3211. A first support structure 3213 is formed on the bottom plate 3211. The middle frame 322 includes a main structure 3221, a load-bearing structure 3222, and a second support structure 3223. The second support structure 3223 supports the load-bearing structure 3222. An optical film 323 and a light guide plate 324 are disposed between the first support structure 3213 and the load-bearing structure 3222, so that the first support structure 3213 supports the load-bearing structure 3222. An array substrate 310 is disposed on the side of the load-bearing structure 3222 away from the second support structure 3223. Figure 5 As shown, the backlight 325 is mounted on the base plate 321 and faces the light-emitting side of the light guide plate 324, forming a direct-lit backlight; Figure 6 As shown, the backlight 325 is disposed on the second support structure 3223 and is opposite to the side of the light guide plate 324 that is perpendicular to the light emitting side, thus forming a side-lit backlight.

[0063] The backlight 325 can be an LED (Light-Emitting Diode) backlight, a CCFL (Cold Cathode Fluorescent Lamp) backlight, an EL (Electro Luminescent) backlight, etc., and is not specifically limited here. The following explanation uses an LED backlight as an example, but this does not constitute a limitation of this disclosure.

[0064] An LED backlight includes light-emitting diodes (LEDs) and a backlight driving circuit for driving the LEDs to emit light. The backlight driving circuit includes a transistor connected to the LED. By applying a PWM signal to the control terminal of the transistor, the transistor is turned on for a certain period of time, causing the LED to emit light. By adjusting the duty cycle of the PWM signal applied to the control terminal of the transistor, the light-emitting duration of the LED can be adjusted, thereby adjusting the backlight brightness.

[0065] A second example provides a driving method for a display panel 30, applied to a timing controller 20. The method includes: in response to an enable pin (EN PIN) signal, controlling the display panel 30 to switch from a first display mode to a second display mode. The first display mode includes: controlling the refresh frequency of the display panel 30 to a first refresh frequency, controlling the shift register 410 in the gate driving circuit 40 to output valid operating levels sequentially, and providing a PWM signal to the backlight driving circuit with a first duty cycle. The second display mode includes: controlling the refresh frequency of the display panel 30 to a second refresh frequency, where the second refresh frequency is less than the first refresh frequency, controlling the shift register 410 in the gate driving circuit 40 connected to two adjacent rows of gate lines to simultaneously output valid operating levels, and providing a PWM signal to the backlight driving circuit with a second duty cycle, where the second duty cycle is less than the first duty cycle.

[0066] In this example, the system board 10 and the timing controller 20 can be connected via an eDP connector. A pin can be defined on the eDP connector. When the timing controller 20 receives an enable pin signal sent by the GPU 110 of the system board 10, it controls the display panel 30 to switch from the first display mode to the second display mode.

[0067] In this example, the timing controller 20 controls the display panel 30 to switch from the first display mode to the second display mode, reducing the refresh rate of the display panel 30. This reduces the number of times the shift register 410 in the gate drive circuit 40 outputs signals per unit time, thereby reducing the power consumption of the display panel 30. Increasing the number of shift registers 410 in the gate drive circuit 40 that simultaneously output valid operating levels to two further halves the pixel clock signal rate inside the timing controller 20 per unit time, thus reducing the power consumption of the timing controller 20 and further reducing the power consumption of the display panel 30. By scanning two rows of gate lines simultaneously, the logic resolution of the display panel 30 is reduced, but the size of the image displayed on the display panel 30 is not affected.

[0068] In this example, in the first display mode, the duty cycle of the PWM signal provided by the timing controller 20 to the backlight driving circuit is a first duty cycle, and in the second display mode, the duty cycle of the PWM signal provided by the timing controller 20 to the backlight driving circuit is a second duty cycle, which is less than the first duty cycle. The timing controller 20 controls the display panel 30 to switch from the first display mode to the second display mode, reducing the backlight brightness of the display panel 30, thereby reducing the power consumption of the display panel 30.

[0069] A third example provides a driving method for a display panel 30, applied to a timing controller 20. The method includes: in response to DPCD (Display Port Configuration data) information, controlling the display panel 30 to switch from a first display mode to a second display mode. The first display mode includes: controlling the refresh rate of the display panel 30 to a first refresh rate; controlling the shift register 410 in the gate driving circuit 40 to output valid operating levels one by one; providing the PWM signal to the backlight driving circuit with a first duty cycle; and providing the grayscale signal to each sub-pixel 330 of the display panel 30 with a first grayscale signal. The second display mode includes: controlling the refresh frequency of the display panel 30 to be a second refresh frequency, which is less than the first refresh frequency; controlling the shift register 410 in the gate drive circuit 40 connected to the two adjacent rows of gate lines to simultaneously output a valid working level; providing the PWM signal to the backlight drive circuit with a second duty cycle, which is less than the first duty cycle; and providing the grayscale signal to each sub-pixel 330 of the display panel 30 with a second grayscale signal, wherein for a sub-pixel 330, the grayscale corresponding to the second grayscale signal is higher than the grayscale corresponding to the first grayscale signal.

[0070] In this example, the GPU 110 on the system board 10 writes to the DPCD of the display panel 30, and the timing controller 20 controls the display panel 30 to switch from the first display mode to display in the second display mode.

[0071] In this example, the timing controller 20 controls the display panel 30 to switch from the first display mode to the second display mode, reducing the refresh rate of the display panel 30. This reduces the number of times the shift register 410 in the gate drive circuit 40 outputs signals per unit time, thereby reducing the power consumption of the display panel 30. Increasing the number of shift registers 410 in the gate drive circuit 40 that simultaneously output valid operating levels to two further halves the pixel clock signal rate inside the timing controller 20 per unit time, thus reducing the power consumption of the timing controller 20 and further reducing the power consumption of the display panel 30. The backlight brightness of the display panel 30 is also reduced, further lowering its power consumption. By scanning two rows of gate lines simultaneously, the logic resolution of the display panel 30 is reduced without affecting the size of the image displayed on the display panel 30.

[0072] In this example, for a sub-pixel 330, the grayscale corresponding to the second grayscale signal received in the second display mode is higher than the grayscale corresponding to the first grayscale signal received in the first display mode. The timing controller 20 controls the display panel 30 to switch from the first display mode to the second display mode, thereby increasing the display grayscale of each sub-pixel 330. This allows for some compensation for the overall reduction in display brightness of the display panel 30 caused by the reduction in backlight brightness, even when the backlight brightness is reduced. This reduces the impact of the reduced backlight brightness on the display effect of the display panel 30 without significantly increasing power consumption, thus still achieving the overall effect of reducing the power consumption of the display panel 30.

[0073] In some examples, for a sub-pixel 330, in the first display mode, the sum of its grayscale brightness and backlight brightness is the first brightness; when the grayscale signal provided to the sub-pixel 330 is the second grayscale signal, and the duty cycle of the PWM signal provided to the backlight driving circuit is the third duty cycle, the sum of the grayscale brightness of the sub-pixel 330 and the backlight brightness is the second brightness; making the second brightness the same as the first brightness, establishing a one-to-one correspondence between the second grayscale signal and the third duty cycle; the second display mode further includes: based on the one-to-one correspondence between the second grayscale signal and the third duty cycle for each sub-pixel 330, determining the second duty cycle of the PWM signal provided to the backlight driving circuit according to the number of sub-pixels 330 with different second grayscale signals, and the third duty cycle corresponding to each different second grayscale signal.

[0074] In one example, as shown in Table 1, there is a one-to-one correspondence between the second grayscale signal and the third duty cycle. The first duty cycle for providing the PWM signal to the backlight driving circuit is 100%. For a sub-pixel 330, the first duty cycle for providing the PWM signal to the backlight driving circuit is 100%, and the grayscale corresponding to the first grayscale signal is the second grayscale. The sum of the grayscale brightness of this sub-pixel 330 and the backlight brightness is the first brightness. Then, when the duty cycle for providing the PWM signal to the backlight driving circuit is reduced to 3%, the grayscale corresponding to the second grayscale signal of this sub-pixel 330 is increased to the 12th grayscale. The sum of the grayscale brightness of this sub-pixel 330 and the backlight brightness is the second brightness, which is the same as the first brightness. That is, by reducing the backlight brightness while increasing the display grayscale of the sub-pixel 330, the sum of the grayscale brightness of this sub-pixel 330 and the backlight brightness remains unchanged before and after adjusting the backlight brightness.

[0075] Table 1

[0076] First grayscale signal Second grayscale signal Third duty cycle V0 V5 0％ V2 V12 3％ V5 V17 6％ … … … V255 V255 100％

[0077] Based on the one-to-one correspondence between the second grayscale signal and the third duty cycle shown in Table 1, taking 20 sub-pixels 330 in the display panel 30 as an example, for a frame of image displayed by the display panel 30, in the first display mode, among these 20 sub-pixels 330, 2 sub-pixels 330 receive the first grayscale signal of grayscale level 30, 5 sub-pixels 330 receive the first grayscale signal of grayscale level 35, 7 sub-pixels 330 receive the first grayscale signal of grayscale level 58, and 6 sub-pixels 330 receive the first grayscale signal of grayscale level 90. The third duty cycle corresponding to grayscale level 30 is 18%, grayscale level 35 is 20%, grayscale level 58 is 25%, and grayscale level 90 is 32%. In the second display mode, the second duty cycle of the PWM signal provided to the backlight driving circuit can be (18% x 2 + 20% x 5 + 25% x 7 + 32% x 6) / 20 = 25.15%. The above is merely an example illustrating the method for determining the pulse duty cycle of the PWM signal provided to the backlight driving circuit in the second display mode and does not constitute a limitation of this disclosure.

[0078] In some examples, the second duty cycle of the PWM signal provided to the backlight drive circuit in the second display mode is determined according to the following formula:

[0079]

[0080] Where P represents the second duty cycle of the PWM signal provided to the backlight driving circuit, A1, A2, ..., An represent the number of each sub-pixel 330 with different second grayscale signals, n represents the number of different second grayscale signals, P1, P2, ..., Pn represent the third duty cycle corresponding to each different second grayscale signal, a represents the number of columns of sub-pixels 330 on the array substrate, b represents the number of rows of sub-pixels 330 on the array substrate, a×b represents the number of sub-pixels 330 on the array substrate, and K represents the compensation coefficient, which can be adjusted as needed.

[0081] In one example, in the first display mode, the timing controller controls the display panel's first refresh rate to 240Hz, the first resolution to 3840*2400, the first duty cycle of the backlight driver circuit's PWM signal to 100%, and the display grayscale of each sub-pixel to grayscale level 127. In the second display mode, the timing controller controls the display panel's second refresh rate to 1Hz, the second resolution to 3840*1200, the second duty cycle of the backlight driver circuit's PWM signal to 20%, and the display grayscale of each sub-pixel to grayscale level 255. In the first display mode, the display's logic power consumption is 3.5W, and the backlight power consumption is 10W. In the second display mode, the display's logic power consumption is 1.9W, and the backlight power consumption is 2.0W. Switching from the first display mode to the second display mode reduces the display panel's overall power consumption by 9.6W, a reduction of 71%.

[0082] This disclosure provides a driving method for a display panel 30, applied to a main control chip, comprising: after a timing controller 20 controls the display panel 30 to operate in a first display mode for a first preset time, sending a first signal to disconnect the main link communication with the timing controller 20; and sending a second signal to restore the main link communication with the timing controller 20.

[0083] In some examples, the main control chip can be a processor with data processing capabilities, such as a CPU (Central Processing Unit) or a GPU110. This disclosure uses a GPU110 as an example of a main control chip, but this should not be construed as limiting the scope of this disclosure.

[0084] In some examples, after the display panel 30 operates in PSR mode for a first preset time, the GPU 110 on the system board 10 sends a first signal to the timing controller 20, causing the timing controller 20 to control the display panel 30 to switch from the first display mode to a second display mode. The first preset time can be set as needed, for example, 20 minutes, 50 minutes, etc. After sending the first signal, the GPU 110 on the system board 10 can disconnect the main link communication with the timing controller 20 and stop sending frame image data to the timing controller 20. When the GPU 110 on the system board 10 needs the display panel 30 to switch from the second display mode to a third display mode, it sends a second signal to the timing controller 20 to restore the main link communication with the timing controller 20 and sends frame image data to the timing controller 20.

[0085] In other examples, the GPU 110 on the system board 10 may also send a first signal to the timing controller 20 based on other conditions. For example, the GPU 110 on the system board 10 may also send a first signal to the timing controller 20 according to the instructions received from the system CPU.

[0086] This disclosure provides a timing controller 20, which includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the driving method of the display panel 30 described above.

[0087] like Figure 7 As shown, in one example, the timing controller 20 may include a processor 210, a memory 220, a bus system 240, and a transceiver 230, wherein the processor 210, the memory 220, and the transceiver 230 are connected through the bus system 240, the memory 220 is used to store computer programs, and the processor 210 is used to execute the computer programs stored in the memory 220 to control the transceiver 230 to send and receive signals.

[0088] Processor 210 can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0089] Memory 220 may include read-only memory and random access memory, and provides computer programs and data to processor 210. A portion of memory 220 may also include non-volatile random access memory. For example, memory 220 may also store device type information.

[0090] In addition to a data bus, the bus system 240 may also include a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 The general labeled all buses as Bus System 240.

[0091] In implementation, the processing performed by the processing device can be accomplished through the integrated logic circuitry in the hardware of the processor 210 or through a computer program in software form. That is, the method steps of this embodiment can be executed by the hardware processor or by a combination of hardware and software modules in the processor.

[0092] This disclosure provides a display device that includes a timing controller 20 of any of the above examples.

[0093] In some examples, the display device also includes a source drive circuit 50, a gate drive circuit 40, and a display panel 30.

[0094] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the display panel driving method provided in any of the above embodiments of this disclosure.

[0095] Computer-readable media can include computer storage media (or non-transitory media) and communication media (or temporary media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0096] In the description of the embodiments of this disclosure, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0097] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the meaning of the above terms in this disclosure based on their understanding.

[0098] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A driving method for a display panel, applied to a timing controller, the driving method for the display panel comprising: In response to the first signal, the display panel is controlled to switch from the first display mode to the second display mode; The first display mode includes: controlling the refresh frequency of the display panel to a first refresh frequency, and controlling the shift registers in the gate drive circuit to output valid working levels one by one; The second display mode includes: controlling the refresh frequency of the display panel to a second refresh frequency, and controlling at least some shift registers in the gate drive circuit to simultaneously output valid operating levels, wherein the second refresh frequency is less than the first refresh frequency.

2. The driving method for the display panel according to claim 1, wherein, The second display mode includes: controlling the refresh frequency of the display panel to a second refresh frequency, and controlling the shift register in the gate drive circuit connected to the two adjacent rows of gate lines to simultaneously output a valid working level.

3. The driving method for the display panel according to claim 1, wherein, The first display mode further includes: providing a PWM signal to the backlight driving circuit with a first duty cycle; the second display mode further includes: providing a PWM signal to the backlight driving circuit with a second duty cycle, wherein the second duty cycle is less than the first duty cycle.

4. The driving method for the display panel according to claim 3, wherein, The first display mode further includes: the grayscale signal provided to each sub-pixel of the display panel is a first grayscale signal; the second display mode further includes: the grayscale signal provided to each sub-pixel of the display panel is a second grayscale signal; for a sub-pixel, the grayscale corresponding to the second grayscale signal is higher than the grayscale corresponding to the first grayscale signal.

5. The driving method for the display panel according to claim 4, wherein, For a sub-pixel, in the first display mode, the sum of its grayscale brightness and backlight brightness is the first brightness; when the grayscale signal provided to the sub-pixel is the second grayscale signal and the duty cycle of the PWM signal provided to the backlight driving circuit is the third duty cycle, the sum of the grayscale brightness of the sub-pixel and the backlight brightness is the second brightness. This makes the second brightness the same as the first brightness, establishing a one-to-one correspondence between the second grayscale signal and the third duty cycle; The second display mode further includes: based on the one-to-one correspondence between the second grayscale signal for each sub-pixel and the third duty cycle, determining the second duty cycle of the PWM signal provided to the backlight driving circuit according to the number of different sub-pixels of the second grayscale signal and the third duty cycle corresponding to each different second grayscale signal.

6. The driving method for a display panel according to claim 5, wherein, The second duty cycle of the PWM signal provided to the backlight drive circuit in the second display mode is determined according to the following formula: Where P represents the second duty cycle of the PWM signal provided to the backlight driving circuit, A1, A2, ..., An represent the number of each sub-pixel of the second grayscale signal, n represents the number of different second grayscale signals, P1, P2, ..., Pn represent the third duty cycle corresponding to each different second grayscale signal, a represents the number of columns of sub-pixels on the array substrate, b represents the number of rows of sub-pixels on the array substrate, a×b represents the number of sub-pixels on the array substrate, and K represents the compensation coefficient.

7. The driving method for a display panel according to claim 1, wherein, Also includes: In response to the first signal, record the handshake parameters between the controller chip and the main control chip; In response to the second signal, the main link communication with the main control chip is restored according to the handshake parameters, and the display panel is controlled to switch from the second display mode to the third display mode. The third display mode includes: controlling the refresh frequency of the display panel to the third refresh frequency, and controlling the shift registers in the gate drive circuit to output valid working levels one by one. The third refresh frequency is greater than the second refresh frequency.

8. The driving method for a display panel according to claim 1, wherein, The first signal includes any one of a command signal, a hard-wired signal, and a conditional trigger signal.

9. A method for driving a display panel, applied to a main control chip, comprising: After the timing controller controls the display panel to run in the first display mode for a first preset time, a first signal is sent to disconnect the main link communication with the timing controller. Send a second signal to restore main link communication with the timing controller.

10. A timing controller comprising a processor and a memory, the memory storing a computer program that, when executed by the processor, implements the driving method for a display panel as described in any one of claims 1 to 8.

11. A display device comprising the timing controller as claimed in claim 10.

Images