Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and can improve the problem of uneven display brightness in the case of multi-frequency display of the display panel. The display panel comprises: first display sub-areas and second display sub-areas arranged in sequence along a first direction; the refresh frequency of the first display sub-areas is different from the refresh frequency of the second display sub-areas; the second display sub-areas comprise first areas and second areas; the first display sub-areas, the first areas and the second areas all comprise a plurality of pixel rows, each pixel row comprises a plurality of sub-pixels arranged in sequence along a second direction; each sub-pixel comprises a pixel circuit, each pixel circuit comprises an initialization voltage terminal, and the initialization voltage terminal is used for providing an initialization voltage for the pixel circuit; the initialization voltage of the pixel circuit of the first display sub-areas is different from the initialization voltage of the pixel circuit of the first areas, and the initialization voltage of the pixel circuit of the first areas is different from the initialization voltage of the pixel circuit of the second areas.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, the requirements for the display effect of display panels are becoming increasingly higher. Currently, a single display panel can include at least two sub-display areas with different refresh rates, meaning the display panel can achieve multi-frequency display with different zones. However, in the case of multi-frequency display with different zones, there is a problem of uneven brightness on the display panel. Summary of the Invention

[0003] This invention provides a display panel and display device that can improve the problem of uneven display brightness in the case of multi-frequency display in the display panel, thereby improving the display effect of the display panel.

[0004] According to one aspect of the present invention, a display panel is provided, comprising:

[0005] A first display sub-area and a second display sub-area are arranged sequentially along a first direction; the refresh rates of the first display sub-area and the second display sub-area are different; the second display sub-area includes the first area and the second area, and the second area is located on the side of the first area away from the first display sub-area.

[0006] The first display sub-area, the first area, and the second area each include multiple pixel rows, and each pixel row includes multiple sub-pixels arranged sequentially along the second direction; wherein the first direction and the second direction intersect each other;

[0007] Each sub-pixel includes a pixel circuit, and each pixel circuit includes an initialization voltage terminal, which is used to provide an initialization voltage to the pixel circuit.

[0008] The initial voltage of the pixel circuit in the first display sub-region is different from the initial voltage of the pixel circuit in the first region, and the initial voltage of the pixel circuit in the first region is different from the initial voltage of the pixel circuit in the second region.

[0009] Optionally, the pixel circuit includes a driving module, and the initialization voltage is used to initialize the control terminal of the driving module;

[0010] The refresh rate of the first display sub-area is less than the refresh rate of the second display sub-area;

[0011] The absolute value of the initialization voltage of the first display sub-area is less than the absolute value of the initialization voltage of the first area, the absolute value of the initialization voltage of the first area is greater than the absolute value of the initialization voltage of the second area, and the absolute value of the initialization voltage of the first display sub-area is less than the absolute value of the initialization voltage of the second area.

[0012] Optionally, the driving module includes a driving transistor, which is a P-type transistor with a negative initial voltage.

[0013] Optionally, along the first direction, the initial voltage of multiple pixel rows in the first region gradually increases, and the initial voltage of each pixel row is the same; or, the initial voltage of multiple pixel rows in the first region is the same fixed value.

[0014] Optionally, the initial voltage of multiple pixel rows in the first region increases in a step-like manner, a curved manner, or a linear manner.

[0015] Optionally, along the first direction, the initial voltage of multiple pixel rows in the second region gradually increases, and the initial voltage of each pixel row is the same; or the initial voltage of multiple pixel rows in the second region is the same fixed value.

[0016] Optionally, the initial voltage of multiple pixel rows in the second region increases in a step-like manner, a curved manner, or a linear manner.

[0017] Optionally, along the first direction, the initial voltage of multiple pixel rows in the second display sub-region gradually increases;

[0018] Optionally, the initial voltage of multiple pixel rows in the second display sub-region increases in a step-like manner, a curved manner, or a linear manner.

[0019] Optionally, the display panel may also include:

[0020] The third display sub-area has the same refresh rate as the first display sub-area; the third display sub-area includes multiple pixel rows, and each pixel row includes multiple sub-pixels arranged sequentially along the second direction; the first display sub-area, the second display sub-area, and the third display sub-area are arranged sequentially along the first direction;

[0021] The initialization voltage of the pixel circuit in the third display sub-region is the same as the initialization voltage of the pixel circuit in the first display sub-region.

[0022] Optionally, the pixel circuit includes a driving module and a first initialization module. The first terminal of the first initialization module is connected to the control terminal or the second terminal of the driving module, and the second terminal of the first initialization module is the initialization voltage terminal. The first initialization module is used to initialize the control terminal of the driving module.

[0023] The display panel further includes: a first scanning circuit, which is connected to the control terminal of the first initialization module via a first scanning line; the first scanning circuit is used to transmit a first scanning signal sequentially to the control terminal of the first initialization module of each pixel circuit of the first display sub-area, the control terminal of the first initialization module of each pixel circuit of the first area, and the control terminal of the first initialization module of each pixel circuit of the second area.

[0024] Optionally, the display panel further includes: a third display sub-area, wherein the first display sub-area, the second display sub-area, and the third display sub-area are arranged sequentially along the first direction; and a first scanning circuit is used to transmit a first scanning signal sequentially to the control terminal of the first initialization module of each pixel circuit of the first display sub-area, the control terminal of the first initialization module of each pixel circuit of the second display sub-area, and the control terminal of the first initialization module of each pixel circuit of the third display sub-area.

[0025] Optionally, the pixel circuit may also include a compensation module, a data writing module, a first light emission control module, a second light emission control module, a second initialization module, a third initialization module, and a storage module;

[0026] The compensation module is connected between the control terminal and the second pole of the drive module; the first pole of the data writing module is connected to the data voltage; the second pole of the data writing module is connected to the first pole of the drive module, and the control terminal of the data writing module is connected to the third scan signal; the first pole of the first light-emitting control module is connected to the first power signal, the second pole of the first light-emitting control module is connected to the first pole of the drive module, the second pole of the drive module is connected to the first pole of the second light-emitting control module, the second pole of the second light-emitting control module is connected to the first pole of the light-emitting device, and the control terminals of the first and second light-emitting control modules are connected to the light-emitting control signal; the second pole of the second initialization module is connected to the second initialization voltage; the control terminals of the second and third initialization modules are connected to the fourth scan signal, the first pole of the third initialization module is connected to the first pole of the light-emitting device, and the second pole of the third initialization module is connected to the third initialization voltage; the first terminal of the storage module is connected to the control terminal of the drive module, and the second terminal of the storage module is connected to the first power signal;

[0027] The first pole of the second initialization module is connected to the second pole of the driver module or to the first pole of the driver module.

[0028] Optionally, the pixel circuit includes a compensation module; the compensation module is connected between the control terminal of the drive module and the second pole.

[0029] The display panel also includes: a second scanning circuit and multiple partition enable signal lines; the second scanning circuit is connected to the partition enable signal lines; the second scanning circuit is connected to the control terminal of the compensation module through the second scanning lines; the second scanning circuit is used to transmit the second scanning signal to the compensation module.

[0030] The second scanning circuit includes multiple cascaded shift register groups. Each shift register group includes k cascaded shift register units, where k is an integer greater than or equal to 2. Each shift register unit includes m shift registers, where m is an integer greater than or equal to 1. Different shift register units in the same shift register group are connected to different partition enable signal lines, and different shift register groups are connected to the same k partition enable signal lines. The output of each shift register is connected to the control terminal of the compensation module of the n-row pixel circuit, where n is an integer greater than or equal to 1.

[0031] The number of rows of the pixel circuit in the first region is greater than or equal to k*m*n rows.

[0032] According to another aspect of the present invention, a display device is provided, including the display panel described in any embodiment of the present invention.

[0033] The technical solution of this invention sets up a first display sub-region and a second display sub-region, with different refresh rates for the first and second display sub-regions. The second display sub-region includes a first region and a second region. Both the first and second display sub-regions include multiple pixel rows, and each pixel row includes multiple sub-pixels arranged sequentially along a second direction. Each sub-pixel includes a pixel circuit, and each pixel circuit includes an initialization voltage terminal used to provide an initialization voltage to the pixel circuit. The initialization voltage of the pixel circuit in the first display sub-region is different from that in the first region, and the initialization voltage of the pixel circuit in the first region is different from that in the second region. This allows the first display sub-region, the first region, and the second region to have different initialization voltages. By setting different initialization voltages, the luminous brightness of the sub-pixels can be adjusted, thereby compensating for the impact of load changes and improving the problem of uneven display brightness on the display panel.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a display panel displaying the same grayscale image.

[0037] Figure 2This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention.

[0038] Figure 3 This is a schematic diagram showing the level changes of different partition enable signals when moving from a low refresh rate display sub-area to a high refresh rate display sub-area.

[0039] Figures 4-7 This is a schematic diagram of a display panel and its corresponding initialization voltage provided in an embodiment of the present invention.

[0040] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention.

[0041] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention.

[0042] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention.

[0043] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] As people's living standards improve, they are constantly exposed to electronic products, leading to a surge in demand for display panels and rapid development in display technology. Ordinary display effects are no longer sufficient to meet people's quality of life. Another highlight is the use of zone refresh technology, where different areas of the display panel refresh at different frequencies. This results in better power efficiency and extends the lifespan of electronic products. However, when zone refresh is enabled, inconsistent frequencies in different areas can cause uneven display, such as dark or bright bands in certain sub-areas. Figure 1 This is a schematic diagram of a display panel displaying the same grayscale image. (See reference) Figure 1 When entering the partition refresh mode, the refresh rates of the first display sub-area 11, the second display sub-area 12, and the third display sub-area 13 of the display panel are different. When moving from a low refresh rate to a high refresh rate display sub-area, the first part of the pixel row of the high refresh rate display sub-area appears darker, causing uneven display brightness of the display panel. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 2 Under partitioned refresh, due to capacitor leakage in the low refresh rate display sub-area or the unstable voltage (stable voltage is) in the high refresh rate display sub-area... Figure 3 Factors such as a drop in voltage (corresponding to a straight line) can cause display sub-areas with low refresh rates to appear too bright or those with high refresh rates to appear too dark. Specifically, pixel circuit 22 includes compensation module 120. The control terminal of compensation module 120 receives the output signal of the second scanning circuit. The pulse frequency of the output signal of the second scanning circuit can be controlled by a partition enable signal. For example, Figure 3 This is a schematic diagram showing the level changes of different partition enable signals when moving from a low refresh rate display sub-region to a high refresh rate display sub-region. (Refer to...) Figure 3 , Figure 3The system includes four partition enable signal lines, VFE1, VFE2, VFE3, and VFE4, transmitting partition enable signals. The stable voltage of the partition enable signal VFE transmitted by VFE1, VFE2, VFE3, and VFE4 decreases sequentially. According to the inventor's research and analysis, the reason why the display sub-area at high refresh rates appears darker is that during the scanning process of a local refresh frame, when moving from a display sub-area at a low refresh rate (e.g., 1Hz) to a display sub-area at a high refresh rate (120Hz), the partition enable signal VFE needs to change from a low level to a high level. This is equivalent to a change in voltage between the low refresh rate (e.g., 1Hz) and the high refresh rate (e.g., 1Hz) display sub-area within a local refresh frame. During the time period corresponding to the display sub-area, the partition enable signal is at a disabled level, such as a low level, so that the second scanning circuit does not output a conduction pulse to the display sub-area with a low refresh rate, and continuously outputs the off level of the compensation module 120. During the scanning time period corresponding to the display sub-area with a high refresh rate (120Hz), the partition enable signal VFE is at an enabled level, such as a high level, so that the second scanning circuit outputs a conduction pulse to the display sub-area with a high refresh rate, so that the compensation module 120 is turned on. However, due to load changes, the partition enable signal VFE cannot switch directly from a low level to a high level, and there is a certain delay. Figure 3 The rise of the middle partition enable signal VFE is a delayed process, i.e., the area circled in red. This causes the high voltage at the control terminal of the transistor in the compensation module 120 of the first partition 121 to be lower than the subsequent stable state. The pull-down coupling of the transistor in the compensation module 120 is relatively weak, resulting in a deviation in the control terminal voltage of the transistor in the drive module 110. For example, the control terminal voltage is too high, causing the first part of the sub-pixel row of the high refresh rate display sub-region (i.e., the first partition 121) to appear darker and abnormal.

[0047] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, see reference. Figure 1 and Figure 2The display panel includes a first display sub-area 11 and a second display sub-area 12, arranged sequentially along a first direction X. The refresh rate of the first display sub-area 11 is different from that of the second display sub-area 12. The second display sub-area 12 includes a first area 121 and a second area 122, with the second area 122 located on the side of the first area 121 away from the first display sub-area 11. The first display sub-area 11, the first area 121, and the second area 122 each include multiple pixel rows 20, and each pixel row 20 includes multiple sub-pixels arranged sequentially along a second direction Y. 21; wherein, the first direction X and the second direction Y intersect each other; each sub-pixel 21 includes a pixel circuit 22, and each pixel circuit 22 includes an initialization voltage terminal, which is used to provide an initialization voltage Vrefn1 to the pixel circuit 22; the initialization voltage Vrefn1 of the pixel circuit 22 of the first display sub-region 11 is different from the initialization voltage Vrefn1 of the pixel circuit 22 of the first region 121, and the initialization voltage Vrefn1 of the pixel circuit 22 of the first region 121 is different from the initialization voltage Vrefn1 of the pixel circuit 22 of the second region 122.

[0048] The refresh rate of the first display sub-area 11 is different from that of the second display sub-area 12. For example, the refresh rate of the first display sub-area 11 can be lower than that of the second display sub-area 12. For instance, the refresh rate of the first display sub-area 11Hz can be 10Hz, 30Hz, 60Hz, or 120Hz. This embodiment of the invention addresses the problem of uneven brightness in the display panel by differentiating the initialization voltage in the main control unit (MCU) module of the display driver chip (DDIC). The main control unit can identify and bind the initialization voltage of the corresponding area based on the partition refresh coordinates, i.e., the number of pixels at the beginning and end of the high refresh rate area, or the information of the display position. The flexible variation of the initialization voltage in different areas can improve the brightness of the first area 121 and avoid the problem of poor display effect in the dark areas of the first area 121.

[0049] The first display sub-region 11, the first region 121, and the second region 122 each include multiple pixel rows 20, which are spaced apart. Each pixel row 20 includes multiple sub-pixels 21 arranged sequentially along the second direction Y. Each sub-pixel 21 includes a pixel circuit 22 and a light-emitting device 200. The pixel circuit 22 can be used to drive the light-emitting device 200 to emit light. The light-emitting device 200 may include an OLED. In one image frame, the initialization voltage terminal provides an initialization voltage Vrefn1 to the first display sub-region 11 during a first time period. The pixel circuit 22 corresponding to the sub-pixels 21 of the multiple pixel rows 20 in the first display sub-region 11 receives the initialization voltage Vrefn1 of the first display sub-region 11. The initialization voltage terminal provides an initialization voltage Vrefn1 to the first region 121 during a second time period. The pixel circuit 22 corresponding to the sub-pixels 21 of the multiple pixel rows 20 in the first region 121 receives the initialization voltage Vrefn1 of the first region 121. The initialization voltage terminal provides an initialization voltage Vrefn1 to the second region 122 during a third time period. The pixel circuit 22 corresponding to the sub-pixels 21 of the multiple pixel rows 20 in the second region 122 receives the initialization voltage Vrefn1 of the second region 122.

[0050] For example, the initialization voltage Vrefn1 can be the voltage used to initialize the control terminal of the driving module 110 of the pixel circuit. By providing different initialization voltages Vrefn1 to different areas, the excessively large voltage of the control terminal of the driving module 110 can be offset, changing the driving current of the sub-pixels in the first area 121, thereby adjusting the light emission brightness of the sub-pixels in the first area 121 and avoiding the appearance of dark bands in the first area 121 that cause uneven display brightness of the display panel. Alternatively, the initialization voltage can be the voltage used to initialize the anode of the light-emitting device 200. By providing different initialization voltages Vrefn1 to different areas, the driving current corresponding to the light-emitting element 20 can be changed, thereby adjusting the brightness of each sub-pixel and improving the problem of uneven display brightness of the display panel.

[0051] In this embodiment of the invention, the initialization voltage Vrefn1 of the pixel circuit 22 of the first display sub-region 11 is different from that of the pixel circuit 22 of the first region 121, and the initialization voltage Vrefn1 of the pixel circuit 22 of the first region 121 is different from that of the pixel circuit 22 of the second region 122. That is, the first display sub-region 11, the first region 121 and the second region 122 have different initialization voltages Vrefn1, thereby adjusting the driving current output by the pixel circuits of the first display sub-region 11, the first region 121 and the second region 122, so that the light emission brightness of the first display sub-region 11, the first region 121 and the second region 122 is similar or the same, thereby improving the problem of uneven display brightness of the display panel.

[0052] The technical solution of this embodiment of the invention sets up a first display sub-region 11 and a second display sub-region 12, with the refresh frequency of the first display sub-region 11 being different from that of the second display sub-region 12; the second display sub-region 12 includes a first region 121 and a second region 122, and both the first display sub-region 11, the first region 121 and the second region 122 include multiple pixel rows 20, each pixel row 20 including multiple sub-pixels 21 arranged sequentially along the second direction Y, each sub-pixel 21 including a pixel circuit 22, and each pixel circuit 22 including an initialization voltage terminal, which is used to provide an initialization voltage Vre to the pixel circuit 22. fn1; The initialization voltage Vrefn1 of the pixel circuit 22 of the first display sub-region 11 is different from the initialization voltage Vrefn1 of the pixel circuit 22 of the first region 121. The initialization voltage Vrefn1 of the pixel circuit 22 of the first region 121 is different from the initialization voltage Vrefn1 of the pixel circuit 22 of the second region 122. This adjusts the driving current output by the pixel circuits of the first display sub-region 11, the first region 121 and the second region 122, so that the light emission brightness of the first display sub-region 11, the first region 121 and the second region 122 is similar or the same, thus improving the problem of uneven display brightness of the display panel.

[0053] Optional, see reference Figure 1 and Figure 2 The pixel circuit 22 includes a driving module 110, and an initialization voltage Vrefn1 is used to initialize the control terminal G of the driving module 110. The refresh frequency of the first display sub-area 11 is less than the refresh frequency of the second display sub-area 12. The absolute value of the initialization voltage Vrefn1 of the first display sub-area 11 is less than the absolute value of the initialization voltage Vrefn1 of the first area 121, the absolute value of the initialization voltage Vrefn1 of the first area 121 is greater than the absolute value of the initialization voltage Vrefn1 of the second area 122, and the absolute value of the initialization voltage Vrefn1 of the first display sub-area 121 is less than the absolute value of the initialization voltage Vrefn1 of the second area 122.

[0054] In this system, the refresh rate of the first display sub-area 11 is lower than that of the second display sub-area 12. In the partitioned refresh mode, the first area 121 will produce a dark band, and the brightness of the first display sub-area 11, the first area 121, and the second area 122 will exhibit a bright-dark-bright phenomenon. The luminous brightness of the sub-pixel 21 is related to the magnitude of the driving current. The initial voltage of the control terminal G of the driving module 110 can be adjusted by the initialization voltage Vrefn1. The larger the absolute value of the initialization voltage Vrefn1, the more fully the capacitor Cst in the storage module 190 in the pixel circuit 22 is reset. The larger the absolute value of the initialization voltage of the control terminal G of the driving module 110, the larger the driving current output by the driving module 110 under the same data voltage, and the higher the luminous brightness of the sub-pixel 21. Therefore, the absolute value of the initialization voltage Vrefn1 of the first display sub-area 11 is set to be less than the absolute value of the initialization voltage Vrefn1 of the first area 121, and the absolute value of the initialization voltage Vrefn1 of the first area 121 is greater than the absolute value of the initialization voltage Vrefn1 of the second area 122. The absolute value of the initialization voltage Vrefn1 of the first display sub-area 121 is less than the absolute value of the initialization voltage Vrefn1 of the second area 122. That is, the absolute value of the initialization voltage Vrefn1 of the first area 121 > the absolute value of the initialization voltage Vrefn1 of the second area 122 > the absolute value of the initialization voltage Vrefn1 of the first display sub-area 11. The first area 121 has a large absolute value of initialization voltage Vrefn1, which can offset the voltage deviation of the control terminal of the drive module 110, thereby reducing the brightness difference between the first display sub-area 11, the first area 121 and the second area 122, and achieving overall brightness balance of the display panel. This avoids the problem of uneven display brightness of the display panel and improves the display brightness of the display panel.

[0055] Optional, see reference Figure 2 The driving module 110 includes a driving transistor T1, which is a P-type transistor with a negative initial voltage.

[0056] The driving module 110 includes a driving transistor T1, which is a P-type transistor. An initialization voltage Vrefn1 provides a negative voltage value to the driving transistor T1. For example, the initialization voltage Vrefn1 of the first display sub-area 11 can be -4V, the initialization voltage Vrefn1 of the first area 121 can be -4.5V, and the initialization voltage Vrefn1 of the second area 122 can be -4.2V. Since a lower initialization voltage leads to a more sufficient reset of the storage capacitor Cst in the storage module 190, the voltage at the control terminal of the driving module 110 will be lower. This increases the driving current output by the driving module 110, improves the brightness of the sub-pixels, and raises the overall brightness of the first area 121 to match that of the first display sub-area 11. This reduces the brightness difference between the first area 121 and the first display sub-area, preventing dark bands from appearing in the high refresh rate area of ​​the first area 121, thereby improving the display effect of the display panel.

[0057] Optional, Figures 4-7 This is a schematic diagram of a display panel and its corresponding initialization voltage provided in an embodiment of the present invention. (Refer to...) Figure 2 , Figures 4-7 Along the first direction X, the initial voltage Vrefn1 of the multiple pixel rows 20 of the first region 121 gradually increases, and the initial voltage Vrefn1 of each pixel row 20 is the same; or, the initial voltage Vrefn1 of the multiple pixel rows 20 of the first region 121 is the same fixed value.

[0058] in, Figure 4 The left side shows a schematic diagram of the display panel. Figure 4 The right side includes initialization voltages Vrefn1 corresponding to different display sub-regions. The first region 121 includes multiple pixel rows 20, each pixel row 20 includes multiple sub-pixels 21 arranged along the second direction Y, and each sub-pixel 21 includes a pixel circuit 22. The initialization voltages Vrefn1 of the pixel circuits 22 of the multiple sub-pixels 21 in each pixel row 20 are the same. Along the first direction X, the initialization voltages Vrefn1 of the multiple pixel rows 20 in the first region 121 are gradually increased. Figures 4-7The initial voltage Vrefn1 of the first zone 121 is gradually increased. The smaller the initial voltage Vrefn1, the larger the absolute value of the initial voltage Vrefn1. Since the pixel row of the first display sub-zone 11 adjacent to the first zone 121 is darker than the pixel row 20 of the second zone 122 adjacent to the first zone 121, the initial voltage Vrefn1 of the first zone 121 is gradually increased. The brightness of the pixel row that is closer to the first zone 121 increases, so that the brightness of each pixel row of the first zone 121 is close to that of the first display sub-zone 11. This further reduces the difference in display brightness of the sub-pixels 21 of adjacent pixel rows 20 and improves the display effect of the display panel.

[0059] Along the first direction X, setting the initial voltage Vrefn1 of multiple pixel rows 20 in the first area 121 to the same fixed value can make the initial voltage Vrefn1 of the pixel circuit 22 of each sub-pixel 21 in the first area 121 the same, making the driving method simpler, and can reduce the difference in luminous brightness between the sub-pixel 21 in the first area 121 and the sub-pixel in the first display sub-area 11, reduce the difference in display brightness of the display panel, and improve the display effect of the display panel.

[0060] Optional, see reference Figure 2 , Figures 4-7 The initial voltage Vrefn1 of multiple pixel rows 20 in the first region 121 increases in a step-like manner, a curved manner, or a straight manner.

[0061] in, Figure 4 and Figure 5 The initial voltage Vrefn1 in the first region 121 increases linearly. Figure 6 and Figure 7 The initial voltage Vrefn1 of the first zone 121 increases in a step-like manner; the initial voltage Vrefn1 of the first zone 121 can increase in a step-like manner, a curve, or a straight line, and the driving method is simple. Specifically, the growth mode of the initial voltage Vrefn1 can be selected according to the brightness distribution of each pixel row in the first zone 121, so as to achieve precise control of the brightness of each pixel row in the first zone 121, reduce the display brightness difference of the display panel, and improve the display effect of the display panel.

[0062] Optional, see reference Figure 2 , Figures 4-7 The initial voltage Vrefn1 of multiple pixel rows 20 in the second region 122 gradually increases, and the initial voltage Vrefn1 of each pixel row 20 is the same; or the initial voltage Vrefn1 of multiple pixel rows 20 in the second region 122 is a fixed value.

[0063] in, Figure 4 and Figure 6The initial voltage Vrefn1 of multiple pixel rows 20 in the second region 121 is the same fixed value. Figure 5 and Figure 7 The initialization voltage Vrefn1 of multiple pixel rows 20 in the second region 121 gradually increases. Since the enable signal voltage in the second region 122 tends to be stable, the brightness of the second region 122 is close to that in the first display sub-region 11. Therefore, it is necessary to set the initialization voltage Vrefn1 in the second region 122 to be close to the initialization voltage Vrefn1 in the first display sub-region 11. By setting the initialization voltage Vrefn1 of multiple pixel rows 20 in the second region 122 to gradually increase along the first direction X, that is, the absolute value of the initialization voltage Vrefn1 in the second region 122 gradually decreases, so that the initialization voltage Vrefn1 of the second region 122 gradually transitions to be close to the initialization voltage Vrefn1 of the first display sub-region 11, avoiding a sudden change in the initialization voltage of the second region 122, which would cause a sudden change in brightness at the junction of the second region 122 and the first region 121. Furthermore, when there is a third display sub-area 13 with a low refresh rate in the display panel, the initialization voltage of the sub-pixels of the second area 122 can smoothly transition to the same initialization voltage as the third display sub-area 13, avoiding brightness changes at the junction of the second area 122 and the third display sub-area 13 due to changes in the initialization voltage Vrefn1, thereby reducing the difference in display brightness of the display panel and improving the display effect of the display panel.

[0064] Along the first direction X, setting the initial voltage Vrefn1 of multiple pixel rows 20 in the second region 122 to the same fixed value ensures that the initial voltage Vrefn1 of the pixel circuit 22 of each sub-pixel 21 in the second region 122 is the same, simplifying the driving method and improving the display effect of the display panel. Optionally, the initial voltage Vrefn1 of multiple pixel rows 20 in the second region 122 increases in a step-like manner, a curved manner, or a linear manner.

[0065] The initial voltage Vrefn1 of the second zone 122 increases in a step-like, curved, or linear manner. The driving method is simple. Specifically, the growth mode of the initial voltage Vrefn1 can be selected according to the brightness distribution of each pixel row in the second zone 122, so as to achieve precise control of the brightness of each pixel row in the second zone 122, reduce the brightness difference of the display panel, and improve the display effect of the display panel.

[0066] Optional, see reference Figure 2 and Figure 5 Along the first direction X, the initial voltage Vrefn1 of multiple pixel rows 20 of the second display sub-region 12 gradually increases.

[0067] In this process, the initial voltage Vrefn1 of the multi-row pixel circuit 22 in the second display sub-area 12 gradually increases. The initial voltage Vrefn1 of the second area 122 is greater than the initial voltage Vrefn1 of the first area 121. While reducing the difference in luminous brightness between the first area 121 and the first display sub-area 11 and the second area 122, the luminous brightness of the second display sub-area 12 can be smoothly transitioned, making the display brightness of the second display sub-area 12 more uniform and the overall display effect of the display panel better.

[0068] Optionally, the initial voltage Vrefn1 of the multiple pixel rows 20 of the second display sub-region 12 increases in a step-like manner, a curved manner, or a linear manner.

[0069] Among them, the initial voltage Vrefn1 of the second display sub-region 12 increases in a step-like manner, a curved manner, or a linear manner, which makes the driving method simpler.

[0070] Optional, see reference Figure 4 The display panel also includes: a third display sub-area 13, the refresh rate of the third display sub-area 13 being the same as the refresh rate of the first display sub-area 11; the third display sub-area 13 including a plurality of pixel rows 20, each pixel row 20 including a plurality of sub-pixels 21 arranged sequentially along the second direction Y; the first display sub-area 11, the second display sub-area 12 and the third display sub-area 13 are arranged sequentially along the first direction X; the initialization voltage Vrefn1 of the pixel circuit 22 of the third display sub-area 13 is the same as the initialization voltage Vrefn1 of the pixel circuit 22 of the first display sub-area 11.

[0071] The refresh rate of the third display sub-area 13 is lower than that of the second display sub-area 12, but equal to that of the first display sub-area 11. By setting the first display sub-area 11, second display sub-area 12, and third display sub-area 13 along the first direction X of the display panel, it can be adapted to the display requirements of different areas of the display panel. The initialization voltage Vrefn1 of the pixel circuit of the third display sub-area 13 is the same as that of the pixel circuit of the first display sub-area 11. This simplifies the driving algorithm, facilitates control, and ensures that the display brightness of the first display sub-area 11 is the same as that of the third display sub-area 13, thereby reducing the difference in display brightness across the display panel and improving its overall brightness.

[0072] Optional, Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 2 , Figures 4-7 and Figure 8The pixel circuit 22 includes a driving module 110 and a first initialization module 130. The first terminal of the first initialization module 130 is connected to the control terminal G or the second terminal D of the driving module 110, and the second terminal of the first initialization module 130 is the initialization voltage terminal. The first initialization module 130 is used to initialize the control terminal G of the driving module 110.

[0073] The display panel further includes: a first scanning circuit, which is connected to the control terminal of the first initialization module 130 via a first scanning line; the first scanning circuit is used to transmit a first scanning signal SN1 sequentially to the control terminal of the first initialization module 130 of each pixel circuit 22 of the first display sub-area 11, the control terminal of the first initialization module 130 of each pixel circuit 22 of the first area 121, and the control terminal of the first initialization module 130 of each pixel circuit 22 of the second area 122.

[0074] The driving module 110 and the first initialization module 130 each include transistors. For example, the driving module 110 includes a P-type driving transistor T1, and the first initialization module includes an N-type fourth transistor T4. (Reference) Figure 2 , Figure 2 The first terminal of the first initialization module 130 is connected to the second terminal D of the drive module 110. Under the control of the first scan signal SN1, the initialization voltage Vrefn1 in the first initialization module 130 is transmitted to the control terminal G of the drive transistor through the first initialization module 130 and the compensation module 120 to initialize the control terminal G of the drive module 110; Reference Figure 8 , Figure 8 The first terminal of the first initialization module 130 is connected to the control terminal G of the driving module 110. Under the control of the first scan signal SN1, the initialization voltage Vrefn1 in the first initialization module 130 is transmitted to the control terminal G of the driving transistor through the first initialization module 130 to initialize the control terminal G of the driving module 110. By adjusting the initialization voltage Vrefn1 of different display sub-areas, the driving current of the pixel circuit 22 can be adjusted, thereby adjusting the light emission brightness of the sub-pixels in the pixel circuit 22, so that the brightness of different display sub-areas is balanced, and the display effect of the display panel is improved.

[0075] Specifically, the first scanning circuit is used to sequentially transmit the first scanning signal SN1 to the control terminal of the first initialization module 130 of each pixel circuit 22 of the first display sub-area 11, the control terminal of the first initialization module 130 of each pixel circuit 22 of the first area 121, and the control terminal of the first initialization module 130 of each pixel circuit 22 of the second area 122. The first display sub-area 11 with a low refresh rate usually corresponds to a large area of ​​background in the image. These parts have relatively small changes, and a low refresh rate can meet the visual requirements. Scanning the first display sub-area 11 with a low refresh rate first can reduce the refresh power consumption of this area while ensuring the visual effect. The first area 121 and the second area 122 with a high refresh rate contain information such as image details and require a higher refresh rate to present a clear effect. However, since their area is relatively small, scanning the low-frequency area first and then performing high-frequency scanning can avoid unnecessary power waste and achieve optimized power management.

[0076] Optional, see reference Figures 4-7 and Figure 8 The display panel also includes a third display sub-area 13, with the first display sub-area 11, the second display sub-area 12 and the third display sub-area 13 arranged sequentially along the first direction X; the first scanning circuit is used to sequentially transmit the first scanning signal SN1 to the control terminal of the first initialization module 130 of each pixel circuit 22 of the first display sub-area 11, the control terminal of the first initialization module 130 of each pixel circuit 22 of the second display sub-area 12 and the control terminal of the first initialization module 130 of each pixel circuit 22 of the third display sub-area 13.

[0077] In this process, the first scanning circuit sequentially transmits the first scanning signal SN1 to the control terminals of the first initialization module 130 of each pixel circuit 22 in the first display sub-area 11, the second display sub-area 12, and the third display sub-area 13. The first and third display sub-areas 11 and 13, which have low refresh rates, typically correspond to large areas of background in the image. These areas have relatively small variations, and a lower refresh rate is sufficient to meet visual requirements. Scanning the first display sub-area 11, which has a low refresh rate, firstly reduces the refresh power consumption of this area while ensuring visual quality. The first and second areas 121 and 122, which have high refresh rates, contain details and other information in the image and require higher refresh rates to present a clear effect. However, since their areas are relatively small, scanning the low-frequency areas first and then performing high-frequency scanning avoids unnecessary power consumption waste and optimizes power consumption management. Finally, scanning the third display sub-area 13, which has a low refresh rate, further optimizes the overall power consumption without affecting the visual quality, achieving refined power consumption management.

[0078] Optional, Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 2 , Figure 8 , Figure 9 and Figure 10 The pixel circuit 22 also includes a compensation module 120, a data writing module 140, a first light-emitting control module 150, a second light-emitting control module 160, a second initialization module 170, a third initialization module 180, and a storage module 190. The compensation module 120 is connected between the control terminal G and the second electrode D of the driving module 110. The first electrode of the data writing module 140 is connected to the data voltage Data. The second electrode of the data writing module 140 is connected to the first electrode S of the driving module 110, and the control terminal of the data writing module 140 is connected to the third scan signal SP1. The first electrode of the first light-emitting control module 150 is connected to the first power signal ELVDD, and the second electrode of the first light-emitting control module 150 is connected to the first electrode S of the driving module 110. The second electrode D of the driving module 110 is connected to the first electrode of the second light-emitting control module 160. The second light-emitting control module 160... The second electrode of the 0 module is electrically connected to the first electrode of the light-emitting device 200. The control terminals of the first light-emitting control module 150 and the second light-emitting control module 160 are connected to the light-emitting control signal EM. The second electrode of the second initialization module 170 is connected to the second initialization voltage Vrefp. The control terminals of the second initialization module 170 and the third initialization module 180 are connected to the fourth scan signal SP2. The first electrode of the third initialization module 180 is connected to the first electrode of the light-emitting device 200. The second electrode of the third initialization module 180 is connected to the third initialization voltage Vrefn2. The first terminal of the storage module 190 is connected to the control terminal G of the driving module 110. The second terminal of the storage module 190 is connected to the first power signal ELVDD. The first electrode of the second initialization module 170 is connected to the second electrode D of the driving module 110 or to the first electrode S of the driving module 110.

[0079] The third and fourth scan signals are both transmitted by the third scan circuit. The compensation module 120, data writing module 140, first light-emitting control module 150, second light-emitting control module 160, second initialization module 170, and third initialization module 180 each include transistors. For example, the compensation module 120 includes an N-type third transistor T3, the data writing module 140 includes a P-type second transistor T2, the first light-emitting control module 150 includes a P-type fifth transistor T5, the second light-emitting control module 160 includes a P-type sixth transistor T6, the second initialization module 170 includes a P-type eighth transistor T8, the third initialization module 180 includes a P-type seventh transistor T7, and the storage module 190 includes a storage capacitor Cst. The second electrode of the light-emitting device 200 is connected to the second power supply signal ELVSS.

[0080] Figure 9 The first pole of the second initialization module 170 is connected to the first pole S of the drive module 110. Under the control of the fourth scan signal SP2, the second initialization voltage Vrefp in the second initialization module 170 is transmitted to the first pole S of the drive module 110, and the first pole S of the drive module 110 is initialized. Figure 10 The first pole of the second initialization module 170 is connected to the second pole D of the drive module 110. Under the control of the fourth scan signal SP2, the second initialization voltage Vrefp in the second initialization module 170 is transmitted to the second pole D of the drive module 110 to initialize the second pole D of the drive module 110.

[0081] For details, please refer to Figure 2 , Figure 2 The driving process of the pixel circuit 22 may include:

[0082] During the initialization phase of the control terminal G of the driving transistor T1, both the first scan signal SN1 and the second scan signal SN2 can be high voltage, and both the third transistor T3 and the fourth transistor T4 are turned on. The initialization voltage Vrefn1 is transmitted to the gate of the driving transistor T1 through the third transistor T3 and the fourth transistor T4, thereby initializing the gate of the driving transistor T1.

[0083] During the data writing phase, the second scan signal SN2 can be a high voltage, the third scan signal SP1 is a low voltage, and both the third transistor T3 and the second transistor T2 are turned on. The data voltage Vdata is transmitted to the control terminal G of the driving transistor T1 through the second transistor T2, the driving transistor T1 and the third transistor T3 to charge the storage capacitor Cst.

[0084] During the anode initialization phase, the fourth scan signal SP2 is at a low voltage, and both the eighth transistor T8 and the seventh transistor T7 are turned on. The second initialization voltage Vrefp in the second initialization module 170 is transmitted to the second terminal D of the driving transistor T1 through the eighth transistor T8 to initialize the second terminal D of the driving transistor T1. The third initialization voltage Vrefn2 in the third initialization module 180 is transmitted to the anode of the light-emitting device 200 through the seventh transistor T7 to initialize the anode of the light-emitting device 200.

[0085] During the light-emitting stage, the light-emitting control signal EM is at a low voltage, and both the fifth transistor T5 and the sixth transistor T6 are turned on; the driving transistor T1 generates a driving current according to the voltage of its control terminal G, driving the light-emitting device to emit light.

[0086] The driving process of pixel circuit 22 is the same as that of the refresh frame. During the hold frame, the second scan signal SN2 remains at a low voltage, the third transistor T3 remains off, and neither the initialization nor data writing phases of the control terminal G of the driving transistor T1 are performed. The voltage at the control terminal G of the driving transistor T1 is maintained by the storage capacitor Cst. Therefore, by adjusting the voltage of the partition enable signal VFE, multi-frequency partition display can be achieved.

[0087] Optional, Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention, see reference. Figure 11 and Figure 2 The pixel circuit includes a compensation module 120; the compensation module 120 is connected between the control terminal G and the second pole D of the drive module 110.

[0088] The display panel also includes: a second scanning circuit and multiple partition enable signal lines, the second scanning circuit being connected to the partition enable signal lines; the second scanning circuit being connected to the control terminal of the compensation module 120 via the second scanning lines; the second scanning circuit being used to transmit the second scanning signal SN2 to the compensation module 120;

[0089] The second scanning circuit includes multiple cascaded shift register groups 30, each group comprising k cascaded shift register units 31, where k is an integer greater than or equal to 2; each shift register unit 31 comprises m shift registers 32, where m is an integer greater than or equal to 1; different shift register units 31 within the same shift register group are connected to different partition enable signal lines, and different shift register groups 30 are connected to the same k partition enable signal lines; the output of each shift register 32 is connected to the control terminal of the compensation module 120 of the n-row pixel circuit 22, where n is an integer greater than or equal to 1; the number of rows of the pixel circuit 22 in the first region 121 is greater than or equal to k*m*n rows.

[0090] The second scanning circuit transmits a second scanning signal SN2 to the compensation module 120. The second scanning circuit also generates the second scanning signal SN2 based on a partition enable signal. The second scanning signal SN2 is connected to the control terminal of the compensation module 23. The display panel includes multiple partition enable signal lines, each of which can receive a partition enable signal VFE output by the chip. The number of rows of the pixel circuit 22 in the first area 121 is greater than or equal to k*m*n rows, the number of rows of the pixel circuit 22 in the second area 122 is greater than or equal to k*m*n rows, and the number of rows of the pixel circuit 22 in the second display sub-area 12 is greater than or equal to k*m*n rows. All shift registers 31 in the second scanning circuit can be connected to the same partition enable signal line. The second scanning line 33 extends along the second direction Y. Figure 11 The shift register group 30 of the second scanning circuit in the display panel can include four cascaded shift register units 31 and four partition enable signal lines, namely VFE1, VFE2, VFE3 and VFE4; one partition enable signal line is connected to m shift registers 32 in one shift register unit 30; each partition enable signal line can drive an m*n row pixel circuit driven by one shift register unit 30, and the number of rows driven by the four partition enable signal lines is one cycle. For example, Figure 11 The diagram illustrates the case where k=4, m=4, and n=4. The display panel includes a first display sub-area 11, a second display sub-area 12, and a third display sub-area 13. The first display sub-area 11 and the third display sub-area 13 have a low refresh rate, while the second display sub-area 12 has a high refresh rate. The minimum number of pixel rows in the first display sub-area 11, the second display sub-area 12, and the third display sub-area 13 is 64 rows. Specifically, the minimum number of pixel rows in the first area of ​​the second display sub-area 12 is 64 rows.

[0091] Based on the above embodiments, this invention also provides a display device, including the display panel described in any embodiment of this invention.

[0092] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0093] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: A first display sub-area and a second display sub-area are arranged sequentially along a first direction; the refresh rate of the first display sub-area is different from the refresh rate of the second display sub-area; the second display sub-area includes a first area and a second area, and the second area is located on the side of the first area away from the first display sub-area; The first display sub-area, the first area, and the second area all include multiple pixel rows, and each pixel row includes multiple sub-pixels arranged sequentially along the second direction; wherein the first direction and the second direction intersect each other; Each of the sub-pixels includes a pixel circuit, and each of the pixel circuits includes an initialization voltage terminal, which is used to provide an initialization voltage to the pixel circuit. The initial voltage of the pixel circuit in the first display sub-region is different from the initial voltage of the pixel circuit in the first region, and the initial voltage of the pixel circuit in the first region is different from the initial voltage of the pixel circuit in the second region.

2. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving module, and the initialization voltage is used to initialize the control terminal of the driving module; The refresh rate of the first display sub-area is lower than the refresh rate of the second display sub-area; The absolute value of the initialization voltage of the first display sub-area is less than the absolute value of the initialization voltage of the first area, the absolute value of the initialization voltage of the first area is greater than the absolute value of the initialization voltage of the second area, and the absolute value of the initialization voltage of the first display sub-area is less than the absolute value of the initialization voltage of the second area. Preferably, the driving module includes a driving transistor, which is a P-type transistor, and the initialization voltage is negative.

3. The display panel according to claim 2, characterized in that, Along the first direction, the initial voltage of multiple pixel rows in the first region gradually increases, and the initial voltage of each pixel row is the same; or, the initial voltage of multiple pixel rows in the first region is the same fixed value. Preferably, the initial voltage of the multiple pixel rows in the first region increases in a step-like manner, a curved manner, or a linear manner.

4. The display panel according to claim 2, characterized in that, Along the first direction, the initial voltage of multiple pixel rows in the second region gradually increases, and the initial voltage of each pixel row is the same; or the initial voltage of multiple pixel rows in the second region is the same fixed value. Preferably, the initial voltage of the multiple pixel rows in the second region increases in a step-like manner, a curved manner, or a linear manner.

5. The display panel according to claim 1, characterized in that, Along the first direction, the initial voltage of multiple pixel rows in the second display sub-region gradually increases; Preferably, the initial voltage of the multiple pixel rows in the second display sub-region increases in a step-like manner, a curved manner, or a linear manner.

6. The display panel according to claim 1, characterized in that, The display panel also includes: The third display sub-area has the same refresh rate as the first display sub-area; the third display sub-area includes multiple pixel rows, and each pixel row includes multiple sub-pixels arranged sequentially along the second direction; the first display sub-area, the second display sub-area, and the third display sub-area are arranged sequentially along the first direction. The initialization voltage of the pixel circuit in the third display sub-region is the same as the initialization voltage of the pixel circuit in the first display sub-region.

7. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving module and a first initialization module. The first terminal of the first initialization module is connected to the control terminal or the second terminal of the driving module, and the second terminal of the first initialization module is the initialization voltage terminal. The first initialization module is used to initialize the control terminal of the drive module; The display panel further includes: a first scanning circuit, which is connected to the control terminal of the first initialization module via a first scanning line; the first scanning circuit is used to transmit a first scanning signal sequentially to the control terminal of the first initialization module of each pixel circuit of the first display sub-area, the control terminal of the first initialization module of each pixel circuit of the first area, and the control terminal of the first initialization module of each pixel circuit of the second area. Preferably, the display panel further includes: a third display sub-area, wherein the first display sub-area, the second display sub-area, and the third display sub-area are arranged sequentially along the first direction; the first scanning circuit is used to transmit a first scanning signal sequentially to the control terminal of the first initialization module of each pixel circuit of the first display sub-area, the control terminal of the first initialization module of each pixel circuit of the second display sub-area, and the control terminal of the first initialization module of each pixel circuit of the third display sub-area.

8. The display panel according to claim 7, characterized in that, The pixel circuit also includes a compensation module, a data writing module, a first light emission control module, a second light emission control module, a second initialization module, a third initialization module, and a storage module; The compensation module is connected between the control terminal and the second pole of the driving module; the first pole of the data writing module is connected to a data voltage; the second pole of the data writing module is connected to the first pole of the driving module, and the control terminal of the data writing module is connected to a third scan signal; the first pole of the first light-emitting control module is connected to a first power signal, the second pole of the first light-emitting control module is connected to the first pole of the driving module, the second pole of the driving module is connected to the first pole of the second light-emitting control module, the second pole of the second light-emitting control module is connected to the first pole of the light-emitting device, and the control terminals of the first and second light-emitting control modules are connected to light-emitting control signals; the second pole of the second initialization module is connected to a second initialization voltage; the control terminals of the second and third initialization modules are connected to a fourth scan signal, the first pole of the third initialization module is connected to the first pole of the light-emitting device, and the second pole of the third initialization module is connected to a third initialization voltage; the first terminal of the storage module is connected to the control terminal of the driving module, and the second terminal of the storage module is connected to a first power signal; The first pole of the second initialization module is connected to the second pole of the driving module or to the first pole of the driving module.

9. The display panel according to claim 7, characterized in that, The pixel circuit includes a compensation module; the compensation module is connected between the control terminal and the second pole of the driving module. The display panel further includes: a second scanning circuit and multiple partition enable signal lines, wherein the second scanning circuit is connected to the partition enable signal lines; the second scanning circuit is connected to the control terminal of the compensation module through the second scanning lines; the second scanning circuit is used to transmit a second scanning signal to the compensation module; The second scanning circuit includes multiple cascaded shift register groups, each shift register group comprising k cascaded shift register units, where k is an integer greater than or equal to 2; each shift register unit comprising m shift registers, where m is an integer greater than or equal to 1; different shift register units within the same shift register group are connected to different partition enable signal lines, and different shift register groups are connected to the same k partition enable signal lines; the output of each shift register is connected to the control terminal of the compensation module of n rows of pixel circuits, where n is an integer greater than or equal to 1. The number of rows of the pixel circuit in the first region is greater than or equal to k*m*n rows.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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