Display panel and method for manufacturing a display panel

Abstract

The application relates to a display panel and a preparation method thereof. The display panel comprises a substrate and a plurality of pixels, and a plurality of sub-pixels are arranged at intervals on one side of the substrate. A plurality of pixel circuits corresponding to the plurality of sub-pixels are arranged on the substrate; the sub-pixels are electrically connected to the corresponding pixel circuits; a plurality of via connection structures corresponding to the plurality of pixel circuits are arranged on the substrate, the via connection structures are electrically connected to the corresponding pixel circuits; a plurality of vias corresponding to the plurality of via connection structures are further arranged on the substrate; the same type of via connection structures corresponding to at least two adjacent sub-pixels are arranged at intervals and located in the same via. The at least two adjacent sub-pixels are defined as a sub-pixel group, and at least two adjacent sub-pixels in the sub-pixel group are symmetrically arranged with a reference plane as a reference object, and the reference plane is parallel to the thickness direction of the substrate. The number of sub-pixels arranged in a unit area on the substrate can be increased, and the resolution of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a display panel and a method for manufacturing the display panel. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels are one of the hottest topics in the field of display panel research today. OLED display panels have advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle and fast response speed.

[0003] In related technologies, if the resolution is low, the display effect of the display panel will also be affected. Therefore, improving the resolution is one of the future development trends of OLED display panels. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and a method for manufacturing the display panel to address the above technical problems, thereby improving the resolution of the display panel.

[0005] According to a first aspect of this application, a display panel is provided, comprising:

[0006] Substrate; and

[0007] Multiple sub-pixels are spaced apart on one side of the substrate;

[0008] The substrate is provided with a plurality of pixel circuits corresponding to the plurality of sub-pixels; the sub-pixels are electrically connected to the corresponding pixel circuits.

[0009] The substrate is provided with a plurality of via connection structures corresponding to the plurality of pixel circuits, and the via connection structures are electrically connected to the corresponding pixel circuits; the plurality of via connection structures include at least two types of via connection structures.

[0010] The substrate is also provided with a plurality of vias corresponding to the plurality of via connection structures;

[0011] At least two adjacent sub-pixels are provided with the same type of via connection structure spaced apart from each other and located in the same via; the at least two adjacent sub-pixels are defined as a sub-pixel group, and at least one pair of adjacent sub-pixels in the sub-pixel group are arranged symmetrically with reference plane as the reference object, and the reference plane is parallel to the thickness direction of the substrate.

[0012] In one embodiment, the sub-pixel group, the via connection structure corresponding to the sub-pixel group, and the via corresponding to the sub-pixel group are arranged symmetrically with the same reference plane as the reference object;

[0013] Optionally, a plurality of the sub-pixels are arranged in a row along a first direction and in a column along a second direction, wherein the first direction and the second direction intersect each other and are both perpendicular to the thickness direction of the substrate;

[0014] Optionally, the via connection structures of the same type corresponding to two adjacent sub-pixels along the first direction are spaced apart from each other and located in the same via; the reference plane is perpendicular to the first direction; or

[0015] Two adjacent sub-pixels along the second direction have the same type of via connection structure spaced apart from each other and located in the same via; the reference plane is perpendicular to the second direction; or

[0016] The sub-pixel group includes four sub-pixels, and each sub-pixel group includes two sub-pixel subgroups that are adjacent and spaced apart along the first direction. Each sub-pixel subgroup includes two sub-pixels that are adjacent and spaced apart along the second direction. The reference plane includes a first reference plane perpendicular to the first direction and a second reference plane perpendicular to the second direction.

[0017] The sub-pixel groups are arranged symmetrically with reference to the first reference plane and the second reference plane, respectively.

[0018] The vias corresponding to the sub-pixel groups are arranged symmetrically with reference to the first reference plane and the second reference plane, respectively.

[0019] The multiple via connection structures corresponding to the sub-pixel group are arranged symmetrically with the first reference plane and the second reference plane as reference objects respectively;

[0020] Optionally, the via connection structures of the same type corresponding to two adjacent rows of sub-pixels are spaced apart from each other and located in the same via; the reference plane is perpendicular to the second direction;

[0021] Optionally, the via connection structures of the same type corresponding to two adjacent columns of sub-pixels are spaced apart from each other and located in the same via; the reference plane is perpendicular to the first direction.

[0022] In one embodiment, the substrate includes a substrate body and a planarization layer stacked together; the plurality of sub-pixels are spaced apart on the side of the planarization layer away from the substrate body; and the plurality of pixel circuits are disposed on the substrate body.

[0023] The plurality of via connection structures includes a plurality of first via connection structures disposed on the planarization layer, and the plurality of vias includes a plurality of first vias disposed on the planarization layer and corresponding to the plurality of first via connection structures;

[0024] The first via connection structures corresponding to at least two adjacent sub-pixels are spaced apart from each other and located in the same first via;

[0025] The sub-pixel includes a first electrode, a light-emitting layer, and a second electrode stacked together;

[0026] One end of the first via connection structure is electrically connected to the first electrode of the corresponding sub-pixel, and the other end of the first via connection structure is electrically connected to the corresponding pixel circuit.

[0027] In one embodiment, the pixel circuit includes a first power signal line, a second power signal line, and a first transistor;

[0028] The first transistor includes a control terminal, a first terminal, and a second terminal;

[0029] The first power signal line is used to input a first power signal to the first terminal of the first transistor, and the first electrode is electrically connected to the second terminal of the first transistor of the corresponding pixel circuit through a corresponding first via connection structure.

[0030] The second electrode of the sub-pixel is electrically connected to the second power signal line of the corresponding pixel circuit.

[0031] In one embodiment, the pixel circuit further includes a data signal line and a second transistor, the second transistor including a control terminal, a first terminal and a second terminal;

[0032] The control terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the second terminal of the second transistor is electrically connected to the data signal line. The control terminal of the second transistor is used to receive the scan signal.

[0033] The plurality of via connection structures includes a plurality of second via connection structures disposed on the substrate body, wherein the first via connection structure and the second via connection structure are different types of via connection structures; the plurality of vias includes a plurality of second vias corresponding to the plurality of second via connection structures and disposed on the substrate body;

[0034] One end of the second via connection structure is electrically connected to the data signal line of the corresponding pixel circuit, and the other end of the second via connection structure is electrically connected to the second terminal of the second transistor of the corresponding pixel circuit.

[0035] The second via connection structures corresponding to at least two adjacent sub-pixels are spaced apart from each other and located in the same second via;

[0036] Optionally, the pixel circuit further includes a storage module, which includes a first terminal and a second terminal; the first terminal of the storage module is electrically connected to a first power signal line; and the second terminal of the storage module is electrically connected to the first terminal of the second transistor.

[0037] Optionally, the substrate body includes a substrate and an insulating layer stacked together; the planarization layer is disposed on the side of the insulating layer away from the substrate;

[0038] The plurality of second vias and the plurality of second via connection structures are all disposed on the insulating layer.

[0039] In one embodiment, the display panel further includes a pixel definition layer;

[0040] A portion of the pixel definition layer is disposed on the side of the planarization layer away from the substrate body, and another portion of the pixel definition layer is disposed within the plurality of first vias to separate all the first via connection structures in the same first via.

[0041] The pixel definition layer is provided with a plurality of pixel openings corresponding to the plurality of sub-pixels, and at least a portion of the sub-pixels are disposed within the corresponding pixel openings;

[0042] Optionally, the pixel opening is configured to correspond one-to-one with the sub-pixel.

[0043] In one embodiment, the plurality of sub-pixels are arranged to form a plurality of repeating units, each of the repeating units including a first sub-pixel, a second sub-pixel and a third sub-pixel;

[0044] The first sub-pixel, the second sub-pixel, and the third sub-pixel each emit different colors.

[0045] Optionally, the same type of via connection structure corresponding to two of the first sub-pixel, the second sub-pixel, and the third sub-pixel of the same repeating unit is located in the same via;

[0046] Optionally, at least two adjacent sub-pixels in two adjacent repeating units correspond to the same type of via connection structure located in the same via;

[0047] Optionally, at least two adjacent repeating units of the same type of via connection structure are located in the same via;

[0048] Optionally, the plurality of repeating units are arranged in rows and columns; the via connection structures of the same type corresponding to two adjacent rows of repeating units are located in the same via; and / or

[0049] The via connection structures of the same type corresponding to two adjacent columns of repeating units are located in the same via.

[0050] In one embodiment, the light emission color of one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is red, the light emission color of another of the first sub-pixel, the second sub-pixel, and the third sub-pixel is green, and the light emission color of yet another of the first sub-pixel, the second sub-pixel, and the third sub-pixel is blue;

[0051] Optionally, the first sub-pixel is rectangular in shape, the second sub-pixel is rectangular in shape, and the third sub-pixel is rectangular in shape;

[0052] Optionally, the repeating unit is rectangular in shape;

[0053] Optionally, the repeating unit is square in shape;

[0054] Optionally, the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged alternately along the target direction; the target direction is parallel to one of the first direction and the second direction, the first direction and the second direction intersect each other, and both are perpendicular to the thickness direction of the substrate;

[0055] Optionally, the plurality of said sub-pixels are arranged in a row along the first direction and in a column along the second direction;

[0056] Optionally, the sub-pixel has a first pixel edge and a second pixel edge disposed opposite to each other along a first direction, the pixel circuit has a first boundary located on the same side as the first pixel edge along the first direction, and a second boundary disposed opposite to the first boundary along the first direction, the distance between the orthographic projection of the first pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding first boundary on the bottom surface of the substrate is less than or equal to a first preset distance.

[0057] The distance between the orthographic projection of the second pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding second boundary on the bottom surface of the substrate is less than or equal to a second preset distance; the first direction is perpendicular to the thickness direction of the substrate;

[0058] Optionally, the sub-pixel has a third pixel edge and a fourth pixel edge disposed opposite to each other along the second direction, the pixel circuit has a third boundary located on the same side as the third pixel edge along the second direction, and a fourth boundary disposed opposite to the third boundary along the second direction, the distance between the orthographic projection of the third pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding third boundary on the bottom surface of the substrate is less than or equal to a third preset distance.

[0059] The distance between the orthographic projection of the fourth pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding fourth boundary on the bottom surface of the substrate is less than or equal to a fourth preset distance.

[0060] The first direction and the second direction intersect each other and are both perpendicular to the thickness direction of the substrate.

[0061] According to a second aspect of this application, a method for manufacturing a display panel is provided, comprising:

[0062] Provide substrate; and

[0063] Multiple sub-pixels are formed on the substrate at intervals;

[0064] The substrate is provided with a plurality of pixel circuits corresponding to the plurality of sub-pixels; the sub-pixels are electrically connected to the corresponding pixel circuits.

[0065] The substrate is provided with a plurality of via connection structures corresponding to the plurality of pixel circuits, and the via connection structures are electrically connected to the corresponding pixel circuits; the plurality of via connection structures include at least two types of via connection structures.

[0066] The substrate is provided with a plurality of vias corresponding to the plurality of via connection structures;

[0067] At least two adjacent sub-pixels are provided with the same type of via connection structure spaced apart from each other and located in the same via; the at least two adjacent sub-pixels are defined as a sub-pixel group, and at least one pair of adjacent sub-pixels in the sub-pixel group are arranged symmetrically with reference plane as the reference object, and the reference plane is parallel to the thickness direction of the substrate.

[0068] In one embodiment, the plurality of via connection structures includes a plurality of first via connection structures, and the plurality of vias includes a plurality of first vias corresponding to the plurality of first via connection structures;

[0069] The provision of the substrate specifically includes: a substrate body and a planarization layer stacked together; wherein the planarization layer is provided with the plurality of first vias;

[0070] The sub-pixel includes a first electrode, a light-emitting layer, and a second electrode stacked together; the formation of multiple sub-pixels spaced apart on the substrate specifically includes:

[0071] A first electrode layer is formed on the substrate, partially disposed within the plurality of first vias;

[0072] The first electrode layer is etched to form a plurality of first electrodes and a plurality of first via connection structures correspondingly disposed in the plurality of first vias; wherein, the first via connection structures corresponding to at least two adjacent sub-pixels are spaced apart from each other and located in the same first via;

[0073] A pixel definition layer is formed on the side of the planarization layer away from the substrate body. The pixel definition layer is partially disposed in the plurality of first vias to separate at least two first via connection structures in at least one first via.

[0074] Optionally, the plurality of sub-pixels spaced apart on the substrate further includes:

[0075] Multiple pixel openings corresponding to the multiple sub-pixels are formed on the pixel definition layer;

[0076] Multiple light-emitting layers and a second electrode layer including all the second electrodes are formed on the pixel definition layer;

[0077] The light-emitting layer is disposed within the corresponding pixel opening and covers the corresponding first electrode; the second electrode layer is disposed on the side of the pixel definition layer away from the planarization layer and covers all the light-emitting layers.

[0078] In the technical solution of this application, compared to the situation where at least two adjacent sub-pixels in a sub-pixel group each use independent vias for the same type of via connection structure (the opening of independent vias requires a certain amount of space below the sub-pixel, which means that the opening of the independent via requires the spacing between adjacent sub-pixels to be greater than or equal to a first spacing), in this application, at least two adjacent sub-pixels in a sub-pixel group share the same via for the same type of via connection structure. In this way, the layout of the at least two adjacent sub-pixels can be more compact (that is, the spacing between two adjacent sub-pixels in the at least two adjacent sub-pixels is less than the first spacing), and the size of the via can be larger than the size of the independent via. This can improve the via opening yield and increase the number of sub-pixels arranged per unit area on the substrate, thereby improving the resolution of the display panel. Attached Figure Description

[0079] Figure 1 A cross-sectional schematic diagram of a display panel according to an embodiment of this application is shown.

[0080] Figure 2 It shows Figure 1 A partial structural diagram.

[0081] Figure 3 A schematic diagram of the arrangement of multiple sub-pixels in one embodiment of this application is shown.

[0082] Figure 4 A schematic diagram of the sub-pixel group, via connection structure, and via arrangement according to an embodiment of this application is shown.

[0083] Figure 5 A schematic diagram of the sub-pixel group, via connection structure, and via arrangement according to another embodiment of this application is shown.

[0084] Figure 6 This illustration shows a schematic diagram of the sub-pixel group, via connection structure, and via arrangement according to another embodiment of this application.

[0085] Figure 7 This illustration shows a schematic diagram of the sub-pixel group, via connection structure, and via arrangement according to another embodiment of this application.

[0086] Figure 8 A cross-sectional schematic diagram of a display panel according to another embodiment of this application is shown.

[0087] Figure 9 A circuit diagram of a pixel circuit according to an embodiment of this application is shown.

[0088] Reference numerals: 10, display panel; 100, substrate; 110, substrate body; 111, substrate; 112, insulating layer; 1121, insulator layer; 120, planarization layer; 200, sub-pixel; 210, first electrode; 220, light-emitting layer; 230, second electrode; 2001, first sub-pixel; 2002, second sub-pixel; 2003, third sub-pixel; 201, first pixel edge; 202, second pixel edge; 300, pixel circuit; 310, first power signal line; 320, second power signal line; 330, data signal line; M1, first transistor; M11, first source; M12, first drain; M13, First gate; M2, Second transistor; M21, Second source; M22, Second drain; M23, Second gate; C, Memory module; 301, First boundary; 302, Second boundary; 400, Via connection structure; 410, First via connection structure; 420, Second via connection structure; 430, Third via connection structure; 440, Fourth via connection structure; 500, Pixel definition layer; 501, Pixel aperture; 610, First encapsulation layer; 620, Second encapsulation layer; K, Via; K1, First via; K2, Second via; P, Reference plane; P1, First reference plane; P2, Second reference plane. Detailed Implementation

[0089] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0090] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0091] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0092] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0093] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0094] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0095] Figure 1 A cross-sectional schematic diagram of a display panel 10 according to an embodiment of this application is shown. Figure 2 It shows Figure 1 A partial structural diagram.

[0096] Please refer to the following: Figure 1 and Figure 2 One embodiment of this application provides a display panel 10, including a substrate 100 and a plurality of sub-pixels 200, the plurality of sub-pixels 200 being spaced apart on one side of the substrate 100. The substrate 100 is provided with a plurality of pixel circuits 300 corresponding to the plurality of sub-pixels 200. Each sub-pixel 200 is electrically connected to its corresponding pixel circuit 300.

[0097] The corresponding sub-pixel 200 can be driven to emit light through the pixel circuit 300, so that different patterns can be displayed using the display panel 10.

[0098] The substrate 100 is provided with a plurality of via connection structures 400 corresponding to a plurality of pixel circuits 300, and the via connection structures 400 are electrically connected to the corresponding pixel circuits 300. The plurality of via connection structures 400 includes at least two types of via connection structures 400.

[0099] In the process of electrically connecting the pixel circuit 300 with the corresponding sub-pixel 200, multiple types of via connection structures 400 are usually involved. One end of the via connection structure 400 of the same type is connected to a component of the first attribute, and the other end of the via connection structure 400 of the same type is connected to a component of the second attribute, so that the via connection structure 400 of the same type is electrically connected between the component of the first attribute and the component of the second attribute. For example, the sub-pixel 200 includes a first electrode 210, a light-emitting layer 220 and a second electrode 230 stacked together. The component of the first attribute is the first electrode, and the component of the second attribute is the pixel circuit 300 (specifically, the component of the second attribute is the second end of the first transistor M1 of the pixel circuit 300).

[0100] The substrate 100 is also provided with a plurality of vias K corresponding to a plurality of via connection structures 400. The via connection structures 400 of the same type corresponding to at least two adjacent sub-pixels 200 are arranged at intervals and located in the same via K. The at least two adjacent sub-pixels are defined as a sub-pixel group. At least one pair of adjacent sub-pixels 200 in the sub-pixel group are arranged symmetrically with reference plane P as the reference object. The reference plane P is parallel to the thickness direction of the substrate 100.

[0101] On the one hand, compared to the situation where at least two adjacent sub-pixels 200 in a sub-pixel group each use independent vias for the same type of via connection structure (the opening of independent vias requires a certain amount of space below the sub-pixel, which means that the opening of the independent via requires the spacing between adjacent sub-pixels to be greater than or equal to the first spacing), in this application, at least two adjacent sub-pixels 200 in a sub-pixel group share the same via K for the same type of via connection structure 400. In this way, the layout of the at least two adjacent sub-pixels 200 can be more compact (that is, the spacing between the two adjacent sub-pixels 200 is less than the first spacing), and the size of the via K can be larger than the size of the independent via. This can improve the opening yield of the via K and increase the number of sub-pixels 200 arranged per unit area on the substrate 100, thereby improving the resolution of the display panel 10.

[0102] On the other hand, at least one pair of adjacent sub-pixels 200 in the sub-pixel group are arranged symmetrically with reference plane P as the reference object. In this way, the two adjacent sub-pixels 200 can be arranged in a mirror image, which is conducive to improving the arrangement convenience of the pixel circuits 300 corresponding to the two adjacent sub-pixels 200. Furthermore, while the sub-pixels 200 are electrically connected to the corresponding pixel circuits 300, it is also conducive to reducing the overall size of the display panel 10.

[0103] In some embodiments, the sub-pixel groups, the via connection structures 400 corresponding to the sub-pixel groups, and the vias K corresponding to the sub-pixel groups are arranged symmetrically with the same reference plane P as the reference object.

[0104] Specifically, the number of sub-pixels 200 in the sub-pixel group is even, which makes it easier for the via connection structures 400 corresponding to at least two adjacent sub-pixels 200 in the sub-pixel group to be symmetrically arranged with reference plane P as the reference object, and also makes it easier for the vias K corresponding to the sub-pixel group to be symmetrically arranged with reference plane P as the reference object.

[0105] The via connection structure 400 includes a first via connection structure 410. Taking the first via connection structure 410 as an example, the via connection structures 400 corresponding to at least two adjacent sub-pixels 200 in the sub-pixel group are symmetrically arranged with reference plane P as the reference object. In this way, it is convenient to make reasonable use of the first region on the substrate 100 located below at least two adjacent sub-pixels 200 (a part of the first region is located below one of the at least two adjacent sub-pixels 200, and another part of the first region is located below the other sub-pixel 200 of the at least two adjacent sub-pixels 200). Another portion is located in the area below the at least one adjacent two sub-pixels 200, so that a corresponding via K can be formed by concentrated punching in the first area. At least two via connection structures 400 can be reasonably distributed in the same via K, which is more conducive to the at least two via connection structures 400 in the same via K being arranged at intervals. In addition, the at least two via connection structures 400 in the same via K are arranged symmetrically, and the via K corresponding to the sub-pixel group is arranged symmetrically with reference plane P as the reference object. This can also improve the flatness of at least two sub-pixels 200 in the sub-pixel group, thereby improving the display effect of the display panel 10.

[0106] In some embodiments, such as Figure 3 As shown, multiple sub-pixels 200 are arranged in rows along the first direction F1 and in columns along the second direction F2. The first direction F1 and the second direction F2 intersect each other and are both perpendicular to the thickness direction of the substrate 100.

[0107] The regular arrangement of multiple sub-pixels 200 is beneficial for making reasonable use of the area occupied on the substrate 100, thereby allowing more sub-pixels 200 to be arranged in a unit area on the substrate 100, which in turn helps to improve the resolution of the display panel 10.

[0108] In some embodiments, such as Figure 1 and Figure 4As shown, the same type of via connection structure 400 corresponding to two adjacent sub-pixels 200 along the first direction F1 are spaced apart from each other and located in the same via K. The reference plane P is perpendicular to the first direction F1.

[0109] It is understood that two adjacent sub-pixels 200 along the first direction F1 are symmetrically arranged with a reference plane P perpendicular to the first direction F1. The via connection structure 400 of the same type corresponding to the two sub-pixels 200 is also symmetrically arranged with the reference plane P, and the corresponding via K is also symmetrically arranged with the reference plane P. In this way, the area on the substrate 100 located below at least one of the two adjacent sub-pixels 200 can be reasonably utilized to open the via K shared by the two sub-pixels 200 in this area. This is beneficial to reduce the spacing between the two sub-pixels 200 along the first direction F1 while meeting the design requirements of the via K, thereby improving the resolution of the display panel 10.

[0110] In other embodiments, such as Figure 5 As shown, the via connection structures 400 of the same type corresponding to two adjacent sub-pixels 200 along the second direction F2 are spaced apart from each other and located in the same via K. The reference plane P is perpendicular to the second direction F2.

[0111] Similarly, while meeting the design requirements of the via K, the spacing between the two sub-pixels 200 along the second direction F2 can be reduced, which is beneficial to improving the resolution of the display panel 10.

[0112] In some other embodiments, such as Figure 6 As shown, a sub-pixel group includes four sub-pixels 200. Each sub-pixel group includes two adjacent and spaced-apart sub-groups arranged along a first direction F1. Each sub-pixel sub-group includes two adjacent and spaced-apart sub-pixels 200 arranged along a second direction F2. The reference plane P includes a first reference plane P1 perpendicular to the first direction F1 and a second reference plane P2 perpendicular to the second direction F2. The sub-pixel groups are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. The vias K corresponding to the sub-pixel groups are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. The multiple via connection structures 400 corresponding to the sub-pixel groups are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively.

[0113] The sub-pixel groups are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. Similarly, the vias K corresponding to the sub-pixel groups are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. Furthermore, the multiple via connection structures 400 corresponding to the sub-pixel groups are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. Therefore, it is convenient to distribute the four sub-pixels 200 of the sub-pixel groups reasonably and compactly. Specifically, it can reduce the spacing between two adjacent sub-pixels 200 along the first direction F1, and also reduce the spacing between two adjacent sub-pixels 200 along the second direction F2, thereby improving the resolution of the display panel 10. It also facilitates improving the flatness of the four sub-pixels 200 in the sub-pixel groups, thus contributing to improving the display effect of the display panel 10.

[0114] In some other embodiments, such as Figure 7 As shown, the via connection structures 400 of the same type corresponding to two adjacent rows of sub-pixels 200 are spaced apart from each other and located in the same via K. The reference plane P is perpendicular to the second direction F2.

[0115] It is understood that two adjacent rows of sub-pixels 200 are symmetrically arranged with reference to the reference plane P perpendicular to the second direction F2. This facilitates the sharing of the same via connection structure 400 of the same type corresponding to the two adjacent rows of sub-pixels 200, and also allows the via K to be symmetrically arranged with reference to the reference plane P perpendicular to the second direction F2. Furthermore, it allows the same type of via connection structure 400 of the same type corresponding to the two adjacent rows of sub-pixels 200 to be symmetrically arranged with reference to the reference plane P perpendicular to the second direction F2. In this way, the spacing between the two adjacent rows of sub-pixels 200 along the second direction F2 can be reduced, thereby improving the resolution of the display panel 10. It also facilitates the improvement of the flatness of the two adjacent rows of sub-pixels 200, which in turn helps to improve the display effect of the display panel 10.

[0116] In other embodiments, the same type of via connection structure 400 corresponding to two adjacent columns of sub-pixels 200 are spaced apart from each other and located in the same via K. The reference plane P is perpendicular to the first direction F1.

[0117] It is understood that two adjacent columns of sub-pixels 200 are symmetrically arranged with reference to the reference plane P perpendicular to the first direction F1. This facilitates the sharing of the same via connection structure 400 of the same type between the two adjacent columns of sub-pixels 200, and also allows the via K to be symmetrically arranged with reference to the reference plane P perpendicular to the first direction F1. Furthermore, it allows the same type of via connection structure 400 of the same type between the two adjacent columns of sub-pixels 200 to be symmetrically arranged with reference to the reference plane P perpendicular to the first direction F1. In this way, the spacing between the two adjacent columns of sub-pixels 200 along the first direction F1 can be reduced, thereby improving the resolution of the display panel 10. It also facilitates the improvement of the flatness of the two adjacent columns of sub-pixels 200, which in turn helps to improve the display effect of the display panel 10.

[0118] In some embodiments, the substrate 100 includes a substrate body 110 and a planarization layer 120 stacked together, and a plurality of sub-pixels 200 are spaced apart on the side of the planarization layer 120 away from the substrate body 110. A plurality of pixel circuits 300 are disposed on the substrate body 110. A plurality of via connection structures 400 include a plurality of first via connection structures 410 disposed on the planarization layer 120, and a plurality of vias K include a plurality of first vias K1 disposed on the planarization layer 120 and corresponding to the plurality of first via connection structures 410. The first via connection structures 410 corresponding to at least two adjacent sub-pixels 200 are spaced apart from each other and located in the same first via K1. The sub-pixel 200 includes a first electrode 210, a light-emitting layer 220 and a second electrode 230 stacked together. One end of the first via connection structure 410 is electrically connected to the first electrode 210 of the sub-pixel 200, and the other end of the first via connection structure 410 is electrically connected to the corresponding pixel circuit 300.

[0119] It can be understood that the first via connection structure 410 is one type of via connection structure 400 among multiple via connection structures 400.

[0120] For example, the first electrode 210 is the anode, and the first via K1 is the anode via.

[0121] Thus, the first via connection structures 410 corresponding to at least two adjacent sub-pixels 200 share the same first via K1, and the at least two first via connection structures 410 within the same first via K1 are spaced apart from each other. This facilitates the independent driving of the corresponding sub-pixels 200 by the corresponding pixel circuit 300, while also reducing the spacing between two adjacent sub-pixels 200, thereby improving the resolution of the display panel 10.

[0122] Optionally, the first via connection structure 410 corresponding to at least two adjacent sub-pixels 200 is symmetrically arranged with reference plane P as the reference object. The first via K1 corresponding to at least two adjacent sub-pixels 200 is symmetrically arranged with reference plane P as the reference object.

[0123] Optionally, the first via connection structures 410 corresponding to two adjacent sub-pixels 200 along the first direction F1 are spaced apart from each other and located in the same first via K1. The reference plane P is perpendicular to the first direction F1.

[0124] Optionally, the first via connection structures 410 corresponding to two adjacent sub-pixels 200 along the second direction F2 are spaced apart from each other and located in the same first via K1. The reference plane P is perpendicular to the second direction F2.

[0125] Optionally, a sub-pixel group includes four sub-pixels 200. Each sub-pixel group includes two adjacent and spaced-apart sub-groups arranged along a first direction F1, and each sub-pixel sub-group includes two adjacent and spaced-apart sub-pixels 200 arranged along a second direction F2. The reference plane P includes a first reference plane P1 perpendicular to the first direction F1 and a second reference plane P2 perpendicular to the second direction F2. The plurality of first via connection structures 410 corresponding to the sub-pixel group are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. The first vias K1 corresponding to the sub-pixel group are also symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively.

[0126] Optionally, two adjacent rows of sub-pixels 200 are symmetrically arranged with reference to a reference plane P perpendicular to the second direction F2. The first via connection structure 410 corresponding to the two adjacent rows of sub-pixels 200 is symmetrically arranged with reference to the reference plane P. The first via K1 corresponding to the two adjacent rows of sub-pixels 200 is symmetrically arranged with reference to the reference plane P.

[0127] Optionally, two adjacent columns of sub-pixels 200 are symmetrically arranged with reference to a reference plane P perpendicular to the first direction F1. The first via connection structure 410 corresponding to the two adjacent columns of sub-pixels 200 is symmetrically arranged with reference to the reference plane P. The first via K1 corresponding to the two adjacent columns of sub-pixels 200 is symmetrically arranged with reference to the reference plane P.

[0128] In some embodiments, the pixel circuit 300 includes a first power signal line 310, a second power signal line 320, and a first transistor M1. The first transistor M1 includes a control terminal, a first terminal, and a second terminal. The first power signal line 310 is used to input a first power signal to the first terminal of the first transistor M1. The first electrode 210 is electrically connected to the second terminal of the first transistor M1 of the corresponding pixel circuit 300 through a corresponding first via connection structure 410. The second electrode 230 of the sub-pixel 200 is electrically connected to the second power signal line 320 of the corresponding pixel circuit 300.

[0129] Specifically, the first transistor M1 includes a first source M11, a first drain M12, and a first gate M13. The first terminal of the first transistor M1 is disposed on one of the first source M11 and the first drain M12, the second terminal of the first transistor M1 is disposed on the other of the first source M11 and the first drain M12, and the control terminal of the first transistor M1 is disposed on the first gate M13.

[0130] In this way, a corresponding scan signal can be input to the control terminal of the first transistor M1, thereby turning on the first transistor M1. A first power signal (VDD) can be input to the corresponding sub-pixel 200 through the first power signal line 310 and the first transistor M1. A second power signal (VSS) can also be input to the corresponding sub-pixel 200 through the second power signal line 320, thereby driving the corresponding sub-pixel 200 to emit light.

[0131] In some embodiments, the pixel circuit 300 further includes a data signal line 330 and a second transistor M2. The second transistor M2 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor M1 is electrically connected to the first terminal of the second transistor M2, and the second terminal of the second transistor M2 is electrically connected to the data signal line 330. The control terminal of the second transistor M2 is used to receive a scan signal. The plurality of via connection structures 400 includes a plurality of second via connection structures 420 disposed on the substrate body 110. The first via connection structure 410 and the second via connection structure 420 are different types of via connection structures 400. The plurality of vias K includes a plurality of second vias K2 corresponding to the plurality of second via connection structures 420 and disposed on the substrate body 110. One end of the second via connection structure 420 is electrically connected to the data signal line 330 of the corresponding pixel circuit 300, and the other end of the second via connection structure 420 is electrically connected to the second terminal of the second transistor M2 of the corresponding pixel circuit 300. The second via connection structures 420 corresponding to at least two adjacent sub-pixels 200 are spaced apart from each other and located in the same second via K2 (e.g., Figure 8 (As shown).

[0132] Specifically, the second transistor M2 includes a second source M21, a second drain M22, and a second gate M23. The first terminal of the second transistor M2 is disposed on one of the second source M21 and the second drain M22, the second terminal of the second transistor M2 is disposed on the other of the second source M21 and the second drain M22, and the control terminal of the second transistor M2 is disposed on the second gate M23.

[0133] Specifically, a portion of the planarization layer 120 is located within a plurality of second vias K2 to space apart at least two second via connection structures 420 in the same second via K2.

[0134] In some embodiments, the pixel circuit 300 can be a 2T1C circuit, a 3T1C circuit, a 5T1C circuit, or a 7T1C circuit. The following description assumes the pixel circuit 300 is a 2T1C circuit (e.g., ...). Figure 9 The following example will be used to illustrate this.

[0135] The pixel circuit 300 also includes a storage module C, which has a first end and a second end. The first end of the storage module C is electrically connected to the first power signal line 310, and the second end of the storage module C is electrically connected to the first end of the second transistor M2.

[0136] Optionally, the storage module C is a capacitor.

[0137] Optionally, the first power signal line 310 is a VDD signal line, and the second power signal line 320 is a VSS signal line.

[0138] The light emission process of subpixel 200 is as follows:

[0139] Data storage stage: A scan signal Scan can be connected to the control terminal of the second transistor M2 to turn on the second transistor M2, so that the data signal Data transmitted by the data signal line 330 can be stored in the storage module C for subsequent writing to the control terminal of the first transistor M1.

[0140] Light-emitting stage: The data signal Data stored in the storage module C is written to the control terminal of the first transistor M1. The first terminal of the first transistor M1 is connected to the first power signal VDD, and the second power signal VSS is connected to the second electrode 230 of the sub-pixel 200. In this way, the first transistor M1 and the second transistor M2 can be turned on, thereby enabling the sub-pixel 200 to emit light. Since the first transistor M1 is controlled by the voltage of the storage module C, and the voltage of the storage module C comes from the data signal Data stored in the storage module C, the brightness of the sub-pixel 200 can be well controlled by the storage module C and the second transistor M2.

[0141] Furthermore, since the second via connection structures 420 corresponding to at least two adjacent sub-pixels 200 are spaced apart from each other and located in the same second via K2, the second via connection structures 420 corresponding to at least two adjacent sub-pixels 200 share the same second via K2, and the at least two second via connection structures 420 in the same second via K2 are spaced apart from each other. This facilitates the independent driving of the corresponding sub-pixel 200 by the corresponding pixel circuit 300, while also reducing the spacing between two adjacent sub-pixels 200, thereby improving the resolution of the display panel 10.

[0142] Optionally, the first via K1 and the second via K2 are staggered. Specifically, the orthographic projection of the first via K1 on the bottom surface of the substrate 100 and the orthographic projection of the second via K2 on the bottom surface of the substrate 100 do not overlap.

[0143] It can be that the first via K1 and the second via K2 are staggered along the first direction F1; it can also be that the first via K1 and the second via K2 are staggered along the second direction F2; or it can be that the first via K1 and the second via K2 are staggered along the first direction F1 and staggered along the second direction F2.

[0144] Optionally, the second via connection structure 420 corresponding to at least two adjacent sub-pixels 200 is symmetrically arranged with reference plane P as the reference object. The second via K2 corresponding to at least two adjacent sub-pixels 200 is symmetrically arranged with reference plane P as the reference object.

[0145] Optionally, the second via connection structures 420 corresponding to two adjacent sub-pixels 200 along the first direction F1 are spaced apart from each other and located in the same second via K2. The reference plane P is perpendicular to the first direction F1.

[0146] Optionally, the second via connection structures 420 corresponding to two adjacent sub-pixels 200 along the second direction F2 are spaced apart from each other and located in the same second via K2. The reference plane P is perpendicular to the second direction F2.

[0147] Optionally, a sub-pixel group includes four sub-pixels 200. Each sub-pixel group comprises two adjacent and spaced-apart sub-groups arranged along a first direction F1, and each sub-pixel sub-group comprises two adjacent and spaced-apart sub-pixels 200 arranged along a second direction F2. The reference plane P includes a first reference plane P1 perpendicular to the first direction F1 and a second reference plane P2 perpendicular to the second direction F2. The plurality of second via connection structures 420 corresponding to the sub-pixel group are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively. Similarly, the second vias K2 corresponding to the sub-pixel group are symmetrically arranged with reference to the first reference plane P1 and the second reference plane P2, respectively.

[0148] Optionally, two adjacent rows of sub-pixels 200 are symmetrically arranged with reference to a reference plane P perpendicular to the second direction F2. The second via connection structure 420 corresponding to the two adjacent rows of sub-pixels 200 is symmetrically arranged with reference to the reference plane P. The second via K2 corresponding to the two adjacent rows of sub-pixels 200 is symmetrically arranged with reference to the reference plane P.

[0149] Optionally, two adjacent columns of sub-pixels 200 are symmetrically arranged with reference to a reference plane P perpendicular to the first direction F1. The second via connection structure 420 corresponding to the two adjacent columns of sub-pixels 200 is symmetrically arranged with reference to the reference plane P. The second via K2 corresponding to the two adjacent columns of sub-pixels 200 is symmetrically arranged with reference to the reference plane P.

[0150] Optionally, the substrate body 110 includes a substrate 111 and an insulating layer 112 stacked together, a planarization layer 120 is disposed on the side of the insulating layer 112 away from the substrate 111, and a plurality of second vias K2 and a plurality of second via connection structures 420 are disposed on the insulating layer 112.

[0151] Specifically, the substrate 111 includes a flexible substrate and at least one buffer layer stacked together.

[0152] Specifically, the insulating layer 112 includes three stacked insulator layers 1121. Along the direction away from the substrate 111, the three insulator layers 1121 are an interlayer insulating layer (GI), an insulating dielectric layer (CI), and an interlayer insulating layer (ILD). The first transistor M1 includes a first transistor body, with a first source M11 and a first drain M12 disposed on the first transistor body. The second transistor M2 includes a second transistor body, with a second source M21 and a second drain M22 disposed on the second transistor body. The insulator layer 1121 closest to the substrate 111 covers the first transistor body and the second transistor body. The first gate M13 of the first transistor M1 and the second gate M23 of the second transistor M2 are spaced apart on the middle insulator layer 1121, and the insulator layer 1121 furthest from the substrate 111 covers the first gate M13 of the first transistor M1 and the second gate M23 of the second transistor M2. The metal layer containing the data signal line 330 and the first power signal line 310 is disposed on the side of the insulating layer 112 away from the substrate 111 (the data signal line 330 and the first power signal line 310 are spaced apart on the side of the insulating layer 112 away from the substrate 111), and the planarization layer 120 covers the metal layer. The second via K2 is disposed through the three insulating layers 1121 so that the second via connection structure 420 located in the second via K2 can be electrically connected to the second end of the data signal line 330 and the second transistor M2 (i.e., the second source M21 of the second transistor M2), and the first power signal line 310 can be electrically connected to the first source M11 of the first transistor M1 through the third via connection structure 430 disposed through the insulating layer 112. The first via connection structure 410 can also be electrically connected to the first drain M12 of the first transistor M1 through the adapter wire disposed in the same layer as the data signal line 330 and the fourth via connection structure 440 disposed through the insulating layer 112.

[0153] In some embodiments, the display panel 10 further includes a pixel definition layer 500, a portion of which is disposed on the side of the planarization layer 120 away from the substrate body 110, and another portion of which is disposed within a plurality of first vias K1 to space apart all the first via connection structures 410 in the same first via K1.

[0154] In this way, the pixel definition layer 500 can better separate all the first via connection structures 410 in the same first via K1, thereby improving the resolution of the display panel 10 and enabling independent control of the sub-pixels 200 through the corresponding pixel circuits 300.

[0155] In this embodiment, the pixel definition layer 500 is provided with a plurality of pixel openings 501 corresponding to a plurality of sub-pixels 200, and at least a portion of the sub-pixels 200 is disposed within the corresponding pixel openings 501.

[0156] Optionally, the pixel aperture 501 is set to correspond one-to-one with the sub-pixel 200.

[0157] In this way, the pixel material corresponding to the sub-pixel 200 of the corresponding color can be vapor-deposited in the corresponding pixel opening 501, which facilitates the spacing of multiple sub-pixels 200 and reduces the color mixing of adjacent sub-pixels 200, thereby improving the display effect of the display panel 10.

[0158] In some embodiments, such as Figure 3 As shown, multiple sub-pixels are arranged to form multiple repeating units. Each repeating unit includes a first sub-pixel 2001, a second sub-pixel 2002, and a third sub-pixel 2003. The emission colors of the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 are all different.

[0159] In this way, the display effect of the display panel 10 can be improved by using sub-pixels 200 with different luminous colors.

[0160] Optionally, the same type of via connection structure 400 corresponding to two of the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 of the same repeating unit is located in the same via K.

[0161] It is possible that the first via connection structure 410 corresponding to two of the first sub-pixel 2001, the second sub-pixel 2002 and the third sub-pixel 2003 of the same repeating unit is located in the same first via K1, and the two first via connection structures 410 and the first via K1 are symmetrically arranged with the same reference plane P as the reference object.

[0162] Alternatively, the second via connection structure 420 corresponding to two of the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 of the same repeating unit is located in the same second via K2, and the two second via connection structures 420 and the second via K2 are symmetrically arranged with the same reference plane P as the reference object.

[0163] Optionally, at least two adjacent sub-pixels 200 in two adjacent repeating units correspond to the same type of via connection structure 400 located in the same via K.

[0164] It is possible that the first via connection structure 410 corresponding to at least two adjacent sub-pixels 200 in two adjacent repeating units is located in the same second via K2, and the at least two adjacent sub-pixels 200, the first via connection structure 410 corresponding to the at least two adjacent sub-pixels 200 and the second via K2 are symmetrically arranged with the same reference plane P as the reference object.

[0165] Alternatively, the second via connection structure 420 corresponding to at least two adjacent sub-pixels 200 in two adjacent repeating units is located in the same second via K2, and the at least two adjacent sub-pixels 200, the second via connection structure 420 corresponding to the at least two adjacent sub-pixels 200, and the second via K2 are symmetrically arranged with the same reference plane P as the reference object.

[0166] Optionally, at least two adjacent repeating units corresponding to the same type of via connection structure 400 are located in the same via K.

[0167] Alternatively, the first via connection structure 410 corresponding to at least two adjacent repeating units may be located in the same first via K1. The at least two adjacent repeating units, the first via connection structure 410 corresponding to the at least two adjacent repeating units, and the first via K1 are symmetrically arranged with the same reference plane P as the reference object.

[0168] Alternatively, the second via connection structures 420 corresponding to at least two adjacent repeating units may be located in the same second via K2. The at least two adjacent repeating units, the second via connection structures 420 corresponding to the at least two adjacent repeating units, and the second via K2 are symmetrically arranged with the same reference plane P as the reference object.

[0169] Optionally, multiple repeating units are arranged in rows and columns, and the same type of via connection structure 400 corresponding to two adjacent rows of repeating units are located in the same via K.

[0170] Alternatively, the first via connection structure 410 corresponding to two adjacent rows of repeating units may be located in the same first via K1, and the two adjacent rows of repeating units, the first via connection structure 410 corresponding to the two adjacent rows of repeating units, and the first via K1 may be symmetrically arranged with the same reference plane P as the reference object.

[0171] Alternatively, the second via connection structure 420 corresponding to two adjacent rows of repeating units may be located in the same second via K2. The two adjacent rows of repeating units, the second via connection structure 420 corresponding to the two adjacent rows of repeating units, and the second via K2 may be symmetrically arranged with the same reference plane P as the reference object.

[0172] Optionally, multiple repeating units are arranged in rows and columns, and the same type of via connection structure 400 corresponding to two adjacent columns of repeating units are located in the same via K.

[0173] It is possible that the first via connection structure 410 corresponding to two adjacent columns of repeating units is located in the same first via K1, and the two adjacent columns of repeating units, the first via connection structure 410 corresponding to the two adjacent columns of repeating units, and the first via K1 are symmetrically arranged with the same reference plane P as the reference object.

[0174] Alternatively, the second via connection structure 420 corresponding to two adjacent repeating units may be located in the same second via K2, and the two adjacent repeating units, the second via connection structure 420 corresponding to the two adjacent repeating units, and the second via K2 may be symmetrically arranged with the same reference plane P as the reference object.

[0175] Optionally, one of the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 emits light in red, another of the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 emits light in green, and yet another of the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 emits light in blue.

[0176] In this way, color display of the display panel 10 can be achieved by using sub-pixels 200 with different luminous colors.

[0177] Optionally, the first sub-pixel 2001 is rectangular in shape, the second sub-pixel 2002 is rectangular in shape, and the third sub-pixel 2003 is rectangular in shape.

[0178] The first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 are all rectangular in shape, which is conducive to the regular arrangement of multiple repeating units and also conducive to the rational use of the occupied area on the substrate 100. This can increase the number of sub-pixels 200 in a unit area on the substrate 100, thereby improving the resolution of the display panel 10.

[0179] Optionally, the repeating unit can be rectangular in shape.

[0180] Specifically, the repeating unit is square in shape.

[0181] Specifically, the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 have the same shape and size in the orthographic projection pattern on the substrate 100.

[0182] This facilitates the regular arrangement of multiple repeating units and makes reasonable use of the area occupied on the substrate 100, thereby increasing the number of sub-pixels 200 per unit area on the substrate 100 and thus improving the resolution of the display panel 10.

[0183] Optionally, the first sub-pixel 2001, the second sub-pixel 2002, and the third sub-pixel 2003 are arranged alternately along the target direction; the target direction is parallel to one of the first direction F1 and the second direction F2, the first direction F1 and the second direction F2 intersect each other, and are both perpendicular to the thickness direction of the substrate 100. Specifically, the first direction F1 and the second direction F2 are perpendicular to the thickness direction of the substrate 100.

[0184] For example, the target direction is parallel to the first direction F1. The size of the light-emitting layer 220 of the first sub-pixel 2001 along the first direction F1 is smaller than the size of the light-emitting layer 220 of the first sub-pixel 2001 along the second direction F2; the size of the light-emitting layer 220 of the second sub-pixel 2002 along the first direction F1 is smaller than the size of the light-emitting layer 220 of the second sub-pixel 2002 along the second direction F2; and the size of the light-emitting layer 220 of the third sub-pixel 2003 along the first direction F1 is smaller than the size of the light-emitting layer 220 of the third sub-pixel 2003 along the second direction F2.

[0185] Optionally, the sub-pixel 200 has a first pixel edge 201 and a second pixel edge 202 disposed opposite to each other along the first direction F1. The pixel circuit 300 has a first boundary 301 located on the same side as the first pixel edge 201 along the first direction F1, and a second boundary 302 disposed opposite to the first boundary 301 along the first direction F1. The distance between the orthographic projection of the first pixel edge 201 on the bottom surface of the substrate 100 and the orthographic projection of the corresponding first boundary 301 on the bottom surface of the substrate 100 is less than or equal to a first preset distance. The distance between the orthographic projection of the second pixel edge 202 on the bottom surface of the substrate 100 and the orthographic projection of the corresponding second boundary 302 on the bottom surface of the substrate 100 is less than or equal to a second preset distance. The first direction F1 is perpendicular to the thickness direction of the substrate 100.

[0186] In this way, the distance between the first pixel edge 201 of the sub-pixel 200 and the corresponding first boundary 301 projected onto the bottom surface of the substrate 100 in the first direction F1 can be smaller. The distance between the second pixel edge 202 of the sub-pixel 200 and the corresponding second boundary 302 projected onto the bottom surface of the substrate 100 in the first direction F1 can also be smaller. As a result, the pixel circuit 300 can be located approximately directly below the corresponding sub-pixel 200. As a result, multiple pixel circuits 300 can be reasonably arranged on the substrate 100. This can improve the resolution of the display panel 10, while also enabling the pixel circuit 300 to independently drive the corresponding sub-pixel 200. It also helps to reduce the size of the display panel along the first direction F1.

[0187] In some embodiments, the sub-pixel 200 has a third pixel edge (not shown) and a fourth pixel edge (not shown) disposed opposite to each other along the second direction F2. The pixel circuit 300 has a third boundary (not shown) located on the same side as the third pixel edge along the second direction F2, and a fourth boundary (not shown) disposed opposite to the third boundary along the second direction. The distance between the orthographic projection of the third pixel edge on the bottom surface of the substrate 100 and the orthographic projection of the corresponding third boundary on the bottom surface of the substrate 100 is less than or equal to a third preset distance. The distance between the orthographic projection of the fourth pixel edge on the bottom surface of the substrate 100 and the orthographic projection of the corresponding fourth boundary on the bottom surface of the substrate 100 is less than or equal to a fourth preset distance. The first direction F1 and the second direction F2 intersect each other and are both perpendicular to the thickness direction of the substrate 100.

[0188] Optionally, the first direction F1 and the second direction F2 are perpendicular to the thickness direction of the substrate 100.

[0189] Similarly, the distance between the third pixel edge of sub-pixel 200 and the orthographic projection of the corresponding third boundary on the bottom surface of substrate 100 in the second direction F2 can be made smaller. The distance between the fourth pixel edge of sub-pixel 200 and the orthographic projection of the corresponding fourth boundary on the bottom surface of substrate 100 in the second direction F2 can also be made smaller. This allows the pixel circuit 300 to be located approximately directly below the corresponding sub-pixel 200. As a result, multiple pixel circuits 300 can be reasonably arranged on substrate 100. This can improve the resolution of display panel 10 while also enabling pixel circuits 300 to independently drive the corresponding sub-pixel 200. It also helps to reduce the size of display panel along the second direction F2.

[0190] An embodiment of this application also discloses a method for manufacturing a display panel 10, comprising the following steps:

[0191] S10, Provide substrate 100.

[0192] S20. A plurality of sub-pixels 200 are formed on the substrate 100 at intervals.

[0193] The substrate 100 is provided with a plurality of pixel circuits 300 corresponding to a plurality of sub-pixels 200. The sub-pixels 200 are electrically connected to their corresponding pixel circuits 300.

[0194] The corresponding sub-pixel 200 can be driven to emit light through the pixel circuit 300, so that different patterns can be displayed using the display panel 10.

[0195] The substrate 100 is provided with a plurality of via connection structures 400 corresponding to a plurality of pixel circuits 300, and the via connection structures 400 are electrically connected to the corresponding pixel circuits 300. The plurality of via connection structures 400 includes at least two types of via connection structures 400.

[0196] In the process of electrically connecting the pixel circuit 300 with the corresponding sub-pixel 200, multiple types of via connection structures 400 are usually involved. One end of the via connection structure 400 of the same type is connected to a component of the first attribute, and the other end of the via connection structure 400 of the same type is connected to a component of the second attribute, so that the via connection structure 400 of the same type is electrically connected between the component of the first attribute and the component of the second attribute. For example, the sub-pixel 200 includes a first electrode 210, a light-emitting layer 220 and a second electrode 230 stacked together. The component of the first attribute is the first electrode 210, and the component of the second attribute is the pixel circuit 300 (specifically, the component of the second attribute is the first transistor M1 of the pixel circuit 300).

[0197] The substrate 100 has a plurality of vias K corresponding to a plurality of via connection structures 400. At least two adjacent sub-pixels 200 are provided with the same type of via connection structure 400 spaced apart from each other and located in the same via K. The at least two adjacent sub-pixels are defined as a sub-pixel group. At least two adjacent sub-pixels 200 in the sub-pixel group are symmetrically arranged with reference plane P as the reference object. The reference plane P is parallel to the thickness direction of the substrate 100.

[0198] In this way, the size of the via K can meet the design requirements, while also increasing the number of sub-pixels 200 arranged per unit area on the substrate 100, thereby increasing the resolution of the display panel 10.

[0199] In some embodiments, the plurality of via connection structures 400 includes a plurality of first via connection structures 410, and the plurality of vias K includes a plurality of first vias K1 corresponding to the plurality of first via connection structures 410.

[0200] Step S10 of providing substrate 100 specifically includes: providing a substrate body 110 and a planarization layer 120 stacked together, wherein the planarization layer 120 is provided with a plurality of first vias K1. Specifically, an initial planarization layer may be formed on one side of the substrate body 110, and the initial planarization layer may be etched to obtain a planarization layer 120 provided with a plurality of first vias K1.

[0201] Step S20, which involves forming a plurality of spaced sub-pixels 200 on the substrate 100, specifically includes:

[0202] S21. A first electrode layer is formed on the substrate 100, which is partially disposed within a plurality of first vias K1.

[0203] S22. The first electrode layer is etched to form a plurality of first electrodes 210 and a plurality of first via connection structures 410 correspondingly disposed in a plurality of first vias K1. The first via connection structures 410 corresponding to at least two adjacent sub-pixels 200 are spaced apart from each other and are located in the same first via K1.

[0204] S23. A pixel definition layer 500 is formed on the side of the planarization layer 120 away from the substrate body 110. The pixel definition layer 500 is partially disposed in a plurality of first vias K1 to separate at least two first via connection structures 410 in at least one first via K1.

[0205] In this way, the pixel definition layer 500 can be used to separate at least two first via connection structures 410 within the same first via K1, thereby enabling the pixel circuit 300 to independently control the corresponding sub-pixel 200, while also increasing the number of sub-pixels 200 arranged per unit area on the substrate 100, and further improving the resolution of the display panel 10.

[0206] Optionally, step S20 of forming a plurality of spaced sub-pixels 200 on the substrate 100 further includes:

[0207] S24. Multiple pixel openings 501 corresponding to multiple sub-pixels 200 are formed on the pixel definition layer 500.

[0208] S25. A plurality of light-emitting layers 220 and a second electrode layer including all the second electrodes 230 are formed on the pixel definition layer 500. The second electrode layer includes all the second electrodes 230 connected together, which is equivalent to the structure of a full-surface cathode.

[0209] The light-emitting layer 220 is disposed within the corresponding pixel opening 501 and covers the corresponding first electrode 210. The second electrode layer is disposed on the side of the pixel definition layer 500 away from the planarization layer 120 and covers all light-emitting layers 220.

[0210] Similarly, the formation process of the second via connection structure 420 and the second via K2 is similar. Multiple second vias K2 are formed on the insulating layer 112, and an initial metal layer is formed on the side of the insulating layer 112 away from the substrate 111. The initial metal layer is etched to obtain the aforementioned metal layer. This metal layer includes multiple data signal lines 330 spaced apart, multiple first power signal lines 310, and the aforementioned adapter lines, etc. The data signal lines 330 are electrically connected to the second source M21 of the second transistor M2 of the corresponding pixel circuit 300 through the corresponding second via connection structure 420. At least two second via connection structures 420 are disposed within the same second via K2. Subsequently, a planarization layer 120 is formed on the side of the insulating layer 112 away from the substrate 111, and a portion of the planarization layer 120 is disposed within the multiple second vias K2.

[0211] Optionally, the method for manufacturing the display panel 10 may further include:

[0212] S30. A first encapsulation layer 610 and a second encapsulation layer 620 covering a plurality of sub-pixels 200 are formed on the pixel definition layer 500. The second encapsulation layer 620 is disposed on the side of the first encapsulation layer 610 away from the substrate 100.

[0213] Thus, the first encapsulation layer 610 and the second encapsulation layer 620 can achieve the effect of dual encapsulation for multiple sub-pixels 200, thereby improving the reliability of the display panel 10 and also improving the display effect of the display panel 10.

[0214] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0215] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate; and Multiple sub-pixels are spaced apart on one side of the substrate; The substrate is provided with a plurality of pixel circuits corresponding to the plurality of sub-pixels; the sub-pixels are electrically connected to the corresponding pixel circuits. The substrate is provided with a plurality of via connection structures corresponding to the plurality of pixel circuits, and the via connection structures are electrically connected to the corresponding pixel circuits; the plurality of via connection structures include at least two types of via connection structures. The substrate is also provided with a plurality of vias corresponding to the plurality of via connection structures; At least two adjacent sub-pixels are provided with the same type of via connection structure spaced apart from each other and located in the same via; the at least two adjacent sub-pixels are defined as a sub-pixel group, and at least one pair of adjacent sub-pixels in the sub-pixel group are arranged symmetrically with reference plane as the reference object, and the reference plane is parallel to the thickness direction of the substrate.

2. The display panel according to claim 1, characterized in that, The sub-pixel group, the via connection structure corresponding to the sub-pixel group, and the via corresponding to the sub-pixel group are arranged symmetrically with the same reference plane as the reference object; Optionally, a plurality of the sub-pixels are arranged in a row along a first direction and in a column along a second direction, wherein the first direction and the second direction intersect each other and are both perpendicular to the thickness direction of the substrate; Optionally, the same type of via connection structure corresponding to two adjacent sub-pixels along the first direction are spaced apart from each other and located in the same via; The reference plane is perpendicular to the first direction; or The via connection structures of the same type corresponding to two adjacent sub-pixels along the second direction are spaced apart from each other and located in the same via; The reference plane is perpendicular to the second direction; or The sub-pixel group includes four sub-pixels, and each sub-pixel group includes two sub-pixel subgroups that are adjacent and spaced apart along the first direction. Each sub-pixel subgroup includes two sub-pixels that are adjacent and spaced apart along the second direction. The reference plane includes a first reference plane perpendicular to the first direction and a second reference plane perpendicular to the second direction. The sub-pixel groups are arranged symmetrically with reference to the first reference plane and the second reference plane, respectively. The vias corresponding to the sub-pixel groups are arranged symmetrically with reference to the first reference plane and the second reference plane, respectively. The multiple via connection structures corresponding to the sub-pixel group are arranged symmetrically with the first reference plane and the second reference plane as reference objects respectively; Optionally, the via connection structures of the same type corresponding to two adjacent rows of sub-pixels are spaced apart from each other and located in the same via; The reference plane is perpendicular to the second direction; Optionally, the via connection structures of the same type corresponding to two adjacent columns of the sub-pixels are spaced apart from each other and located in the same via; The reference plane is perpendicular to the first direction.

3. The display panel according to claim 1, characterized in that, The substrate includes a substrate body and a planarization layer stacked together; the plurality of sub-pixels are spaced apart on the side of the planarization layer away from the substrate body; the plurality of pixel circuits are disposed on the substrate body; The plurality of via connection structures includes a plurality of first via connection structures disposed on the planarization layer, and the plurality of vias includes a plurality of first vias disposed on the planarization layer and corresponding to the plurality of first via connection structures; The first via connection structures corresponding to at least two adjacent sub-pixels are spaced apart from each other and located in the same first via; The sub-pixel includes a first electrode, a light-emitting layer, and a second electrode stacked together; One end of the first via connection structure is electrically connected to the first electrode of the corresponding sub-pixel, and the other end of the first via connection structure is electrically connected to the corresponding pixel circuit.

4. The display panel according to claim 3, characterized in that, The pixel circuit includes a first power signal line, a second power signal line, and a first transistor; The first transistor includes a control terminal, a first terminal, and a second terminal; The first power signal line is used to input a first power signal to the first terminal of the first transistor, and the first electrode is electrically connected to the second terminal of the first transistor of the corresponding pixel circuit through a corresponding first via connection structure. The second electrode of the sub-pixel is electrically connected to the second power signal line of the corresponding pixel circuit.

5. The display panel according to claim 4, characterized in that, The pixel circuit also includes a data signal line and a second transistor, the second transistor including a control terminal, a first terminal and a second terminal; The control terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the second terminal of the second transistor is electrically connected to the data signal line. The control terminal of the second transistor is used to receive the scan signal. The plurality of via connection structures includes a plurality of second via connection structures disposed on the substrate body, wherein the first via connection structure and the second via connection structure are different types of via connection structures; The plurality of vias includes a plurality of second vias that correspond to the plurality of second via connection structures and are disposed on the substrate body; One end of the second via connection structure is electrically connected to the data signal line of the corresponding pixel circuit, and the other end of the second via connection structure is electrically connected to the second terminal of the second transistor of the corresponding pixel circuit. The second via connection structures corresponding to at least two adjacent sub-pixels are spaced apart from each other and located in the same second via; Optionally, the pixel circuit further includes a storage module, which includes a first terminal and a second terminal; the first terminal of the storage module is electrically connected to a first power signal line; and the second terminal of the storage module is electrically connected to the first terminal of the second transistor. Optionally, the substrate body includes a substrate and an insulating layer stacked together; the planarization layer is disposed on the side of the insulating layer away from the substrate; The plurality of second vias and the plurality of second via connection structures are all disposed on the insulating layer.

6. The display panel according to any one of claims 3-5, characterized in that, The display panel also includes a pixel definition layer; A portion of the pixel definition layer is disposed on the side of the planarization layer away from the substrate body, and another portion of the pixel definition layer is disposed within the plurality of first vias to separate all the first via connection structures in the same first via. The pixel definition layer is provided with a plurality of pixel openings corresponding to the plurality of sub-pixels, and at least a portion of the sub-pixels are disposed within the corresponding pixel openings; Optionally, the pixel opening is configured to correspond one-to-one with the sub-pixel.

7. The display panel according to any one of claims 1-5, characterized in that, The plurality of sub-pixels are arranged to form a plurality of repeating units, each of the repeating units including a first sub-pixel, a second sub-pixel and a third sub-pixel; The first sub-pixel, the second sub-pixel, and the third sub-pixel each emit different colors. Optionally, the same type of via connection structure corresponding to two of the first sub-pixel, the second sub-pixel, and the third sub-pixel of the same repeating unit is located in the same via; Optionally, at least two adjacent sub-pixels in two adjacent repeating units correspond to the same type of via connection structure located in the same via; Optionally, at least two adjacent repeating units of the same type of via connection structure are located in the same via; Optionally, the plurality of repeating units are arranged in rows and columns; the via connection structures of the same type corresponding to two adjacent rows of repeating units are located in the same via; and / or The via connection structures of the same type corresponding to two adjacent columns of repeating units are located in the same via.

8. The display panel according to claim 7, characterized in that, The light emission color of one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is red; the light emission color of another of the first sub-pixel, the second sub-pixel, and the third sub-pixel is green; and the light emission color of yet another of the first sub-pixel, the second sub-pixel, and the third sub-pixel is blue. Optionally, the first sub-pixel is rectangular in shape, the second sub-pixel is rectangular in shape, and the third sub-pixel is rectangular in shape; Optionally, the repeating unit is rectangular in shape; Optionally, the repeating unit is square in shape; Optionally, the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged alternately along the target direction; the target direction is parallel to one of the first direction and the second direction, the first direction and the second direction intersect each other, and both are perpendicular to the thickness direction of the substrate; Optionally, the plurality of said sub-pixels are arranged in a row along the first direction and in a column along the second direction; Optionally, the sub-pixel has a first pixel edge and a second pixel edge disposed opposite to each other along a first direction, the pixel circuit has a first boundary located on the same side as the first pixel edge along the first direction, and a second boundary disposed opposite to the first boundary along the first direction, the distance between the orthographic projection of the first pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding first boundary on the bottom surface of the substrate is less than or equal to a first preset distance. The distance between the orthographic projection of the second pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding second boundary on the bottom surface of the substrate is less than or equal to a second preset distance; the first direction is perpendicular to the thickness direction of the substrate; Optionally, the sub-pixel has a third pixel edge and a fourth pixel edge disposed opposite to each other along the second direction, the pixel circuit has a third boundary located on the same side as the third pixel edge along the second direction, and a fourth boundary disposed opposite to the third boundary along the second direction, the distance between the orthographic projection of the third pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding third boundary on the bottom surface of the substrate is less than or equal to a third preset distance. The distance between the orthographic projection of the fourth pixel edge on the bottom surface of the substrate and the orthographic projection of the corresponding fourth boundary on the bottom surface of the substrate is less than or equal to a fourth preset distance. The first direction and the second direction intersect each other and are both perpendicular to the thickness direction of the substrate.

9. A method for manufacturing a display panel, characterized in that, include: Provide substrate; and Multiple sub-pixels are formed on the substrate at intervals; The substrate is provided with a plurality of pixel circuits corresponding to the plurality of sub-pixels; the sub-pixels are electrically connected to the corresponding pixel circuits. The substrate is provided with a plurality of via connection structures corresponding to the plurality of pixel circuits, and the via connection structures are electrically connected to the corresponding pixel circuits; the plurality of via connection structures include at least two types of via connection structures. The substrate is provided with a plurality of vias corresponding to the plurality of via connection structures; At least two adjacent sub-pixels are provided with the same type of via connection structure spaced apart from each other and located in the same via; the at least two adjacent sub-pixels are defined as a sub-pixel group, and at least one pair of adjacent sub-pixels in the sub-pixel group are arranged symmetrically with reference plane as the reference object, and the reference plane is parallel to the thickness direction of the substrate.

10. The method for manufacturing a display panel according to claim 9, characterized in that, The plurality of via connection structures includes a plurality of first via connection structures, and the plurality of vias includes a plurality of first vias corresponding to the plurality of first via connection structures; The provision of the substrate specifically includes: a substrate body and a planarization layer stacked together; wherein the planarization layer is provided with the plurality of first vias; The sub-pixel includes a first electrode, a light-emitting layer, and a second electrode stacked together; the formation of multiple sub-pixels spaced apart on the substrate specifically includes: A first electrode layer is formed on the substrate, partially disposed within the plurality of first vias; The first electrode layer is etched to form a plurality of first electrodes and a plurality of first via connection structures correspondingly disposed in the plurality of first vias; wherein, the first via connection structures corresponding to at least two adjacent sub-pixels are spaced apart from each other and located in the same first via; A pixel definition layer is formed on the side of the planarization layer away from the substrate body. The pixel definition layer is partially disposed in the plurality of first vias to separate at least two first via connection structures in at least one first via. Optionally, the plurality of sub-pixels spaced apart on the substrate further includes: Multiple pixel openings corresponding to the multiple sub-pixels are formed on the pixel definition layer; Multiple light-emitting layers and a second electrode layer including all the second electrodes are formed on the pixel definition layer; The light-emitting layer is disposed within the corresponding pixel opening and covers the corresponding first electrode; The second electrode layer is disposed on the side of the pixel definition layer opposite to the planarization layer and covers all the light-emitting layers.

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