Display device and driving method thereof

Abstract

Embodiments of the present application disclose a display device and a driving method thereof. The display device comprises a plurality of pixels arranged in an array, at least two data line groups, at least two on-off control modules, at least two gate control signal lines and a driving module. The data line group comprises at least two data lines, the data lines are connected to at least some of the pixels in at least one column, the data line group is connected to the driving module through the corresponding on-off control module, different data line groups correspond to different on-off control modules. The control end of the on-off control module is connected to the corresponding gate control signal line, the gate control signal lines corresponding to different on-off control modules are different, the driving module is used to control the on duration of the on-off control module through the gate control signal line when scanning each row of pixels, control the on duration of the driving module and the corresponding data line group, wherein the on durations of the at least two on-off control modules are different. The present application can improve the crosstalk between the data lines of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display device and its driving method. Background Technology

[0002] Currently, the wiring in display panels is too dense, resulting in insufficient distance between adjacent lines. This causes electromagnetic fields generated during signal transmission to interfere with each other, leading to crosstalk issues in the display panel and affecting the image display quality. Summary of the Invention

[0003] This invention provides a display device and its driving method to improve crosstalk between data lines on a display panel and enhance the quality of the displayed image.

[0004] According to one aspect of the present invention, a display device is provided, the display device comprising an array of multiple pixels, at least two data line groups, at least two on / off control modules, at least two gating control signal lines, and a driving module;

[0005] The data line group includes at least two data lines, and the data lines are connected to at least a portion of the pixels in at least one column of pixels. The data line group is connected to the driving module through a corresponding on / off control module, and different data line groups correspond to different on / off control modules.

[0006] The control terminal of the on / off control module is connected to the corresponding gating control signal line. Different on / off control modules correspond to different gating control signal lines. The driving module is used to control the conduction duration of the on / off control module through the gating control signal line when scanning each row of pixels, and to control the conduction duration of the driving module and the corresponding data line group. At least two on / off control modules have different conduction durations, and at least two on / off control modules are simultaneously turned off when scanning each row of pixels ends.

[0007] Optionally, the on / off control module includes at least two switching units;

[0008] The data lines in the data line group are connected to the drive module through the corresponding switch units. Different data lines correspond to different switch units, and the control terminal of the switch unit is connected to the gating control signal line.

[0009] Optionally, the switching unit includes a transistor;

[0010] The first terminal of the transistor is connected to the corresponding data line, the second terminal of the transistor is connected to the driving module, and the control terminal of the transistor serves as the control terminal of the switching unit.

[0011] Optionally, the transistor includes at least one of NMOS and PMOS.

[0012] Optionally, the data line extends along a first direction, and multiple data lines are arranged along a second direction, the second direction intersecting the first direction.

[0013] Optionally, the data lines in the data line group are arranged adjacent to each other along the second direction, and the conduction duration of the on / off control module corresponding to the data line group arranged along the second direction is sequentially extended or shortened.

[0014] Optionally, the data lines in the data line group are spaced apart along the second direction.

[0015] Optionally, the driving module and the on / off control module are integrated in the driving chip, or the on / off control module is integrated in the display panel.

[0016] Optionally, the driving module includes multiple operational amplifier units;

[0017] Each data line in each group of data lines is connected to an operational amplifier unit through a corresponding on / off control module.

[0018] Optionally, the drive module includes multiple switch drive units;

[0019] Each of the gating control signal lines is connected to one of the switch driving units.

[0020] Optionally, the number of data lines included in the data line group is determined in advance through panel line crosstalk testing.

[0021] According to another aspect of the present invention, a display device driving method is provided, which is executed using a display device as described in any embodiment of the present invention, the method comprising:

[0022] When scanning each row of pixels, the driving module controls the conduction duration of the on / off control module through the gating control signal line, thereby controlling the conduction duration of the driving module and the corresponding data line group. At least two of the on / off control modules have different conduction durations, and at least two of the on / off control modules simultaneously turn off when scanning each row of pixels ends.

[0023] Optionally, the on / off control module, which controls the data line group to be turned on first in the drive module, is turned on during a portion of the idle time before scanning each row of pixels;

[0024] Except for the idle time of the on / off control module that controls the data line group and the drive module to be connected first, all other idle times are turned off.

[0025] Optionally, along the arrangement direction of the data line groups, the conduction duration of the on / off control module connected to each data line group increases or decreases sequentially.

[0026] In this embodiment of the invention, when scanning each row of pixels, the driving module controls the conduction duration of different on / off control modules through different gating control signal lines. This controls the conduction duration of the driving module and different data line groups to be different, thereby achieving asynchronous changes in the data signals of the data lines of different data line groups. This reduces the degree of electromagnetic coupling caused by parasitic capacitance and parasitic inductance, reduces the interaction between reflected signals, reduces the possibility of common-mode interference, reduces crosstalk, and improves the quality of the displayed image. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of another display device provided in an embodiment of the present invention;

[0030] Figure 3 A timing diagram of a gating control signal line provided in an embodiment of the present invention;

[0031] Figure 4 A display device driving method provided in an embodiment of the present invention;

[0032] Figure 5 A timing diagram of another gating control signal line provided in an embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] Panel line crosstalk refers to the phenomenon where electromagnetic interference on one signal line inadvertently couples to another adjacent signal line in a panel circuit, thus affecting its normal signal transmission. Parasitic capacitance exists between transmission lines (such as data lines) in the panel wiring of a display device. When the signal on one transmission line changes, a coupling current is generated on adjacent transmission lines through the parasitic capacitance. This coupling current causes voltage changes on the interfered line, resulting in crosstalk. For example, high-frequency signal changes on a signal line can transfer energy through the capacitance between the signal line and adjacent signal lines. When the signal edge changes rapidly, the crosstalk caused by capacitive coupling is more pronounced.

[0036] Furthermore, the overly close arrangement of data lines and pixel electrodes in the display panel creates parasitic capacitance between them. When the data line voltage changes, capacitive coupling occurs through this parasitic capacitance to the gate of the driving transistor, causing a change in the gate potential and conduction level of the driving transistor. For example, in the transition zone between black and white in a black-and-white image, the precisely controlled current may deviate, resulting in abnormal pixel charging and discharging. This leads to bright and dark lines (the brightness of which is related to the coupling strength) appearing in the transition zone, compromising the integrity and accuracy of the image. Specifically, the driving transistor corresponding to a black pixel, which should be off or have only a minimal current flowing through it, may become more conductive due to changes in its gate potential, allowing extra current to flow into the pixel and causing overcharging, resulting in an unwanted bright line. Conversely, the driving transistor corresponding to a white pixel may be underconducted, resulting in undercharging and a dark line.

[0037] To address the aforementioned problems, this invention provides a display device that can improve crosstalk between data lines on the display panel and enhance the quality of the displayed image. Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 1As shown, the display device includes a plurality of pixels 110 arranged in an array, at least two data line groups 120, at least two on / off control modules 130, at least two gating control signal lines 140, and a driving module 150.

[0038] The data line group 120 includes at least two data lines 121, and the data lines 121 are connected to at least a portion of the pixels 110 in at least one column of pixels 110. The data line group 120 is connected to the drive module 150 through a corresponding on / off control module 130. Different data line groups 120 correspond to different on / off control modules 130.

[0039] The control terminal of the on / off control module 130 is connected to the corresponding gating control signal line 140. Different on / off control modules 130 correspond to different gating control signal lines 140. The driving module 150 is used to control the conduction duration of the on / off control module 130 through the gating control signal line 140 when scanning each row of pixels 110, and to control the conduction duration of the driving module 150 and the corresponding data line group 120. At least two on / off control modules 130 have different conduction durations, and at least two on / off control modules 130 are simultaneously turned off when scanning each row of pixels 110 ends.

[0040] Each gating control signal line 140 is used to transmit an on / off signal to control the conduction state of the on / off control module 130; the data line 121 is used to transmit a data signal to drive the corresponding row pixel 110 to write data voltage; the on / off signal transmitted by the gating control signal line 140 and the data signal transmitted by the data line 121 are both signals generated by the drive module 150. The number of data line groups 120 and on / off control modules 130 are the same, and the number of gating control signal lines 140 is the same as the number of on / off control modules 130.

[0041] Specifically, when scanning each row of pixels 110, the driving module 150 can control the conduction duration of different on / off control modules 130 to be different through different gating control signal lines 140, and control the different on / off control modules 130 to be turned off simultaneously at the end of scanning each row of pixels 110. This controls the conduction duration of the driving module 150 and different data line groups 120 to be different, and controls the conduction time of different data line groups 120 to partially overlap with that of the driving module 150. In other words, by controlling the start time of each on / off control module 130 to be different, the start time of each data line group 120 to transmit data signals is different, thereby reducing crosstalk between data lines 121.

[0042] Each data line group 120 starts transmitting data signals at a different time, meaning that different data line groups 120 do not start transmitting data signals simultaneously. When only some data lines 121 (one data line group 120) have data signal changes at the same time (i.e., the data signal changes of data lines 121 in different data line groups 120 are asynchronous), it can prevent different data line groups 120 from being in a state of strong electromagnetic field coupling at the same time. This reduces the degree of electromagnetic coupling caused by parasitic capacitance and parasitic inductance, reduces crosstalk, and improves the quality of the display screen.

[0043] Furthermore, during data signal transmission, signal reflection can cause signal distortion and crosstalk. When the data signals of data lines 121 in multiple data line groups 120 change synchronously, if the characteristic impedances of the data lines 121 in each data line group 120 are not perfectly matched, the reflected signals of the transmitted data signals in each data line group 120 will interfere with each other, increasing the possibility of crosstalk. However, if the data signals of the data lines 121 in different data line groups 120 change asynchronously, the complexity of the signal reflection situation in each data line group 120 can be reduced, the interaction between reflected signals can be reduced, and thus crosstalk can be reduced.

[0044] When the data signals of data lines 121 in multiple data line groups 120 change synchronously, common-mode interference may occur, meaning that interference currents in the same direction appear on all data lines 121. This common-mode interference creates an additional electromagnetic field between the data lines 121, exacerbating crosstalk. When the data signals of data lines 121 in different data line groups 120 change asynchronously, the possibility of common-mode interference is reduced, thus helping to reduce crosstalk.

[0045] In this embodiment of the invention, when scanning each row of pixels 110, the driving module 150 controls the conduction duration of different on / off control modules 130 through different gating control signal lines 140, thereby controlling the conduction duration of the driving module 150 and different data line groups 120 to be different. This achieves asynchronous changes in the data signals of the data lines 121 of different data line groups 120, thereby reducing the degree of electromagnetic coupling generated by parasitic capacitance and parasitic inductance, reducing the interaction between reflected signals, reducing the possibility of common-mode interference, reducing crosstalk, and improving the quality of the displayed image.

[0046] Based on the above embodiments, optionally, the number of data lines 121 included in the data line group 120 is determined in advance through panel line crosstalk test, so as to reduce crosstalk of data signals transmitted between data lines 121 in the same group, thereby further improving the quality of the display screen.

[0047] Among them, panel line crosstalk test is an important test item for evaluating the performance of display panels. It can be used to detect the mutual interference between signals between different lines in the panel.

[0048] The testing principle of panel line crosstalk is as follows: Since signal lines in a display panel generate electromagnetic fields when transmitting signals, these fields may couple when adjacent lines are close together, causing a signal on one line to couple to another, resulting in crosstalk. During testing, specific test signals are typically input onto some lines, and then other lines are checked for abnormal crosstalk signals. The amplitude, frequency, and other parameters of the crosstalk signal are measured using specialized instruments to assess the degree of line crosstalk.

[0049] Pre-determining the number of data lines 121 included in the data line group 120 through panel crosstalk testing ensures the signal transmission quality of the display panel, preventing issues such as ghosting, flickering, and color distortion caused by crosstalk, and guaranteeing that the panel can display clear and stable images. Furthermore, it helps display panel manufacturers optimize panel design and manufacturing processes. By detecting crosstalk problems, defects in circuit layout, insulation design, etc., can be identified for improvement, thereby increasing product reliability and yield.

[0050] As can be seen from the above, the present invention can avoid producing a display panel with unqualified crosstalk by simply determining the number of data lines 121 included in the data line group 120 in advance through panel line crosstalk test before the production of the display panel, thus greatly reducing the defect rate of the display panel production.

[0051] Based on the above embodiments, optionally, Figure 2 This is a schematic diagram of another display device provided in an embodiment of the present invention, such as... Figure 2 As shown, the on / off control module 130 includes at least two switching units; the data line 121 in the data line group 120 is connected to the drive module 150 through the corresponding switching unit. Different data lines 121 correspond to different switching units, and the control terminal of the switching unit is connected to the gating control signal line 140.

[0052] Specifically, the number of switching units included in each on / off control module 130 is the same as the number of data lines 121 included in its connected data line group 120. Each data line 121 in each data line group 120 is connected to the drive module 150 through a switching unit in the corresponding on / off control module 130. The control terminals of all switching units in the same on / off control module 130 are connected to the same gating control signal line 140, so that all switching units included in the same on / off control module 130 are simultaneously turned on or off, thereby enabling each data line 121 in the same data line group 120 to transmit data signals simultaneously.

[0053] Based on the above embodiments, optionally, the switching unit includes a transistor; the first terminal of the transistor is connected to the corresponding data line 121, the second terminal of the transistor is connected to the driving module 150, and the control terminal of the transistor serves as the control terminal of the switching unit.

[0054] The transistor includes at least one of NMOS and PMOS.

[0055] Specifically, the first terminal of the NMOS is connected to the corresponding data line 121, the second terminal of the NMOS is connected to the driving module 150, and the control terminal of the NMOS is connected to a gating control signal line 140. All the NMOS terminals included in the on / off control module 130 are connected to the same gating control signal line 140.

[0056] Similarly, the first terminal of the PMOS is connected to the corresponding data line 121, the second terminal of the PMOS is connected to the drive module 150, and the control terminal of the PMOS is connected to a gating control signal line 140. In this configuration, the control terminals of all PMOS components in the on / off control module 130 are connected to the same gating control signal line 140.

[0057] Figure 2 The transistor is exemplarily shown as an NMOS. When the control terminal of the NMOS is high, the NMOS can control the data line 121 connected to the corresponding driver module 150 to be turned on; when the control terminal of the NMOS is low, the NMOS can control the data line 121 connected to the corresponding driver module 150 to be turned off.

[0058] When the control terminal of the PMOS is high, the PMOS can control the data line 121 connected to the corresponding PMOS in the drive module 150 to turn off; when the control terminal of the PMOS is low, the PMOS can control the data line 121 connected to the corresponding PMOS in the drive module 150 to turn on.

[0059] Based on the above embodiments, alternatively, refer to the following: Figure 1 or Figure 2 Data line 121 extends along a first direction X, and multiple data lines 121 are arranged along a second direction Y, which intersects with the first direction. The first direction is... Figure 1 or Figure 2 The vertical direction in the middle, the second direction is Figure 1 or Figure 2 The horizontal direction in the middle.

[0060] The data lines 121 in the data line group 120 are arranged adjacently along the second direction, and the conduction time of the on / off control module 130 connected to the data line group 120 arranged along the second direction is extended or shortened in sequence.

[0061] For example, Figure 3 A timing diagram of a gating control signal line provided in an embodiment of the present invention. Figure 3 The conduction time of the on / off control module connected to the data line group arranged along the second direction is shortened sequentially.

[0062] If the on / off control module includes an NMOS transistor, when the control terminal of the NMOS is high, the NMOS can control the data line connected to the corresponding driver module to be turned on; when the control terminal of the NMOS is low, the NMOS can control the data line connected to the corresponding driver module to be turned off. Based on the timing signals SW1, SW2, and SW3 of the on / off control modules connected to the first data line group arranged along the second direction, it can be seen that the off-time of the on / off control module connected to the first data line group arranged along the second direction is less than the off-time of the on / off control module connected to the second data line group arranged along the second direction, the off-time of the on / off control module connected to the third data line group arranged along the second direction is less than the off-time of the on / off control module connected to the third data line group arranged along the second direction, and so on. Therefore, it can be seen that the duration of the low-level input to the on / off control modules connected to the on / off control modules connected to the data line groups arranged along the second direction increases sequentially, and the duration of the high-level input to the on / off control modules connected to the data line groups arranged along the second direction decreases sequentially. Thus, it can be seen that the on-time of the on / off control modules connected to the data line groups arranged along the second direction decreases sequentially.

[0063] If the on / off control module includes NMOS transistors Figure 3 The first timing signal SW1 shown is the timing signal of the on / off control module corresponding to the last data line group arranged along the second direction. Figure 3 The second timing signal SW2 shown is the timing signal of the on / off control module corresponding to the second-to-last data line group arranged along the second direction. Figure 3 The third timing signal SW3 shown is the timing signal for the on / off control module connected to the third-to-last data line group arranged along the second direction, ...; thus, the conduction duration of the on / off control modules connected to the data line groups arranged along the second direction is sequentially extended. This will not be elaborated further in this scheme.

[0064] If the on / off control module includes PMOS transistors Figure 3 The low level of each timing signal shown changes to a high level, and the high level changes to a low level, which can sequentially shorten the conduction time of the on / off control module connected to the data line group arranged along the second direction; this will not be elaborated further in this solution.

[0065] If the on / off control module includes PMOS transistors Figure 3 The first timing signal SW1 shown is the timing signal of the on / off control module connected to the last data line group arranged along the second direction. The low level of the timing signal changes to the high level, and the high level changes to the low level. Figure 3 The second timing signal SW2 shown is the timing signal of the on / off control module corresponding to the second to last data line group arranged along the second direction. The low level of the timing signal changes to the high level, and the high level changes to the low level. Figure 3 The third timing signal SW3 shown is the timing signal for the on / off control module connected to the third-to-last data line group arranged along the second direction. The low level of the timing signal changes to a high level, and the high level changes to a low level; ...; thus, the conduction duration of the on / off control module connected to the data line group arranged along the second direction is sequentially extended. This will not be elaborated further in this scheme.

[0066] It is important to note that the on / off control module with the longest conduction time connected to the data line group arranged along the second direction is turned on first, and the on / off control module with the shortest conduction time connected to the data line group arranged along the second direction is turned on last. The above example is merely an illustrative illustration of one way to control the on / off control modules; there are no specific restrictions on the conduction order of each on / off control module, and it can be designed according to design requirements.

[0067] Optionally, based on the above embodiments, the data lines in the data line group are spaced apart along the second direction.

[0068] In this system, the data signals of the same group of data lines are transmitted at the same time, meaning that the data signals of the data lines in the same group change simultaneously. The data lines in the same group will be in a state of strong electromagnetic field coupling at the same time. The degree of electromagnetic coupling between the data lines through parasitic capacitance and parasitic inductance is related to the distance between the data lines. Therefore, the data lines in the data line group are spaced apart along the second direction, which can reduce the degree of electromagnetic coupling between the data lines through parasitic capacitance and parasitic inductance, thereby reducing crosstalk and improving the quality of the display.

[0069] Data signals within the same data cable group are transmitted simultaneously, meaning the data signals of the data cables in the same group change concurrently. The reflected signals from these signals interfere with each other, increasing the likelihood of crosstalk. The interference between reflected signals from the data cables in the same group is related to the distance between the data cables. Therefore, by arranging the data cables in a data cable group at intervals along a second direction, the interaction between reflected signals can be reduced, thereby lowering crosstalk and improving the quality of the displayed image.

[0070] When data signals in the same data line group are transmitted simultaneously, meaning the data signals of the data lines in the same group change at the same time, common-mode interference (CMI) occurs, resulting in interference currents in the same direction on the data lines. The synchronous changes in the data signals of the data lines in a data line group generate CCMI, which is related to the distance between the data lines. Therefore, by spacing the data lines in a data line group along a second direction, the likelihood of CCMI can be reduced, crosstalk can be minimized, and the quality of the display image can be improved.

[0071] Based on the above embodiments, optionally, the driving module and the on / off control module are integrated in the driving chip, or the on / off control module is integrated in the display panel.

[0072] When the driver module and the on / off control module are integrated into the driver chip, the functionality and integration of the driver chip are enhanced. When scanning each row of pixels, the driver chip can control the conduction duration of different data line groups with different gating control signal lines, and control the conduction time of different data line groups to partially overlap with that of the driver chip. In other words, by controlling the timing of the start of data signal transmission for each data line group to be different, electromagnetic coupling between data lines of different data line groups is reduced.

[0073] When the on / off control module is integrated into the display panel and the driving module is integrated into the driving chip, the driving chip can control the conduction duration of different on / off control modules through different gating control signal lines when scanning each row of pixels. This controls the conduction duration of the driving chip and different data line groups to be different, and the conduction time of different data line groups and the driving chip partially overlaps. In other words, by controlling the start time of each on / off control module to be different, the start time of data signal transmission of each data line group is different, thereby reducing the electromagnetic coupling between the data lines of different data line groups.

[0074] Based on the above embodiments, optionally, the driving module includes multiple operational amplifier units; each data line of each group of data lines is connected to an operational amplifier unit through a corresponding on / off control module.

[0075] The driver module includes the same number of operational amplifier units as the number of data lines. Each data line in each data line group is connected to an operational amplifier unit through a switching unit of the same on / off control module. Each operational amplifier unit provides a data signal to the data line it is connected to.

[0076] Operational amplifier (op-amp) units amplify weak input data signals to a level suitable for driving the display panel pixels, thus meeting the display device's level display requirements. Op-amp units also feature high input impedance and low output impedance, acting as a buffer between input and output. This prevents the display panel pixel circuitry from affecting the preceding data signal source, ensuring stable data signal transmission.

[0077] Based on the above embodiments, optionally, the driving module includes multiple switch driving units; each strobe control signal line is connected to a switch driving unit.

[0078] The number of switch drive units is the same as the number of gating control signal lines. Each switch drive unit generates an on / off signal to provide to one gating control signal line. Different switch drive units generate different on / off signals.

[0079] This invention also provides a display device driving method, which is executed by the display device provided in any embodiment of this invention. Figure 4 A display device driving method provided in an embodiment of the present invention, such as Figure 4 As shown, the display device driving method specifically includes:

[0080] S110. When scanning each row of pixels, the drive module controls the conduction duration of the on / off control module through the gating control signal line, thereby controlling the conduction duration of the drive module and the corresponding data line group. At least two on / off control modules have different conduction durations, and at least two on / off control modules are simultaneously turned off when scanning each row of pixels ends.

[0081] In this embodiment of the invention, when scanning each row of pixels, the driving module controls the conduction duration of different on / off control modules through different gating control signal lines. This controls the conduction duration of the driving module and different data line groups to be different, thereby achieving asynchronous changes in the data signals of the data lines of different data line groups. This reduces the degree of electromagnetic coupling caused by parasitic capacitance and parasitic inductance, reduces the interaction between reflected signals, reduces the possibility of common-mode interference, reduces crosstalk, and improves the quality of the displayed image.

[0082] Based on the above embodiments, optionally, the on / off control module that controls the data line group and the drive module to be turned on first is turned on during a portion of the idle time before scanning each row of pixels; except for the on / off control module that controls the data line group and the drive module to be turned on first, the idle time is turned off.

[0083] For example, Figure 5 Another timing diagram of the gating control signal line provided in an embodiment of the present invention, such as Figure 5As shown, the Horizontal Synchronization Signal (HSYNC) is a signal used to synchronize the horizontal scanning of an image. When displaying an image, the display panel needs to scan pixels in a specific order and rhythm. The HSYNC signal indicates the start and end of each row of pixel scans. When the display controller receives the HSYNC signal, it knows that the scanning of a row of pixels is about to begin or has ended, thus controlling the display panel to illuminate or control the corresponding pixels in the correct order and timing to ensure correct horizontal display and synchronization of the image.

[0084] The horizontal synchronization signal includes multiple line scan times T2 and multiple idle times T1; where, the line scan time T2 is the time to scan each row of pixels, that is, the time for the data line to transmit data signals; the idle time T1 is the time from the end of scanning the previous row of pixels to the start of scanning the next row of pixels.

[0085] The on / off control module that controls the data line group and the drive module to be turned on first can be set to conduct during a partial idle time T1 before scanning each row of pixels. The conduction time of this module is greater than or equal to one row scan time T2, and less than or equal to the sum of one row scan time T2 and one idle time T1. Specifically, when the conduction time of this module equals the sum of one row scan time T2 and one idle time T1, it means that the module is always in the on / off state.

[0086] Furthermore, since the drive module does not provide data signals to the data lines during the idle time T1, all on / off control modules except those controlling the data line group and the drive module that are first turned on during the idle time are turned off. This means that all on / off control modules except those controlling the data line group and the drive module that are first turned on must be turned on within the line scan time T2. In addition, the minimum on-time of these on / off control modules must be greater than or equal to 3 / 4 of the line scan time T2 to ensure that the pixels acquiring data signals have sufficient charging time.

[0087] Based on the above embodiments, optionally, along the arrangement direction of the data line group, the conduction time of the on / off control module connected to each data line group increases or decreases sequentially.

[0088] For example, Figure 3 A timing diagram of a gating control signal line provided in an embodiment of the present invention. Figure 3 The conduction time of the on / off control modules connected to the data line groups arranged along the second direction decreases sequentially.

[0089] If the on / off control module includes an NMOS transistor, when the control terminal of the NMOS is high, the NMOS can control the data line connected to the corresponding driver module to be turned on; when the control terminal of the NMOS is low, the NMOS can control the data line connected to the corresponding driver module to be turned off. Based on the timing signals SW1, SW2, and SW3 of the on / off control modules connected to the first data line group arranged along the second direction, it can be seen that the off-time of the on / off control module connected to the first data line group arranged along the second direction is less than the off-time of the on / off control module connected to the second data line group arranged along the second direction, the off-time of the on / off control module connected to the third data line group arranged along the second direction is less than the off-time of the on / off control module connected to the third data line group arranged along the second direction, and so on. Therefore, it can be seen that the duration of the low-level input to the on / off control modules connected to the data line groups arranged along the second direction increases sequentially, and the duration of the high-level input to the on / off control modules connected to the data line groups arranged along the second direction decreases sequentially. Thus, it can be seen that the on-time of the on / off control modules connected to the data line groups arranged along the second direction decreases sequentially.

[0090] It should be noted that this solution only needs to ensure that the conduction duration of the on / off control module connected to each data line group increases or decreases sequentially during the row scanning time. The above example is only an illustrative way to control the on / off control module. There are no specific restrictions on the conduction order of each on / off control module. You can design it yourself according to your design requirements.

[0091] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display device, characterized in that, It includes multiple pixels arranged in an array, at least two data line groups, at least two on / off control modules, at least two gating control signal lines, and a drive module; The data line group includes at least two data lines, and the data lines are connected to at least a portion of the pixels in at least one column of pixels. The data line group is connected to the driving module through a corresponding on / off control module, and different data line groups correspond to different on / off control modules. The control terminal of the on / off control module is connected to the corresponding gating control signal line. Different on / off control modules correspond to different gating control signal lines. The driving module is used to control the conduction duration of the on / off control module through the gating control signal line when scanning each row of pixels, and to control the conduction duration of the driving module and the corresponding data line group. At least two on / off control modules have different conduction durations, and at least two on / off control modules are simultaneously turned off when scanning each row of pixels ends.

2. The display device according to claim 1, characterized in that, The on / off control module includes at least two switching units; The data lines in the data line group are connected to the drive module through the corresponding switch units. Different data lines correspond to different switch units, and the control terminal of the switch unit is connected to the gating control signal line. Optionally, the switching unit includes a transistor; The first terminal of the transistor is connected to the corresponding data line, the second terminal of the transistor is connected to the driving module, and the control terminal of the transistor serves as the control terminal of the switching unit. Optionally, the transistor includes at least one of NMOS and PMOS.

3. The display device according to claim 1, characterized in that, The data line extends along a first direction, and multiple data lines are arranged along a second direction, which intersects with the first direction.

4. The display device according to claim 3, characterized in that, The data lines in the data line group are arranged adjacent to each other along the second direction, and the conduction time of the on / off control module corresponding to the data line group arranged along the second direction is sequentially extended or shortened.

5. The display device according to claim 3, characterized in that, The data cable group includes data cables that are spaced apart along the second direction.

6. The display device according to claim 1, characterized in that, The driving module and the on / off control module are integrated in the driving chip, or the on / off control module is integrated in the display panel.

7. The display device according to claim 6, characterized in that, The driving module includes multiple operational amplifier units; Each data line in each group of data lines is connected to an operational amplifier unit through a corresponding on / off control module. Optionally, the drive module includes multiple switch drive units; Each of the gating control signal lines is connected to one of the switch driving units.

8. The display device according to claim 1, characterized in that, The number of data lines included in the data line group is determined in advance through panel line crosstalk testing.

9. A display device driving method, performed using the display device according to any one of claims 1-8, characterized in that, include: When scanning each row of pixels, the driving module controls the conduction duration of the on / off control module through the gating control signal line, thereby controlling the conduction duration of the driving module and the corresponding data line group. At least two of the on / off control modules have different conduction durations, and at least two of the on / off control modules simultaneously turn off when scanning each row of pixels ends.

10. The display device driving method according to claim 9, characterized in that, The on / off control module, which controls the data line group and the first to be turned on by the drive module, is turned on during a portion of the idle time before scanning each row of pixels; Except for the idle time of the on / off control module that controls the data line group and the drive module to be connected first, all other idle times are turned off. Optionally, along the arrangement direction of the data line groups, the conduction duration of the on / off control module connected to each data line group increases or decreases sequentially.

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